| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.1057144953 |
|
|
Oct 15 11:44:57 AM UTC 24 |
Oct 15 11:45:00 AM UTC 24 |
949952017 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.1667298841 |
|
|
Oct 15 11:44:46 AM UTC 24 |
Oct 15 11:45:01 AM UTC 24 |
598424763 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.1721399249 |
|
|
Oct 15 11:44:27 AM UTC 24 |
Oct 15 11:45:03 AM UTC 24 |
7857608098 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.188568486 |
|
|
Oct 15 11:44:57 AM UTC 24 |
Oct 15 11:45:03 AM UTC 24 |
147228073 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.1050019636 |
|
|
Oct 15 11:44:57 AM UTC 24 |
Oct 15 11:45:04 AM UTC 24 |
1053082522 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.2372627297 |
|
|
Oct 15 11:45:02 AM UTC 24 |
Oct 15 11:45:08 AM UTC 24 |
192769061 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.1851189289 |
|
|
Oct 15 11:45:00 AM UTC 24 |
Oct 15 11:45:08 AM UTC 24 |
455523489 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2148898802 |
|
|
Oct 15 11:45:08 AM UTC 24 |
Oct 15 11:45:11 AM UTC 24 |
364369593 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.631924540 |
|
|
Oct 15 11:45:03 AM UTC 24 |
Oct 15 11:45:18 AM UTC 24 |
3461719973 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.3732407912 |
|
|
Oct 15 11:41:40 AM UTC 24 |
Oct 15 11:45:20 AM UTC 24 |
21336395664 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1502637809 |
|
|
Oct 15 11:45:04 AM UTC 24 |
Oct 15 11:45:24 AM UTC 24 |
2117856361 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.1592563850 |
|
|
Oct 15 11:45:10 AM UTC 24 |
Oct 15 11:45:26 AM UTC 24 |
2764154352 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.860679494 |
|
|
Oct 15 11:45:25 AM UTC 24 |
Oct 15 11:45:28 AM UTC 24 |
474227436 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.4285220648 |
|
|
Oct 15 11:44:18 AM UTC 24 |
Oct 15 11:45:28 AM UTC 24 |
2258337829 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.3283659265 |
|
|
Oct 15 11:45:25 AM UTC 24 |
Oct 15 11:45:29 AM UTC 24 |
655582648 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.4086147177 |
|
|
Oct 15 11:45:19 AM UTC 24 |
Oct 15 11:45:32 AM UTC 24 |
2232559101 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3235235345 |
|
|
Oct 15 11:44:53 AM UTC 24 |
Oct 15 11:45:33 AM UTC 24 |
3439691474 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1148899137 |
|
|
Oct 15 11:46:17 AM UTC 24 |
Oct 15 11:47:14 AM UTC 24 |
4565303419 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_perf.360241833 |
|
|
Oct 15 11:45:27 AM UTC 24 |
Oct 15 11:45:33 AM UTC 24 |
453266477 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_hrst.1152205087 |
|
|
Oct 15 11:45:30 AM UTC 24 |
Oct 15 11:45:36 AM UTC 24 |
419541151 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.269248977 |
|
|
Oct 15 11:44:15 AM UTC 24 |
Oct 15 11:45:38 AM UTC 24 |
3118080235 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_perf.2142326743 |
|
|
Oct 15 11:44:19 AM UTC 24 |
Oct 15 11:45:39 AM UTC 24 |
26235814925 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.1903924407 |
|
|
Oct 15 11:45:29 AM UTC 24 |
Oct 15 11:45:39 AM UTC 24 |
1354781406 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.4231648452 |
|
|
Oct 15 11:45:40 AM UTC 24 |
Oct 15 11:45:43 AM UTC 24 |
491198359 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.344000453 |
|
|
Oct 15 11:45:37 AM UTC 24 |
Oct 15 11:45:43 AM UTC 24 |
1115298681 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.1799702557 |
|
|
Oct 15 11:43:31 AM UTC 24 |
Oct 15 11:45:45 AM UTC 24 |
2172295177 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.1558774271 |
|
|
Oct 15 11:45:40 AM UTC 24 |
Oct 15 11:45:46 AM UTC 24 |
987968568 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_alert_test.1073780754 |
|
|
Oct 15 11:45:44 AM UTC 24 |
Oct 15 11:45:46 AM UTC 24 |
24899607 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.3278115317 |
|
|
Oct 15 11:45:35 AM UTC 24 |
Oct 15 11:45:47 AM UTC 24 |
517735699 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.2997795845 |
|
|
Oct 15 11:45:44 AM UTC 24 |
Oct 15 11:45:47 AM UTC 24 |
307043521 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.685405835 |
|
|
Oct 15 11:45:42 AM UTC 24 |
Oct 15 11:45:48 AM UTC 24 |
1001070389 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_override.1340618612 |
|
|
Oct 15 11:45:46 AM UTC 24 |
Oct 15 11:45:48 AM UTC 24 |
22102499 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.2992455208 |
|
|
Oct 15 11:45:43 AM UTC 24 |
Oct 15 11:45:49 AM UTC 24 |
2702489905 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.2381042277 |
|
|
Oct 15 11:44:27 AM UTC 24 |
Oct 15 11:45:49 AM UTC 24 |
59409230128 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.2977690563 |
|
|
Oct 15 11:45:48 AM UTC 24 |
Oct 15 11:45:51 AM UTC 24 |
136258827 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2263541500 |
|
|
Oct 15 11:45:50 AM UTC 24 |
Oct 15 11:45:56 AM UTC 24 |
387118633 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.4212439151 |
|
|
Oct 15 11:45:48 AM UTC 24 |
Oct 15 11:46:01 AM UTC 24 |
165332735 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.4107258259 |
|
|
Oct 15 11:44:56 AM UTC 24 |
Oct 15 11:46:02 AM UTC 24 |
5209898600 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_perf.3011623555 |
|
|
Oct 15 11:45:50 AM UTC 24 |
Oct 15 11:46:04 AM UTC 24 |
3977058380 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3412978638 |
|
|
Oct 15 11:46:02 AM UTC 24 |
Oct 15 11:46:06 AM UTC 24 |
130221589 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2179567953 |
|
|
Oct 15 11:45:46 AM UTC 24 |
Oct 15 11:46:12 AM UTC 24 |
1308552412 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.1407066462 |
|
|
Oct 15 11:46:04 AM UTC 24 |
Oct 15 11:46:17 AM UTC 24 |
547447519 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.3034724626 |
|
|
Oct 15 11:46:12 AM UTC 24 |
Oct 15 11:46:17 AM UTC 24 |
681129660 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.2269611355 |
|
|
Oct 15 11:44:16 AM UTC 24 |
Oct 15 11:46:18 AM UTC 24 |
8580432595 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1982001857 |
|
|
Oct 15 11:45:57 AM UTC 24 |
Oct 15 11:46:18 AM UTC 24 |
2643461974 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.3604073623 |
|
|
Oct 15 11:46:19 AM UTC 24 |
Oct 15 11:46:22 AM UTC 24 |
600027904 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.3192524431 |
|
|
Oct 15 11:46:13 AM UTC 24 |
Oct 15 11:46:22 AM UTC 24 |
2680477705 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.664890100 |
|
|
Oct 15 11:46:22 AM UTC 24 |
Oct 15 11:46:24 AM UTC 24 |
296697906 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_perf.1718056019 |
|
|
Oct 15 11:46:23 AM UTC 24 |
Oct 15 11:46:31 AM UTC 24 |
2142045508 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.12951820 |
|
|
Oct 15 11:44:24 AM UTC 24 |
Oct 15 11:46:31 AM UTC 24 |
2125289040 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1518525987 |
|
|
Oct 15 11:46:19 AM UTC 24 |
Oct 15 11:46:32 AM UTC 24 |
4877416326 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.3377569059 |
|
|
Oct 15 11:46:25 AM UTC 24 |
Oct 15 11:46:34 AM UTC 24 |
2136455397 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.1388705679 |
|
|
Oct 15 11:44:58 AM UTC 24 |
Oct 15 11:46:38 AM UTC 24 |
5896911093 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.1141137862 |
|
|
Oct 15 11:46:39 AM UTC 24 |
Oct 15 11:46:43 AM UTC 24 |
2482595697 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.1549383197 |
|
|
Oct 15 11:46:11 AM UTC 24 |
Oct 15 11:47:20 AM UTC 24 |
19516552190 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1139366773 |
|
|
Oct 15 11:45:48 AM UTC 24 |
Oct 15 11:46:45 AM UTC 24 |
2622198924 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.3367449070 |
|
|
Oct 15 11:46:43 AM UTC 24 |
Oct 15 11:46:46 AM UTC 24 |
289867048 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2812377397 |
|
|
Oct 15 11:46:38 AM UTC 24 |
Oct 15 11:46:47 AM UTC 24 |
3879775338 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.303794630 |
|
|
Oct 15 11:46:06 AM UTC 24 |
Oct 15 11:46:49 AM UTC 24 |
32190532071 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.657021145 |
|
|
Oct 15 11:46:47 AM UTC 24 |
Oct 15 11:46:50 AM UTC 24 |
109424281 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.1291002598 |
|
|
Oct 15 11:46:47 AM UTC 24 |
Oct 15 11:46:52 AM UTC 24 |
1823726711 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3459218092 |
|
|
Oct 15 11:46:48 AM UTC 24 |
Oct 15 11:46:53 AM UTC 24 |
1910844895 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.113062608 |
|
|
Oct 15 11:46:47 AM UTC 24 |
Oct 15 11:46:53 AM UTC 24 |
2267628977 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3757458743 |
|
|
Oct 15 11:46:50 AM UTC 24 |
Oct 15 11:46:53 AM UTC 24 |
317106446 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_alert_test.2920489176 |
|
|
Oct 15 11:46:51 AM UTC 24 |
Oct 15 11:46:53 AM UTC 24 |
52735142 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_override.1718718087 |
|
|
Oct 15 11:46:53 AM UTC 24 |
Oct 15 11:46:56 AM UTC 24 |
26667253 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.1204622509 |
|
|
Oct 15 11:46:54 AM UTC 24 |
Oct 15 11:46:58 AM UTC 24 |
301798793 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.3862536348 |
|
|
Oct 15 11:42:35 AM UTC 24 |
Oct 15 11:47:01 AM UTC 24 |
22092198781 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.535790587 |
|
|
Oct 15 11:45:50 AM UTC 24 |
Oct 15 11:47:02 AM UTC 24 |
11547860053 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.2797552799 |
|
|
Oct 15 11:46:58 AM UTC 24 |
Oct 15 11:47:06 AM UTC 24 |
279980631 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_perf.341051235 |
|
|
Oct 15 11:44:59 AM UTC 24 |
Oct 15 11:47:10 AM UTC 24 |
4848452874 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.532552473 |
|
|
Oct 15 11:47:08 AM UTC 24 |
Oct 15 11:47:11 AM UTC 24 |
70860861 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.2346729733 |
|
|
Oct 15 11:46:56 AM UTC 24 |
Oct 15 11:47:13 AM UTC 24 |
1105835088 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.382170825 |
|
|
Oct 15 11:47:12 AM UTC 24 |
Oct 15 11:47:16 AM UTC 24 |
168259609 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_perf.780056892 |
|
|
Oct 15 11:47:03 AM UTC 24 |
Oct 15 11:47:17 AM UTC 24 |
709837488 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.1127170118 |
|
|
Oct 15 11:47:20 AM UTC 24 |
Oct 15 11:47:32 AM UTC 24 |
2067961676 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1266962931 |
|
|
Oct 15 11:41:20 AM UTC 24 |
Oct 15 11:47:32 AM UTC 24 |
53941419821 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.859645720 |
|
|
Oct 15 11:42:16 AM UTC 24 |
Oct 15 11:49:35 AM UTC 24 |
15195214756 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.3851597778 |
|
|
Oct 15 11:47:17 AM UTC 24 |
Oct 15 11:47:37 AM UTC 24 |
1506438527 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.2931824646 |
|
|
Oct 15 11:47:15 AM UTC 24 |
Oct 15 11:47:38 AM UTC 24 |
2162856471 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.2654783280 |
|
|
Oct 15 11:47:38 AM UTC 24 |
Oct 15 11:47:40 AM UTC 24 |
713477707 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.3420691188 |
|
|
Oct 15 11:46:52 AM UTC 24 |
Oct 15 11:47:40 AM UTC 24 |
1076881190 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1733551462 |
|
|
Oct 15 11:47:38 AM UTC 24 |
Oct 15 11:47:41 AM UTC 24 |
210706919 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.1259067024 |
|
|
Oct 15 11:42:49 AM UTC 24 |
Oct 15 11:47:44 AM UTC 24 |
10042464740 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.1144828947 |
|
|
Oct 15 11:48:55 AM UTC 24 |
Oct 15 11:49:34 AM UTC 24 |
22512208886 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.3573790318 |
|
|
Oct 15 11:47:42 AM UTC 24 |
Oct 15 11:47:47 AM UTC 24 |
300513377 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3799038940 |
|
|
Oct 15 11:45:12 AM UTC 24 |
Oct 15 11:47:47 AM UTC 24 |
16441600747 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.1804737663 |
|
|
Oct 15 11:47:29 AM UTC 24 |
Oct 15 11:47:48 AM UTC 24 |
11632925471 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.1737363009 |
|
|
Oct 15 11:47:32 AM UTC 24 |
Oct 15 11:47:48 AM UTC 24 |
5640532070 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_perf.3797207263 |
|
|
Oct 15 11:47:39 AM UTC 24 |
Oct 15 11:47:49 AM UTC 24 |
3870507139 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.450129750 |
|
|
Oct 15 11:41:45 AM UTC 24 |
Oct 15 11:47:49 AM UTC 24 |
72542790740 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.3237366684 |
|
|
Oct 15 11:47:11 AM UTC 24 |
Oct 15 11:47:50 AM UTC 24 |
730293054 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.1161789226 |
|
|
Oct 15 11:44:30 AM UTC 24 |
Oct 15 11:47:50 AM UTC 24 |
19809064370 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3505016759 |
|
|
Oct 15 11:47:41 AM UTC 24 |
Oct 15 11:47:51 AM UTC 24 |
2056763468 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.1122251382 |
|
|
Oct 15 11:47:48 AM UTC 24 |
Oct 15 11:47:52 AM UTC 24 |
150766539 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.1686251762 |
|
|
Oct 15 11:47:49 AM UTC 24 |
Oct 15 11:47:53 AM UTC 24 |
2066504746 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.215618716 |
|
|
Oct 15 11:47:48 AM UTC 24 |
Oct 15 11:47:53 AM UTC 24 |
566111615 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.1669036545 |
|
|
Oct 15 11:47:49 AM UTC 24 |
Oct 15 11:47:53 AM UTC 24 |
103770461 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_alert_test.1211168886 |
|
|
Oct 15 11:47:52 AM UTC 24 |
Oct 15 11:47:54 AM UTC 24 |
25451926 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.3328359533 |
|
|
Oct 15 11:47:50 AM UTC 24 |
Oct 15 11:47:54 AM UTC 24 |
465666146 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.4148067461 |
|
|
Oct 15 11:47:51 AM UTC 24 |
Oct 15 11:47:54 AM UTC 24 |
170994443 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.4011131343 |
|
|
Oct 15 11:47:15 AM UTC 24 |
Oct 15 11:47:54 AM UTC 24 |
71600151103 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.161214760 |
|
|
Oct 15 11:47:49 AM UTC 24 |
Oct 15 11:47:55 AM UTC 24 |
1261326865 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_override.2841785572 |
|
|
Oct 15 11:47:53 AM UTC 24 |
Oct 15 11:47:55 AM UTC 24 |
17932007 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.3071461461 |
|
|
Oct 15 11:47:54 AM UTC 24 |
Oct 15 11:47:56 AM UTC 24 |
73156756 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.2658979329 |
|
|
Oct 15 11:47:16 AM UTC 24 |
Oct 15 11:47:57 AM UTC 24 |
1514046001 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.3071687208 |
|
|
Oct 15 11:47:48 AM UTC 24 |
Oct 15 11:47:57 AM UTC 24 |
1282905506 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.587303861 |
|
|
Oct 15 11:47:56 AM UTC 24 |
Oct 15 11:48:00 AM UTC 24 |
162614750 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.310971303 |
|
|
Oct 15 11:47:57 AM UTC 24 |
Oct 15 11:48:01 AM UTC 24 |
279798351 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.4241377181 |
|
|
Oct 15 11:47:55 AM UTC 24 |
Oct 15 11:48:02 AM UTC 24 |
517395909 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.3757235913 |
|
|
Oct 15 11:47:55 AM UTC 24 |
Oct 15 11:48:03 AM UTC 24 |
534036321 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.3007503495 |
|
|
Oct 15 11:46:54 AM UTC 24 |
Oct 15 11:48:12 AM UTC 24 |
5716769943 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.3710110408 |
|
|
Oct 15 11:48:04 AM UTC 24 |
Oct 15 11:48:17 AM UTC 24 |
1132029894 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.282296828 |
|
|
Oct 15 11:47:59 AM UTC 24 |
Oct 15 11:48:18 AM UTC 24 |
1960111137 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.512881533 |
|
|
Oct 15 11:45:52 AM UTC 24 |
Oct 15 11:48:24 AM UTC 24 |
23393205034 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.4294331732 |
|
|
Oct 15 11:48:24 AM UTC 24 |
Oct 15 11:48:27 AM UTC 24 |
179587745 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.3545221917 |
|
|
Oct 15 11:48:25 AM UTC 24 |
Oct 15 11:48:28 AM UTC 24 |
338860024 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_alert_test.1883624538 |
|
|
Oct 15 11:49:44 AM UTC 24 |
Oct 15 11:49:46 AM UTC 24 |
101443760 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3252890085 |
|
|
Oct 15 11:46:53 AM UTC 24 |
Oct 15 11:48:30 AM UTC 24 |
19534833695 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.120200949 |
|
|
Oct 15 11:48:02 AM UTC 24 |
Oct 15 11:48:30 AM UTC 24 |
1217410246 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.1072017156 |
|
|
Oct 15 11:48:18 AM UTC 24 |
Oct 15 11:48:31 AM UTC 24 |
4700058692 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.2287555889 |
|
|
Oct 15 11:49:34 AM UTC 24 |
Oct 15 11:49:37 AM UTC 24 |
620959599 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.1632001287 |
|
|
Oct 15 11:47:52 AM UTC 24 |
Oct 15 11:48:31 AM UTC 24 |
10120598547 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.2994868001 |
|
|
Oct 15 11:48:32 AM UTC 24 |
Oct 15 11:48:35 AM UTC 24 |
74750607 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.2462136989 |
|
|
Oct 15 11:44:56 AM UTC 24 |
Oct 15 11:48:36 AM UTC 24 |
3932356321 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.797835177 |
|
|
Oct 15 11:45:47 AM UTC 24 |
Oct 15 11:48:36 AM UTC 24 |
12588746188 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.713049760 |
|
|
Oct 15 11:49:22 AM UTC 24 |
Oct 15 11:49:36 AM UTC 24 |
10215214867 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.3077936118 |
|
|
Oct 15 11:48:31 AM UTC 24 |
Oct 15 11:48:38 AM UTC 24 |
2359662641 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.2375711784 |
|
|
Oct 15 11:48:36 AM UTC 24 |
Oct 15 11:48:39 AM UTC 24 |
1141715311 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.579583160 |
|
|
Oct 15 11:48:37 AM UTC 24 |
Oct 15 11:48:39 AM UTC 24 |
59487839 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_perf.470095430 |
|
|
Oct 15 11:48:28 AM UTC 24 |
Oct 15 11:48:40 AM UTC 24 |
911117344 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.2224657206 |
|
|
Oct 15 11:48:37 AM UTC 24 |
Oct 15 11:48:40 AM UTC 24 |
61829087 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1780217322 |
|
|
Oct 15 11:49:31 AM UTC 24 |
Oct 15 11:49:34 AM UTC 24 |
225537352 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_perf.299563872 |
|
|
Oct 15 11:47:55 AM UTC 24 |
Oct 15 11:48:40 AM UTC 24 |
5679357334 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.2424190494 |
|
|
Oct 15 11:47:56 AM UTC 24 |
Oct 15 11:48:41 AM UTC 24 |
3263321722 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_alert_test.1833680392 |
|
|
Oct 15 11:48:40 AM UTC 24 |
Oct 15 11:48:43 AM UTC 24 |
24563758 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.4255379177 |
|
|
Oct 15 11:48:38 AM UTC 24 |
Oct 15 11:48:43 AM UTC 24 |
4077334197 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.1409343427 |
|
|
Oct 15 11:48:03 AM UTC 24 |
Oct 15 11:49:33 AM UTC 24 |
4032702838 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.1852944656 |
|
|
Oct 15 11:48:38 AM UTC 24 |
Oct 15 11:48:44 AM UTC 24 |
2127903619 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_override.1798083332 |
|
|
Oct 15 11:48:41 AM UTC 24 |
Oct 15 11:48:44 AM UTC 24 |
95292354 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.536175134 |
|
|
Oct 15 11:48:01 AM UTC 24 |
Oct 15 11:48:46 AM UTC 24 |
20367754042 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.2151120021 |
|
|
Oct 15 11:48:44 AM UTC 24 |
Oct 15 11:48:46 AM UTC 24 |
116790795 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.1327173950 |
|
|
Oct 15 11:48:40 AM UTC 24 |
Oct 15 11:48:47 AM UTC 24 |
548477200 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.2198754248 |
|
|
Oct 15 11:48:45 AM UTC 24 |
Oct 15 11:48:50 AM UTC 24 |
834169711 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.3700038338 |
|
|
Oct 15 11:47:54 AM UTC 24 |
Oct 15 11:48:50 AM UTC 24 |
4610701779 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.2358543358 |
|
|
Oct 15 11:48:33 AM UTC 24 |
Oct 15 11:48:53 AM UTC 24 |
602206713 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.2579324178 |
|
|
Oct 15 11:48:45 AM UTC 24 |
Oct 15 11:48:55 AM UTC 24 |
443326084 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1546875551 |
|
|
Oct 15 11:48:51 AM UTC 24 |
Oct 15 11:48:57 AM UTC 24 |
402007520 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.3750998727 |
|
|
Oct 15 11:47:01 AM UTC 24 |
Oct 15 11:49:09 AM UTC 24 |
13479493359 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.1881859573 |
|
|
Oct 15 11:48:47 AM UTC 24 |
Oct 15 11:49:12 AM UTC 24 |
2002714227 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.1520374696 |
|
|
Oct 15 11:48:54 AM UTC 24 |
Oct 15 11:49:14 AM UTC 24 |
1790896914 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.1592967178 |
|
|
Oct 15 11:48:57 AM UTC 24 |
Oct 15 11:49:21 AM UTC 24 |
1443356006 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.78785080 |
|
|
Oct 15 11:49:13 AM UTC 24 |
Oct 15 11:49:26 AM UTC 24 |
2031680491 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.2819644086 |
|
|
Oct 15 11:48:40 AM UTC 24 |
Oct 15 11:49:28 AM UTC 24 |
4490665900 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.1978816459 |
|
|
Oct 15 11:49:29 AM UTC 24 |
Oct 15 11:49:32 AM UTC 24 |
453973567 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.2713030689 |
|
|
Oct 15 11:51:02 AM UTC 24 |
Oct 15 11:51:36 AM UTC 24 |
11689876195 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_perf.2341741341 |
|
|
Oct 15 11:49:32 AM UTC 24 |
Oct 15 11:49:40 AM UTC 24 |
559426785 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.4187481974 |
|
|
Oct 15 11:49:38 AM UTC 24 |
Oct 15 11:49:41 AM UTC 24 |
1813557943 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.3642873450 |
|
|
Oct 15 11:49:37 AM UTC 24 |
Oct 15 11:49:43 AM UTC 24 |
1762969844 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.3732134307 |
|
|
Oct 15 11:50:56 AM UTC 24 |
Oct 15 11:51:35 AM UTC 24 |
2844426168 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.3198615336 |
|
|
Oct 15 11:49:34 AM UTC 24 |
Oct 15 11:49:43 AM UTC 24 |
1251586539 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.2688490147 |
|
|
Oct 15 11:49:36 AM UTC 24 |
Oct 15 11:49:44 AM UTC 24 |
475668292 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.666142928 |
|
|
Oct 15 11:49:41 AM UTC 24 |
Oct 15 11:49:46 AM UTC 24 |
3898687484 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.4090056223 |
|
|
Oct 15 11:49:42 AM UTC 24 |
Oct 15 11:49:47 AM UTC 24 |
598422338 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.4289421832 |
|
|
Oct 15 11:49:43 AM UTC 24 |
Oct 15 11:49:49 AM UTC 24 |
496729612 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_override.3203238182 |
|
|
Oct 15 11:49:47 AM UTC 24 |
Oct 15 11:49:49 AM UTC 24 |
29647033 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.3166894088 |
|
|
Oct 15 11:49:49 AM UTC 24 |
Oct 15 11:49:51 AM UTC 24 |
83369532 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.1776488140 |
|
|
Oct 15 11:48:29 AM UTC 24 |
Oct 15 11:49:51 AM UTC 24 |
9254092397 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.2512988484 |
|
|
Oct 15 11:45:00 AM UTC 24 |
Oct 15 11:49:52 AM UTC 24 |
23397389395 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.3267997129 |
|
|
Oct 15 11:47:55 AM UTC 24 |
Oct 15 11:49:53 AM UTC 24 |
7154502824 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.3863794130 |
|
|
Oct 15 11:49:53 AM UTC 24 |
Oct 15 11:49:58 AM UTC 24 |
257713738 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.2804627133 |
|
|
Oct 15 11:49:51 AM UTC 24 |
Oct 15 11:50:04 AM UTC 24 |
316169096 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.3814781491 |
|
|
Oct 15 11:49:50 AM UTC 24 |
Oct 15 11:50:06 AM UTC 24 |
1255898109 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1676275082 |
|
|
Oct 15 11:49:54 AM UTC 24 |
Oct 15 11:50:06 AM UTC 24 |
1244443475 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3441614368 |
|
|
Oct 15 11:49:58 AM UTC 24 |
Oct 15 11:50:07 AM UTC 24 |
623026669 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.718225669 |
|
|
Oct 15 11:41:57 AM UTC 24 |
Oct 15 11:50:10 AM UTC 24 |
38278932593 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2405253948 |
|
|
Oct 15 11:48:45 AM UTC 24 |
Oct 15 11:50:21 AM UTC 24 |
12190287555 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.2326453249 |
|
|
Oct 15 11:50:07 AM UTC 24 |
Oct 15 11:50:24 AM UTC 24 |
699726017 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.909795166 |
|
|
Oct 15 11:50:11 AM UTC 24 |
Oct 15 11:50:25 AM UTC 24 |
1499932908 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.1121342066 |
|
|
Oct 15 11:46:23 AM UTC 24 |
Oct 15 11:50:32 AM UTC 24 |
15446084306 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_perf.2107314295 |
|
|
Oct 15 11:49:52 AM UTC 24 |
Oct 15 11:50:33 AM UTC 24 |
52264456594 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_perf.3240625968 |
|
|
Oct 15 11:42:15 AM UTC 24 |
Oct 15 11:50:34 AM UTC 24 |
12563421258 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.3553720062 |
|
|
Oct 15 11:50:22 AM UTC 24 |
Oct 15 11:50:35 AM UTC 24 |
1951315946 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.818183539 |
|
|
Oct 15 11:50:34 AM UTC 24 |
Oct 15 11:50:38 AM UTC 24 |
384201765 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3495031165 |
|
|
Oct 15 11:47:41 AM UTC 24 |
Oct 15 11:50:38 AM UTC 24 |
34101049465 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.3547271832 |
|
|
Oct 15 11:50:35 AM UTC 24 |
Oct 15 11:50:39 AM UTC 24 |
361937572 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.1003915200 |
|
|
Oct 15 11:50:27 AM UTC 24 |
Oct 15 11:50:40 AM UTC 24 |
1164195524 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_perf.2304394659 |
|
|
Oct 15 11:50:36 AM UTC 24 |
Oct 15 11:50:42 AM UTC 24 |
494655119 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_mode_toggle.1383235162 |
|
|
Oct 15 11:50:39 AM UTC 24 |
Oct 15 11:50:43 AM UTC 24 |
787837771 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.2737574112 |
|
|
Oct 15 11:50:39 AM UTC 24 |
Oct 15 11:50:44 AM UTC 24 |
1405640755 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.3350004554 |
|
|
Oct 15 11:44:41 AM UTC 24 |
Oct 15 11:50:45 AM UTC 24 |
46882702084 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.1426755128 |
|
|
Oct 15 11:50:44 AM UTC 24 |
Oct 15 11:50:46 AM UTC 24 |
183137155 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.3275253582 |
|
|
Oct 15 11:49:11 AM UTC 24 |
Oct 15 11:50:46 AM UTC 24 |
2026945387 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.24673457 |
|
|
Oct 15 11:50:39 AM UTC 24 |
Oct 15 11:50:46 AM UTC 24 |
3553011015 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.334192247 |
|
|
Oct 15 11:50:43 AM UTC 24 |
Oct 15 11:50:46 AM UTC 24 |
543442713 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_alert_test.1893388754 |
|
|
Oct 15 11:50:48 AM UTC 24 |
Oct 15 11:50:50 AM UTC 24 |
22975500 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.1704519326 |
|
|
Oct 15 11:50:08 AM UTC 24 |
Oct 15 11:50:50 AM UTC 24 |
3965151511 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.3205900594 |
|
|
Oct 15 11:42:54 AM UTC 24 |
Oct 15 11:50:50 AM UTC 24 |
56660648280 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.3734666093 |
|
|
Oct 15 11:50:46 AM UTC 24 |
Oct 15 11:50:51 AM UTC 24 |
1875719501 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.2773413948 |
|
|
Oct 15 11:50:47 AM UTC 24 |
Oct 15 11:50:53 AM UTC 24 |
1780056529 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_override.1020132098 |
|
|
Oct 15 11:50:51 AM UTC 24 |
Oct 15 11:50:53 AM UTC 24 |
26798478 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.376070202 |
|
|
Oct 15 11:50:47 AM UTC 24 |
Oct 15 11:50:53 AM UTC 24 |
584840429 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.3976548431 |
|
|
Oct 15 11:50:45 AM UTC 24 |
Oct 15 11:50:54 AM UTC 24 |
326539168 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.2833245222 |
|
|
Oct 15 11:49:47 AM UTC 24 |
Oct 15 11:50:55 AM UTC 24 |
2039345933 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.3321009036 |
|
|
Oct 15 11:50:52 AM UTC 24 |
Oct 15 11:50:55 AM UTC 24 |
109042168 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3768525672 |
|
|
Oct 15 11:49:44 AM UTC 24 |
Oct 15 11:50:57 AM UTC 24 |
6594226127 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.1681827126 |
|
|
Oct 15 11:50:54 AM UTC 24 |
Oct 15 11:51:00 AM UTC 24 |
1460827395 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.3756757833 |
|
|
Oct 15 11:50:25 AM UTC 24 |
Oct 15 11:51:01 AM UTC 24 |
16765426732 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.4136213374 |
|
|
Oct 15 11:49:47 AM UTC 24 |
Oct 15 11:51:01 AM UTC 24 |
13928868156 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1224822204 |
|
|
Oct 15 11:50:58 AM UTC 24 |
Oct 15 11:51:02 AM UTC 24 |
216746142 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.3943980105 |
|
|
Oct 15 11:50:40 AM UTC 24 |
Oct 15 11:51:04 AM UTC 24 |
590822301 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.4012496011 |
|
|
Oct 15 11:49:15 AM UTC 24 |
Oct 15 11:51:06 AM UTC 24 |
20356502616 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.1147822550 |
|
|
Oct 15 11:49:52 AM UTC 24 |
Oct 15 11:51:06 AM UTC 24 |
13371304590 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.794330489 |
|
|
Oct 15 11:51:05 AM UTC 24 |
Oct 15 11:51:14 AM UTC 24 |
3094130827 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.2734261632 |
|
|
Oct 15 11:51:06 AM UTC 24 |
Oct 15 11:51:15 AM UTC 24 |
2146814276 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.806627399 |
|
|
Oct 15 11:48:44 AM UTC 24 |
Oct 15 11:51:17 AM UTC 24 |
9162389084 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.949053573 |
|
|
Oct 15 11:50:53 AM UTC 24 |
Oct 15 11:51:18 AM UTC 24 |
2517730326 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.3052046448 |
|
|
Oct 15 11:50:56 AM UTC 24 |
Oct 15 11:51:19 AM UTC 24 |
6037622896 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_override.3200638830 |
|
|
Oct 15 11:51:34 AM UTC 24 |
Oct 15 11:51:36 AM UTC 24 |
29469130 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.4056018740 |
|
|
Oct 15 11:51:02 AM UTC 24 |
Oct 15 11:51:19 AM UTC 24 |
4047209960 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.2721801878 |
|
|
Oct 15 11:50:36 AM UTC 24 |
Oct 15 11:51:20 AM UTC 24 |
20456562186 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.988095955 |
|
|
Oct 15 11:51:18 AM UTC 24 |
Oct 15 11:51:22 AM UTC 24 |
313913886 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.2368671512 |
|
|
Oct 15 11:51:19 AM UTC 24 |
Oct 15 11:51:23 AM UTC 24 |
685521795 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.4033787940 |
|
|
Oct 15 11:51:20 AM UTC 24 |
Oct 15 11:51:26 AM UTC 24 |
861196233 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_perf.2102040591 |
|
|
Oct 15 11:43:32 AM UTC 24 |
Oct 15 11:51:26 AM UTC 24 |
7746000770 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.1333215971 |
|
|
Oct 15 11:51:16 AM UTC 24 |
Oct 15 11:51:28 AM UTC 24 |
4922100288 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.821474145 |
|
|
Oct 15 11:51:26 AM UTC 24 |
Oct 15 11:51:30 AM UTC 24 |
153134607 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_perf.3914163456 |
|
|
Oct 15 11:51:20 AM UTC 24 |
Oct 15 11:51:30 AM UTC 24 |
784629225 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.2589079342 |
|
|
Oct 15 11:51:23 AM UTC 24 |
Oct 15 11:51:30 AM UTC 24 |
1340214502 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.780374899 |
|
|
Oct 15 11:41:20 AM UTC 24 |
Oct 15 11:51:30 AM UTC 24 |
17089088998 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.4046030051 |
|
|
Oct 15 11:50:51 AM UTC 24 |
Oct 15 11:51:32 AM UTC 24 |
3984451075 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.3824467604 |
|
|
Oct 15 11:51:26 AM UTC 24 |
Oct 15 11:51:33 AM UTC 24 |
540402594 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_alert_test.760318781 |
|
|
Oct 15 11:51:32 AM UTC 24 |
Oct 15 11:51:34 AM UTC 24 |
16592970 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.2456145222 |
|
|
Oct 15 11:51:27 AM UTC 24 |
Oct 15 11:51:34 AM UTC 24 |
141135876 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.154956963 |
|
|
Oct 15 11:51:32 AM UTC 24 |
Oct 15 11:51:35 AM UTC 24 |
505987491 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_stress_all.997631814 |
|
|
Oct 15 11:47:14 AM UTC 24 |
Oct 15 11:51:37 AM UTC 24 |
8942416407 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.1435828176 |
|
|
Oct 15 11:51:29 AM UTC 24 |
Oct 15 11:51:35 AM UTC 24 |
494981943 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.878481453 |
|
|
Oct 15 11:51:31 AM UTC 24 |
Oct 15 11:51:36 AM UTC 24 |
864707235 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.1195812116 |
|
|
Oct 15 11:51:31 AM UTC 24 |
Oct 15 11:51:37 AM UTC 24 |
1219878292 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.3685704244 |
|
|
Oct 15 11:48:13 AM UTC 24 |
Oct 15 11:51:38 AM UTC 24 |
25270181655 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.3641148981 |
|
|
Oct 15 11:51:36 AM UTC 24 |
Oct 15 11:51:38 AM UTC 24 |
296638876 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.1720380239 |
|
|
Oct 15 11:43:57 AM UTC 24 |
Oct 15 11:51:39 AM UTC 24 |
41795545408 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.2570813342 |
|
|
Oct 15 11:51:37 AM UTC 24 |
Oct 15 11:51:41 AM UTC 24 |
63873578 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.3158034071 |
|
|
Oct 15 11:50:51 AM UTC 24 |
Oct 15 11:51:46 AM UTC 24 |
1739072225 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.1662242226 |
|
|
Oct 15 11:51:36 AM UTC 24 |
Oct 15 11:51:47 AM UTC 24 |
279498136 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.3087651533 |
|
|
Oct 15 11:51:37 AM UTC 24 |
Oct 15 11:51:50 AM UTC 24 |
2123971042 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_perf.3359772284 |
|
|
Oct 15 11:51:37 AM UTC 24 |
Oct 15 11:51:50 AM UTC 24 |
3368713134 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.4072138920 |
|
|
Oct 15 11:51:39 AM UTC 24 |
Oct 15 11:51:51 AM UTC 24 |
199942438 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.3253792949 |
|
|
Oct 15 11:45:29 AM UTC 24 |
Oct 15 11:51:51 AM UTC 24 |
104698732480 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.2702655395 |
|
|
Oct 15 11:50:55 AM UTC 24 |
Oct 15 11:51:54 AM UTC 24 |
2078087585 ps |