I2C Simulation Results

Wednesday August 05 2020 02:00:07AM UTC

Revision: d1235737 on master

Testplan

Simulator: XCELIUM

Milestone Name Tests Passing Total Pass Rate
V1 sanity i2c_sanity 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 50 50 100.00
V1 csr_rw i2c_csr_rw 50 50 100.00
V1 csr_bit_bash i2c_csr_bit_bash 50 50 100.00
V1 csr_aliasing i2c_csr_aliasing 50 50 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 50 50 100.00
V1 TOTAL 300 300 100.00
V2 error i2c_error 0 0 --
V2 stress_all_with_reset i2c_stress_all_with_rand_reset 0 0 --
V2 perf i2c_perf 10 10 100.00
V2 stress i2c_stress 0 0 --
V2 override i2c_override 50 50 100.00
V2 fifo_watermark i2c_fifo_watermark 50 50 100.00
V2 fifo_overflow i2c_fifo_overflow 50 50 100.00
V2 fmt_reset fmt_reset 0 0 --
V2 rx_reset rx_reset 0 0 --
V2 fifo_full i2c_fifo_full 50 50 100.00
V2 stretch_timeout, i2c_stretch_timeout 50 50 100.00
V2 rx_oversample rx_oversample 0 0 --
V2 rw_loopback rw_loopback 0 0 --
V2 intr_test i2c_intr_test 50 50 100.00
V2 oob_addr_access i2c_tl_errors 20 20 100.00
V2 illegal_access i2c_tl_errors 20 20 100.00
V2 outstanding_access i2c_csr_hw_reset 50 50 100.00
i2c_csr_rw 50 50 100.00
i2c_csr_aliasing 50 50 100.00
i2c_same_csr_outstanding 50 50 100.00
V2 partial_access i2c_csr_hw_reset 50 50 100.00
i2c_csr_rw 50 50 100.00
i2c_csr_aliasing 50 50 100.00
V2 TOTAL 700 700 100.00
TOTAL 1000 1000 100.00

Coverage Results

Coverage Dashboard

Score Block Expression Toggle Statement Fsm Assertion CoverGroup
68.95 97.56 90.62 64.40 -- 96.67 83.80 16.67

Past Results