I2C Lint Results
Sunday April 28 2024 19:02:25 UTC
Branch: os_regression
Tool: VERILATOR
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
0 |
0 |
2 |
0 |
53 |
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Messages for Build Mode 'default'
Flow Errors
ERROR: %Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:136:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
ERROR: Failed to build lowrisc:ip:i2c:0.1 : '['make', 'Vi2c.mk']' exited with an error: 2
Lint Warnings
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:136:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:338:44: Operator SUB expects 32 bits on the RHS, but RHS's VARREF 'acq_fifo_depth_i' generates 9 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:338:29: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:479:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:564:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:760:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:799:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:850:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:898:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:925:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:945:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:988:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:1011:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:121:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:121:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:122:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:122:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:46: Operator SUB expects 16 bits on the LHS, but LHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:46: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thigh_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:59: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:129:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:129:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sto_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 't_buf_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:60: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'tsu_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:343:35: Operator ADD expects 17 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:489:41: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:634:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:643:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:651:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:660:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:678:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:687:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:703:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:716:24: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:725:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:739:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:751:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:760:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:777:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:790:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:799:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:821:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:829:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:839:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv:234:36: Signal unoptimizable: Feedback to clock or circular logic: 'i2c.i2c_core.u_fifos.ram_arb_gnt'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv:98:28: Signal unoptimizable: Feedback to clock or circular logic: 'i2c.i2c_core.u_fifos.u_rx_fifo_sram_adapter.oup_buf_wvalid'
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