I2C Lint Results
Saturday July 20 2024 23:02:34 UTC
Branch: os_regression
Tool: VERILATOR
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
0 |
0 |
2 |
0 |
49 |
0 |
Messages for Build Mode 'default'
Flow Errors
ERROR: %Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:133:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
ERROR: Failed to build lowrisc:ip:i2c:0.1 : '['make', 'Vi2c.mk']' exited with an error: 2
Lint Warnings
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:133:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:267:44: Operator SUB expects 32 bits on the RHS, but RHS's VARREF 'acq_fifo_depth_i' generates 9 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:267:29: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:416:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:508:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:718:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:757:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:808:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:856:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:883:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:903:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:946:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:969:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:124:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:125:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_sta_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:46: Operator SUB expects 16 bits on the LHS, but LHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:127:46: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:128:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thigh_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:130:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_f_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tlow_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:131:59: Operator SUB expects 16 bits on the RHS, but RHS's VARREF 'thd_dat_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:132:45: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 't_r_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:132:45: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'tsu_sto_i' generates 13 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:393:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:489:41: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:671:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:679:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:687:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:695:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:715:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:725:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:740:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:756:24: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:765:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:779:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:794:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:803:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:819:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:834:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:842:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:863:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-WIDTH: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv:878:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv:234:36: Signal unoptimizable: Feedback to clock or circular logic: 'i2c.i2c_core.u_fifos.ram_arb_gnt'
%Warning-UNOPTFLAT: ../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv:98:28: Signal unoptimizable: Feedback to clock or circular logic: 'i2c.i2c_core.u_fifos.u_rx_fifo_sram_adapter.oup_buf_wvalid'
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