KEYMGR Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 47.900s 1.925ms 50 50 100.00
V1 random keymgr_random 1.769m 13.813ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.380s 103.180us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.580s 57.142us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 15.760s 1.081ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 10.720s 504.510us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.920s 192.937us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.580s 57.142us 20 20 100.00
keymgr_csr_aliasing 10.720s 504.510us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 1.290m 2.121ms 50 50 100.00
V2 sideload keymgr_sideload 49.930s 5.222ms 50 50 100.00
keymgr_sideload_kmac 1.064m 2.124ms 50 50 100.00
keymgr_sideload_aes 1.402m 8.681ms 50 50 100.00
keymgr_sideload_otbn 27.860s 1.520ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 35.780s 14.179ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 38.560s 1.407ms 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.232m 5.343ms 45 50 90.00
V2 invalid_sw_input keymgr_sw_invalid_input 33.850s 5.446ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.311m 4.716ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 26.720s 1.043ms 49 50 98.00
V2 stress_all keymgr_stress_all 10.117m 19.924ms 50 50 100.00
V2 intr_test keymgr_intr_test 0.880s 60.184us 50 50 100.00
V2 alert_test keymgr_alert_test 0.990s 16.554us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 5.480s 771.522us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 5.480s 771.522us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.380s 103.180us 5 5 100.00
keymgr_csr_rw 1.580s 57.142us 20 20 100.00
keymgr_csr_aliasing 10.720s 504.510us 5 5 100.00
keymgr_same_csr_outstanding 4.100s 116.909us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.380s 103.180us 5 5 100.00
keymgr_csr_rw 1.580s 57.142us 20 20 100.00
keymgr_csr_aliasing 10.720s 504.510us 5 5 100.00
keymgr_same_csr_outstanding 4.100s 116.909us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S sec_cm_additional_check keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
keymgr_tl_intg_err 29.490s 16.871ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 19.760s 3.424ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 19.760s 3.424ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 19.760s 3.424ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 19.760s 3.424ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 15.570s 430.634us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 29.490s 16.871ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 19.760s 3.424ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.290m 2.121ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.769m 13.813ms 50 50 100.00
keymgr_csr_rw 1.580s 57.142us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.769m 13.813ms 50 50 100.00
keymgr_csr_rw 1.580s 57.142us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.769m 13.813ms 50 50 100.00
keymgr_csr_rw 1.580s 57.142us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 38.560s 1.407ms 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.311m 4.716ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.311m 4.716ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.769m 13.813ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 25.530s 4.681ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 26.380s 2.759ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 38.560s 1.407ms 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 26.380s 2.759ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 26.380s 2.759ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 26.380s 2.759ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 33.390s 1.606ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 26.380s 2.759ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 15.380s 1.240ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 1098 1110 98.92

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 14 87.50
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.82 99.09 98.21 98.39 100.00 99.08 98.38 91.56

Failure Buckets

Past Results