KEYMGR Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 32.650s 1.532ms 50 50 100.00
V1 random keymgr_random 51.920s 8.383ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.360s 30.072us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.630s 113.170us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 21.310s 2.231ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 17.260s 2.058ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.020s 90.008us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.630s 113.170us 20 20 100.00
keymgr_csr_aliasing 17.260s 2.058ms 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.074m 9.436ms 50 50 100.00
V2 sideload keymgr_sideload 1.160m 1.937ms 50 50 100.00
keymgr_sideload_kmac 48.210s 2.123ms 50 50 100.00
keymgr_sideload_aes 46.890s 1.773ms 50 50 100.00
keymgr_sideload_otbn 40.450s 15.274ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 24.500s 11.762ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 10.110s 789.328us 48 50 96.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.111m 15.362ms 45 50 90.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.671m 8.231ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.738m 16.552ms 49 50 98.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 15.190s 518.230us 50 50 100.00
V2 stress_all keymgr_stress_all 4.017m 7.877ms 48 50 96.00
V2 intr_test keymgr_intr_test 0.970s 19.680us 50 50 100.00
V2 alert_test keymgr_alert_test 1.040s 34.060us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.400s 125.509us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.400s 125.509us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.360s 30.072us 5 5 100.00
keymgr_csr_rw 1.630s 113.170us 20 20 100.00
keymgr_csr_aliasing 17.260s 2.058ms 5 5 100.00
keymgr_same_csr_outstanding 4.190s 231.309us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.360s 30.072us 5 5 100.00
keymgr_csr_rw 1.630s 113.170us 20 20 100.00
keymgr_csr_aliasing 17.260s 2.058ms 5 5 100.00
keymgr_same_csr_outstanding 4.190s 231.309us 20 20 100.00
V2 TOTAL 730 740 98.65
V2S sec_cm_additional_check keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
keymgr_tl_intg_err 11.710s 394.695us 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 27.230s 6.776ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 27.230s 6.776ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 27.230s 6.776ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 27.230s 6.776ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 19.040s 515.040us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 11.710s 394.695us 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 27.230s 6.776ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.074m 9.436ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 51.920s 8.383ms 50 50 100.00
keymgr_csr_rw 1.630s 113.170us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 51.920s 8.383ms 50 50 100.00
keymgr_csr_rw 1.630s 113.170us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 51.920s 8.383ms 50 50 100.00
keymgr_csr_rw 1.630s 113.170us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 10.110s 789.328us 48 50 96.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.738m 16.552ms 49 50 98.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.738m 16.552ms 49 50 98.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 51.920s 8.383ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 16.500s 4.595ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.381m 2.049ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 10.110s 789.328us 48 50 96.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.381m 2.049ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.381m 2.049ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.381m 2.049ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 35.590s 3.944ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.381m 2.049ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 16.360s 244.240us 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 1096 1110 98.74

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 12 75.00
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.77 99.09 98.17 98.10 100.00 99.08 98.38 91.58

Failure Buckets

Past Results