KEYMGR Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	42.010s	2.363ms	50	50	100.00
V1	random	keymgr_random	35.600s	4.276ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.190s	15.908us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.440s	92.965us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	30.820s	7.151ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.160s	127.517us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.480s	380.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.440s	92.965us	20	20	100.00
		keymgr_csr_aliasing	7.160s	127.517us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.381m	3.234ms	49	50	98.00
V2	sideload	keymgr_sideload	32.930s	2.744ms	50	50	100.00
		keymgr_sideload_kmac	56.000s	6.369ms	50	50	100.00
		keymgr_sideload_aes	1.044m	8.861ms	50	50	100.00
		keymgr_sideload_otbn	55.930s	6.505ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	39.450s	3.443ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	1.201m	4.959ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.216m	23.555ms	46	50	92.00
V2	invalid_sw_input	keymgr_sw_invalid_input	42.800s	4.327ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.104m	9.722ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	21.770s	3.353ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.806m	35.207ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.890s	15.310us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.120s	90.544us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.700s	580.515us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.700s	580.515us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.190s	15.908us	5	5	100.00
		keymgr_csr_rw	1.440s	92.965us	20	20	100.00
		keymgr_csr_aliasing	7.160s	127.517us	5	5	100.00
		keymgr_same_csr_outstanding	3.500s	113.375us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.190s	15.908us	5	5	100.00
		keymgr_csr_rw	1.440s	92.965us	20	20	100.00
		keymgr_csr_aliasing	7.160s	127.517us	5	5	100.00
		keymgr_same_csr_outstanding	3.500s	113.375us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	sec_cm_additional_check	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
		keymgr_tl_intg_err	45.650s	4.796ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	51.220s	2.578ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	51.220s	2.578ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	51.220s	2.578ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	51.220s	2.578ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	18.130s	2.009ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	45.650s	4.796ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	51.220s	2.578ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.381m	3.234ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	35.600s	4.276ms	50	50	100.00
		keymgr_csr_rw	1.440s	92.965us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	35.600s	4.276ms	50	50	100.00
		keymgr_csr_rw	1.440s	92.965us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	35.600s	4.276ms	50	50	100.00
		keymgr_csr_rw	1.440s	92.965us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.201m	4.959ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.104m	9.722ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.104m	9.722ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	35.600s	4.276ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	30.380s	4.165ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	46.140s	3.444ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.201m	4.959ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	46.140s	3.444ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	46.140s	3.444ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	46.140s	3.444ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	51.060s	17.731ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	46.140s	3.444ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.870s	1.430ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1094	1110	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.85	99.09	98.13	98.58	100.00	99.08	98.38	91.66

Failure Buckets

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 6 failures:

Test keymgr_stress_all has 1 failures.

6.keymgr_stress_all.2506962037
Line 1669, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 535677365 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 535677365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 5 failures.

8.keymgr_stress_all_with_rand_reset.1343434629
Line 1067, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 183800813 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 183800813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.keymgr_stress_all_with_rand_reset.1176423152
Line 839, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 310836190 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 310836190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_kmac_rsp_err has 1 failures.

25.keymgr_kmac_rsp_err.3022656898
Line 739, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 583142741 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 583142741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

37.keymgr_lc_disable.2824270849
Line 290, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  81942751 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  81942751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

42.keymgr_stress_all.12188290
Line 525, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 342551956 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 342551956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.keymgr_stress_all.2675945792
Line 2809, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1448356651 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 1448356651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1012) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 3 failures:

Test keymgr_kmac_rsp_err has 3 failures.

28.keymgr_kmac_rsp_err.2455432370
Line 251, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  17285640 ps: (keymgr_scoreboard.sv:1012) [uvm_test_top.env.scoreboard] Check failed act != exp (13869088684237589750254652523805745455607483863801036890679746459828093165537791491588571856622399023237062105618617026565482111249848026196070403725767172517264109158653608084529711787476928653895065151144545054044724683359892261722165281617097594405080313023185422630061514654493928509930176321983960780647599776589687321065927407487447623040344 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f950f48b231d1cc19f260cb3db5526faddb4438adc75878b72d3572726bb51d4774eb35655ade3fa5247960185f8bec5ec879c32348ecc8d697fd538086625999d1fec91ff5b34a9f3db8cac99bb60be80c394c6bcbacdf199ce0e2f5e1fc3edec5c02973a1734eeacb9d5531418bc7d58] vs 13869088684237589750254652523805745455607483863801036890679746459828093165537791491588571856622399023237062105618617026565482111249848026196070403725767172517264109158653608084529711787476928653895065151144545054044724683359892261722165281617097594405080313023185422630061514654493928509930176321983960780647599776589687321065927407487447623040344 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f950f48b231d1cc19f260cb3db5526faddb4438adc75878b72d3572726bb51d4774eb35655ade3fa5247960185f8bec5ec879c32348ecc8d697fd538086625999d1fec91ff5b34a9f3db8cac99bb60be80c394c6bcbacdf199ce0e2f5e1fc3edec5c02973a1734eeacb9d5531418bc7d58]) cdi_type: Attestation
  
   DiversificationKey act: 0xc394c6bcbacdf199ce0e2f5e1fc3edec5c02973a1734eeacb9d5531418bc7d58, exp: 0xc394c6bcbacdf199ce0e2f5e1fc3edec5c02973a1734eeacb9d5531418bc7d58
   RomDigest act: 0x879c32348ecc8d697fd538086625999d1fec91ff5b34a9f3db8cac99bb60be80, exp: 0x879c32348ecc8d697fd538086625999d1fec91ff5b34a9f3db8cac99bb60be80
   HealthMeasurement act: 0x4eb35655ade3fa5247960185f8bec5ec, exp: 0x4eb35655ade3fa5247960185f8bec5ec

33.keymgr_kmac_rsp_err.2677508716
Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  20338480 ps: (keymgr_scoreboard.sv:1012) [uvm_test_top.env.scoreboard] Check failed act != exp (5097843121459657985394740158001280628831944861539553440346093197639634094324788409328383116127404705577373218040594560942866513941141788344583466677332577047651468518747453299434029095245796632120757941077452834519860866515019697110320683368534512492906053816204792769331665097650567665944890813779535497843762000250213469172311891139975584362794020865674216389185639980438368935064749326736008682017077838168547203178155663 [0xb83e601388bf14bbc9e65a90348984396833dbc02c1cd7241cc1b945c66d240a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f960cc83afcf6880ddd830c1d7b8889420824d17535d4825fb8523a28a59c46529fc3cf95ea0aeae39f3bf0e0f7a98bddb1e6f70f4a63c66d1328c7c1c7e1d44142a0b4d9e0a6652be6974978f326e939cb82ee1481f556b3334d77304bc2a909b210915f6737497feb26e8e5f75c9ce8f] vs 5097843121459657985394740158001280628831944861539553440346093197639634094324788409328383116127404705577373218040594560942866513941141788344583466677332577047651468518747453299434029095245796632120757941077452834519860866515019697110320683368534512492906053816204792769331665097650567665944890813779535497843762000250213469172311891139975584362794020865674216389185639980438368935064749326736008682017077838168547203178155663 [0xb83e601388bf14bbc9e65a90348984396833dbc02c1cd7241cc1b945c66d240a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f960cc83afcf6880ddd830c1d7b8889420824d17535d4825fb8523a28a59c46529fc3cf95ea0aeae39f3bf0e0f7a98bddb1e6f70f4a63c66d1328c7c1c7e1d44142a0b4d9e0a6652be6974978f326e939cb82ee1481f556b3334d77304bc2a909b210915f6737497feb26e8e5f75c9ce8f]) cdi_type: Attestation
  
   DiversificationKey act: 0xb82ee1481f556b3334d77304bc2a909b210915f6737497feb26e8e5f75c9ce8f, exp: 0xb82ee1481f556b3334d77304bc2a909b210915f6737497feb26e8e5f75c9ce8f
   RomDigest act: 0x1e6f70f4a63c66d1328c7c1c7e1d44142a0b4d9e0a6652be6974978f326e939c, exp: 0x1e6f70f4a63c66d1328c7c1c7e1d44142a0b4d9e0a6652be6974978f326e939c
   HealthMeasurement act: 0xfc3cf95ea0aeae39f3bf0e0f7a98bddb, exp: 0xfc3cf95ea0aeae39f3bf0e0f7a98bddb

... and 1 more failures.

UVM_FATAL (keymgr_if.sv:368) [keymgr_if] timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 30.keymgr_custom_cm.3869883239
    Line 310, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 229859887 ps: (keymgr_if.sv:368) [keymgr_if] timeout occurred!
  UVM_INFO @ 229859887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 35.keymgr_cfg_regwen.4080526114
    Line 338, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  14949927 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @  14949927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:671) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 45.keymgr_stress_all_with_rand_reset.1444337190
    Line 838, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 215486755 ps: (keymgr_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (4 [0x4] vs 2 [0x2])
  UVM_INFO @ 215486755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```