Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11248

1

T1

4

T2

19

T3

15

auto[Attestation]

7860

1

T1

7

T2

2

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2930	1			T1	1		T2	5		T3	2
auto[Aes]	3393	1			T1	1		T2	2		T3	5
auto[Kmac]	3503	1			T1	1		T2	3		T3	2
auto[Otbn]	3399	1			T1	3		T2	3		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7638	1			T1	8		T2	2		T3	8
auto[OpGenId]	5883	1			T1	5		T2	8		T3	9
auto[OpGenSwOut]	6084	1			T1	4		T2	6		T3	4
auto[OpGenHwOut]	7141	1			T1	2		T2	7		T3	6
auto[OpDisable]	132	1			T2	1		T39	2		T40	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9882

1

T1

1

T2

2

T3

8

auto[OpDoneFail]

16996

1

T1

18

T2

22

T3

19

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6469	1			T1	1		T2	16		T3	12
auto[StInit]	4363	1			T1	18		T2	3		T3	2
auto[StCreatorRootKey]	2896	1			T3	2		T13	5		T14	4
auto[StOwnerIntKey]	2600	1			T3	2		T13	3		T14	4
auto[StOwnerKey]	2248	1			T3	2		T14	2		T15	2
auto[StDisabled]	7307	1			T2	5		T3	7		T15	7
auto[StInvalid]	995	1			T36	20		T102	15		T98	24

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	354	1			T2	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T16	1		T7	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	96	1			T13	2		T24	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T80	1		T187	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T58	1		T24	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	215	1			T24	1		T39	3		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T188	1		T189	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	327	1			T2	1		T3	1		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T24	1		T39	2		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	69	1			T3	1		T53	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T13	1		T53	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	53	1			T191	1		T70	2		T73	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	188	1			T39	1		T70	2		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	23	1			T36	1		T98	1		T88	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	310	1			T2	2		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	138	1			T3	1		T39	2		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T13	1		T39	2		T193	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T24	1		T187	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T18	1		T192	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	209	1			T58	1		T24	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	29	1			T194	2		T195	2		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	300	1			T2	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T1	2		T19	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T16	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T18	1		T181	1		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	45	1			T40	1		T196	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T16	1		T58	2		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T102	1		T197	1		T198	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	100	1			T39	2		T4	1		T51	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	131	1			T1	1		T7	1		T39	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	60	1			T13	1		T39	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T40	2		T200	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T16	1		T114	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T2	1		T80	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T36	1		T88	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	101	1			T39	1		T51	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T1	1		T14	1		T131	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T39	1		T193	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	67	1			T16	1		T53	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	46	1			T58	1		T70	1		T202	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	200	1			T16	1		T39	5		T75	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	36	1			T201	1		T195	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T4	2		T51	2		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T39	1		T77	1		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T39	1		T70	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T24	1		T39	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T39	1		T70	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	190	1			T80	1		T24	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	29	1			T98	1		T197	2		T195	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	92	1			T4	1		T51	3		T5	7
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T7	1		T131	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T16	1		T19	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	51	1			T39	1		T75	1		T40	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	50	1			T39	1		T40	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	222	1			T191	1		T39	3		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	16	1			T36	1		T98	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	311	1			T2	3		T3	2		T18	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	117	1			T16	1		T103	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T14	1		T17	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T40	1		T203	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T14	1		T39	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	160	1			T58	1		T40	3		T145	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T102	1		T98	2		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	412	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T16	1		T78	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T18	1		T78	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	83	1			T204	1		T200	1		T205	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T18	1		T78	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	297	1			T2	1		T16	3		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T102	1		T194	2		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	492	1			T2	1		T16	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	136	1			T13	1		T16	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T16	1		T18	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T13	1		T71	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T58	1		T73	1		T40	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	286	1			T24	1		T39	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T98	1		T88	1		T201	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	410	1			T2	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T16	2		T17	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T14	2		T17	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T17	1		T79	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T15	1		T16	1		T79	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T102	1		T98	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T39	1		T51	1		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T17	1		T39	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T40	1		T202	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T39	1		T40	1		T4	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T202	1		T205	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T16	1		T24	2		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T88	2		T194	3		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T39	1		T4	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	131	1			T16	1		T17	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T14	1		T131	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T3	1		T78	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T39	2		T40	2		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	257	1			T3	1		T16	1		T78	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	36	1			T102	1		T98	2		T88	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T39	2		T51	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	154	1			T1	1		T74	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T131	1		T39	2		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T14	1		T16	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	71	1			T71	1		T74	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	256	1			T16	1		T58	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T98	2		T194	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	69	1			T39	3		T4	2		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T206	1		T181	1		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T15	1		T131	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T15	1		T79	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	255	1			T2	1		T15	3		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	40	1			T36	1		T102	1		T88	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	202	1			T13	2		T80	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	735	1			T2	1		T14	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	181	1			T3	1		T13	1		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	674	1			T2	1		T3	1		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	195	1			T13	1		T18	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	705	1			T2	2		T3	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	174	1			T16	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	696	1			T1	2		T2	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T13	1		T39	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	447	1			T1	1		T2	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	180	1			T16	1		T53	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	466	1			T1	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	203	1			T24	1		T39	3		T70	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	420	1			T80	1		T24	1		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	171	1			T16	1		T19	1		T39	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	456	1			T7	1		T131	1		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T14	2		T17	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	627	1			T2	3		T3	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	257	1			T18	2		T78	2		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	873	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	256	1			T13	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	964	1			T2	1		T13	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T14	2		T16	2		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	843	1			T1	1		T2	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	168	1			T39	1		T40	2		T4	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	388	1			T16	1		T17	1		T24	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T3	1		T14	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	497	1			T3	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	228	1			T14	1		T131	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	532	1			T1	1		T16	2		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T3	1		T15	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	524	1			T2	1		T15	3		T79	1