Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30899

1

T1

24

T2

24

T3

30

auto[1]

270

1

T70

5

T135

6

T145

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30907	1			T1	24		T2	24		T3	30
auto[134217728:268435455]	7	1			T145	1		T292	1		T298	1
auto[268435456:402653183]	7	1			T135	1		T255	1		T272	1
auto[402653184:536870911]	7	1			T145	1		T238	1		T348	1
auto[536870912:671088639]	7	1			T254	1		T330	2		T392	1
auto[671088640:805306367]	6	1			T70	1		T135	1		T348	1
auto[805306368:939524095]	7	1			T330	1		T348	1		T300	1
auto[939524096:1073741823]	10	1			T136	1		T254	1		T330	1
auto[1073741824:1207959551]	11	1			T136	1		T285	1		T322	1
auto[1207959552:1342177279]	7	1			T145	1		T360	1		T249	2
auto[1342177280:1476395007]	7	1			T145	1		T263	1		T255	1
auto[1476395008:1610612735]	9	1			T145	1		T263	1		T255	1
auto[1610612736:1744830463]	13	1			T145	1		T255	1		T348	1
auto[1744830464:1879048191]	6	1			T135	1		T263	1		T289	1
auto[1879048192:2013265919]	10	1			T145	1		T255	1		T270	1
auto[2013265920:2147483647]	10	1			T254	1		T263	1		T255	1
auto[2147483648:2281701375]	11	1			T145	1		T393	1		T341	1
auto[2281701376:2415919103]	5	1			T135	1		T289	1		T348	1
auto[2415919104:2550136831]	11	1			T254	1		T285	1		T348	1
auto[2550136832:2684354559]	8	1			T263	1		T270	1		T322	1
auto[2684354560:2818572287]	11	1			T145	1		T255	1		T289	1
auto[2818572288:2952790015]	8	1			T255	1		T270	1		T236	1
auto[2952790016:3087007743]	5	1			T70	1		T255	1		T233	1
auto[3087007744:3221225471]	7	1			T394	1		T289	1		T270	2
auto[3221225472:3355443199]	11	1			T70	2		T145	1		T254	1
auto[3355443200:3489660927]	7	1			T263	1		T393	1		T270	1
auto[3489660928:3623878655]	9	1			T255	1		T298	1		T322	1
auto[3623878656:3758096383]	6	1			T70	1		T145	1		T270	1
auto[3758096384:3892314111]	13	1			T135	1		T263	1		T255	1
auto[3892314112:4026531839]	7	1			T270	1		T272	1		T300	2
auto[4026531840:4160749567]	6	1			T254	1		T298	1		T272	1
auto[4160749568:4294967295]	13	1			T135	1		T298	1		T270	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30899	1			T1	24		T2	24		T3	30
auto[0:134217727]	auto[1]	8	1			T348	1		T322	1		T249	1
auto[134217728:268435455]	auto[1]	7	1			T145	1		T292	1		T298	1
auto[268435456:402653183]	auto[1]	7	1			T135	1		T255	1		T272	1
auto[402653184:536870911]	auto[1]	7	1			T145	1		T238	1		T348	1
auto[536870912:671088639]	auto[1]	7	1			T254	1		T330	2		T392	1
auto[671088640:805306367]	auto[1]	6	1			T70	1		T135	1		T348	1
auto[805306368:939524095]	auto[1]	7	1			T330	1		T348	1		T300	1
auto[939524096:1073741823]	auto[1]	10	1			T136	1		T254	1		T330	1
auto[1073741824:1207959551]	auto[1]	11	1			T136	1		T285	1		T322	1
auto[1207959552:1342177279]	auto[1]	7	1			T145	1		T360	1		T249	2
auto[1342177280:1476395007]	auto[1]	7	1			T145	1		T263	1		T255	1
auto[1476395008:1610612735]	auto[1]	9	1			T145	1		T263	1		T255	1
auto[1610612736:1744830463]	auto[1]	13	1			T145	1		T255	1		T348	1
auto[1744830464:1879048191]	auto[1]	6	1			T135	1		T263	1		T289	1
auto[1879048192:2013265919]	auto[1]	10	1			T145	1		T255	1		T270	1
auto[2013265920:2147483647]	auto[1]	10	1			T254	1		T263	1		T255	1
auto[2147483648:2281701375]	auto[1]	11	1			T145	1		T393	1		T341	1
auto[2281701376:2415919103]	auto[1]	5	1			T135	1		T289	1		T348	1
auto[2415919104:2550136831]	auto[1]	11	1			T254	1		T285	1		T348	1
auto[2550136832:2684354559]	auto[1]	8	1			T263	1		T270	1		T322	1
auto[2684354560:2818572287]	auto[1]	11	1			T145	1		T255	1		T289	1
auto[2818572288:2952790015]	auto[1]	8	1			T255	1		T270	1		T236	1
auto[2952790016:3087007743]	auto[1]	5	1			T70	1		T255	1		T233	1
auto[3087007744:3221225471]	auto[1]	7	1			T394	1		T289	1		T270	2
auto[3221225472:3355443199]	auto[1]	11	1			T70	2		T145	1		T254	1
auto[3355443200:3489660927]	auto[1]	7	1			T263	1		T393	1		T270	1
auto[3489660928:3623878655]	auto[1]	9	1			T255	1		T298	1		T322	1
auto[3623878656:3758096383]	auto[1]	6	1			T70	1		T145	1		T270	1
auto[3758096384:3892314111]	auto[1]	13	1			T135	1		T263	1		T255	1
auto[3892314112:4026531839]	auto[1]	7	1			T270	1		T272	1		T300	2
auto[4026531840:4160749567]	auto[1]	6	1			T254	1		T298	1		T272	1
auto[4160749568:4294967295]	auto[1]	13	1			T135	1		T298	1		T270	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1658

1

T1

5

T2

4

T16

3

auto[1]

1641

1

T16

4

T7

1

T53

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T73	2		T40	4		T135	1
auto[134217728:268435455]	110	1			T16	1		T24	1		T73	2
auto[268435456:402653183]	122	1			T2	1		T39	1		T181	1
auto[402653184:536870911]	94	1			T39	1		T181	1		T4	1
auto[536870912:671088639]	88	1			T24	1		T181	1		T40	1
auto[671088640:805306367]	84	1			T38	1		T181	1		T40	3
auto[805306368:939524095]	122	1			T1	1		T58	2		T70	1
auto[939524096:1073741823]	99	1			T2	1		T7	1		T77	1
auto[1073741824:1207959551]	137	1			T1	1		T16	1		T39	3
auto[1207959552:1342177279]	78	1			T38	1		T40	1		T36	1
auto[1342177280:1476395007]	98	1			T39	1		T40	2		T4	2
auto[1476395008:1610612735]	98	1			T24	1		T39	1		T40	2
auto[1610612736:1744830463]	103	1			T39	2		T70	1		T25	1
auto[1744830464:1879048191]	112	1			T1	1		T7	1		T77	1
auto[1879048192:2013265919]	101	1			T1	1		T16	1		T131	1
auto[2013265920:2147483647]	78	1			T39	2		T77	1		T181	1
auto[2147483648:2281701375]	106	1			T53	1		T39	1		T73	1
auto[2281701376:2415919103]	89	1			T53	1		T39	1		T40	1
auto[2415919104:2550136831]	95	1			T77	1		T395	1		T51	2
auto[2550136832:2684354559]	89	1			T40	2		T4	1		T51	1
auto[2684354560:2818572287]	102	1			T53	1		T39	1		T77	1
auto[2818572288:2952790015]	107	1			T16	1		T24	1		T39	2
auto[2952790016:3087007743]	93	1			T38	1		T40	3		T4	2
auto[3087007744:3221225471]	105	1			T38	1		T39	2		T70	1
auto[3221225472:3355443199]	110	1			T53	1		T39	1		T40	1
auto[3355443200:3489660927]	115	1			T40	1		T4	4		T5	1
auto[3489660928:3623878655]	114	1			T53	1		T39	2		T40	1
auto[3623878656:3758096383]	94	1			T77	1		T40	1		T145	1
auto[3758096384:3892314111]	113	1			T1	1		T2	2		T40	2
auto[3892314112:4026531839]	122	1			T38	1		T193	1		T40	2
auto[4026531840:4160749567]	120	1			T16	2		T53	1		T103	1
auto[4160749568:4294967295]	110	1			T16	1		T58	3		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T40	1		T145	1		T51	1
auto[0:134217727]	auto[1]	44	1			T73	2		T40	3		T135	1
auto[134217728:268435455]	auto[0]	52	1			T16	1		T25	1		T40	3
auto[134217728:268435455]	auto[1]	58	1			T24	1		T73	2		T40	1
auto[268435456:402653183]	auto[0]	65	1			T2	1		T39	1		T135	1
auto[268435456:402653183]	auto[1]	57	1			T181	1		T40	1		T51	1
auto[402653184:536870911]	auto[0]	43	1			T55	2		T57	1		T41	1
auto[402653184:536870911]	auto[1]	51	1			T39	1		T181	1		T4	1
auto[536870912:671088639]	auto[0]	49	1			T24	1		T256	1		T202	1
auto[536870912:671088639]	auto[1]	39	1			T181	1		T40	1		T187	1
auto[671088640:805306367]	auto[0]	45	1			T40	2		T187	1		T86	1
auto[671088640:805306367]	auto[1]	39	1			T38	1		T181	1		T40	1
auto[805306368:939524095]	auto[0]	60	1			T1	1		T58	2		T145	1
auto[805306368:939524095]	auto[1]	62	1			T70	1		T86	1		T51	1
auto[939524096:1073741823]	auto[0]	55	1			T2	1		T77	1		T47	1
auto[939524096:1073741823]	auto[1]	44	1			T7	1		T40	1		T187	1
auto[1073741824:1207959551]	auto[0]	67	1			T1	1		T16	1		T39	2
auto[1073741824:1207959551]	auto[1]	70	1			T39	1		T187	1		T4	2
auto[1207959552:1342177279]	auto[0]	42	1			T38	1		T36	1		T102	1
auto[1207959552:1342177279]	auto[1]	36	1			T40	1		T316	1		T23	1
auto[1342177280:1476395007]	auto[0]	48	1			T39	1		T40	1		T4	1
auto[1342177280:1476395007]	auto[1]	50	1			T40	1		T4	1		T5	2
auto[1476395008:1610612735]	auto[0]	44	1			T39	1		T40	2		T200	1
auto[1476395008:1610612735]	auto[1]	54	1			T24	1		T46	1		T86	1
auto[1610612736:1744830463]	auto[0]	50	1			T39	1		T70	1		T25	1
auto[1610612736:1744830463]	auto[1]	53	1			T39	1		T4	2		T55	2
auto[1744830464:1879048191]	auto[0]	60	1			T1	1		T7	1		T77	1
auto[1744830464:1879048191]	auto[1]	52	1			T40	2		T135	1		T4	1
auto[1879048192:2013265919]	auto[0]	50	1			T1	1		T131	1		T256	1
auto[1879048192:2013265919]	auto[1]	51	1			T16	1		T58	1		T51	1
auto[2013265920:2147483647]	auto[0]	45	1			T39	2		T40	1		T145	1
auto[2013265920:2147483647]	auto[1]	33	1			T77	1		T181	1		T40	1
auto[2147483648:2281701375]	auto[0]	52	1			T39	1		T77	1		T40	1
auto[2147483648:2281701375]	auto[1]	54	1			T53	1		T73	1		T193	1
auto[2281701376:2415919103]	auto[0]	50	1			T39	1		T40	1		T54	1
auto[2281701376:2415919103]	auto[1]	39	1			T53	1		T51	1		T5	1
auto[2415919104:2550136831]	auto[0]	47	1			T395	1		T55	1		T102	2
auto[2415919104:2550136831]	auto[1]	48	1			T77	1		T51	2		T5	1
auto[2550136832:2684354559]	auto[0]	37	1			T85	1		T396	1		T41	2
auto[2550136832:2684354559]	auto[1]	52	1			T40	2		T4	1		T51	1
auto[2684354560:2818572287]	auto[0]	57	1			T53	1		T40	1		T316	1
auto[2684354560:2818572287]	auto[1]	45	1			T39	1		T77	1		T181	1
auto[2818572288:2952790015]	auto[0]	57	1			T16	1		T39	2		T40	1
auto[2818572288:2952790015]	auto[1]	50	1			T24	1		T40	1		T4	2
auto[2952790016:3087007743]	auto[0]	49	1			T38	1		T40	2		T51	1
auto[2952790016:3087007743]	auto[1]	44	1			T40	1		T4	2		T85	1
auto[3087007744:3221225471]	auto[0]	50	1			T38	1		T39	1		T70	1
auto[3087007744:3221225471]	auto[1]	55	1			T39	1		T33	1		T5	1
auto[3221225472:3355443199]	auto[0]	48	1			T53	1		T62	1		T5	1
auto[3221225472:3355443199]	auto[1]	62	1			T39	1		T40	1		T200	1
auto[3355443200:3489660927]	auto[0]	59	1			T40	1		T4	2		T22	1
auto[3355443200:3489660927]	auto[1]	56	1			T4	2		T5	1		T55	1
auto[3489660928:3623878655]	auto[0]	55	1			T40	1		T22	2		T316	1
auto[3489660928:3623878655]	auto[1]	59	1			T53	1		T39	2		T205	1
auto[3623878656:3758096383]	auto[0]	38	1			T77	1		T40	1		T397	2
auto[3623878656:3758096383]	auto[1]	56	1			T145	1		T4	2		T203	1
auto[3758096384:3892314111]	auto[0]	54	1			T1	1		T2	2		T40	1
auto[3758096384:3892314111]	auto[1]	59	1			T40	1		T187	1		T200	1
auto[3892314112:4026531839]	auto[0]	60	1			T193	1		T40	2		T205	1
auto[3892314112:4026531839]	auto[1]	62	1			T38	1		T4	1		T256	1
auto[4026531840:4160749567]	auto[0]	68	1			T39	1		T145	1		T55	1
auto[4026531840:4160749567]	auto[1]	52	1			T16	2		T53	1		T103	1
auto[4160749568:4294967295]	auto[0]	55	1			T58	2		T38	1		T24	1
auto[4160749568:4294967295]	auto[1]	55	1			T16	1		T58	1		T103	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1636

1

T1

4

T2

4

T16

4

auto[1]

1665

1

T1

1

T16

3

T7

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T1	1		T53	1		T58	1
auto[134217728:268435455]	102	1			T16	1		T39	1		T40	2
auto[268435456:402653183]	98	1			T1	1		T58	1		T39	2
auto[402653184:536870911]	123	1			T2	1		T38	1		T40	4
auto[536870912:671088639]	103	1			T7	1		T40	1		T4	1
auto[671088640:805306367]	109	1			T1	1		T2	1		T193	1
auto[805306368:939524095]	96	1			T58	1		T181	1		T40	1
auto[939524096:1073741823]	94	1			T39	1		T40	2		T397	1
auto[1073741824:1207959551]	98	1			T1	1		T39	2		T40	1
auto[1207959552:1342177279]	105	1			T16	1		T39	1		T73	1
auto[1342177280:1476395007]	91	1			T58	1		T39	2		T73	1
auto[1476395008:1610612735]	97	1			T16	1		T73	1		T77	1
auto[1610612736:1744830463]	108	1			T135	1		T4	1		T395	1
auto[1744830464:1879048191]	117	1			T16	2		T7	1		T39	1
auto[1879048192:2013265919]	89	1			T53	1		T39	2		T77	1
auto[2013265920:2147483647]	94	1			T38	2		T70	1		T25	1
auto[2147483648:2281701375]	108	1			T2	1		T77	1		T40	3
auto[2281701376:2415919103]	93	1			T2	1		T53	2		T58	1
auto[2415919104:2550136831]	95	1			T24	1		T39	1		T4	1
auto[2550136832:2684354559]	108	1			T1	1		T38	1		T24	1
auto[2684354560:2818572287]	104	1			T77	2		T40	2		T145	1
auto[2818572288:2952790015]	107	1			T40	1		T46	1		T200	1
auto[2952790016:3087007743]	106	1			T24	1		T39	2		T40	1
auto[3087007744:3221225471]	100	1			T70	1		T40	2		T4	1
auto[3221225472:3355443199]	93	1			T39	2		T181	1		T40	2
auto[3355443200:3489660927]	129	1			T70	1		T40	2		T4	2
auto[3489660928:3623878655]	105	1			T16	2		T131	1		T38	1
auto[3623878656:3758096383]	127	1			T58	1		T38	1		T40	2
auto[3758096384:3892314111]	101	1			T39	1		T181	1		T4	1
auto[3892314112:4026531839]	116	1			T103	1		T193	1		T181	1
auto[4026531840:4160749567]	94	1			T53	2		T39	1		T73	1
auto[4160749568:4294967295]	97	1			T24	1		T39	2		T4	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T187	1		T22	1		T254	1
auto[0:134217727]	auto[1]	42	1			T1	1		T53	1		T58	1
auto[134217728:268435455]	auto[0]	57	1			T16	1		T39	1		T40	2
auto[134217728:268435455]	auto[1]	45	1			T135	1		T239	1		T5	2
auto[268435456:402653183]	auto[0]	53	1			T1	1		T58	1		T39	2
auto[268435456:402653183]	auto[1]	45	1			T77	1		T40	1		T4	1
auto[402653184:536870911]	auto[0]	58	1			T2	1		T38	1		T40	2
auto[402653184:536870911]	auto[1]	65	1			T40	2		T4	1		T256	1
auto[536870912:671088639]	auto[0]	49	1			T7	1		T40	1		T51	1
auto[536870912:671088639]	auto[1]	54	1			T4	1		T256	1		T51	1
auto[671088640:805306367]	auto[0]	56	1			T1	1		T2	1		T193	1
auto[671088640:805306367]	auto[1]	53	1			T40	3		T135	1		T145	1
auto[805306368:939524095]	auto[0]	42	1			T187	1		T273	1		T55	2
auto[805306368:939524095]	auto[1]	54	1			T58	1		T181	1		T40	1
auto[939524096:1073741823]	auto[0]	51	1			T39	1		T47	1		T205	1
auto[939524096:1073741823]	auto[1]	43	1			T40	2		T397	1		T202	1
auto[1073741824:1207959551]	auto[0]	51	1			T1	1		T39	1		T36	1
auto[1073741824:1207959551]	auto[1]	47	1			T39	1		T40	1		T205	1
auto[1207959552:1342177279]	auto[0]	42	1			T39	1		T145	1		T4	1
auto[1207959552:1342177279]	auto[1]	63	1			T16	1		T73	1		T86	2
auto[1342177280:1476395007]	auto[0]	47	1			T58	1		T39	1		T5	1
auto[1342177280:1476395007]	auto[1]	44	1			T39	1		T73	1		T40	2
auto[1476395008:1610612735]	auto[0]	45	1			T16	1		T77	1		T40	1
auto[1476395008:1610612735]	auto[1]	52	1			T73	1		T40	1		T4	1
auto[1610612736:1744830463]	auto[0]	53	1			T395	1		T5	1		T36	1
auto[1610612736:1744830463]	auto[1]	55	1			T135	1		T4	1		T200	2
auto[1744830464:1879048191]	auto[0]	55	1			T16	1		T40	1		T135	1
auto[1744830464:1879048191]	auto[1]	62	1			T16	1		T7	1		T39	1
auto[1879048192:2013265919]	auto[0]	49	1			T39	1		T77	1		T135	1
auto[1879048192:2013265919]	auto[1]	40	1			T53	1		T39	1		T55	1
auto[2013265920:2147483647]	auto[0]	52	1			T38	1		T70	1		T25	1
auto[2013265920:2147483647]	auto[1]	42	1			T38	1		T4	1		T5	1
auto[2147483648:2281701375]	auto[0]	54	1			T2	1		T77	1		T54	1
auto[2147483648:2281701375]	auto[1]	54	1			T40	3		T4	1		T5	1
auto[2281701376:2415919103]	auto[0]	51	1			T2	1		T53	1		T58	1
auto[2281701376:2415919103]	auto[1]	42	1			T53	1		T24	1		T25	1
auto[2415919104:2550136831]	auto[0]	44	1			T24	1		T39	1		T4	1
auto[2415919104:2550136831]	auto[1]	51	1			T51	1		T136	1		T5	1
auto[2550136832:2684354559]	auto[0]	46	1			T1	1		T38	1		T40	2
auto[2550136832:2684354559]	auto[1]	62	1			T24	1		T181	2		T40	1
auto[2684354560:2818572287]	auto[0]	51	1			T62	1		T47	1		T51	1
auto[2684354560:2818572287]	auto[1]	53	1			T77	2		T40	2		T145	1
auto[2818572288:2952790015]	auto[0]	59	1			T40	1		T200	1		T36	1
auto[2818572288:2952790015]	auto[1]	48	1			T46	1		T202	1		T33	1
auto[2952790016:3087007743]	auto[0]	49	1			T39	1		T40	1		T256	1
auto[2952790016:3087007743]	auto[1]	57	1			T24	1		T39	1		T135	1
auto[3087007744:3221225471]	auto[0]	49	1			T70	1		T4	1		T54	1
auto[3087007744:3221225471]	auto[1]	51	1			T40	2		T203	1		T47	1
auto[3221225472:3355443199]	auto[0]	42	1			T39	2		T181	1		T40	1
auto[3221225472:3355443199]	auto[1]	51	1			T40	1		T187	1		T46	1
auto[3355443200:3489660927]	auto[0]	70	1			T40	2		T200	1		T136	1
auto[3355443200:3489660927]	auto[1]	59	1			T70	1		T4	2		T203	1
auto[3489660928:3623878655]	auto[0]	57	1			T16	1		T131	1		T38	1
auto[3489660928:3623878655]	auto[1]	48	1			T16	1		T40	1		T86	1
auto[3623878656:3758096383]	auto[0]	60	1			T58	1		T38	1		T398	1
auto[3623878656:3758096383]	auto[1]	67	1			T40	2		T4	1		T199	1
auto[3758096384:3892314111]	auto[0]	55	1			T39	1		T395	1		T202	1
auto[3758096384:3892314111]	auto[1]	46	1			T181	1		T4	1		T55	2
auto[3892314112:4026531839]	auto[0]	45	1			T40	1		T54	1		T22	1
auto[3892314112:4026531839]	auto[1]	71	1			T103	1		T193	1		T181	1
auto[4026531840:4160749567]	auto[0]	47	1			T53	1		T39	1		T40	2
auto[4026531840:4160749567]	auto[1]	47	1			T53	1		T73	1		T40	1
auto[4160749568:4294967295]	auto[0]	45	1			T39	1		T5	1		T36	1
auto[4160749568:4294967295]	auto[1]	52	1			T24	1		T39	1		T4	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1635

1

T1

5

T2

4

T16

3

auto[1]

1669

1

T16

4

T7

2

T53

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T16	1		T38	1		T39	2
auto[134217728:268435455]	114	1			T16	1		T38	1		T77	1
auto[268435456:402653183]	97	1			T103	1		T39	2		T77	1
auto[402653184:536870911]	103	1			T38	1		T39	1		T40	1
auto[536870912:671088639]	93	1			T2	1		T24	1		T46	1
auto[671088640:805306367]	100	1			T2	1		T39	1		T73	1
auto[805306368:939524095]	96	1			T193	1		T40	1		T200	1
auto[939524096:1073741823]	96	1			T16	1		T131	1		T25	2
auto[1073741824:1207959551]	89	1			T2	1		T7	1		T193	1
auto[1207959552:1342177279]	84	1			T58	1		T39	1		T40	1
auto[1342177280:1476395007]	110	1			T53	1		T58	2		T24	1
auto[1476395008:1610612735]	98	1			T1	1		T53	1		T103	1
auto[1610612736:1744830463]	97	1			T77	1		T40	3		T187	1
auto[1744830464:1879048191]	102	1			T58	1		T39	2		T70	1
auto[1879048192:2013265919]	117	1			T39	1		T40	2		T4	1
auto[2013265920:2147483647]	99	1			T1	1		T39	1		T40	1
auto[2147483648:2281701375]	113	1			T135	1		T145	1		T397	1
auto[2281701376:2415919103]	97	1			T53	2		T58	1		T39	1
auto[2415919104:2550136831]	109	1			T1	1		T58	1		T24	1
auto[2550136832:2684354559]	104	1			T1	1		T16	2		T53	1
auto[2684354560:2818572287]	94	1			T1	1		T2	1		T39	2
auto[2818572288:2952790015]	101	1			T181	1		T40	4		T62	1
auto[2952790016:3087007743]	112	1			T7	1		T39	1		T70	1
auto[3087007744:3221225471]	117	1			T39	2		T73	1		T25	1
auto[3221225472:3355443199]	116	1			T53	1		T39	1		T77	1
auto[3355443200:3489660927]	106	1			T24	2		T70	1		T40	5
auto[3489660928:3623878655]	100	1			T39	2		T135	1		T4	2
auto[3623878656:3758096383]	98	1			T16	2		T39	1		T40	2
auto[3758096384:3892314111]	107	1			T77	1		T40	2		T145	1
auto[3892314112:4026531839]	99	1			T181	1		T40	1		T187	1
auto[4026531840:4160749567]	133	1			T24	1		T40	1		T4	1
auto[4160749568:4294967295]	111	1			T38	1		T39	1		T40	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T16	1		T38	1		T39	1
auto[0:134217727]	auto[1]	44	1			T39	1		T73	1		T395	1
auto[134217728:268435455]	auto[0]	57	1			T77	1		T40	1		T4	1
auto[134217728:268435455]	auto[1]	57	1			T16	1		T38	1		T40	1
auto[268435456:402653183]	auto[0]	45	1			T39	1		T145	1		T202	1
auto[268435456:402653183]	auto[1]	52	1			T103	1		T39	1		T77	1
auto[402653184:536870911]	auto[0]	54	1			T38	1		T40	1		T5	1
auto[402653184:536870911]	auto[1]	49	1			T39	1		T4	1		T200	1
auto[536870912:671088639]	auto[0]	42	1			T2	1		T397	1		T47	1
auto[536870912:671088639]	auto[1]	51	1			T24	1		T46	1		T51	2
auto[671088640:805306367]	auto[0]	53	1			T2	1		T39	1		T5	1
auto[671088640:805306367]	auto[1]	47	1			T73	1		T40	1		T273	1
auto[805306368:939524095]	auto[0]	52	1			T55	1		T48	1		T41	1
auto[805306368:939524095]	auto[1]	44	1			T193	1		T40	1		T200	1
auto[939524096:1073741823]	auto[0]	56	1			T131	1		T25	1		T40	2
auto[939524096:1073741823]	auto[1]	40	1			T16	1		T25	1		T40	1
auto[1073741824:1207959551]	auto[0]	47	1			T2	1		T193	1		T135	1
auto[1073741824:1207959551]	auto[1]	42	1			T7	1		T181	1		T40	1
auto[1207959552:1342177279]	auto[0]	42	1			T39	1		T397	1		T51	1
auto[1207959552:1342177279]	auto[1]	42	1			T58	1		T40	1		T145	1
auto[1342177280:1476395007]	auto[0]	56	1			T53	1		T58	1		T40	1
auto[1342177280:1476395007]	auto[1]	54	1			T58	1		T24	1		T181	1
auto[1476395008:1610612735]	auto[0]	55	1			T1	1		T38	1		T39	1
auto[1476395008:1610612735]	auto[1]	43	1			T53	1		T103	1		T181	2
auto[1610612736:1744830463]	auto[0]	46	1			T40	2		T4	1		T47	1
auto[1610612736:1744830463]	auto[1]	51	1			T77	1		T40	1		T187	1
auto[1744830464:1879048191]	auto[0]	45	1			T58	1		T39	1		T70	1
auto[1744830464:1879048191]	auto[1]	57	1			T39	1		T40	1		T4	2
auto[1879048192:2013265919]	auto[0]	56	1			T40	1		T62	1		T136	1
auto[1879048192:2013265919]	auto[1]	61	1			T39	1		T40	1		T4	1
auto[2013265920:2147483647]	auto[0]	47	1			T1	1		T40	1		T135	1
auto[2013265920:2147483647]	auto[1]	52	1			T39	1		T4	1		T205	1
auto[2147483648:2281701375]	auto[0]	56	1			T145	1		T397	1		T86	1
auto[2147483648:2281701375]	auto[1]	57	1			T135	1		T5	1		T55	1
auto[2281701376:2415919103]	auto[0]	57	1			T53	1		T58	1		T39	1
auto[2281701376:2415919103]	auto[1]	40	1			T53	1		T40	1		T4	1
auto[2415919104:2550136831]	auto[0]	60	1			T1	1		T58	1		T256	1
auto[2415919104:2550136831]	auto[1]	49	1			T24	1		T193	1		T40	1
auto[2550136832:2684354559]	auto[0]	55	1			T1	1		T16	2		T38	1
auto[2550136832:2684354559]	auto[1]	49	1			T53	1		T77	1		T40	2
auto[2684354560:2818572287]	auto[0]	45	1			T1	1		T2	1		T39	2
auto[2684354560:2818572287]	auto[1]	49	1			T73	1		T40	1		T4	1
auto[2818572288:2952790015]	auto[0]	49	1			T181	1		T40	3		T62	1
auto[2818572288:2952790015]	auto[1]	52	1			T40	1		T203	1		T202	1
auto[2952790016:3087007743]	auto[0]	48	1			T77	1		T51	1		T55	1
auto[2952790016:3087007743]	auto[1]	64	1			T7	1		T39	1		T70	1
auto[3087007744:3221225471]	auto[0]	55	1			T39	1		T25	1		T4	1
auto[3087007744:3221225471]	auto[1]	62	1			T39	1		T73	1		T181	1
auto[3221225472:3355443199]	auto[0]	57	1			T40	2		T187	1		T200	1
auto[3221225472:3355443199]	auto[1]	59	1			T53	1		T39	1		T77	1
auto[3355443200:3489660927]	auto[0]	53	1			T24	2		T70	1		T40	4
auto[3355443200:3489660927]	auto[1]	53	1			T40	1		T4	2		T86	1
auto[3489660928:3623878655]	auto[0]	45	1			T39	1		T4	1		T51	1
auto[3489660928:3623878655]	auto[1]	55	1			T39	1		T135	1		T4	1
auto[3623878656:3758096383]	auto[0]	44	1			T40	1		T54	1		T200	1
auto[3623878656:3758096383]	auto[1]	54	1			T16	2		T39	1		T40	1
auto[3758096384:3892314111]	auto[0]	48	1			T77	1		T40	1		T145	1
auto[3758096384:3892314111]	auto[1]	59	1			T40	1		T55	1		T254	1
auto[3892314112:4026531839]	auto[0]	46	1			T187	1		T51	1		T36	1
auto[3892314112:4026531839]	auto[1]	53	1			T181	1		T40	1		T4	2
auto[4026531840:4160749567]	auto[0]	62	1			T24	1		T4	1		T51	2
auto[4026531840:4160749567]	auto[1]	71	1			T40	1		T203	1		T86	1
auto[4160749568:4294967295]	auto[0]	54	1			T40	1		T338	1		T102	2
auto[4160749568:4294967295]	auto[1]	57	1			T38	1		T39	1		T40	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1633

1

T1

5

T2

4

T16

5

auto[1]

1673

1

T16

3

T7

2

T53

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T38	1		T24	1		T39	1
auto[134217728:268435455]	96	1			T1	1		T39	1		T40	2
auto[268435456:402653183]	89	1			T73	1		T40	2		T4	1
auto[402653184:536870911]	104	1			T16	1		T39	1		T40	2
auto[536870912:671088639]	92	1			T58	1		T24	1		T39	1
auto[671088640:805306367]	116	1			T1	1		T53	1		T103	1
auto[805306368:939524095]	118	1			T53	1		T39	1		T193	1
auto[939524096:1073741823]	110	1			T40	2		T62	1		T202	1
auto[1073741824:1207959551]	111	1			T16	1		T58	2		T40	5
auto[1207959552:1342177279]	110	1			T16	1		T53	1		T39	1
auto[1342177280:1476395007]	98	1			T58	1		T39	1		T40	1
auto[1476395008:1610612735]	101	1			T1	2		T2	1		T38	1
auto[1610612736:1744830463]	102	1			T16	1		T131	1		T73	1
auto[1744830464:1879048191]	92	1			T7	1		T103	1		T38	1
auto[1879048192:2013265919]	96	1			T2	1		T70	2		T77	1
auto[2013265920:2147483647]	110	1			T16	2		T58	1		T77	1
auto[2147483648:2281701375]	94	1			T24	1		T39	2		T47	2
auto[2281701376:2415919103]	98	1			T39	1		T40	2		T200	1
auto[2415919104:2550136831]	119	1			T2	1		T39	1		T25	1
auto[2550136832:2684354559]	97	1			T39	2		T187	1		T4	1
auto[2684354560:2818572287]	115	1			T16	1		T58	1		T39	1
auto[2818572288:2952790015]	87	1			T205	1		T5	2		T55	1
auto[2952790016:3087007743]	114	1			T2	1		T38	2		T39	1
auto[3087007744:3221225471]	112	1			T53	1		T73	1		T40	1
auto[3221225472:3355443199]	98	1			T53	1		T73	1		T25	1
auto[3355443200:3489660927]	108	1			T39	4		T77	1		T40	2
auto[3489660928:3623878655]	71	1			T7	1		T38	1		T40	1
auto[3623878656:3758096383]	109	1			T1	1		T40	1		T4	2
auto[3758096384:3892314111]	112	1			T16	1		T53	1		T77	1
auto[3892314112:4026531839]	108	1			T24	1		T39	1		T70	1
auto[4026531840:4160749567]	106	1			T24	1		T181	1		T40	2
auto[4160749568:4294967295]	100	1			T39	2		T25	1		T181	1