Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2893

1

T1

5

T2

4

T16

7

auto[1]

274

1

T70

3

T135

10

T145

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T77	2		T40	3		T135	1
auto[134217728:268435455]	89	1			T16	1		T39	1		T40	1
auto[268435456:402653183]	116	1			T24	1		T39	1		T40	1
auto[402653184:536870911]	93	1			T24	1		T70	1		T73	1
auto[536870912:671088639]	119	1			T25	1		T40	1		T187	1
auto[671088640:805306367]	85	1			T16	1		T40	1		T145	1
auto[805306368:939524095]	106	1			T131	1		T58	1		T39	1
auto[939524096:1073741823]	112	1			T53	1		T39	1		T73	1
auto[1073741824:1207959551]	107	1			T70	1		T77	2		T40	2
auto[1207959552:1342177279]	98	1			T58	1		T39	1		T73	1
auto[1342177280:1476395007]	106	1			T39	1		T193	1		T40	1
auto[1476395008:1610612735]	85	1			T38	1		T39	1		T181	1
auto[1610612736:1744830463]	98	1			T16	1		T39	1		T40	2
auto[1744830464:1879048191]	87	1			T135	1		T397	1		T86	1
auto[1879048192:2013265919]	92	1			T7	1		T24	1		T39	2
auto[2013265920:2147483647]	87	1			T4	1		T46	1		T22	1
auto[2147483648:2281701375]	95	1			T16	1		T24	1		T70	1
auto[2281701376:2415919103]	90	1			T1	1		T58	1		T39	2
auto[2415919104:2550136831]	105	1			T1	1		T2	2		T58	1
auto[2550136832:2684354559]	104	1			T1	2		T39	1		T77	1
auto[2684354560:2818572287]	104	1			T16	1		T103	1		T135	4
auto[2818572288:2952790015]	99	1			T40	1		T51	1		T60	1
auto[2952790016:3087007743]	111	1			T39	1		T73	1		T40	1
auto[3087007744:3221225471]	108	1			T39	1		T181	1		T40	2
auto[3221225472:3355443199]	94	1			T1	1		T39	1		T40	1
auto[3355443200:3489660927]	110	1			T58	1		T24	1		T193	1
auto[3489660928:3623878655]	104	1			T53	1		T39	2		T187	1
auto[3623878656:3758096383]	95	1			T40	2		T135	2		T256	1
auto[3758096384:3892314111]	88	1			T58	1		T181	2		T40	2
auto[3892314112:4026531839]	95	1			T16	2		T39	1		T40	1
auto[4026531840:4160749567]	89	1			T2	1		T38	1		T24	1
auto[4160749568:4294967295]	97	1			T2	1		T53	1		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	91	1			T77	2		T40	3		T4	1
auto[0:134217727]	auto[1]	8	1			T135	1		T330	1		T298	1
auto[134217728:268435455]	auto[0]	83	1			T16	1		T39	1		T40	1
auto[134217728:268435455]	auto[1]	6	1			T135	1		T255	1		T272	1
auto[268435456:402653183]	auto[0]	105	1			T24	1		T39	1		T40	1
auto[268435456:402653183]	auto[1]	11	1			T145	1		T348	3		T322	1
auto[402653184:536870911]	auto[0]	87	1			T24	1		T70	1		T73	1
auto[402653184:536870911]	auto[1]	6	1			T348	1		T322	2		T332	1
auto[536870912:671088639]	auto[0]	108	1			T25	1		T40	1		T187	1
auto[536870912:671088639]	auto[1]	11	1			T145	1		T330	1		T322	1
auto[671088640:805306367]	auto[0]	75	1			T16	1		T40	1		T4	1
auto[671088640:805306367]	auto[1]	10	1			T145	1		T292	1		T298	1
auto[805306368:939524095]	auto[0]	96	1			T131	1		T58	1		T39	1
auto[805306368:939524095]	auto[1]	10	1			T238	1		T285	1		T270	1
auto[939524096:1073741823]	auto[0]	104	1			T53	1		T39	1		T73	1
auto[939524096:1073741823]	auto[1]	8	1			T263	1		T255	1		T270	2
auto[1073741824:1207959551]	auto[0]	99	1			T70	1		T77	2		T40	2
auto[1073741824:1207959551]	auto[1]	8	1			T332	1		T236	1		T300	2
auto[1207959552:1342177279]	auto[0]	91	1			T58	1		T39	1		T73	1
auto[1207959552:1342177279]	auto[1]	7	1			T135	1		T145	1		T322	1
auto[1342177280:1476395007]	auto[0]	101	1			T39	1		T193	1		T40	1
auto[1342177280:1476395007]	auto[1]	5	1			T393	1		T322	1		T249	1
auto[1476395008:1610612735]	auto[0]	78	1			T38	1		T39	1		T181	1
auto[1476395008:1610612735]	auto[1]	7	1			T300	2		T401	1		T308	2
auto[1610612736:1744830463]	auto[0]	84	1			T16	1		T39	1		T40	2
auto[1610612736:1744830463]	auto[1]	14	1			T145	1		T254	1		T255	1
auto[1744830464:1879048191]	auto[0]	81	1			T397	1		T86	1		T239	1
auto[1744830464:1879048191]	auto[1]	6	1			T135	1		T255	1		T236	1
auto[1879048192:2013265919]	auto[0]	87	1			T7	1		T24	1		T39	2
auto[1879048192:2013265919]	auto[1]	5	1			T255	1		T236	1		T300	1
auto[2013265920:2147483647]	auto[0]	76	1			T4	1		T46	1		T22	1
auto[2013265920:2147483647]	auto[1]	11	1			T255	1		T348	2		T393	1
auto[2147483648:2281701375]	auto[0]	90	1			T16	1		T24	1		T70	1
auto[2147483648:2281701375]	auto[1]	5	1			T236	1		T360	1		T402	1
auto[2281701376:2415919103]	auto[0]	84	1			T1	1		T58	1		T39	2
auto[2281701376:2415919103]	auto[1]	6	1			T70	1		T394	1		T236	1
auto[2415919104:2550136831]	auto[0]	99	1			T1	1		T2	2		T58	1
auto[2415919104:2550136831]	auto[1]	6	1			T135	1		T298	1		T402	1
auto[2550136832:2684354559]	auto[0]	94	1			T1	2		T39	1		T77	1
auto[2550136832:2684354559]	auto[1]	10	1			T330	1		T270	2		T322	1
auto[2684354560:2818572287]	auto[0]	91	1			T16	1		T103	1		T135	1
auto[2684354560:2818572287]	auto[1]	13	1			T135	3		T348	1		T270	1
auto[2818572288:2952790015]	auto[0]	85	1			T40	1		T51	1		T60	1
auto[2818572288:2952790015]	auto[1]	14	1			T289	1		T332	1		T272	1
auto[2952790016:3087007743]	auto[0]	98	1			T39	1		T73	1		T40	1
auto[2952790016:3087007743]	auto[1]	13	1			T135	1		T263	1		T289	1
auto[3087007744:3221225471]	auto[0]	100	1			T39	1		T181	1		T40	2
auto[3087007744:3221225471]	auto[1]	8	1			T254	1		T394	1		T270	1
auto[3221225472:3355443199]	auto[0]	89	1			T1	1		T39	1		T40	1
auto[3221225472:3355443199]	auto[1]	5	1			T136	1		T348	1		T308	1
auto[3355443200:3489660927]	auto[0]	100	1			T58	1		T24	1		T193	1
auto[3355443200:3489660927]	auto[1]	10	1			T330	1		T238	1		T255	2
auto[3489660928:3623878655]	auto[0]	91	1			T53	1		T39	2		T187	1
auto[3489660928:3623878655]	auto[1]	13	1			T145	1		T254	1		T255	1
auto[3623878656:3758096383]	auto[0]	89	1			T40	2		T135	1		T256	1
auto[3623878656:3758096383]	auto[1]	6	1			T135	1		T289	1		T348	1
auto[3758096384:3892314111]	auto[0]	81	1			T58	1		T181	2		T40	2
auto[3758096384:3892314111]	auto[1]	7	1			T145	1		T254	1		T255	1
auto[3892314112:4026531839]	auto[0]	83	1			T16	2		T39	1		T40	1
auto[3892314112:4026531839]	auto[1]	12	1			T263	1		T330	1		T270	1
auto[4026531840:4160749567]	auto[0]	79	1			T2	1		T38	1		T24	1
auto[4026531840:4160749567]	auto[1]	10	1			T70	2		T348	3		T402	1
auto[4160749568:4294967295]	auto[0]	94	1			T2	1		T53	1		T103	1
auto[4160749568:4294967295]	auto[1]	3	1			T332	1		T250	1		T409	1