Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.87 99.07 98.03 98.90 100.00 99.11 98.41 91.61


Total test records in report: 1090
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T1012 /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.4011061951 Jan 24 02:41:25 PM PST 24 Jan 24 02:41:38 PM PST 24 291955446 ps
T1013 /workspace/coverage/default/3.keymgr_sideload_otbn.1377245334 Jan 24 02:39:19 PM PST 24 Jan 24 02:40:17 PM PST 24 1845718810 ps
T399 /workspace/coverage/default/46.keymgr_cfg_regwen.1687930246 Jan 24 02:49:53 PM PST 24 Jan 24 02:50:31 PM PST 24 1093062918 ps
T1014 /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1265339572 Jan 24 02:41:06 PM PST 24 Jan 24 02:42:25 PM PST 24 5268026346 ps
T1015 /workspace/coverage/default/8.keymgr_smoke.3308158255 Jan 24 02:40:32 PM PST 24 Jan 24 02:41:21 PM PST 24 1707361744 ps
T1016 /workspace/coverage/default/43.keymgr_direct_to_disabled.3662547987 Jan 24 02:49:00 PM PST 24 Jan 24 02:49:21 PM PST 24 534804406 ps
T1017 /workspace/coverage/default/37.keymgr_sw_invalid_input.1895060311 Jan 24 02:47:33 PM PST 24 Jan 24 02:48:08 PM PST 24 482770915 ps
T1018 /workspace/coverage/default/33.keymgr_sw_invalid_input.2370030923 Jan 24 02:46:53 PM PST 24 Jan 24 02:47:44 PM PST 24 1682390862 ps
T1019 /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2234177203 Jan 24 02:44:39 PM PST 24 Jan 24 02:45:01 PM PST 24 186511722 ps
T1020 /workspace/coverage/default/1.keymgr_direct_to_disabled.2662784499 Jan 24 02:54:00 PM PST 24 Jan 24 02:54:34 PM PST 24 96191865 ps
T1021 /workspace/coverage/default/40.keymgr_smoke.1386094964 Jan 24 02:48:06 PM PST 24 Jan 24 02:48:42 PM PST 24 955867573 ps
T1022 /workspace/coverage/default/23.keymgr_stress_all.1590421237 Jan 24 02:44:23 PM PST 24 Jan 24 02:44:51 PM PST 24 86292507 ps
T1023 /workspace/coverage/default/24.keymgr_smoke.502565708 Jan 24 03:31:51 PM PST 24 Jan 24 03:32:41 PM PST 24 5860600803 ps
T1024 /workspace/coverage/default/23.keymgr_sideload_otbn.1586858595 Jan 24 02:44:22 PM PST 24 Jan 24 02:44:54 PM PST 24 1107619857 ps
T1025 /workspace/coverage/default/35.keymgr_stress_all.2750092191 Jan 24 02:47:14 PM PST 24 Jan 24 02:47:54 PM PST 24 511497057 ps
T1026 /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2877398586 Jan 24 03:06:37 PM PST 24 Jan 24 03:06:56 PM PST 24 156621559 ps
T1027 /workspace/coverage/default/45.keymgr_sideload_aes.2565427684 Jan 24 02:49:31 PM PST 24 Jan 24 02:49:49 PM PST 24 97980336 ps
T1028 /workspace/coverage/default/23.keymgr_direct_to_disabled.1983277969 Jan 24 04:26:50 PM PST 24 Jan 24 04:26:57 PM PST 24 87251087 ps
T1029 /workspace/coverage/default/19.keymgr_sw_invalid_input.2362338654 Jan 24 02:42:57 PM PST 24 Jan 24 02:43:34 PM PST 24 131536433 ps
T1030 /workspace/coverage/default/16.keymgr_sideload_aes.1872973646 Jan 24 02:42:12 PM PST 24 Jan 24 02:43:25 PM PST 24 1860000719 ps
T1031 /workspace/coverage/default/42.keymgr_sideload_protect.2480719162 Jan 24 02:48:48 PM PST 24 Jan 24 02:49:13 PM PST 24 1325784874 ps
T1032 /workspace/coverage/default/34.keymgr_sideload.135624458 Jan 24 02:46:49 PM PST 24 Jan 24 02:47:43 PM PST 24 4167962434 ps
T1033 /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4062536542 Jan 24 02:39:58 PM PST 24 Jan 24 02:40:13 PM PST 24 75531774 ps
T288 /workspace/coverage/default/8.keymgr_cfg_regwen.275656236 Jan 24 02:40:44 PM PST 24 Jan 24 02:41:08 PM PST 24 255317387 ps
T295 /workspace/coverage/default/49.keymgr_kmac_rsp_err.1148089811 Jan 24 02:50:48 PM PST 24 Jan 24 02:51:13 PM PST 24 3201939312 ps
T1034 /workspace/coverage/default/16.keymgr_custom_cm.1804796164 Jan 24 02:42:22 PM PST 24 Jan 24 02:42:55 PM PST 24 481330562 ps
T1035 /workspace/coverage/default/36.keymgr_sideload.468973332 Jan 24 02:47:13 PM PST 24 Jan 24 02:47:42 PM PST 24 85657178 ps
T1036 /workspace/coverage/default/48.keymgr_sideload_protect.4230643105 Jan 24 02:50:05 PM PST 24 Jan 24 02:50:28 PM PST 24 178351558 ps
T1037 /workspace/coverage/default/26.keymgr_sideload_kmac.1107155 Jan 24 02:54:02 PM PST 24 Jan 24 02:55:07 PM PST 24 1181251426 ps
T368 /workspace/coverage/default/22.keymgr_kmac_rsp_err.62276978 Jan 24 02:44:14 PM PST 24 Jan 24 02:44:40 PM PST 24 113198232 ps
T1038 /workspace/coverage/default/42.keymgr_sideload_aes.4225777671 Jan 24 02:48:45 PM PST 24 Jan 24 02:49:11 PM PST 24 456369692 ps
T1039 /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3620450481 Jan 24 02:42:27 PM PST 24 Jan 24 02:42:43 PM PST 24 126736388 ps
T1040 /workspace/coverage/default/19.keymgr_sideload_aes.3579315134 Jan 24 02:42:58 PM PST 24 Jan 24 02:43:33 PM PST 24 155758322 ps
T1041 /workspace/coverage/default/44.keymgr_custom_cm.2590976131 Jan 24 02:49:26 PM PST 24 Jan 24 02:49:41 PM PST 24 46998707 ps
T1042 /workspace/coverage/default/39.keymgr_stress_all.3156975675 Jan 24 02:48:02 PM PST 24 Jan 24 02:49:44 PM PST 24 2486150442 ps
T1043 /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1116489797 Jan 24 02:39:44 PM PST 24 Jan 24 02:40:03 PM PST 24 73958323 ps
T1044 /workspace/coverage/default/42.keymgr_sideload_otbn.1638457575 Jan 24 02:48:45 PM PST 24 Jan 24 02:49:08 PM PST 24 66773881 ps
T1045 /workspace/coverage/default/8.keymgr_random.1795153005 Jan 24 02:40:44 PM PST 24 Jan 24 02:40:57 PM PST 24 116353892 ps
T1046 /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.107891491 Jan 24 02:43:03 PM PST 24 Jan 24 02:43:44 PM PST 24 1138897707 ps
T94 /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1519669724 Jan 24 02:42:57 PM PST 24 Jan 24 02:43:34 PM PST 24 79820108 ps
T1047 /workspace/coverage/default/5.keymgr_hwsw_invalid_input.829276182 Jan 24 02:39:44 PM PST 24 Jan 24 02:40:05 PM PST 24 363905708 ps
T1048 /workspace/coverage/default/20.keymgr_sideload.790716984 Jan 24 02:43:05 PM PST 24 Jan 24 02:43:41 PM PST 24 135311982 ps
T1049 /workspace/coverage/default/21.keymgr_random.4126675705 Jan 24 02:43:59 PM PST 24 Jan 24 02:44:20 PM PST 24 314790839 ps
T1050 /workspace/coverage/default/9.keymgr_sideload_kmac.1945933900 Jan 24 02:40:50 PM PST 24 Jan 24 02:41:06 PM PST 24 21069501 ps
T1051 /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2420050634 Jan 24 02:42:55 PM PST 24 Jan 24 02:43:34 PM PST 24 348940440 ps
T1052 /workspace/coverage/default/49.keymgr_sideload_aes.2493778653 Jan 24 02:50:07 PM PST 24 Jan 24 02:51:23 PM PST 24 5389398020 ps
T1053 /workspace/coverage/default/0.keymgr_sw_invalid_input.1405285436 Jan 24 02:38:34 PM PST 24 Jan 24 02:38:50 PM PST 24 335116932 ps
T1054 /workspace/coverage/default/45.keymgr_random.2884444013 Jan 24 02:49:32 PM PST 24 Jan 24 02:49:52 PM PST 24 881454869 ps
T1055 /workspace/coverage/default/6.keymgr_alert_test.101957065 Jan 24 03:50:03 PM PST 24 Jan 24 03:50:09 PM PST 24 17712217 ps
T1056 /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2144400921 Jan 24 02:42:32 PM PST 24 Jan 24 02:42:49 PM PST 24 100507877 ps
T408 /workspace/coverage/default/3.keymgr_cfg_regwen.1424986600 Jan 24 02:39:21 PM PST 24 Jan 24 02:39:42 PM PST 24 111950425 ps
T1057 /workspace/coverage/default/47.keymgr_lc_disable.1129480945 Jan 24 02:49:49 PM PST 24 Jan 24 02:50:14 PM PST 24 203258490 ps
T1058 /workspace/coverage/default/40.keymgr_sideload_protect.706456117 Jan 24 02:48:23 PM PST 24 Jan 24 02:48:52 PM PST 24 80221296 ps
T1059 /workspace/coverage/default/28.keymgr_direct_to_disabled.2197842672 Jan 24 02:45:48 PM PST 24 Jan 24 02:45:56 PM PST 24 28420947 ps
T1060 /workspace/coverage/default/13.keymgr_custom_cm.2438037669 Jan 24 02:41:54 PM PST 24 Jan 24 02:42:02 PM PST 24 74245738 ps
T1061 /workspace/coverage/default/33.keymgr_sideload.848120659 Jan 24 02:46:47 PM PST 24 Jan 24 02:46:58 PM PST 24 53168211 ps
T1062 /workspace/coverage/default/30.keymgr_sideload.2688744183 Jan 24 04:33:48 PM PST 24 Jan 24 04:33:59 PM PST 24 261049317 ps
T410 /workspace/coverage/default/41.keymgr_cfg_regwen.1356965574 Jan 24 02:48:31 PM PST 24 Jan 24 02:48:58 PM PST 24 365315491 ps
T1063 /workspace/coverage/default/3.keymgr_sideload_kmac.3571454815 Jan 24 02:39:19 PM PST 24 Jan 24 02:40:17 PM PST 24 3642206658 ps
T1064 /workspace/coverage/default/31.keymgr_random.3547079195 Jan 24 02:46:16 PM PST 24 Jan 24 02:46:22 PM PST 24 98718040 ps
T1065 /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2234031782 Jan 24 03:10:51 PM PST 24 Jan 24 03:10:57 PM PST 24 124698987 ps
T179 /workspace/coverage/default/10.keymgr_custom_cm.4025999968 Jan 24 02:41:04 PM PST 24 Jan 24 02:41:22 PM PST 24 684039195 ps
T1066 /workspace/coverage/default/23.keymgr_custom_cm.3043353837 Jan 24 02:44:28 PM PST 24 Jan 24 02:44:53 PM PST 24 528683143 ps
T1067 /workspace/coverage/default/13.keymgr_sync_async_fault_cross.424869703 Jan 24 03:02:29 PM PST 24 Jan 24 03:02:42 PM PST 24 279618770 ps
T1068 /workspace/coverage/default/35.keymgr_kmac_rsp_err.110565955 Jan 24 02:47:15 PM PST 24 Jan 24 02:47:49 PM PST 24 187255157 ps
T1069 /workspace/coverage/default/40.keymgr_custom_cm.1291454897 Jan 24 02:57:23 PM PST 24 Jan 24 02:57:40 PM PST 24 43759115 ps
T1070 /workspace/coverage/default/45.keymgr_kmac_rsp_err.1648159475 Jan 24 02:49:37 PM PST 24 Jan 24 02:50:01 PM PST 24 347111529 ps
T1071 /workspace/coverage/default/32.keymgr_sideload_aes.1606547676 Jan 24 02:58:43 PM PST 24 Jan 24 02:58:57 PM PST 24 802236504 ps
T1072 /workspace/coverage/default/47.keymgr_stress_all.1496692820 Jan 24 02:49:57 PM PST 24 Jan 24 02:50:30 PM PST 24 416795459 ps
T1073 /workspace/coverage/default/16.keymgr_lc_disable.1006356620 Jan 24 02:42:24 PM PST 24 Jan 24 02:42:41 PM PST 24 147004221 ps
T342 /workspace/coverage/default/14.keymgr_kmac_rsp_err.75545701 Jan 24 02:42:05 PM PST 24 Jan 24 02:42:18 PM PST 24 208864541 ps
T1074 /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2451338703 Jan 24 02:49:22 PM PST 24 Jan 24 02:49:37 PM PST 24 110162937 ps
T1075 /workspace/coverage/default/3.keymgr_alert_test.3222854557 Jan 24 02:39:29 PM PST 24 Jan 24 02:39:46 PM PST 24 18646919 ps
T1076 /workspace/coverage/default/41.keymgr_sideload_protect.1910747175 Jan 24 02:48:38 PM PST 24 Jan 24 02:49:01 PM PST 24 29659083 ps
T1077 /workspace/coverage/default/11.keymgr_custom_cm.2438462622 Jan 24 04:02:58 PM PST 24 Jan 24 04:03:05 PM PST 24 195631653 ps
T1078 /workspace/coverage/default/9.keymgr_custom_cm.2187736824 Jan 24 02:40:57 PM PST 24 Jan 24 02:41:16 PM PST 24 1013455602 ps
T1079 /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3378888228 Jan 24 02:47:15 PM PST 24 Jan 24 02:47:51 PM PST 24 82666987 ps
T1080 /workspace/coverage/default/30.keymgr_sw_invalid_input.1502175660 Jan 24 02:46:07 PM PST 24 Jan 24 02:46:18 PM PST 24 1653039320 ps
T296 /workspace/coverage/default/34.keymgr_kmac_rsp_err.1791726164 Jan 24 02:46:56 PM PST 24 Jan 24 02:47:18 PM PST 24 41516519 ps
T1081 /workspace/coverage/default/40.keymgr_sideload_aes.1721105415 Jan 24 03:47:03 PM PST 24 Jan 24 03:47:12 PM PST 24 190661270 ps
T1082 /workspace/coverage/default/47.keymgr_custom_cm.166869680 Jan 24 02:49:53 PM PST 24 Jan 24 02:50:18 PM PST 24 57628941 ps
T1083 /workspace/coverage/default/37.keymgr_sideload_kmac.2125729850 Jan 24 02:47:37 PM PST 24 Jan 24 02:48:09 PM PST 24 185875156 ps
T1084 /workspace/coverage/default/24.keymgr_sw_invalid_input.1752738397 Jan 24 02:44:39 PM PST 24 Jan 24 02:44:58 PM PST 24 297990352 ps
T105 /workspace/coverage/default/4.keymgr_sec_cm.619583075 Jan 24 02:39:39 PM PST 24 Jan 24 02:40:08 PM PST 24 3522838347 ps
T1085 /workspace/coverage/default/37.keymgr_sideload.1477181094 Jan 24 03:32:17 PM PST 24 Jan 24 03:32:24 PM PST 24 204505875 ps
T1086 /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2277993584 Jan 24 02:43:58 PM PST 24 Jan 24 02:44:19 PM PST 24 160038887 ps
T1087 /workspace/coverage/default/13.keymgr_cfg_regwen.3752536555 Jan 24 02:41:42 PM PST 24 Jan 24 02:41:53 PM PST 24 59052802 ps
T1088 /workspace/coverage/default/18.keymgr_sideload_otbn.1893308723 Jan 24 02:43:06 PM PST 24 Jan 24 02:43:43 PM PST 24 64283312 ps
T1089 /workspace/coverage/default/24.keymgr_cfg_regwen.3655313307 Jan 24 02:44:38 PM PST 24 Jan 24 02:44:55 PM PST 24 421006686 ps
T1090 /workspace/coverage/default/2.keymgr_sideload_protect.4113391712 Jan 24 02:39:08 PM PST 24 Jan 24 02:39:23 PM PST 24 71105954 ps

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3134844198
Short name T16
Test name
Test status
Simulation time 2622815368 ps
CPU time 10.05 seconds
Started Jan 24 02:49:22 PM PST 24
Finished Jan 24 02:49:44 PM PST 24
Peak memory 222144 kb
Host smart-120c0f1c-201d-40c0-aef9-81c7fa746f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134844198 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3134844198
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2303668333
Short name T40
Test name
Test status
Simulation time 1541785622 ps
CPU time 57.2 seconds
Started Jan 24 02:41:04 PM PST 24
Finished Jan 24 02:42:14 PM PST 24
Peak memory 215092 kb
Host smart-a4451833-4b48-4ad7-9303-f0f120d8ec96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303668333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2303668333
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3733194175
Short name T39
Test name
Test status
Simulation time 328497326 ps
CPU time 15.83 seconds
Started Jan 24 02:49:21 PM PST 24
Finished Jan 24 02:49:49 PM PST 24
Peak memory 221640 kb
Host smart-3fddfdee-f0f0-44bf-a9e8-ef7b0c4e2bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733194175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3733194175
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2281258541
Short name T10
Test name
Test status
Simulation time 3446371392 ps
CPU time 23.77 seconds
Started Jan 24 02:39:08 PM PST 24
Finished Jan 24 02:39:43 PM PST 24
Peak memory 230644 kb
Host smart-7e55f38e-ebea-4a0c-8dc5-2ea0cf32668a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281258541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2281258541
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1394365828
Short name T116
Test name
Test status
Simulation time 1898778573 ps
CPU time 10.04 seconds
Started Jan 24 01:33:35 PM PST 24
Finished Jan 24 01:34:16 PM PST 24
Peak memory 213324 kb
Host smart-d0e282af-727e-4e6c-ba91-bae2b2b11cef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394365828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1394365828
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2351371652
Short name T55
Test name
Test status
Simulation time 61917123029 ps
CPU time 425.4 seconds
Started Jan 24 04:24:29 PM PST 24
Finished Jan 24 04:31:37 PM PST 24
Peak memory 222096 kb
Host smart-e0a8e029-3c42-45d5-b3de-54a3d26dfcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351371652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2351371652
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.532302755
Short name T48
Test name
Test status
Simulation time 2112297306 ps
CPU time 41.71 seconds
Started Jan 24 02:39:57 PM PST 24
Finished Jan 24 02:40:50 PM PST 24
Peak memory 221988 kb
Host smart-16d63bcf-9744-4939-8bdd-080d5c14056d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532302755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.532302755
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3239952314
Short name T7
Test name
Test status
Simulation time 420038881 ps
CPU time 4.37 seconds
Started Jan 24 02:48:45 PM PST 24
Finished Jan 24 02:49:10 PM PST 24
Peak memory 222272 kb
Host smart-9f6256d1-2f63-4bf6-8198-fa5fa05acc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239952314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3239952314
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1377813916
Short name T145
Test name
Test status
Simulation time 908719825 ps
CPU time 27.24 seconds
Started Jan 24 02:49:54 PM PST 24
Finished Jan 24 02:50:44 PM PST 24
Peak memory 214696 kb
Host smart-be0c3e2a-4152-44f2-8837-c31efd01f57a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377813916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1377813916
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2788438922
Short name T43
Test name
Test status
Simulation time 2385079497 ps
CPU time 73.1 seconds
Started Jan 24 03:17:52 PM PST 24
Finished Jan 24 03:19:07 PM PST 24
Peak memory 215128 kb
Host smart-2068d6a9-72a8-4056-898d-af16a223c2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788438922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2788438922
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4065718936
Short name T18
Test name
Test status
Simulation time 153412313 ps
CPU time 3.09 seconds
Started Jan 24 02:42:39 PM PST 24
Finished Jan 24 02:43:07 PM PST 24
Peak memory 209496 kb
Host smart-f2b7349a-9699-4699-a8e6-e8b07bb3cd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065718936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4065718936
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.367521925
Short name T322
Test name
Test status
Simulation time 3057212226 ps
CPU time 128.91 seconds
Started Jan 24 04:17:42 PM PST 24
Finished Jan 24 04:19:56 PM PST 24
Peak memory 214916 kb
Host smart-221c4068-cdbb-4b91-a9f3-466629899af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367521925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.367521925
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1291888784
Short name T23
Test name
Test status
Simulation time 412189040 ps
CPU time 4.73 seconds
Started Jan 24 02:44:42 PM PST 24
Finished Jan 24 02:45:01 PM PST 24
Peak memory 207932 kb
Host smart-aed96ea8-18fe-4d54-be95-f07e1df740af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291888784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1291888784
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1687930246
Short name T399
Test name
Test status
Simulation time 1093062918 ps
CPU time 15.53 seconds
Started Jan 24 02:49:53 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 213900 kb
Host smart-83a717b4-9b12-47b4-8e5f-7ffb6dd81d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687930246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1687930246
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3224280488
Short name T5
Test name
Test status
Simulation time 2213414997 ps
CPU time 31.15 seconds
Started Jan 24 02:47:20 PM PST 24
Finished Jan 24 02:48:21 PM PST 24
Peak memory 221376 kb
Host smart-3e9b72c7-2b54-4c9a-8e13-23808fc8550c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224280488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3224280488
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3972980302
Short name T308
Test name
Test status
Simulation time 1978934639 ps
CPU time 104.23 seconds
Started Jan 24 02:41:10 PM PST 24
Finished Jan 24 02:43:07 PM PST 24
Peak memory 215028 kb
Host smart-90d84d93-4d15-4476-83f4-e7fe6b8432d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972980302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3972980302
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4025999968
Short name T179
Test name
Test status
Simulation time 684039195 ps
CPU time 4.79 seconds
Started Jan 24 02:41:04 PM PST 24
Finished Jan 24 02:41:22 PM PST 24
Peak memory 217328 kb
Host smart-060e7118-9715-447d-adc6-4b0351a5faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025999968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4025999968
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2388388299
Short name T135
Test name
Test status
Simulation time 1347497552 ps
CPU time 70.52 seconds
Started Jan 24 02:45:49 PM PST 24
Finished Jan 24 02:47:04 PM PST 24
Peak memory 213820 kb
Host smart-ab4cdeea-e453-455f-aa00-0b0af3d8ec49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388388299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2388388299
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.273351729
Short name T90
Test name
Test status
Simulation time 457050747 ps
CPU time 5.46 seconds
Started Jan 24 02:50:11 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 213772 kb
Host smart-6cfcf9af-a9b3-4dca-9e98-8af3c0ec78c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273351729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.273351729
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2342402579
Short name T98
Test name
Test status
Simulation time 286894537 ps
CPU time 6.86 seconds
Started Jan 24 02:49:01 PM PST 24
Finished Jan 24 02:49:25 PM PST 24
Peak memory 213684 kb
Host smart-15b39a2b-7ff8-4378-9e96-49a5e21a81a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342402579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2342402579
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3616349116
Short name T120
Test name
Test status
Simulation time 122253068 ps
CPU time 4.29 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 218128 kb
Host smart-97b28211-c06e-4ab2-83cc-842ed56a8d43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616349116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3616349116
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2065694244
Short name T249
Test name
Test status
Simulation time 266355070 ps
CPU time 14.85 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:44 PM PST 24
Peak memory 214676 kb
Host smart-6fe2b129-e869-410a-b3e2-307df38cac42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065694244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2065694244
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3663614314
Short name T33
Test name
Test status
Simulation time 262178780 ps
CPU time 4.21 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:44:58 PM PST 24
Peak memory 207640 kb
Host smart-6ab49bc2-6907-4a52-bf08-eb0112124f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663614314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3663614314
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2737928297
Short name T51
Test name
Test status
Simulation time 1075426248 ps
CPU time 28.43 seconds
Started Jan 24 02:40:45 PM PST 24
Finished Jan 24 02:41:24 PM PST 24
Peak memory 214384 kb
Host smart-d104dfe7-7d66-4bab-b1e9-a9fefc4bec7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737928297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2737928297
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2956569386
Short name T222
Test name
Test status
Simulation time 160297879 ps
CPU time 2.98 seconds
Started Jan 24 02:44:43 PM PST 24
Finished Jan 24 02:45:00 PM PST 24
Peak memory 207900 kb
Host smart-6706be8f-6159-445f-b5e0-80baa554fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956569386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2956569386
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4036078224
Short name T149
Test name
Test status
Simulation time 561646334 ps
CPU time 8.78 seconds
Started Jan 24 01:14:27 PM PST 24
Finished Jan 24 01:15:00 PM PST 24
Peak memory 208416 kb
Host smart-3dda1e1c-bdbb-4acd-b7d0-735f6bf57c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036078224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4036078224
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2666152586
Short name T406
Test name
Test status
Simulation time 1668046647 ps
CPU time 21.1 seconds
Started Jan 24 02:42:13 PM PST 24
Finished Jan 24 02:42:42 PM PST 24
Peak memory 214528 kb
Host smart-1de3fce2-d12d-4cd3-a876-f733efd5095c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666152586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2666152586
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.221325620
Short name T52
Test name
Test status
Simulation time 4874648540 ps
CPU time 48.6 seconds
Started Jan 24 03:03:46 PM PST 24
Finished Jan 24 03:04:55 PM PST 24
Peak memory 214348 kb
Host smart-9b1374a0-7a53-4cf6-bccc-da8ac7c30479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221325620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.221325620
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2192098097
Short name T259
Test name
Test status
Simulation time 57381294 ps
CPU time 3.67 seconds
Started Jan 24 02:46:48 PM PST 24
Finished Jan 24 02:47:00 PM PST 24
Peak memory 221924 kb
Host smart-cd5542de-7fe6-425e-a59c-7420eb511ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192098097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2192098097
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2660127818
Short name T134
Test name
Test status
Simulation time 39635862 ps
CPU time 2.75 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:15:43 PM PST 24
Peak memory 213672 kb
Host smart-cd3e2dea-4116-4a40-8daa-a2476430111e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660127818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2660127818
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2135082348
Short name T6
Test name
Test status
Simulation time 482151806 ps
CPU time 5.72 seconds
Started Jan 24 02:39:02 PM PST 24
Finished Jan 24 02:39:10 PM PST 24
Peak memory 214152 kb
Host smart-29ef08de-e0d6-4755-ba15-4d953907c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135082348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2135082348
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3251146923
Short name T99
Test name
Test status
Simulation time 162788639 ps
CPU time 0.73 seconds
Started Jan 24 02:41:42 PM PST 24
Finished Jan 24 02:41:50 PM PST 24
Peak memory 205408 kb
Host smart-a2c731af-cc42-4104-8de0-b94a98330b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251146923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3251146923
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2189258389
Short name T41
Test name
Test status
Simulation time 3426952732 ps
CPU time 87.25 seconds
Started Jan 24 02:42:47 PM PST 24
Finished Jan 24 02:44:51 PM PST 24
Peak memory 220024 kb
Host smart-b463bcd1-715c-4586-aed4-2e2cde3691f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189258389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2189258389
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3612802611
Short name T263
Test name
Test status
Simulation time 95847113 ps
CPU time 3.87 seconds
Started Jan 24 03:35:10 PM PST 24
Finished Jan 24 03:35:21 PM PST 24
Peak memory 214616 kb
Host smart-7331750a-8829-451c-b194-61ce9937e3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612802611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3612802611
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3042488387
Short name T148
Test name
Test status
Simulation time 311659733 ps
CPU time 10.94 seconds
Started Jan 24 02:20:08 PM PST 24
Finished Jan 24 02:20:38 PM PST 24
Peak memory 208992 kb
Host smart-f7ca174f-5c11-49e3-9764-1ed3125e9eee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042488387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3042488387
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.275656236
Short name T288
Test name
Test status
Simulation time 255317387 ps
CPU time 13.91 seconds
Started Jan 24 02:40:44 PM PST 24
Finished Jan 24 02:41:08 PM PST 24
Peak memory 213704 kb
Host smart-e54d8c19-d00d-458d-8ae7-1f3bb730add9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275656236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.275656236
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3659995233
Short name T243
Test name
Test status
Simulation time 196179191 ps
CPU time 7.91 seconds
Started Jan 24 04:20:26 PM PST 24
Finished Jan 24 04:20:35 PM PST 24
Peak memory 221936 kb
Host smart-b3f4d94d-6a1d-4c39-b1bb-32fa0bb6f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659995233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3659995233
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3204677531
Short name T247
Test name
Test status
Simulation time 3898499250 ps
CPU time 60.32 seconds
Started Jan 24 02:49:42 PM PST 24
Finished Jan 24 02:50:59 PM PST 24
Peak memory 222152 kb
Host smart-b6a13a3c-bb17-4eb0-af50-e9daeff2968f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204677531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3204677531
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3982688244
Short name T109
Test name
Test status
Simulation time 1180353347 ps
CPU time 32.48 seconds
Started Jan 24 02:47:44 PM PST 24
Finished Jan 24 02:48:47 PM PST 24
Peak memory 222036 kb
Host smart-55f2e3c1-57e7-4c6d-a7c6-fde0bec8ecc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982688244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3982688244
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3784460139
Short name T178
Test name
Test status
Simulation time 135402060 ps
CPU time 2.58 seconds
Started Jan 24 02:40:36 PM PST 24
Finished Jan 24 02:40:52 PM PST 24
Peak memory 214268 kb
Host smart-51f7654e-6eab-437a-82d4-2f1354671fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784460139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3784460139
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3788524912
Short name T241
Test name
Test status
Simulation time 118525192 ps
CPU time 3.63 seconds
Started Jan 24 02:56:07 PM PST 24
Finished Jan 24 02:56:13 PM PST 24
Peak memory 210804 kb
Host smart-f5feb511-54b4-4d1d-808a-fa10b878106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788524912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3788524912
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.62276978
Short name T368
Test name
Test status
Simulation time 113198232 ps
CPU time 4.43 seconds
Started Jan 24 02:44:14 PM PST 24
Finished Jan 24 02:44:40 PM PST 24
Peak memory 220696 kb
Host smart-e29e965d-f831-46c7-8cc4-e0bb40bfa1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62276978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.62276978
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4034666949
Short name T4
Test name
Test status
Simulation time 2334837826 ps
CPU time 67.3 seconds
Started Jan 24 02:48:04 PM PST 24
Finished Jan 24 02:49:40 PM PST 24
Peak memory 213872 kb
Host smart-4b00e134-ca3b-424d-bb1c-b5cba53ea6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034666949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4034666949
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3995152331
Short name T146
Test name
Test status
Simulation time 154259992 ps
CPU time 6.48 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:58 PM PST 24
Peak memory 221792 kb
Host smart-23266881-e0d1-4697-a4a0-5a4a8dec9393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995152331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3995152331
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3733270649
Short name T30
Test name
Test status
Simulation time 54218339 ps
CPU time 2.72 seconds
Started Jan 24 02:43:37 PM PST 24
Finished Jan 24 02:44:07 PM PST 24
Peak memory 214144 kb
Host smart-abd9f17f-70b6-417e-ba1c-32bbe90d8e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733270649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3733270649
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3981703585
Short name T332
Test name
Test status
Simulation time 1749792838 ps
CPU time 88.23 seconds
Started Jan 24 03:33:13 PM PST 24
Finished Jan 24 03:34:44 PM PST 24
Peak memory 214760 kb
Host smart-25e75389-69bb-40e5-b51c-5f9fcca24138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981703585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3981703585
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.232253742
Short name T298
Test name
Test status
Simulation time 76786903 ps
CPU time 5.39 seconds
Started Jan 24 02:44:13 PM PST 24
Finished Jan 24 02:44:41 PM PST 24
Peak memory 214776 kb
Host smart-9cc6015f-d041-431f-ba65-17322cd932bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232253742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.232253742
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3636533808
Short name T226
Test name
Test status
Simulation time 1431542218 ps
CPU time 51.06 seconds
Started Jan 24 02:46:02 PM PST 24
Finished Jan 24 02:46:59 PM PST 24
Peak memory 215756 kb
Host smart-3b976708-f71e-4546-8c4b-6388b7a4512b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636533808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3636533808
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1726846484
Short name T85
Test name
Test status
Simulation time 271134563 ps
CPU time 5.51 seconds
Started Jan 24 02:48:48 PM PST 24
Finished Jan 24 02:49:14 PM PST 24
Peak memory 220552 kb
Host smart-a36a19bb-c447-41ad-b8dc-999fe5e4375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726846484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1726846484
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1389473200
Short name T300
Test name
Test status
Simulation time 1188771925 ps
CPU time 16.85 seconds
Started Jan 24 02:49:28 PM PST 24
Finished Jan 24 02:49:58 PM PST 24
Peak memory 221592 kb
Host smart-e3e677b5-a48d-48d5-a5fe-d184508fbf9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389473200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1389473200
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4179184262
Short name T132
Test name
Test status
Simulation time 142325660 ps
CPU time 3.43 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:45 PM PST 24
Peak memory 207776 kb
Host smart-03838f55-2883-4748-ba3f-eeea3017fe19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179184262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4179184262
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2835287304
Short name T84
Test name
Test status
Simulation time 857933580 ps
CPU time 4.05 seconds
Started Jan 24 03:51:31 PM PST 24
Finished Jan 24 03:51:36 PM PST 24
Peak memory 217004 kb
Host smart-4a0e4163-223c-4453-ad2b-07cd01f19b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835287304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2835287304
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2195963691
Short name T174
Test name
Test status
Simulation time 361389944 ps
CPU time 6.79 seconds
Started Jan 24 02:44:17 PM PST 24
Finished Jan 24 02:44:45 PM PST 24
Peak memory 222248 kb
Host smart-7b2fdcc1-d1b8-4d77-b10e-23b1a0ed95cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195963691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2195963691
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.75545701
Short name T342
Test name
Test status
Simulation time 208864541 ps
CPU time 7.63 seconds
Started Jan 24 02:42:05 PM PST 24
Finished Jan 24 02:42:18 PM PST 24
Peak memory 209932 kb
Host smart-51939ba3-6c3c-4254-9947-045dddf164e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75545701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.75545701
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.125953366
Short name T335
Test name
Test status
Simulation time 325814106 ps
CPU time 3.53 seconds
Started Jan 24 02:41:54 PM PST 24
Finished Jan 24 02:42:02 PM PST 24
Peak memory 206096 kb
Host smart-47b204b1-4a05-4790-83ab-12c5bfcee522
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125953366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.125953366
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1589116917
Short name T195
Test name
Test status
Simulation time 4102236986 ps
CPU time 19.32 seconds
Started Jan 24 02:45:53 PM PST 24
Finished Jan 24 02:46:17 PM PST 24
Peak memory 219432 kb
Host smart-5d67f4d6-cdf6-4e2c-94dc-beb766270cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589116917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1589116917
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1424986600
Short name T408
Test name
Test status
Simulation time 111950425 ps
CPU time 6.07 seconds
Started Jan 24 02:39:21 PM PST 24
Finished Jan 24 02:39:42 PM PST 24
Peak memory 213956 kb
Host smart-cc113d65-0377-4675-b66c-c113843ea97b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424986600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1424986600
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2231153138
Short name T166
Test name
Test status
Simulation time 271586255 ps
CPU time 2.85 seconds
Started Jan 24 02:46:04 PM PST 24
Finished Jan 24 02:46:13 PM PST 24
Peak memory 209324 kb
Host smart-17f01ba7-c25e-483a-8975-62bca31626d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231153138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2231153138
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3841453626
Short name T47
Test name
Test status
Simulation time 82657645 ps
CPU time 3.53 seconds
Started Jan 24 02:45:49 PM PST 24
Finished Jan 24 02:45:57 PM PST 24
Peak memory 217636 kb
Host smart-d195e86a-7264-4be6-abfb-97de64acba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841453626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3841453626
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.126261871
Short name T287
Test name
Test status
Simulation time 3495467209 ps
CPU time 33.22 seconds
Started Jan 24 06:21:33 PM PST 24
Finished Jan 24 06:22:09 PM PST 24
Peak memory 221740 kb
Host smart-aac0ae6c-2f68-4fe5-b763-5245031e89ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126261871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.126261871
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3532878172
Short name T217
Test name
Test status
Simulation time 1414445491 ps
CPU time 54.86 seconds
Started Jan 24 02:42:27 PM PST 24
Finished Jan 24 02:43:34 PM PST 24
Peak memory 215864 kb
Host smart-25ada970-33b1-48d6-b841-b34f45a8b8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532878172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3532878172
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1546441203
Short name T319
Test name
Test status
Simulation time 730153431 ps
CPU time 13.61 seconds
Started Jan 24 02:42:40 PM PST 24
Finished Jan 24 02:43:21 PM PST 24
Peak memory 213728 kb
Host smart-fdb50d0f-553f-4e2b-a351-de6689e94a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546441203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1546441203
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.708694386
Short name T225
Test name
Test status
Simulation time 1529944100 ps
CPU time 4.57 seconds
Started Jan 24 02:42:36 PM PST 24
Finished Jan 24 02:42:58 PM PST 24
Peak memory 219304 kb
Host smart-f671c6b6-8037-4011-98b0-53ae4d49c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708694386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.708694386
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3067865372
Short name T258
Test name
Test status
Simulation time 7891591702 ps
CPU time 46.58 seconds
Started Jan 24 02:46:29 PM PST 24
Finished Jan 24 02:47:22 PM PST 24
Peak memory 221372 kb
Host smart-c8fe435e-1b22-42be-bef4-5796d8444ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067865372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3067865372
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.713740013
Short name T250
Test name
Test status
Simulation time 880895529 ps
CPU time 42.43 seconds
Started Jan 24 03:46:33 PM PST 24
Finished Jan 24 03:47:18 PM PST 24
Peak memory 213760 kb
Host smart-3466148c-6415-4e6b-9ddc-b08e5d62e547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713740013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.713740013
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.109346405
Short name T324
Test name
Test status
Simulation time 289063984 ps
CPU time 7.1 seconds
Started Jan 24 02:47:16 PM PST 24
Finished Jan 24 02:47:55 PM PST 24
Peak memory 213740 kb
Host smart-9d43319c-dde2-4539-b83f-9698d2e31a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109346405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.109346405
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2496457096
Short name T150
Test name
Test status
Simulation time 1326950702 ps
CPU time 13.13 seconds
Started Jan 24 01:26:13 PM PST 24
Finished Jan 24 01:27:24 PM PST 24
Peak memory 208816 kb
Host smart-6a18f891-c5e4-4d98-a82a-107c1c47d464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496457096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2496457096
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1514435326
Short name T159
Test name
Test status
Simulation time 199398247 ps
CPU time 5.57 seconds
Started Jan 24 02:38:40 PM PST 24
Finished Jan 24 02:38:54 PM PST 24
Peak memory 209680 kb
Host smart-1616602c-4060-4d16-9517-0ebc60530b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514435326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1514435326
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3659212668
Short name T12
Test name
Test status
Simulation time 2943317757 ps
CPU time 22.43 seconds
Started Jan 24 04:15:16 PM PST 24
Finished Jan 24 04:15:40 PM PST 24
Peak memory 234532 kb
Host smart-532c704d-e401-45fa-bc69-e0972b4ed4da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659212668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3659212668
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1562343180
Short name T153
Test name
Test status
Simulation time 635174603 ps
CPU time 3.97 seconds
Started Jan 24 02:45:09 PM PST 24
Finished Jan 24 02:45:34 PM PST 24
Peak memory 209744 kb
Host smart-a931a368-a362-424f-819b-cfa2225158ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562343180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1562343180
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1594138970
Short name T158
Test name
Test status
Simulation time 698701906 ps
CPU time 4.64 seconds
Started Jan 24 02:49:06 PM PST 24
Finished Jan 24 02:49:27 PM PST 24
Peak memory 210180 kb
Host smart-94c5a029-ca8a-443b-9aa7-30a97a6889b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594138970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1594138970
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3915954509
Short name T176
Test name
Test status
Simulation time 154789772 ps
CPU time 2.95 seconds
Started Jan 24 02:49:40 PM PST 24
Finished Jan 24 02:49:59 PM PST 24
Peak memory 217364 kb
Host smart-04e6cf16-08cd-4052-a60a-1f0b1199444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915954509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3915954509
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.873382565
Short name T180
Test name
Test status
Simulation time 441691380 ps
CPU time 5.55 seconds
Started Jan 24 02:40:43 PM PST 24
Finished Jan 24 02:41:00 PM PST 24
Peak memory 222184 kb
Host smart-4bb19dd5-ed50-4fef-8b42-b1e48ef6a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873382565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.873382565
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.786759303
Short name T731
Test name
Test status
Simulation time 144530048 ps
CPU time 2.97 seconds
Started Jan 24 05:24:20 PM PST 24
Finished Jan 24 05:24:23 PM PST 24
Peak memory 209020 kb
Host smart-3ec307a3-d472-4481-93db-1db8f9a1ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786759303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.786759303
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2775049729
Short name T353
Test name
Test status
Simulation time 147198672 ps
CPU time 3.06 seconds
Started Jan 24 02:41:06 PM PST 24
Finished Jan 24 02:41:21 PM PST 24
Peak memory 221816 kb
Host smart-9633f787-76cb-4e33-87a6-eb1e84f296a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775049729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2775049729
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1848266398
Short name T282
Test name
Test status
Simulation time 2321000353 ps
CPU time 6.14 seconds
Started Jan 24 02:41:11 PM PST 24
Finished Jan 24 02:41:32 PM PST 24
Peak memory 208000 kb
Host smart-8bd8d0a3-c7bc-4bf6-ab74-618e76bed0d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848266398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1848266398
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2015685521
Short name T343
Test name
Test status
Simulation time 1284805473 ps
CPU time 32.6 seconds
Started Jan 24 02:41:31 PM PST 24
Finished Jan 24 02:42:12 PM PST 24
Peak memory 213680 kb
Host smart-5092a85f-7947-4d67-bf89-2005ece0aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015685521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2015685521
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2083111559
Short name T367
Test name
Test status
Simulation time 118268110 ps
CPU time 3.98 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:26 PM PST 24
Peak memory 213748 kb
Host smart-ddfe82b5-3005-45a0-8b14-c01a94efce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083111559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2083111559
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2144400921
Short name T1056
Test name
Test status
Simulation time 100507877 ps
CPU time 3.34 seconds
Started Jan 24 02:42:32 PM PST 24
Finished Jan 24 02:42:49 PM PST 24
Peak memory 208380 kb
Host smart-135c53ab-371e-4f4a-bb0d-b76bea40aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144400921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2144400921
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2192438823
Short name T232
Test name
Test status
Simulation time 41555180 ps
CPU time 3.01 seconds
Started Jan 24 02:42:37 PM PST 24
Finished Jan 24 02:43:03 PM PST 24
Peak memory 213816 kb
Host smart-207066ab-041e-4dcf-b609-b00882e83027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192438823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2192438823
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1519669724
Short name T94
Test name
Test status
Simulation time 79820108 ps
CPU time 3.03 seconds
Started Jan 24 02:42:57 PM PST 24
Finished Jan 24 02:43:34 PM PST 24
Peak memory 222024 kb
Host smart-ed7b4802-1f1f-4a8e-be9a-59eb1a1f00e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519669724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1519669724
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2200192631
Short name T758
Test name
Test status
Simulation time 36447463 ps
CPU time 2.91 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:50 PM PST 24
Peak memory 214556 kb
Host smart-f0a843a5-6770-4b99-89f2-e6811a651d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200192631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2200192631
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3344187692
Short name T89
Test name
Test status
Simulation time 1252724736 ps
CPU time 5.69 seconds
Started Jan 24 02:45:46 PM PST 24
Finished Jan 24 02:45:57 PM PST 24
Peak memory 208908 kb
Host smart-f3ff7abc-80fd-48bf-9380-f2bbb080c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344187692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3344187692
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1791726164
Short name T296
Test name
Test status
Simulation time 41516519 ps
CPU time 2.8 seconds
Started Jan 24 02:46:56 PM PST 24
Finished Jan 24 02:47:18 PM PST 24
Peak memory 213652 kb
Host smart-2a36ab8b-4d8a-4a0f-abf2-d630896dc89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791726164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1791726164
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2705779007
Short name T360
Test name
Test status
Simulation time 459909914 ps
CPU time 4.96 seconds
Started Jan 24 02:48:54 PM PST 24
Finished Jan 24 02:49:18 PM PST 24
Peak memory 213784 kb
Host smart-2f20dec7-e3b3-45ff-8faf-c5380ce0a0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705779007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2705779007
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2272999814
Short name T316
Test name
Test status
Simulation time 3281238533 ps
CPU time 34.81 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:51:25 PM PST 24
Peak memory 221204 kb
Host smart-829bcd82-5876-4f54-894d-eb87e8451c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272999814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2272999814
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_random.2848219587
Short name T329
Test name
Test status
Simulation time 331546387 ps
CPU time 4.17 seconds
Started Jan 24 02:39:43 PM PST 24
Finished Jan 24 02:40:01 PM PST 24
Peak memory 213956 kb
Host smart-313ad92b-cb96-450e-8801-2661b9639820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848219587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2848219587
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.461886947
Short name T177
Test name
Test status
Simulation time 274656746 ps
CPU time 7.08 seconds
Started Jan 24 02:46:53 PM PST 24
Finished Jan 24 02:47:18 PM PST 24
Peak memory 216524 kb
Host smart-d2893507-dd1c-4c3b-adbd-57e5ae2b0dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461886947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.461886947
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.418284724
Short name T567
Test name
Test status
Simulation time 2104337726 ps
CPU time 15.4 seconds
Started Jan 24 01:14:00 PM PST 24
Finished Jan 24 01:14:42 PM PST 24
Peak memory 205496 kb
Host smart-dd9f2bf6-65eb-43b1-86b9-0bb3cc319f85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418284724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.418284724
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2918827193
Short name T474
Test name
Test status
Simulation time 1724872538 ps
CPU time 13.43 seconds
Started Jan 24 01:14:08 PM PST 24
Finished Jan 24 01:14:47 PM PST 24
Peak memory 205492 kb
Host smart-acf1daa6-464c-4897-836f-ab6f05b1548b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918827193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
918827193
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2794162146
Short name T137
Test name
Test status
Simulation time 58322305 ps
CPU time 1.12 seconds
Started Jan 24 01:13:59 PM PST 24
Finished Jan 24 01:14:27 PM PST 24
Peak memory 205564 kb
Host smart-1a2082e5-3d0e-453f-bea5-4bd4959e19e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794162146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
794162146
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.478618176
Short name T514
Test name
Test status
Simulation time 31885067 ps
CPU time 1.71 seconds
Started Jan 24 01:14:25 PM PST 24
Finished Jan 24 01:14:50 PM PST 24
Peak memory 213676 kb
Host smart-c0eac9e1-9b41-44c0-a5f3-d671a2f74e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478618176 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.478618176
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3713779167
Short name T425
Test name
Test status
Simulation time 106066019 ps
CPU time 1.54 seconds
Started Jan 24 01:14:01 PM PST 24
Finished Jan 24 01:14:29 PM PST 24
Peak memory 205572 kb
Host smart-c7e775fd-0dee-4c1a-9232-c71fe2f6e2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713779167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3713779167
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.931223268
Short name T529
Test name
Test status
Simulation time 12644672 ps
CPU time 0.85 seconds
Started Jan 24 01:14:07 PM PST 24
Finished Jan 24 01:14:33 PM PST 24
Peak memory 205224 kb
Host smart-10421f8f-1580-4b24-ac07-f95f56f29607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931223268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.931223268
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3009989103
Short name T501
Test name
Test status
Simulation time 31129195 ps
CPU time 1.44 seconds
Started Jan 24 01:14:08 PM PST 24
Finished Jan 24 01:14:35 PM PST 24
Peak memory 205540 kb
Host smart-e94601c6-d6e2-48c4-9152-711388e047da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009989103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3009989103
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2213415631
Short name T465
Test name
Test status
Simulation time 245848850 ps
CPU time 1.86 seconds
Started Jan 24 01:14:08 PM PST 24
Finished Jan 24 01:14:35 PM PST 24
Peak memory 213928 kb
Host smart-6c795a43-3263-471f-904f-93f26a84ee3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213415631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2213415631
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1481477794
Short name T533
Test name
Test status
Simulation time 4999669242 ps
CPU time 14.73 seconds
Started Jan 24 01:14:08 PM PST 24
Finished Jan 24 01:14:47 PM PST 24
Peak memory 213820 kb
Host smart-b7ffe33f-31dd-4321-b5c5-a01c415fd153
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481477794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1481477794
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3825029890
Short name T432
Test name
Test status
Simulation time 202322553 ps
CPU time 3.12 seconds
Started Jan 24 01:13:59 PM PST 24
Finished Jan 24 01:14:29 PM PST 24
Peak memory 216856 kb
Host smart-500973a7-711d-4ee2-9b46-811a9988fd96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825029890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3825029890
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1861535111
Short name T133
Test name
Test status
Simulation time 1017156162 ps
CPU time 5.47 seconds
Started Jan 24 01:14:08 PM PST 24
Finished Jan 24 01:14:39 PM PST 24
Peak memory 208676 kb
Host smart-fadc8801-904d-48fc-b291-9f9c1e29358e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861535111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1861535111
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4102200868
Short name T548
Test name
Test status
Simulation time 132415948 ps
CPU time 8.77 seconds
Started Jan 24 01:14:13 PM PST 24
Finished Jan 24 01:14:45 PM PST 24
Peak memory 205412 kb
Host smart-e763183a-204d-41e1-a3a9-162be58677ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102200868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
102200868
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3112765403
Short name T515
Test name
Test status
Simulation time 613776216 ps
CPU time 15.2 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 205504 kb
Host smart-9c5253ba-dd83-4c78-92d8-69af0d612d7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112765403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
112765403
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.204958487
Short name T466
Test name
Test status
Simulation time 198467819 ps
CPU time 1.19 seconds
Started Jan 24 01:14:18 PM PST 24
Finished Jan 24 01:14:40 PM PST 24
Peak memory 205476 kb
Host smart-82e1be6f-278a-4862-ba20-3cbd43f58c74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204958487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.204958487
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.84858061
Short name T437
Test name
Test status
Simulation time 12565424 ps
CPU time 0.87 seconds
Started Jan 24 01:14:20 PM PST 24
Finished Jan 24 01:14:41 PM PST 24
Peak memory 205348 kb
Host smart-dc7a8ead-8d9f-4f34-96d5-96ffcda90475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84858061 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.84858061
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3063210956
Short name T476
Test name
Test status
Simulation time 107850088 ps
CPU time 1.34 seconds
Started Jan 24 01:14:25 PM PST 24
Finished Jan 24 01:14:50 PM PST 24
Peak memory 205372 kb
Host smart-553b24d7-3732-452b-b577-0696310082cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063210956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3063210956
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3342076164
Short name T183
Test name
Test status
Simulation time 32720515 ps
CPU time 0.71 seconds
Started Jan 24 01:14:22 PM PST 24
Finished Jan 24 01:14:44 PM PST 24
Peak memory 205128 kb
Host smart-e0c33490-79c2-44f7-83af-75fc713bf33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342076164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3342076164
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1288558970
Short name T142
Test name
Test status
Simulation time 171457736 ps
CPU time 3.23 seconds
Started Jan 24 01:14:23 PM PST 24
Finished Jan 24 01:14:48 PM PST 24
Peak memory 205500 kb
Host smart-a9f59ec4-42a4-4afb-b4b0-9e48fda7089a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288558970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1288558970
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2890699075
Short name T452
Test name
Test status
Simulation time 191182459 ps
CPU time 4.84 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:46 PM PST 24
Peak memory 222104 kb
Host smart-7ba9a935-5d5e-46eb-9d83-c3da8b4547ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890699075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2890699075
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.48979868
Short name T555
Test name
Test status
Simulation time 79967070 ps
CPU time 3.61 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:46 PM PST 24
Peak memory 213920 kb
Host smart-cb795e11-a593-414f-b39c-e7790cf1bd97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48979868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_shadow_reg_errors_with_csr_rw.48979868
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1300375833
Short name T125
Test name
Test status
Simulation time 84349256 ps
CPU time 2.28 seconds
Started Jan 24 01:14:20 PM PST 24
Finished Jan 24 01:14:43 PM PST 24
Peak memory 213596 kb
Host smart-45256e46-7695-4dbd-932f-2e034aae8d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300375833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1300375833
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3019329159
Short name T161
Test name
Test status
Simulation time 208695436 ps
CPU time 4.89 seconds
Started Jan 24 01:14:15 PM PST 24
Finished Jan 24 01:14:42 PM PST 24
Peak memory 208752 kb
Host smart-9a9944a3-d1ca-4492-a1f3-1edb81bbd39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019329159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3019329159
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3076376695
Short name T457
Test name
Test status
Simulation time 235241133 ps
CPU time 1.33 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:15:41 PM PST 24
Peak memory 213732 kb
Host smart-706e00a8-8277-4246-8f46-2ce9be813dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076376695 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3076376695
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3871129417
Short name T534
Test name
Test status
Simulation time 110936330 ps
CPU time 1.52 seconds
Started Jan 24 01:15:10 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 205480 kb
Host smart-9b826bd8-2e9b-4dc8-ac60-76d800fa8463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871129417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3871129417
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2681093441
Short name T560
Test name
Test status
Simulation time 22803778 ps
CPU time 1 seconds
Started Jan 24 01:15:03 PM PST 24
Finished Jan 24 01:15:35 PM PST 24
Peak memory 205340 kb
Host smart-780a52de-0649-493a-b309-e0fe55438ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681093441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2681093441
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.133833364
Short name T520
Test name
Test status
Simulation time 103067303 ps
CPU time 2.36 seconds
Started Jan 24 01:15:09 PM PST 24
Finished Jan 24 01:15:45 PM PST 24
Peak memory 205548 kb
Host smart-2d372eb2-b368-42f5-bb15-8d0f07005445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133833364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.133833364
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2985962534
Short name T486
Test name
Test status
Simulation time 108099630 ps
CPU time 3.07 seconds
Started Jan 24 01:14:59 PM PST 24
Finished Jan 24 01:15:32 PM PST 24
Peak memory 213944 kb
Host smart-daecca26-d1a3-4b79-80b1-9bd83535d837
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985962534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2985962534
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3283553001
Short name T122
Test name
Test status
Simulation time 203102560 ps
CPU time 5.26 seconds
Started Jan 24 01:14:58 PM PST 24
Finished Jan 24 01:15:33 PM PST 24
Peak memory 214020 kb
Host smart-0599b114-9602-4957-a732-052d30287da7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283553001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3283553001
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1453453093
Short name T551
Test name
Test status
Simulation time 25119990 ps
CPU time 1.92 seconds
Started Jan 24 01:14:55 PM PST 24
Finished Jan 24 01:15:26 PM PST 24
Peak memory 213672 kb
Host smart-e764fdb0-dc55-4859-b182-da6f93e8ff7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453453093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1453453093
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2703956232
Short name T165
Test name
Test status
Simulation time 57830945 ps
CPU time 3.18 seconds
Started Jan 24 01:15:03 PM PST 24
Finished Jan 24 01:15:38 PM PST 24
Peak memory 208336 kb
Host smart-b990bd23-f32f-49f1-90ef-368fd87ee63f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703956232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2703956232
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3021617779
Short name T485
Test name
Test status
Simulation time 25077987 ps
CPU time 1.2 seconds
Started Jan 24 01:15:21 PM PST 24
Finished Jan 24 01:16:07 PM PST 24
Peak memory 213696 kb
Host smart-8871f335-d4ce-4af6-b7e3-f14a43174928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021617779 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3021617779
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.951379755
Short name T143
Test name
Test status
Simulation time 17333834 ps
CPU time 1.04 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:51 PM PST 24
Peak memory 205268 kb
Host smart-220db0d5-0a44-4724-9224-19b60035504f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951379755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.951379755
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2894725783
Short name T509
Test name
Test status
Simulation time 33467594 ps
CPU time 0.69 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:15:41 PM PST 24
Peak memory 205184 kb
Host smart-47fd74d8-a8e3-4b8a-ad18-d7744944d999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894725783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2894725783
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4242004955
Short name T556
Test name
Test status
Simulation time 56841770 ps
CPU time 1.76 seconds
Started Jan 24 01:15:07 PM PST 24
Finished Jan 24 01:15:40 PM PST 24
Peak memory 205528 kb
Host smart-1263cfdb-fd63-4f36-b4e8-7cb035c377f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242004955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4242004955
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1492432039
Short name T121
Test name
Test status
Simulation time 187517833 ps
CPU time 3.97 seconds
Started Jan 24 01:15:02 PM PST 24
Finished Jan 24 01:15:37 PM PST 24
Peak memory 222064 kb
Host smart-6cd288c8-e144-470b-a7f8-c323272ba411
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492432039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1492432039
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2406210241
Short name T462
Test name
Test status
Simulation time 182399588 ps
CPU time 4.81 seconds
Started Jan 24 01:15:07 PM PST 24
Finished Jan 24 01:15:43 PM PST 24
Peak memory 219624 kb
Host smart-847ba519-7529-4772-9e4b-7344b3e66549
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406210241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2406210241
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2991716684
Short name T530
Test name
Test status
Simulation time 134664205 ps
CPU time 2.32 seconds
Started Jan 24 01:15:09 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 215880 kb
Host smart-da596476-548d-4da4-803e-78bf052c1ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991716684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2991716684
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2991278220
Short name T167
Test name
Test status
Simulation time 175443210 ps
CPU time 5.96 seconds
Started Jan 24 01:15:07 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 208688 kb
Host smart-8056a611-06dc-4bff-8d94-834d3a8ba8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991278220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2991278220
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.775592212
Short name T563
Test name
Test status
Simulation time 113442239 ps
CPU time 1.2 seconds
Started Jan 24 01:15:22 PM PST 24
Finished Jan 24 01:16:08 PM PST 24
Peak memory 216468 kb
Host smart-1e13d3f0-fbc2-41cc-bab7-097c4b2959fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775592212 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.775592212
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1379867702
Short name T438
Test name
Test status
Simulation time 59713522 ps
CPU time 1.6 seconds
Started Jan 24 01:15:09 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 205516 kb
Host smart-846571ba-6f76-43a5-b04e-68c20680b9ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379867702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1379867702
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3085184266
Short name T475
Test name
Test status
Simulation time 120214715 ps
CPU time 0.92 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:52 PM PST 24
Peak memory 205056 kb
Host smart-3fc7f533-73b6-4793-af14-2439c7f41ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085184266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3085184266
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3941985663
Short name T141
Test name
Test status
Simulation time 104218477 ps
CPU time 2.54 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:48 PM PST 24
Peak memory 205496 kb
Host smart-2174e36e-4644-43a1-9da1-56be27029900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941985663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3941985663
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3053041590
Short name T172
Test name
Test status
Simulation time 270046314 ps
CPU time 3.26 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:54 PM PST 24
Peak memory 213676 kb
Host smart-fd0c66fd-f58a-4c58-92f8-a19f93b25663
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053041590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3053041590
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1191427081
Short name T518
Test name
Test status
Simulation time 89605503 ps
CPU time 4.07 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 213976 kb
Host smart-5b542c45-bed5-43d3-a095-1fcc4a23343f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191427081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1191427081
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.865887248
Short name T489
Test name
Test status
Simulation time 66205356 ps
CPU time 1.32 seconds
Started Jan 24 01:30:05 PM PST 24
Finished Jan 24 01:30:34 PM PST 24
Peak memory 213788 kb
Host smart-50515d2d-6393-4bac-ad96-3d05260eacfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865887248 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.865887248
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1146402551
Short name T415
Test name
Test status
Simulation time 11252941 ps
CPU time 0.86 seconds
Started Jan 24 01:37:56 PM PST 24
Finished Jan 24 01:38:24 PM PST 24
Peak memory 205208 kb
Host smart-169c2833-2245-41c8-ac24-3d5cc2d8ad7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146402551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1146402551
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.386415772
Short name T448
Test name
Test status
Simulation time 141732224 ps
CPU time 2.17 seconds
Started Jan 24 01:15:09 PM PST 24
Finished Jan 24 01:15:44 PM PST 24
Peak memory 205520 kb
Host smart-58afebbc-b99b-4ba1-91c3-61e36c44e511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386415772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.386415772
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2764929006
Short name T467
Test name
Test status
Simulation time 1287116645 ps
CPU time 7.71 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:53 PM PST 24
Peak memory 213844 kb
Host smart-8b38993c-f38d-4dd6-a39e-6c70fc96de54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764929006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2764929006
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3299336694
Short name T545
Test name
Test status
Simulation time 3901007892 ps
CPU time 13.01 seconds
Started Jan 24 01:15:21 PM PST 24
Finished Jan 24 01:16:19 PM PST 24
Peak memory 213976 kb
Host smart-184394b0-9833-4a73-b818-066cd1fe828d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299336694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3299336694
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4061982810
Short name T482
Test name
Test status
Simulation time 168761803 ps
CPU time 3.32 seconds
Started Jan 24 01:15:09 PM PST 24
Finished Jan 24 01:15:45 PM PST 24
Peak memory 216772 kb
Host smart-d19434ce-cc56-40ad-a2db-d8cc55283f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061982810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4061982810
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4075095889
Short name T440
Test name
Test status
Simulation time 86494886 ps
CPU time 1.75 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:15:42 PM PST 24
Peak memory 213796 kb
Host smart-57bf4d5c-2a45-49e6-869c-1cd7d303a527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075095889 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4075095889
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1012281664
Short name T477
Test name
Test status
Simulation time 38378283 ps
CPU time 0.88 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 205184 kb
Host smart-c8a8439d-85cc-46c0-a7d2-4d5541698021
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012281664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1012281664
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2212771759
Short name T470
Test name
Test status
Simulation time 20978306 ps
CPU time 0.72 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:47 PM PST 24
Peak memory 205192 kb
Host smart-f569c194-7f56-4e0a-ba2c-5c687762ecd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212771759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2212771759
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2395987793
Short name T553
Test name
Test status
Simulation time 288509832 ps
CPU time 4.14 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:49 PM PST 24
Peak memory 205396 kb
Host smart-87ab292e-e595-43b9-a1db-a24c0541d851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395987793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2395987793
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1662017748
Short name T118
Test name
Test status
Simulation time 115256392 ps
CPU time 2.54 seconds
Started Jan 24 01:38:51 PM PST 24
Finished Jan 24 01:39:05 PM PST 24
Peak memory 213924 kb
Host smart-9ed51784-b0a5-40d3-aa11-e0225704b0ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662017748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1662017748
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1744601086
Short name T565
Test name
Test status
Simulation time 161727023 ps
CPU time 4.48 seconds
Started Jan 24 01:43:58 PM PST 24
Finished Jan 24 01:44:15 PM PST 24
Peak memory 214004 kb
Host smart-b3a0e478-1cac-4a1b-8606-a15a33bcb711
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744601086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1744601086
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3913048677
Short name T127
Test name
Test status
Simulation time 104136654 ps
CPU time 1.84 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:48 PM PST 24
Peak memory 213664 kb
Host smart-668c2530-4478-453c-ad54-ef78d8a9c832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913048677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3913048677
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.65795947
Short name T126
Test name
Test status
Simulation time 1103534094 ps
CPU time 13.22 seconds
Started Jan 24 01:40:51 PM PST 24
Finished Jan 24 01:41:47 PM PST 24
Peak memory 208352 kb
Host smart-bf04d002-8ad1-4ab4-a136-c17aa977618c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65795947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.65795947
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2007666499
Short name T439
Test name
Test status
Simulation time 157159341 ps
CPU time 1.59 seconds
Started Jan 24 01:30:55 PM PST 24
Finished Jan 24 01:31:46 PM PST 24
Peak memory 205492 kb
Host smart-42b29c6b-1300-4e06-8612-d92c440816f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007666499 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2007666499
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3096351696
Short name T447
Test name
Test status
Simulation time 43461196 ps
CPU time 1.16 seconds
Started Jan 24 01:15:11 PM PST 24
Finished Jan 24 01:15:46 PM PST 24
Peak memory 205516 kb
Host smart-2ae7c4d4-f262-410a-a009-d5f2a50f980d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096351696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3096351696
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2952436080
Short name T519
Test name
Test status
Simulation time 19005107 ps
CPU time 0.71 seconds
Started Jan 24 01:15:14 PM PST 24
Finished Jan 24 01:15:53 PM PST 24
Peak memory 204992 kb
Host smart-b2425e45-3491-4756-9882-f6ed41cc5ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952436080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2952436080
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3661304873
Short name T508
Test name
Test status
Simulation time 363246076 ps
CPU time 3.56 seconds
Started Jan 24 01:15:20 PM PST 24
Finished Jan 24 01:16:09 PM PST 24
Peak memory 205340 kb
Host smart-57e8caa9-f3d7-4ed7-a9e4-1edd6c0d675a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661304873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3661304873
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3593867639
Short name T504
Test name
Test status
Simulation time 309714769 ps
CPU time 2.74 seconds
Started Jan 24 01:49:01 PM PST 24
Finished Jan 24 01:49:19 PM PST 24
Peak memory 213848 kb
Host smart-e33972af-59e9-48d2-9974-7e704543aa28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593867639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3593867639
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1767551932
Short name T531
Test name
Test status
Simulation time 751472181 ps
CPU time 4.24 seconds
Started Jan 24 01:48:29 PM PST 24
Finished Jan 24 01:48:34 PM PST 24
Peak memory 214024 kb
Host smart-92ee3fc0-d036-42c8-bc95-5cec43bf018c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767551932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1767551932
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.564561692
Short name T513
Test name
Test status
Simulation time 92374126 ps
CPU time 3.17 seconds
Started Jan 24 01:15:20 PM PST 24
Finished Jan 24 01:16:08 PM PST 24
Peak memory 213544 kb
Host smart-1df74f58-b3f4-4bb1-9c61-3ae551b48c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564561692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.564561692
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1674371677
Short name T160
Test name
Test status
Simulation time 255741102 ps
CPU time 7.49 seconds
Started Jan 24 01:41:50 PM PST 24
Finished Jan 24 01:42:00 PM PST 24
Peak memory 208568 kb
Host smart-e5439475-6207-4e74-81f3-3031528cd1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674371677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1674371677
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1191908816
Short name T493
Test name
Test status
Simulation time 82623513 ps
CPU time 1.4 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:52 PM PST 24
Peak memory 205416 kb
Host smart-337431c9-e19c-4f4e-9e9a-dda09b4ebfee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191908816 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1191908816
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3315921821
Short name T543
Test name
Test status
Simulation time 29633247 ps
CPU time 1.17 seconds
Started Jan 24 01:15:19 PM PST 24
Finished Jan 24 01:16:06 PM PST 24
Peak memory 205400 kb
Host smart-d10a8552-56dd-4c7f-927d-681164a9a3b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315921821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3315921821
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.420162539
Short name T456
Test name
Test status
Simulation time 11648645 ps
CPU time 0.84 seconds
Started Jan 24 01:28:10 PM PST 24
Finished Jan 24 01:28:37 PM PST 24
Peak memory 205200 kb
Host smart-439fde91-5685-4e43-b303-01cc96b65778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420162539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.420162539
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3888447603
Short name T458
Test name
Test status
Simulation time 92396971 ps
CPU time 1.53 seconds
Started Jan 24 01:48:10 PM PST 24
Finished Jan 24 01:48:18 PM PST 24
Peak memory 205548 kb
Host smart-dc4f9b5a-d4e6-44b5-8852-b9f60ce99f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888447603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3888447603
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1318295526
Short name T488
Test name
Test status
Simulation time 189795622 ps
CPU time 4.02 seconds
Started Jan 24 02:02:24 PM PST 24
Finished Jan 24 02:02:42 PM PST 24
Peak memory 213920 kb
Host smart-014e674b-dd5e-4f46-b307-45def9596daa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318295526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1318295526
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.817808314
Short name T463
Test name
Test status
Simulation time 71101087 ps
CPU time 2.44 seconds
Started Jan 24 01:15:20 PM PST 24
Finished Jan 24 01:16:08 PM PST 24
Peak memory 213620 kb
Host smart-6d9c098a-f70b-45ed-a0f8-a6a0361ed985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817808314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.817808314
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2158845966
Short name T156
Test name
Test status
Simulation time 408892230 ps
CPU time 3.5 seconds
Started Jan 24 01:38:33 PM PST 24
Finished Jan 24 01:38:59 PM PST 24
Peak memory 208844 kb
Host smart-8ee38683-c065-4030-a627-aab9123805e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158845966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2158845966
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1202114122
Short name T550
Test name
Test status
Simulation time 57368468 ps
CPU time 1.35 seconds
Started Jan 24 01:21:48 PM PST 24
Finished Jan 24 01:22:47 PM PST 24
Peak memory 213740 kb
Host smart-51cf9df5-09a9-4c5a-ba75-552361276f8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202114122 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1202114122
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1276996830
Short name T511
Test name
Test status
Simulation time 95064915 ps
CPU time 1.06 seconds
Started Jan 24 01:15:15 PM PST 24
Finished Jan 24 01:15:56 PM PST 24
Peak memory 205568 kb
Host smart-c7356a6d-655e-41be-9e0d-3936134e51e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276996830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1276996830
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.785233057
Short name T459
Test name
Test status
Simulation time 52266509 ps
CPU time 0.75 seconds
Started Jan 24 01:15:17 PM PST 24
Finished Jan 24 01:16:01 PM PST 24
Peak memory 205076 kb
Host smart-ff77c42a-5827-4bad-9f42-c9fd3fa3c2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785233057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.785233057
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.690272796
Short name T537
Test name
Test status
Simulation time 222062286 ps
CPU time 2.48 seconds
Started Jan 24 01:44:08 PM PST 24
Finished Jan 24 01:44:26 PM PST 24
Peak memory 205552 kb
Host smart-bfdc14c1-24fd-48a1-9150-a2a3fd829404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690272796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.690272796
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3861398801
Short name T444
Test name
Test status
Simulation time 82755347 ps
CPU time 2.7 seconds
Started Jan 24 01:15:16 PM PST 24
Finished Jan 24 01:16:00 PM PST 24
Peak memory 221936 kb
Host smart-d7b2a5ef-3d7c-4da3-ae3d-c099751414e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861398801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3861398801
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3459563429
Short name T144
Test name
Test status
Simulation time 944625495 ps
CPU time 8.57 seconds
Started Jan 24 02:57:25 PM PST 24
Finished Jan 24 02:57:49 PM PST 24
Peak memory 214068 kb
Host smart-391e9452-c347-48f1-9150-cd37035bb1ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459563429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3459563429
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2618631955
Short name T427
Test name
Test status
Simulation time 76116723 ps
CPU time 2.52 seconds
Started Jan 24 01:15:16 PM PST 24
Finished Jan 24 01:16:00 PM PST 24
Peak memory 213532 kb
Host smart-5402e771-a299-47c7-bc76-02f73cba9b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618631955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2618631955
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.573424755
Short name T147
Test name
Test status
Simulation time 115946131 ps
CPU time 5.08 seconds
Started Jan 24 02:42:39 PM PST 24
Finished Jan 24 02:43:11 PM PST 24
Peak memory 208516 kb
Host smart-3a4363f3-2ffb-4c3a-8d4c-6030dd1da3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573424755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.573424755
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1536173263
Short name T549
Test name
Test status
Simulation time 16148687 ps
CPU time 1.3 seconds
Started Jan 24 01:15:16 PM PST 24
Finished Jan 24 01:15:58 PM PST 24
Peak memory 213628 kb
Host smart-ce203061-37e6-4f14-a5a4-4e48cf015f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536173263 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1536173263
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3871270262
Short name T468
Test name
Test status
Simulation time 337073671 ps
CPU time 1.25 seconds
Started Jan 24 01:19:56 PM PST 24
Finished Jan 24 01:21:00 PM PST 24
Peak memory 205412 kb
Host smart-3ffe6c22-7b2f-44a5-b5cf-b38b484bc791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871270262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3871270262
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4110147669
Short name T517
Test name
Test status
Simulation time 38868053 ps
CPU time 0.72 seconds
Started Jan 24 01:15:12 PM PST 24
Finished Jan 24 01:15:48 PM PST 24
Peak memory 205168 kb
Host smart-ab13c7d7-86c3-4d7b-a74b-1f7c711235cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110147669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4110147669
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4274193710
Short name T526
Test name
Test status
Simulation time 215007643 ps
CPU time 1.67 seconds
Started Jan 24 01:44:12 PM PST 24
Finished Jan 24 01:44:31 PM PST 24
Peak memory 205448 kb
Host smart-c1b53c26-8497-4003-a46b-fcd96dd40727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274193710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4274193710
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.704347989
Short name T115
Test name
Test status
Simulation time 129724028 ps
CPU time 1.34 seconds
Started Jan 24 01:15:13 PM PST 24
Finished Jan 24 01:15:51 PM PST 24
Peak memory 213944 kb
Host smart-44deb9be-816e-4707-8691-27b1d82b81ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704347989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.704347989
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3430666301
Short name T117
Test name
Test status
Simulation time 1383940685 ps
CPU time 8.84 seconds
Started Jan 24 01:29:00 PM PST 24
Finished Jan 24 01:29:25 PM PST 24
Peak memory 219748 kb
Host smart-49539c9f-4b14-4854-ba37-e6e59c6b13be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430666301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3430666301
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1481978623
Short name T536
Test name
Test status
Simulation time 302972530 ps
CPU time 2.21 seconds
Started Jan 24 01:40:05 PM PST 24
Finished Jan 24 01:40:57 PM PST 24
Peak memory 213668 kb
Host smart-fd44c51c-0982-476f-b48e-31fadb4cc5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481978623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1481978623
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.465384716
Short name T168
Test name
Test status
Simulation time 2305749956 ps
CPU time 9.34 seconds
Started Jan 24 01:15:14 PM PST 24
Finished Jan 24 01:16:02 PM PST 24
Peak memory 209156 kb
Host smart-58876f2c-3e35-4264-bc56-c593db03921a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465384716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.465384716
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.821094290
Short name T505
Test name
Test status
Simulation time 58005262 ps
CPU time 1.29 seconds
Started Jan 24 01:25:18 PM PST 24
Finished Jan 24 01:26:05 PM PST 24
Peak memory 213744 kb
Host smart-985865ef-fae4-4731-8582-680697671b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821094290 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.821094290
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1041753553
Short name T139
Test name
Test status
Simulation time 28283674 ps
CPU time 1.48 seconds
Started Jan 24 01:29:38 PM PST 24
Finished Jan 24 01:29:53 PM PST 24
Peak memory 205500 kb
Host smart-8281509b-dbac-4838-98f9-30c56077d7e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041753553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1041753553
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2801135842
Short name T495
Test name
Test status
Simulation time 9759477 ps
CPU time 0.77 seconds
Started Jan 24 01:20:09 PM PST 24
Finished Jan 24 01:21:14 PM PST 24
Peak memory 205140 kb
Host smart-7fbba6f1-8984-42cb-a0b7-c0786dc19639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801135842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2801135842
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.692527147
Short name T186
Test name
Test status
Simulation time 108962140 ps
CPU time 3.05 seconds
Started Jan 24 01:15:28 PM PST 24
Finished Jan 24 01:16:18 PM PST 24
Peak memory 205588 kb
Host smart-9494b502-29ba-4b5e-86e2-c4b8fae0ab10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692527147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.692527147
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2545441465
Short name T170
Test name
Test status
Simulation time 45607724 ps
CPU time 2.08 seconds
Started Jan 24 01:33:16 PM PST 24
Finished Jan 24 01:33:40 PM PST 24
Peak memory 214004 kb
Host smart-a19cc563-0fba-4bb1-9a49-795af302c36b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545441465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2545441465
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.364407268
Short name T140
Test name
Test status
Simulation time 217332450 ps
CPU time 5.22 seconds
Started Jan 24 01:32:45 PM PST 24
Finished Jan 24 01:33:24 PM PST 24
Peak memory 213992 kb
Host smart-cfde5115-c7ca-4ac2-80ed-c3bffeda7b85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364407268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.364407268
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3618015926
Short name T424
Test name
Test status
Simulation time 125603505 ps
CPU time 4.9 seconds
Started Jan 24 01:40:16 PM PST 24
Finished Jan 24 01:41:18 PM PST 24
Peak memory 215880 kb
Host smart-1762a485-4147-4f5e-a0f4-33983b6d3f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618015926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3618015926
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3875925422
Short name T516
Test name
Test status
Simulation time 1790293761 ps
CPU time 7.65 seconds
Started Jan 24 01:14:22 PM PST 24
Finished Jan 24 01:14:50 PM PST 24
Peak memory 205488 kb
Host smart-a95755d7-ec90-4854-a280-d6b95eb8157f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875925422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
875925422
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.861637888
Short name T441
Test name
Test status
Simulation time 254393724 ps
CPU time 15.12 seconds
Started Jan 24 01:14:18 PM PST 24
Finished Jan 24 01:14:55 PM PST 24
Peak memory 205560 kb
Host smart-baa0b415-6528-4dd7-b44b-ad4dc3f39054
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861637888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.861637888
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2244398784
Short name T449
Test name
Test status
Simulation time 237020930 ps
CPU time 1.17 seconds
Started Jan 24 01:14:20 PM PST 24
Finished Jan 24 01:14:42 PM PST 24
Peak memory 205532 kb
Host smart-a6437033-c01b-45d7-9cfa-78333b153b44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244398784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
244398784
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3397912966
Short name T129
Test name
Test status
Simulation time 83386358 ps
CPU time 1.67 seconds
Started Jan 24 01:14:27 PM PST 24
Finished Jan 24 01:14:53 PM PST 24
Peak memory 213600 kb
Host smart-f1a96986-9cf9-4719-97a6-5be7e8b200f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397912966 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3397912966
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3428959358
Short name T525
Test name
Test status
Simulation time 18956157 ps
CPU time 1.17 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:43 PM PST 24
Peak memory 205460 kb
Host smart-c3f5d020-e844-4b8f-99a9-e0771689dcbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428959358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3428959358
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3741314508
Short name T446
Test name
Test status
Simulation time 12732449 ps
CPU time 0.96 seconds
Started Jan 24 01:14:15 PM PST 24
Finished Jan 24 01:14:38 PM PST 24
Peak memory 205228 kb
Host smart-5552a84b-6b37-4ede-a235-45e972497abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741314508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3741314508
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3395694776
Short name T433
Test name
Test status
Simulation time 73046059 ps
CPU time 1.83 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:54 PM PST 24
Peak memory 205468 kb
Host smart-178b88b6-2e66-4e1f-b856-2c419a615434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395694776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3395694776
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.946506485
Short name T527
Test name
Test status
Simulation time 228802783 ps
CPU time 5.4 seconds
Started Jan 24 01:14:14 PM PST 24
Finished Jan 24 01:14:42 PM PST 24
Peak memory 213820 kb
Host smart-de53990f-3391-4332-a6d4-77dcce2be49e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946506485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.946506485
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2628465830
Short name T559
Test name
Test status
Simulation time 1934215111 ps
CPU time 16 seconds
Started Jan 24 01:14:21 PM PST 24
Finished Jan 24 01:14:58 PM PST 24
Peak memory 213932 kb
Host smart-016a8f00-9bc2-49ac-a9aa-78ad533c418d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628465830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2628465830
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.316550036
Short name T128
Test name
Test status
Simulation time 115718566 ps
CPU time 4.12 seconds
Started Jan 24 01:14:18 PM PST 24
Finished Jan 24 01:14:44 PM PST 24
Peak memory 215960 kb
Host smart-a87c2765-66e1-414d-85bf-ca21067b7a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316550036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.316550036
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3576687349
Short name T496
Test name
Test status
Simulation time 8428802 ps
CPU time 0.8 seconds
Started Jan 24 01:15:33 PM PST 24
Finished Jan 24 01:16:22 PM PST 24
Peak memory 205148 kb
Host smart-cdd897e0-4f57-44fb-8c24-c7b7c40ab731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576687349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3576687349
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3433316325
Short name T510
Test name
Test status
Simulation time 40687112 ps
CPU time 0.9 seconds
Started Jan 24 01:15:32 PM PST 24
Finished Jan 24 01:16:21 PM PST 24
Peak memory 205372 kb
Host smart-cf61f3e3-1fc9-49e2-beca-e9853ba6aa7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433316325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3433316325
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2335737401
Short name T528
Test name
Test status
Simulation time 8669930 ps
CPU time 0.85 seconds
Started Jan 24 01:15:38 PM PST 24
Finished Jan 24 01:16:27 PM PST 24
Peak memory 204732 kb
Host smart-d464ab95-5371-47d7-9961-5644ca5ffedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335737401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2335737401
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.88143220
Short name T557
Test name
Test status
Simulation time 12112397 ps
CPU time 0.73 seconds
Started Jan 24 01:15:37 PM PST 24
Finished Jan 24 01:16:25 PM PST 24
Peak memory 205216 kb
Host smart-b7231e43-4c41-4403-9b47-47ed09c7a053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88143220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.88143220
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2051529090
Short name T428
Test name
Test status
Simulation time 80517731 ps
CPU time 0.69 seconds
Started Jan 24 01:15:38 PM PST 24
Finished Jan 24 01:16:26 PM PST 24
Peak memory 204808 kb
Host smart-7788383c-4686-4bbd-911a-ab03eaad7602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051529090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2051529090
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.328571729
Short name T185
Test name
Test status
Simulation time 16289663 ps
CPU time 0.75 seconds
Started Jan 24 01:15:34 PM PST 24
Finished Jan 24 01:16:22 PM PST 24
Peak memory 205152 kb
Host smart-dc860934-7b74-4c00-a836-60dcdbf6f8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328571729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.328571729
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3811790308
Short name T490
Test name
Test status
Simulation time 9681667 ps
CPU time 0.79 seconds
Started Jan 24 01:35:42 PM PST 24
Finished Jan 24 01:36:10 PM PST 24
Peak memory 205152 kb
Host smart-860c7a4e-f286-4ebc-946f-00eca4c7a7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811790308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3811790308
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2646038405
Short name T461
Test name
Test status
Simulation time 39776376 ps
CPU time 0.79 seconds
Started Jan 24 01:15:40 PM PST 24
Finished Jan 24 01:16:28 PM PST 24
Peak memory 205068 kb
Host smart-9dc5a760-b9ed-44dd-826a-e0075e99ba3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646038405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2646038405
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1795961331
Short name T541
Test name
Test status
Simulation time 11743588 ps
CPU time 0.83 seconds
Started Jan 24 01:32:48 PM PST 24
Finished Jan 24 01:33:22 PM PST 24
Peak memory 205196 kb
Host smart-143bb7a9-7282-47a1-ad8f-c151d0cdc620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795961331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1795961331
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3442386246
Short name T445
Test name
Test status
Simulation time 7899913 ps
CPU time 0.82 seconds
Started Jan 24 01:39:20 PM PST 24
Finished Jan 24 01:39:24 PM PST 24
Peak memory 205128 kb
Host smart-233dd21f-2d1f-42a2-8364-fb47cde18766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442386246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3442386246
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3137324920
Short name T138
Test name
Test status
Simulation time 135250291 ps
CPU time 7.57 seconds
Started Jan 24 01:14:27 PM PST 24
Finished Jan 24 01:14:59 PM PST 24
Peak memory 205364 kb
Host smart-3f218b1d-f258-4788-8af3-30e581de979b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137324920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
137324920
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2397024293
Short name T539
Test name
Test status
Simulation time 4276922961 ps
CPU time 8.65 seconds
Started Jan 24 01:14:24 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 205444 kb
Host smart-ea4730ee-3941-4983-80cd-bdb1a8891097
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397024293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
397024293
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1303247125
Short name T455
Test name
Test status
Simulation time 35826181 ps
CPU time 1.23 seconds
Started Jan 24 01:14:34 PM PST 24
Finished Jan 24 01:15:00 PM PST 24
Peak memory 205508 kb
Host smart-a32d8c12-8b20-443f-b7ad-b7259dd216ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303247125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
303247125
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2522279942
Short name T498
Test name
Test status
Simulation time 82415830 ps
CPU time 1.12 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:53 PM PST 24
Peak memory 205556 kb
Host smart-bb026ff3-cf45-4ddf-8081-637db12870ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522279942 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2522279942
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.806712259
Short name T484
Test name
Test status
Simulation time 23923919 ps
CPU time 0.94 seconds
Started Jan 24 01:14:24 PM PST 24
Finished Jan 24 01:14:48 PM PST 24
Peak memory 205324 kb
Host smart-48fd940e-4fdd-485d-847b-cd4d65472795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806712259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.806712259
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2409188840
Short name T418
Test name
Test status
Simulation time 19512487 ps
CPU time 0.87 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:53 PM PST 24
Peak memory 205120 kb
Host smart-9c626642-b0de-4308-893a-44bcde49e885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409188840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2409188840
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1988519546
Short name T522
Test name
Test status
Simulation time 110874465 ps
CPU time 2.56 seconds
Started Jan 24 01:14:34 PM PST 24
Finished Jan 24 01:15:02 PM PST 24
Peak memory 205588 kb
Host smart-9d315952-9d7d-46e8-9682-bd5f1f41f844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988519546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1988519546
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1327635561
Short name T119
Test name
Test status
Simulation time 697091271 ps
CPU time 5.28 seconds
Started Jan 24 01:14:36 PM PST 24
Finished Jan 24 01:15:08 PM PST 24
Peak memory 213824 kb
Host smart-a4fd6e53-c803-4c96-9393-681a8ae0c3ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327635561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1327635561
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1856525757
Short name T554
Test name
Test status
Simulation time 709088457 ps
CPU time 8.01 seconds
Started Jan 24 01:14:30 PM PST 24
Finished Jan 24 01:15:03 PM PST 24
Peak memory 213856 kb
Host smart-6b647c85-326d-46aa-9d74-0ee7e6032a1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856525757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1856525757
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2408796814
Short name T130
Test name
Test status
Simulation time 168795163 ps
CPU time 3.81 seconds
Started Jan 24 01:14:30 PM PST 24
Finished Jan 24 01:14:59 PM PST 24
Peak memory 213756 kb
Host smart-d7b1553a-0411-48a9-b00d-8fd407584947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408796814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2408796814
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1157946045
Short name T431
Test name
Test status
Simulation time 23350690 ps
CPU time 0.72 seconds
Started Jan 24 01:15:27 PM PST 24
Finished Jan 24 01:16:15 PM PST 24
Peak memory 205120 kb
Host smart-8eeb705a-8241-4303-bbd3-3b4c2df3f1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157946045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1157946045
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1504931866
Short name T471
Test name
Test status
Simulation time 115003381 ps
CPU time 0.88 seconds
Started Jan 24 01:15:33 PM PST 24
Finished Jan 24 01:16:21 PM PST 24
Peak memory 205224 kb
Host smart-ba89db3b-0540-4986-8a78-cbe7b91972b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504931866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1504931866
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1854539507
Short name T429
Test name
Test status
Simulation time 11322497 ps
CPU time 0.77 seconds
Started Jan 24 01:15:41 PM PST 24
Finished Jan 24 01:16:29 PM PST 24
Peak memory 205216 kb
Host smart-c6722369-9de0-48d2-aeb1-343e9b44fdfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854539507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1854539507
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4180421726
Short name T422
Test name
Test status
Simulation time 28780662 ps
CPU time 0.92 seconds
Started Jan 24 01:15:38 PM PST 24
Finished Jan 24 01:16:27 PM PST 24
Peak memory 205216 kb
Host smart-1bac70b8-aefa-474c-9b4c-346d120c4459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180421726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4180421726
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4231029126
Short name T450
Test name
Test status
Simulation time 10684618 ps
CPU time 0.77 seconds
Started Jan 24 01:15:48 PM PST 24
Finished Jan 24 01:16:33 PM PST 24
Peak memory 204560 kb
Host smart-e044bf75-1986-4382-8f42-e84b2cc9a2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231029126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4231029126
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3163202532
Short name T423
Test name
Test status
Simulation time 14376900 ps
CPU time 0.88 seconds
Started Jan 24 01:15:44 PM PST 24
Finished Jan 24 01:16:30 PM PST 24
Peak memory 205412 kb
Host smart-36cd253a-4d9d-4fb1-9007-a2c0a1234b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163202532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3163202532
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3335174563
Short name T492
Test name
Test status
Simulation time 27502998 ps
CPU time 0.8 seconds
Started Jan 24 01:15:46 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205184 kb
Host smart-d347c157-1ff8-4119-a82a-7c1af0d4714e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335174563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3335174563
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3279063398
Short name T544
Test name
Test status
Simulation time 12843477 ps
CPU time 0.85 seconds
Started Jan 24 01:15:44 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205228 kb
Host smart-13ebe7d9-ecd6-4fe0-bf02-0a36fc568cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279063398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3279063398
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.370300908
Short name T443
Test name
Test status
Simulation time 44024752 ps
CPU time 0.76 seconds
Started Jan 24 01:15:46 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205196 kb
Host smart-71f09ec7-0631-458d-8fb7-fe6929231a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370300908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.370300908
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3435883098
Short name T552
Test name
Test status
Simulation time 9966672 ps
CPU time 0.84 seconds
Started Jan 24 01:15:48 PM PST 24
Finished Jan 24 01:16:32 PM PST 24
Peak memory 205196 kb
Host smart-2ad72d26-4b0c-457a-9ccd-e5e7ddbd340d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435883098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3435883098
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1146460443
Short name T464
Test name
Test status
Simulation time 244571591 ps
CPU time 6.57 seconds
Started Jan 24 01:14:29 PM PST 24
Finished Jan 24 01:15:00 PM PST 24
Peak memory 205316 kb
Host smart-c00bf08e-e03c-451c-9f88-90df2157050f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146460443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
146460443
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.747533770
Short name T416
Test name
Test status
Simulation time 1743348862 ps
CPU time 26.46 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:15:19 PM PST 24
Peak memory 205540 kb
Host smart-dccd0287-a29f-43bb-b145-0868738e5e46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747533770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.747533770
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1652217918
Short name T420
Test name
Test status
Simulation time 36877525 ps
CPU time 1 seconds
Started Jan 24 01:14:24 PM PST 24
Finished Jan 24 01:14:48 PM PST 24
Peak memory 205260 kb
Host smart-d08eefd5-9fe2-4a11-933d-ee0edbd65c8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652217918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
652217918
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.117527294
Short name T473
Test name
Test status
Simulation time 43036949 ps
CPU time 1.34 seconds
Started Jan 24 01:14:34 PM PST 24
Finished Jan 24 01:15:00 PM PST 24
Peak memory 205524 kb
Host smart-a77e6f49-d8f8-48c1-aa03-97e6aaa1526f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117527294 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.117527294
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2379919045
Short name T481
Test name
Test status
Simulation time 22426518 ps
CPU time 1.08 seconds
Started Jan 24 01:14:30 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 205480 kb
Host smart-42dd0a07-1780-4528-a57d-12a8d1e922ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379919045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2379919045
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.453720332
Short name T532
Test name
Test status
Simulation time 16449210 ps
CPU time 0.71 seconds
Started Jan 24 01:14:36 PM PST 24
Finished Jan 24 01:15:02 PM PST 24
Peak memory 204984 kb
Host smart-b47fbd0a-41d3-4076-a498-2f3eb5952f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453720332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.453720332
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3337962028
Short name T479
Test name
Test status
Simulation time 42720285 ps
CPU time 1.5 seconds
Started Jan 24 01:14:26 PM PST 24
Finished Jan 24 01:14:51 PM PST 24
Peak memory 205532 kb
Host smart-0765b28a-2164-432b-a7cb-49530296c0fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337962028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3337962028
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.846942990
Short name T540
Test name
Test status
Simulation time 121705116 ps
CPU time 4.16 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 213936 kb
Host smart-76c0a5e8-d4a3-47cb-8f0d-c1721041b81c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846942990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.846942990
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3170357672
Short name T419
Test name
Test status
Simulation time 161036297 ps
CPU time 8.46 seconds
Started Jan 24 01:14:34 PM PST 24
Finished Jan 24 01:15:07 PM PST 24
Peak memory 214108 kb
Host smart-a9e05e45-7633-4ee4-99fb-bbde8d9e646f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170357672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3170357672
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1650297829
Short name T507
Test name
Test status
Simulation time 688579519 ps
CPU time 4.47 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:57 PM PST 24
Peak memory 214544 kb
Host smart-1a060bb5-67b8-4907-a7e9-348c3aa9ee63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650297829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1650297829
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3198563029
Short name T163
Test name
Test status
Simulation time 191064719 ps
CPU time 2.95 seconds
Started Jan 24 01:14:28 PM PST 24
Finished Jan 24 01:14:56 PM PST 24
Peak memory 208808 kb
Host smart-1bedb363-8760-4238-86be-cc9c14b424f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198563029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3198563029
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.382728629
Short name T497
Test name
Test status
Simulation time 26300300 ps
CPU time 0.79 seconds
Started Jan 24 01:15:42 PM PST 24
Finished Jan 24 01:16:29 PM PST 24
Peak memory 205144 kb
Host smart-9d1bd2a3-bab9-4772-8382-892708b30cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382728629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.382728629
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1771536590
Short name T460
Test name
Test status
Simulation time 8034178 ps
CPU time 0.79 seconds
Started Jan 24 01:15:47 PM PST 24
Finished Jan 24 01:16:32 PM PST 24
Peak memory 205112 kb
Host smart-a30f1974-4d30-4f56-8808-d82925cffe91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771536590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1771536590
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.666154540
Short name T417
Test name
Test status
Simulation time 22268169 ps
CPU time 0.92 seconds
Started Jan 24 01:15:47 PM PST 24
Finished Jan 24 01:16:32 PM PST 24
Peak memory 205188 kb
Host smart-44d0e5d1-ac95-4273-be84-0894b8b19750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666154540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.666154540
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3415612742
Short name T182
Test name
Test status
Simulation time 11519605 ps
CPU time 0.78 seconds
Started Jan 24 01:15:41 PM PST 24
Finished Jan 24 01:16:29 PM PST 24
Peak memory 205068 kb
Host smart-fa1bb7ea-95e4-461b-bea6-a72d5e1b67cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415612742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3415612742
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2724614352
Short name T499
Test name
Test status
Simulation time 10592989 ps
CPU time 0.83 seconds
Started Jan 24 01:15:46 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205140 kb
Host smart-3fa17990-4161-4fc5-bc7d-1c8cec6178ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724614352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2724614352
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1884550830
Short name T472
Test name
Test status
Simulation time 51588965 ps
CPU time 0.7 seconds
Started Jan 24 01:15:48 PM PST 24
Finished Jan 24 01:16:33 PM PST 24
Peak memory 204552 kb
Host smart-7c52292d-30a3-4af2-998b-51eccc9db3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884550830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1884550830
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1428186795
Short name T562
Test name
Test status
Simulation time 17095839 ps
CPU time 0.69 seconds
Started Jan 24 01:15:46 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205196 kb
Host smart-7e39b93f-a76a-4e67-b3d2-b1f626495f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428186795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1428186795
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3091568723
Short name T503
Test name
Test status
Simulation time 16042023 ps
CPU time 0.75 seconds
Started Jan 24 01:15:48 PM PST 24
Finished Jan 24 01:16:32 PM PST 24
Peak memory 205212 kb
Host smart-ff7c516a-23ae-405a-81bb-a450e32d4259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091568723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3091568723
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.67817980
Short name T453
Test name
Test status
Simulation time 12428973 ps
CPU time 0.71 seconds
Started Jan 24 01:15:46 PM PST 24
Finished Jan 24 01:16:31 PM PST 24
Peak memory 205196 kb
Host smart-c309f0a6-75b6-4c8a-b5ba-65a0d150aa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67817980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.67817980
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1923683703
Short name T454
Test name
Test status
Simulation time 21141798 ps
CPU time 0.8 seconds
Started Jan 24 01:16:00 PM PST 24
Finished Jan 24 01:16:40 PM PST 24
Peak memory 204984 kb
Host smart-4be6cb12-d8f3-49a1-861d-791266bc8018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923683703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1923683703
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3539263832
Short name T500
Test name
Test status
Simulation time 15738111 ps
CPU time 1.42 seconds
Started Jan 24 01:14:38 PM PST 24
Finished Jan 24 01:15:08 PM PST 24
Peak memory 213692 kb
Host smart-ac3289e2-7215-4fb6-874c-6324eba4916c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539263832 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3539263832
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3295031552
Short name T436
Test name
Test status
Simulation time 52537400 ps
CPU time 1.09 seconds
Started Jan 24 01:14:40 PM PST 24
Finished Jan 24 01:15:10 PM PST 24
Peak memory 205444 kb
Host smart-bbfbab5a-23fb-404e-8652-70c7efcd2afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295031552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3295031552
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2116060267
Short name T561
Test name
Test status
Simulation time 51241455 ps
CPU time 0.88 seconds
Started Jan 24 01:14:42 PM PST 24
Finished Jan 24 01:15:12 PM PST 24
Peak memory 205204 kb
Host smart-870279ae-3b24-4742-aa3b-f3c3c7128135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116060267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2116060267
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4110754242
Short name T521
Test name
Test status
Simulation time 99615941 ps
CPU time 2.6 seconds
Started Jan 24 01:14:41 PM PST 24
Finished Jan 24 01:15:14 PM PST 24
Peak memory 205496 kb
Host smart-dae636fc-cf51-4c4a-ac5c-20d014eb5cda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110754242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4110754242
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3375482848
Short name T123
Test name
Test status
Simulation time 149576246 ps
CPU time 8.08 seconds
Started Jan 24 01:14:30 PM PST 24
Finished Jan 24 01:15:03 PM PST 24
Peak memory 213868 kb
Host smart-e7d64630-84ac-4987-9374-78816518c747
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375482848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3375482848
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.183550085
Short name T483
Test name
Test status
Simulation time 191990357 ps
CPU time 3.12 seconds
Started Jan 24 01:14:38 PM PST 24
Finished Jan 24 01:15:09 PM PST 24
Peak memory 216092 kb
Host smart-94141d73-0e23-4922-a3a7-d727cc73f5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183550085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.183550085
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.656222317
Short name T173
Test name
Test status
Simulation time 159901510 ps
CPU time 6.83 seconds
Started Jan 24 01:14:46 PM PST 24
Finished Jan 24 01:15:22 PM PST 24
Peak memory 213644 kb
Host smart-c9b8f79d-9701-4f2b-8340-ef229b1ffbea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656222317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
656222317
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.264060495
Short name T480
Test name
Test status
Simulation time 24347560 ps
CPU time 1.46 seconds
Started Jan 24 01:14:46 PM PST 24
Finished Jan 24 01:15:16 PM PST 24
Peak memory 213648 kb
Host smart-1ea41c71-978a-40f0-934a-b79305bad9cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264060495 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.264060495
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.290712402
Short name T434
Test name
Test status
Simulation time 11128462 ps
CPU time 1.02 seconds
Started Jan 24 01:47:50 PM PST 24
Finished Jan 24 01:48:11 PM PST 24
Peak memory 205372 kb
Host smart-ca9ba43e-3827-40f4-b512-98abcc64516d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290712402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.290712402
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2334494464
Short name T435
Test name
Test status
Simulation time 9966242 ps
CPU time 0.8 seconds
Started Jan 24 01:14:46 PM PST 24
Finished Jan 24 01:15:16 PM PST 24
Peak memory 205188 kb
Host smart-5f52b329-caf9-4e87-80a7-2cc517aea1af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334494464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2334494464
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1940197394
Short name T535
Test name
Test status
Simulation time 29581086 ps
CPU time 1.38 seconds
Started Jan 24 01:14:39 PM PST 24
Finished Jan 24 01:15:09 PM PST 24
Peak memory 205252 kb
Host smart-f26cdfa9-dc1f-4f58-a7fd-0f8f95f6e0e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940197394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1940197394
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2590952115
Short name T430
Test name
Test status
Simulation time 269781341 ps
CPU time 2.4 seconds
Started Jan 24 01:14:37 PM PST 24
Finished Jan 24 01:15:08 PM PST 24
Peak memory 213924 kb
Host smart-d893df0e-3fba-4190-9401-88299da7c6cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590952115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2590952115
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1653922534
Short name T523
Test name
Test status
Simulation time 84880047 ps
CPU time 3.9 seconds
Started Jan 24 01:14:41 PM PST 24
Finished Jan 24 01:15:15 PM PST 24
Peak memory 219248 kb
Host smart-924e9689-2bd9-40dc-a434-d1e08fec550b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653922534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1653922534
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1392137948
Short name T469
Test name
Test status
Simulation time 93258512 ps
CPU time 1.61 seconds
Started Jan 24 01:14:39 PM PST 24
Finished Jan 24 01:15:09 PM PST 24
Peak memory 213688 kb
Host smart-a59fd930-a3b9-4f3e-be26-5a10ef15fdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392137948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1392137948
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.335178968
Short name T151
Test name
Test status
Simulation time 257022199 ps
CPU time 4.89 seconds
Started Jan 24 01:23:05 PM PST 24
Finished Jan 24 01:24:01 PM PST 24
Peak memory 208792 kb
Host smart-b71a5cf3-a3d9-4e43-ae68-7ebd6e9f7ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335178968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
335178968
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3896529373
Short name T451
Test name
Test status
Simulation time 125531034 ps
CPU time 1.59 seconds
Started Jan 24 02:07:08 PM PST 24
Finished Jan 24 02:07:46 PM PST 24
Peak memory 213712 kb
Host smart-af20608e-eee3-4419-81c4-4fbf5a6048b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896529373 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3896529373
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4075043129
Short name T547
Test name
Test status
Simulation time 15764364 ps
CPU time 1.04 seconds
Started Jan 24 01:14:45 PM PST 24
Finished Jan 24 01:15:15 PM PST 24
Peak memory 205328 kb
Host smart-3be867d7-6d0a-4ec1-a2d1-6bf9411d9a1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075043129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4075043129
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1852660706
Short name T421
Test name
Test status
Simulation time 41218779 ps
CPU time 0.83 seconds
Started Jan 24 01:14:41 PM PST 24
Finished Jan 24 01:15:10 PM PST 24
Peak memory 205124 kb
Host smart-358e6266-1226-4408-b29e-3791475cc3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852660706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1852660706
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2311356227
Short name T546
Test name
Test status
Simulation time 119086895 ps
CPU time 3.57 seconds
Started Jan 24 01:23:37 PM PST 24
Finished Jan 24 01:24:25 PM PST 24
Peak memory 205484 kb
Host smart-050b04b6-0aa5-4211-8624-3eaec225ca0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311356227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2311356227
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3759342288
Short name T171
Test name
Test status
Simulation time 276341335 ps
CPU time 4.86 seconds
Started Jan 24 01:14:43 PM PST 24
Finished Jan 24 01:15:17 PM PST 24
Peak memory 213912 kb
Host smart-b5bf09aa-2023-41ec-968e-b4adf2aaed80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759342288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3759342288
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.994789698
Short name T494
Test name
Test status
Simulation time 78252426 ps
CPU time 3.42 seconds
Started Jan 24 01:14:41 PM PST 24
Finished Jan 24 01:15:15 PM PST 24
Peak memory 214008 kb
Host smart-515f768f-60e6-4288-9076-41d52f381869
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994789698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.994789698
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.222595545
Short name T502
Test name
Test status
Simulation time 230237805 ps
CPU time 3.59 seconds
Started Jan 24 01:14:39 PM PST 24
Finished Jan 24 01:15:11 PM PST 24
Peak memory 221608 kb
Host smart-a326322f-82fe-47eb-b760-41b223c8701a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222595545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.222595545
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1751066599
Short name T152
Test name
Test status
Simulation time 217821656 ps
CPU time 6.25 seconds
Started Jan 24 01:14:42 PM PST 24
Finished Jan 24 01:15:18 PM PST 24
Peak memory 213620 kb
Host smart-259707e9-eb8b-4991-bb18-fc367f5f9c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751066599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1751066599
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1919173957
Short name T564
Test name
Test status
Simulation time 108440218 ps
CPU time 1.53 seconds
Started Jan 24 01:14:59 PM PST 24
Finished Jan 24 01:15:31 PM PST 24
Peak memory 213744 kb
Host smart-bcfc7ddb-5764-4235-95cd-1af00a0c1d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919173957 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1919173957
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1431386478
Short name T538
Test name
Test status
Simulation time 128984142 ps
CPU time 1.65 seconds
Started Jan 24 01:14:59 PM PST 24
Finished Jan 24 01:15:30 PM PST 24
Peak memory 205472 kb
Host smart-2c1b01ce-4d53-4a92-9e80-7fb045965907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431386478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1431386478
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1888390946
Short name T184
Test name
Test status
Simulation time 13659016 ps
CPU time 0.88 seconds
Started Jan 24 01:14:57 PM PST 24
Finished Jan 24 01:15:28 PM PST 24
Peak memory 205372 kb
Host smart-74db142a-a556-494a-ab88-e4ac06fde059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888390946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1888390946
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2057535044
Short name T524
Test name
Test status
Simulation time 123814158 ps
CPU time 2.43 seconds
Started Jan 24 01:14:59 PM PST 24
Finished Jan 24 01:15:31 PM PST 24
Peak memory 205488 kb
Host smart-9f803b0a-486f-407f-9bb1-bbbe434ad3f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057535044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2057535044
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1363582393
Short name T512
Test name
Test status
Simulation time 328053719 ps
CPU time 3.12 seconds
Started Jan 24 01:14:39 PM PST 24
Finished Jan 24 01:15:10 PM PST 24
Peak memory 213936 kb
Host smart-2f0deccd-dbd7-4a05-aacd-533d4cd54c0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363582393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1363582393
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3004606176
Short name T558
Test name
Test status
Simulation time 214102002 ps
CPU time 4.85 seconds
Started Jan 24 01:23:08 PM PST 24
Finished Jan 24 01:24:03 PM PST 24
Peak memory 213996 kb
Host smart-3c0688ce-9909-4213-8e06-fead2f56bd2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004606176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3004606176
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2338337665
Short name T478
Test name
Test status
Simulation time 507484955 ps
CPU time 4.84 seconds
Started Jan 24 01:39:28 PM PST 24
Finished Jan 24 01:40:28 PM PST 24
Peak memory 213704 kb
Host smart-d8824f2a-577c-4a16-885e-9f70295e2230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338337665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2338337665
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2336654387
Short name T169
Test name
Test status
Simulation time 152804537 ps
CPU time 6.07 seconds
Started Jan 24 01:14:58 PM PST 24
Finished Jan 24 01:15:34 PM PST 24
Peak memory 209028 kb
Host smart-f1e5540c-724d-4807-a668-9fda18ee5326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336654387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2336654387
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.357624250
Short name T542
Test name
Test status
Simulation time 21250565 ps
CPU time 1.95 seconds
Started Jan 24 01:14:59 PM PST 24
Finished Jan 24 01:15:31 PM PST 24
Peak memory 213704 kb
Host smart-57b25898-9a24-4810-b9e3-67e68755b5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357624250 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.357624250
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1368658772
Short name T566
Test name
Test status
Simulation time 19384832 ps
CPU time 1.12 seconds
Started Jan 24 01:15:04 PM PST 24
Finished Jan 24 01:15:36 PM PST 24
Peak memory 205284 kb
Host smart-981ebbc0-84b7-4847-887e-186514565cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368658772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1368658772
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4197440491
Short name T487
Test name
Test status
Simulation time 9486663 ps
CPU time 0.8 seconds
Started Jan 24 01:15:00 PM PST 24
Finished Jan 24 01:15:31 PM PST 24
Peak memory 205120 kb
Host smart-e9385cec-d986-4257-afa8-4fd57bed4bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197440491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4197440491
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1527871651
Short name T426
Test name
Test status
Simulation time 85954825 ps
CPU time 2.26 seconds
Started Jan 24 01:14:58 PM PST 24
Finished Jan 24 01:15:30 PM PST 24
Peak memory 205464 kb
Host smart-f99a0419-8c9d-471b-a0b8-4b672c9a7839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527871651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1527871651
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4219074902
Short name T442
Test name
Test status
Simulation time 391057976 ps
CPU time 3.28 seconds
Started Jan 24 01:15:00 PM PST 24
Finished Jan 24 01:15:34 PM PST 24
Peak memory 213964 kb
Host smart-c5ea7a7d-c77d-4829-8d2a-6e4c9afbabde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219074902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4219074902
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2755474829
Short name T506
Test name
Test status
Simulation time 182177450 ps
CPU time 8.73 seconds
Started Jan 24 01:14:56 PM PST 24
Finished Jan 24 01:15:34 PM PST 24
Peak memory 219660 kb
Host smart-5a40aed3-085a-466e-8043-a5fdc078b488
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755474829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2755474829
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1818479309
Short name T491
Test name
Test status
Simulation time 71043891 ps
CPU time 3.58 seconds
Started Jan 24 01:14:57 PM PST 24
Finished Jan 24 01:15:30 PM PST 24
Peak memory 216692 kb
Host smart-feb65aee-ac8f-4e3f-bd78-03df693df1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818479309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1818479309
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1287370814
Short name T164
Test name
Test status
Simulation time 748050989 ps
CPU time 9.92 seconds
Started Jan 24 01:15:00 PM PST 24
Finished Jan 24 01:15:40 PM PST 24
Peak memory 208616 kb
Host smart-4aab00c4-fe4c-4da9-9a16-c6d6aebecaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287370814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1287370814
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3480445568
Short name T591
Test name
Test status
Simulation time 44512450 ps
CPU time 0.83 seconds
Started Jan 24 02:38:44 PM PST 24
Finished Jan 24 02:38:52 PM PST 24
Peak memory 205400 kb
Host smart-69e83687-730f-4b9a-96a7-ef6904edf83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480445568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3480445568
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3381589299
Short name T393
Test name
Test status
Simulation time 3357020280 ps
CPU time 101.31 seconds
Started Jan 24 02:38:34 PM PST 24
Finished Jan 24 02:40:28 PM PST 24
Peak memory 217696 kb
Host smart-d62a16b7-3852-4eea-a713-c1b490d9b1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381589299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3381589299
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.607771678
Short name T891
Test name
Test status
Simulation time 212955160 ps
CPU time 10.74 seconds
Started Jan 24 02:59:19 PM PST 24
Finished Jan 24 02:59:42 PM PST 24
Peak memory 208248 kb
Host smart-3ecce50c-97e8-42a2-a47e-5db62d255b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607771678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.607771678
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3315078148
Short name T951
Test name
Test status
Simulation time 107729095 ps
CPU time 5.03 seconds
Started Jan 24 03:41:07 PM PST 24
Finished Jan 24 03:41:25 PM PST 24
Peak memory 220640 kb
Host smart-6f969f42-3aa8-4ba0-aa1d-4208ba4f629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315078148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3315078148
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3771536316
Short name T898
Test name
Test status
Simulation time 383592510 ps
CPU time 7.8 seconds
Started Jan 24 02:38:37 PM PST 24
Finished Jan 24 02:38:56 PM PST 24
Peak memory 208736 kb
Host smart-826fcd59-d944-4870-a6d4-7dabba91c3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771536316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3771536316
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.698998819
Short name T658
Test name
Test status
Simulation time 5185425934 ps
CPU time 51.39 seconds
Started Jan 24 02:52:06 PM PST 24
Finished Jan 24 02:53:02 PM PST 24
Peak memory 208888 kb
Host smart-940630d7-5bb7-4a3e-98e2-32e2f2926589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698998819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.698998819
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3734041053
Short name T104
Test name
Test status
Simulation time 2917602016 ps
CPU time 22.9 seconds
Started Jan 24 02:38:44 PM PST 24
Finished Jan 24 02:39:14 PM PST 24
Peak memory 233580 kb
Host smart-2e46d846-b71c-40ea-8b43-08a6f2352666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734041053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3734041053
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1839836479
Short name T876
Test name
Test status
Simulation time 98211676 ps
CPU time 3.11 seconds
Started Jan 24 02:38:34 PM PST 24
Finished Jan 24 02:38:49 PM PST 24
Peak memory 207096 kb
Host smart-0065bc3f-bd0c-462a-b37e-b6da57edeb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839836479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1839836479
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2706043278
Short name T801
Test name
Test status
Simulation time 44339204 ps
CPU time 2.62 seconds
Started Jan 24 03:05:33 PM PST 24
Finished Jan 24 03:05:54 PM PST 24
Peak memory 206204 kb
Host smart-ea85ce98-b916-4c83-aabd-2ab1d519e7ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706043278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2706043278
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3622573590
Short name T741
Test name
Test status
Simulation time 186021180 ps
CPU time 2.71 seconds
Started Jan 24 04:04:50 PM PST 24
Finished Jan 24 04:04:59 PM PST 24
Peak memory 206108 kb
Host smart-89030a77-a53c-44fc-ae83-16ebed93257d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622573590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3622573590
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.436893867
Short name T612
Test name
Test status
Simulation time 11992783494 ps
CPU time 27.08 seconds
Started Jan 24 02:38:40 PM PST 24
Finished Jan 24 02:39:16 PM PST 24
Peak memory 207348 kb
Host smart-57b5392f-c053-42da-b4b5-709a158a6c34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436893867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.436893867
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4132748369
Short name T790
Test name
Test status
Simulation time 2004830789 ps
CPU time 22.96 seconds
Started Jan 24 03:31:15 PM PST 24
Finished Jan 24 03:31:45 PM PST 24
Peak memory 207584 kb
Host smart-591499c4-30b8-485f-8ade-1a92e5ebb0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132748369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4132748369
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4291192732
Short name T721
Test name
Test status
Simulation time 70953802 ps
CPU time 3.45 seconds
Started Jan 24 02:38:33 PM PST 24
Finished Jan 24 02:38:49 PM PST 24
Peak memory 205844 kb
Host smart-ed1bf842-b61e-49b5-a958-665e3c16598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291192732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4291192732
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3912628406
Short name T611
Test name
Test status
Simulation time 79269789 ps
CPU time 3.52 seconds
Started Jan 24 02:51:16 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 217676 kb
Host smart-e3f0bbcb-2500-46d5-81de-628d652c19af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912628406 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3912628406
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1405285436
Short name T1053
Test name
Test status
Simulation time 335116932 ps
CPU time 3.9 seconds
Started Jan 24 02:38:34 PM PST 24
Finished Jan 24 02:38:50 PM PST 24
Peak memory 213788 kb
Host smart-6128e789-0800-44c7-b1d4-71f595262ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405285436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1405285436
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.406152913
Short name T571
Test name
Test status
Simulation time 10061965 ps
CPU time 0.84 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:01 PM PST 24
Peak memory 205396 kb
Host smart-38484bbf-0812-4db7-94d0-a0845037ab75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406152913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.406152913
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.859472981
Short name T405
Test name
Test status
Simulation time 81546762 ps
CPU time 3.37 seconds
Started Jan 24 02:38:46 PM PST 24
Finished Jan 24 02:38:56 PM PST 24
Peak memory 213808 kb
Host smart-0f6c33a6-4cce-418b-89d4-a3633d10d56d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859472981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.859472981
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2662784499
Short name T1020
Test name
Test status
Simulation time 96191865 ps
CPU time 3.72 seconds
Started Jan 24 02:54:00 PM PST 24
Finished Jan 24 02:54:34 PM PST 24
Peak memory 206668 kb
Host smart-c452b967-8f24-43b9-b1ed-ef9122f2ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662784499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2662784499
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3029494111
Short name T242
Test name
Test status
Simulation time 492389663 ps
CPU time 8.49 seconds
Started Jan 24 02:38:56 PM PST 24
Finished Jan 24 02:39:10 PM PST 24
Peak memory 210388 kb
Host smart-2c6f91e9-2068-4262-af91-9cb2e18fd211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029494111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3029494111
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1570789405
Short name T604
Test name
Test status
Simulation time 194037665 ps
CPU time 4.13 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:04 PM PST 24
Peak memory 213736 kb
Host smart-978987e4-033d-4b4e-9b7c-b48ff1e12995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570789405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1570789405
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1206895017
Short name T73
Test name
Test status
Simulation time 1612908406 ps
CPU time 5.82 seconds
Started Jan 24 02:38:43 PM PST 24
Finished Jan 24 02:38:56 PM PST 24
Peak memory 207688 kb
Host smart-6a67f576-edd2-4184-b2a9-df26b47624c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206895017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1206895017
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1893330337
Short name T608
Test name
Test status
Simulation time 94514045 ps
CPU time 2.64 seconds
Started Jan 24 02:38:42 PM PST 24
Finished Jan 24 02:38:53 PM PST 24
Peak memory 205996 kb
Host smart-688a24fb-1e35-4666-b1c7-ebf065d40b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893330337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1893330337
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1922392759
Short name T584
Test name
Test status
Simulation time 2937063714 ps
CPU time 19.5 seconds
Started Jan 24 02:38:43 PM PST 24
Finished Jan 24 02:39:10 PM PST 24
Peak memory 207400 kb
Host smart-da98c0d5-605e-400d-8eed-d2bacc0e66fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922392759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1922392759
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2567924547
Short name T842
Test name
Test status
Simulation time 96947057 ps
CPU time 3.04 seconds
Started Jan 24 02:38:48 PM PST 24
Finished Jan 24 02:38:56 PM PST 24
Peak memory 206156 kb
Host smart-45f1a47b-171f-4008-a958-8887d0567815
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567924547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2567924547
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2856529973
Short name T206
Test name
Test status
Simulation time 100233624 ps
CPU time 3.54 seconds
Started Jan 24 02:38:45 PM PST 24
Finished Jan 24 02:38:55 PM PST 24
Peak memory 208132 kb
Host smart-91145e9e-6893-48f5-8fcf-3be11a196dd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856529973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2856529973
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3695571871
Short name T199
Test name
Test status
Simulation time 111801212 ps
CPU time 2.53 seconds
Started Jan 24 02:38:51 PM PST 24
Finished Jan 24 02:38:59 PM PST 24
Peak memory 208612 kb
Host smart-2455180d-d1a7-4741-90a0-10aed9b98152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695571871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3695571871
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3376322036
Short name T936
Test name
Test status
Simulation time 340565773 ps
CPU time 3.04 seconds
Started Jan 24 02:38:42 PM PST 24
Finished Jan 24 02:38:53 PM PST 24
Peak memory 205888 kb
Host smart-4aabdc50-67c8-4c96-b78e-0ffc0e252f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376322036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3376322036
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1685038802
Short name T230
Test name
Test status
Simulation time 2127469040 ps
CPU time 39.07 seconds
Started Jan 24 02:58:33 PM PST 24
Finished Jan 24 02:59:17 PM PST 24
Peak memory 221408 kb
Host smart-7ae285af-dbcb-413c-9aea-94e5ef63c9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685038802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1685038802
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1620418804
Short name T637
Test name
Test status
Simulation time 187123632 ps
CPU time 3.67 seconds
Started Jan 24 02:38:50 PM PST 24
Finished Jan 24 02:38:59 PM PST 24
Peak memory 222144 kb
Host smart-f0bb0d3b-a1a4-46ff-a316-ffb4257e3e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620418804 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1620418804
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3420163626
Short name T377
Test name
Test status
Simulation time 831590015 ps
CPU time 6.76 seconds
Started Jan 24 02:39:06 PM PST 24
Finished Jan 24 02:39:25 PM PST 24
Peak memory 217608 kb
Host smart-e1b997cf-ed8b-44a6-8ca6-b425ad371f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420163626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3420163626
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.762678253
Short name T745
Test name
Test status
Simulation time 143759306 ps
CPU time 4.84 seconds
Started Jan 24 02:39:08 PM PST 24
Finished Jan 24 02:39:24 PM PST 24
Peak memory 209516 kb
Host smart-79231ee0-275f-482c-b899-14fb5beceec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762678253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.762678253
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2574048810
Short name T967
Test name
Test status
Simulation time 50907291 ps
CPU time 0.83 seconds
Started Jan 24 02:57:30 PM PST 24
Finished Jan 24 02:57:45 PM PST 24
Peak memory 205488 kb
Host smart-a6ac2293-e5fb-49d1-8175-c73521acd5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574048810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2574048810
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2505733229
Short name T238
Test name
Test status
Simulation time 47749677 ps
CPU time 2.84 seconds
Started Jan 24 02:41:06 PM PST 24
Finished Jan 24 02:41:21 PM PST 24
Peak memory 213852 kb
Host smart-78b0f30d-7cf9-4774-bdfc-bd16d60cc98e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505733229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2505733229
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2764889738
Short name T63
Test name
Test status
Simulation time 127418506 ps
CPU time 3.6 seconds
Started Jan 24 02:41:08 PM PST 24
Finished Jan 24 02:41:24 PM PST 24
Peak memory 208696 kb
Host smart-36b9e04f-d745-4470-b3c4-5bab9762680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764889738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2764889738
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1265339572
Short name T1014
Test name
Test status
Simulation time 5268026346 ps
CPU time 66.6 seconds
Started Jan 24 02:41:06 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 213948 kb
Host smart-08c3dc96-4537-4f87-98e8-1a2bff29f323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265339572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1265339572
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2186140498
Short name T221
Test name
Test status
Simulation time 768306954 ps
CPU time 5.35 seconds
Started Jan 24 02:41:09 PM PST 24
Finished Jan 24 02:41:26 PM PST 24
Peak memory 209392 kb
Host smart-e360065c-8983-4907-a0e3-b8dba5135828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186140498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2186140498
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2392842268
Short name T726
Test name
Test status
Simulation time 1278357564 ps
CPU time 31.8 seconds
Started Jan 24 02:41:04 PM PST 24
Finished Jan 24 02:41:48 PM PST 24
Peak memory 209132 kb
Host smart-abb7ea0c-173f-42a9-b8ab-44fca5983b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392842268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2392842268
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3752087384
Short name T234
Test name
Test status
Simulation time 153965772 ps
CPU time 5.44 seconds
Started Jan 24 02:41:01 PM PST 24
Finished Jan 24 02:41:20 PM PST 24
Peak memory 207276 kb
Host smart-a24e7dbc-f1cb-4056-bbda-4e06c454ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752087384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3752087384
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4262589214
Short name T641
Test name
Test status
Simulation time 135820004 ps
CPU time 2.38 seconds
Started Jan 24 02:41:06 PM PST 24
Finished Jan 24 02:41:21 PM PST 24
Peak memory 206056 kb
Host smart-48d3bc5d-fe2f-4b17-a54d-a956644bd0ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262589214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4262589214
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1653538267
Short name T901
Test name
Test status
Simulation time 72394106 ps
CPU time 1.96 seconds
Started Jan 24 02:41:06 PM PST 24
Finished Jan 24 02:41:20 PM PST 24
Peak memory 205964 kb
Host smart-5dbec175-95c9-4c45-875e-c9efcf56d9b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653538267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1653538267
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2258828859
Short name T961
Test name
Test status
Simulation time 513572309 ps
CPU time 6.04 seconds
Started Jan 24 02:41:08 PM PST 24
Finished Jan 24 02:41:26 PM PST 24
Peak memory 205800 kb
Host smart-96c6c4b1-5e28-4434-b4d8-c04c84aebbce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258828859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2258828859
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3276042767
Short name T725
Test name
Test status
Simulation time 194875415 ps
CPU time 2.81 seconds
Started Jan 24 02:41:03 PM PST 24
Finished Jan 24 02:41:18 PM PST 24
Peak memory 207748 kb
Host smart-8b4f0f37-200f-4645-bb20-9ad7a3b7e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276042767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3276042767
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.4019469649
Short name T80
Test name
Test status
Simulation time 93210551 ps
CPU time 3.78 seconds
Started Jan 24 02:40:53 PM PST 24
Finished Jan 24 02:41:11 PM PST 24
Peak memory 207996 kb
Host smart-ca151fe4-ce46-4647-ac3b-12c10408400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019469649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4019469649
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1144088504
Short name T605
Test name
Test status
Simulation time 525056052 ps
CPU time 3.96 seconds
Started Jan 24 03:20:59 PM PST 24
Finished Jan 24 03:21:14 PM PST 24
Peak memory 219680 kb
Host smart-b5429248-781f-4d6e-9a57-601907cbe29d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144088504 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1144088504
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.453072151
Short name T849
Test name
Test status
Simulation time 226470086 ps
CPU time 4.11 seconds
Started Jan 24 02:41:04 PM PST 24
Finished Jan 24 02:41:21 PM PST 24
Peak memory 209500 kb
Host smart-42fff3c7-aa52-46d6-943d-2caba0452165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453072151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.453072151
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2775114121
Short name T579
Test name
Test status
Simulation time 331317466 ps
CPU time 3.84 seconds
Started Jan 24 02:41:07 PM PST 24
Finished Jan 24 02:41:22 PM PST 24
Peak memory 209156 kb
Host smart-cd9eb54a-031f-45e1-b100-aa2a386a2427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775114121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2775114121
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.56363563
Short name T996
Test name
Test status
Simulation time 48719284 ps
CPU time 0.87 seconds
Started Jan 24 02:41:24 PM PST 24
Finished Jan 24 02:41:33 PM PST 24
Peak memory 205392 kb
Host smart-386efa34-07dc-4ea0-9f0a-29fc5fd07b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56363563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.56363563
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2438462622
Short name T1077
Test name
Test status
Simulation time 195631653 ps
CPU time 5.77 seconds
Started Jan 24 04:02:58 PM PST 24
Finished Jan 24 04:03:05 PM PST 24
Peak memory 208384 kb
Host smart-287d982b-2a42-47f8-825c-f5ed63719fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438462622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2438462622
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.995474195
Short name T396
Test name
Test status
Simulation time 80703864 ps
CPU time 2.26 seconds
Started Jan 24 02:41:10 PM PST 24
Finished Jan 24 02:41:27 PM PST 24
Peak memory 207960 kb
Host smart-13063de4-29d4-4806-b560-761126990253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995474195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.995474195
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2877398586
Short name T1026
Test name
Test status
Simulation time 156621559 ps
CPU time 5.61 seconds
Started Jan 24 03:06:37 PM PST 24
Finished Jan 24 03:06:56 PM PST 24
Peak memory 219216 kb
Host smart-7cb061d6-9b82-4e96-8a51-ac64830fb358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877398586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2877398586
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2157465936
Short name T892
Test name
Test status
Simulation time 2272492755 ps
CPU time 62.7 seconds
Started Jan 24 02:41:11 PM PST 24
Finished Jan 24 02:42:28 PM PST 24
Peak memory 217340 kb
Host smart-fc02c6b3-8933-4d5f-9910-bd4b4b3c09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157465936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2157465936
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1295213326
Short name T932
Test name
Test status
Simulation time 327452658 ps
CPU time 4.29 seconds
Started Jan 24 02:41:16 PM PST 24
Finished Jan 24 02:41:33 PM PST 24
Peak memory 208556 kb
Host smart-579b25d4-9051-4639-aa13-cc45ce0493c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295213326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1295213326
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1626983355
Short name T796
Test name
Test status
Simulation time 122638959 ps
CPU time 3.47 seconds
Started Jan 24 04:10:32 PM PST 24
Finished Jan 24 04:10:40 PM PST 24
Peak memory 206060 kb
Host smart-9a6e0818-1839-453a-9423-54b1ca2f958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626983355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1626983355
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2369435040
Short name T600
Test name
Test status
Simulation time 702704072 ps
CPU time 18.5 seconds
Started Jan 24 03:10:59 PM PST 24
Finished Jan 24 03:11:22 PM PST 24
Peak memory 208032 kb
Host smart-9550da9a-ea64-4071-9203-e7754c009e73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369435040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2369435040
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4201010217
Short name T948
Test name
Test status
Simulation time 256423113 ps
CPU time 8.91 seconds
Started Jan 24 02:56:02 PM PST 24
Finished Jan 24 02:56:14 PM PST 24
Peak memory 207348 kb
Host smart-87a9ff09-4332-49ec-866e-05344ae42220
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201010217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4201010217
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.907656781
Short name T398
Test name
Test status
Simulation time 59498694 ps
CPU time 2.08 seconds
Started Jan 24 02:41:12 PM PST 24
Finished Jan 24 02:41:28 PM PST 24
Peak memory 208372 kb
Host smart-4b824789-045e-43e9-9749-8f20b956ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907656781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.907656781
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1237993538
Short name T386
Test name
Test status
Simulation time 108077884 ps
CPU time 3.27 seconds
Started Jan 24 02:41:09 PM PST 24
Finished Jan 24 02:41:24 PM PST 24
Peak memory 207580 kb
Host smart-effff456-d696-4951-a4cd-0d192b81ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237993538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1237993538
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4279115472
Short name T795
Test name
Test status
Simulation time 161645300 ps
CPU time 6.73 seconds
Started Jan 24 02:41:31 PM PST 24
Finished Jan 24 02:41:47 PM PST 24
Peak memory 214208 kb
Host smart-bfe6471e-5c79-4d65-a146-53c8d9c45bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279115472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4279115472
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.4011061951
Short name T1012
Test name
Test status
Simulation time 291955446 ps
CPU time 5.55 seconds
Started Jan 24 02:41:25 PM PST 24
Finished Jan 24 02:41:38 PM PST 24
Peak memory 215660 kb
Host smart-d1794613-6738-482b-8137-1799fdb5d463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011061951 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.4011061951
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3092010875
Short name T333
Test name
Test status
Simulation time 187725323 ps
CPU time 5.57 seconds
Started Jan 24 02:47:14 PM PST 24
Finished Jan 24 02:47:49 PM PST 24
Peak memory 208444 kb
Host smart-1a5a5641-46ab-46a4-8674-8a2995df210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092010875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3092010875
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3580735444
Short name T639
Test name
Test status
Simulation time 189681124 ps
CPU time 2.89 seconds
Started Jan 24 02:41:16 PM PST 24
Finished Jan 24 02:41:32 PM PST 24
Peak memory 209680 kb
Host smart-1d0f182f-d457-49cf-a1e1-b7ffaab61646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580735444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3580735444
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1842800100
Short name T136
Test name
Test status
Simulation time 705295379 ps
CPU time 3.26 seconds
Started Jan 24 02:41:24 PM PST 24
Finished Jan 24 02:41:35 PM PST 24
Peak memory 214676 kb
Host smart-a84b10ef-c556-405b-a302-ef4723e7ed18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842800100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1842800100
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1226712767
Short name T21
Test name
Test status
Simulation time 80501867 ps
CPU time 3.03 seconds
Started Jan 24 02:41:26 PM PST 24
Finished Jan 24 02:41:37 PM PST 24
Peak memory 219004 kb
Host smart-41ec681b-8c1e-4a6a-8295-888a18bd1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226712767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1226712767
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.767456635
Short name T366
Test name
Test status
Simulation time 85847561 ps
CPU time 3.28 seconds
Started Jan 24 02:41:23 PM PST 24
Finished Jan 24 02:41:35 PM PST 24
Peak memory 209356 kb
Host smart-56c6c8c6-cec3-4fcd-9e80-b3c50b0fcd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767456635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.767456635
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2001180462
Short name T96
Test name
Test status
Simulation time 82098125 ps
CPU time 3.72 seconds
Started Jan 24 02:41:23 PM PST 24
Finished Jan 24 02:41:35 PM PST 24
Peak memory 213800 kb
Host smart-3a2c4644-4e80-4157-93cf-a81226c74652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001180462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2001180462
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.736317452
Short name T773
Test name
Test status
Simulation time 34834890 ps
CPU time 2.57 seconds
Started Jan 24 02:41:31 PM PST 24
Finished Jan 24 02:41:42 PM PST 24
Peak memory 215192 kb
Host smart-27da03c4-cdf0-46d9-8b1f-1aa111c56390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736317452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.736317452
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.398200396
Short name T889
Test name
Test status
Simulation time 113212710 ps
CPU time 3.49 seconds
Started Jan 24 02:41:26 PM PST 24
Finished Jan 24 02:41:36 PM PST 24
Peak memory 207256 kb
Host smart-5d7995c3-cdad-4d78-9e6c-457068e45793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398200396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.398200396
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1567470488
Short name T851
Test name
Test status
Simulation time 513367430 ps
CPU time 8.22 seconds
Started Jan 24 02:41:26 PM PST 24
Finished Jan 24 02:41:41 PM PST 24
Peak memory 208016 kb
Host smart-71ed6c10-c4dd-4a46-a3c6-1c5e62b61de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567470488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1567470488
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2426405250
Short name T904
Test name
Test status
Simulation time 5885945563 ps
CPU time 40.65 seconds
Started Jan 24 02:41:28 PM PST 24
Finished Jan 24 02:42:17 PM PST 24
Peak memory 207492 kb
Host smart-38a1593a-ae3a-4d40-b10a-e0e5447f8c95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426405250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2426405250
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2462042336
Short name T650
Test name
Test status
Simulation time 331122135 ps
CPU time 4.38 seconds
Started Jan 24 02:48:44 PM PST 24
Finished Jan 24 02:49:08 PM PST 24
Peak memory 207968 kb
Host smart-07f583a4-bbcd-4dce-ae5c-914d606215e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462042336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2462042336
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4222685132
Short name T782
Test name
Test status
Simulation time 991041482 ps
CPU time 3.27 seconds
Started Jan 24 02:41:31 PM PST 24
Finished Jan 24 02:41:43 PM PST 24
Peak memory 206032 kb
Host smart-b254cacf-41e9-456e-a817-f85092e241ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222685132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4222685132
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.840321122
Short name T601
Test name
Test status
Simulation time 55956147 ps
CPU time 1.67 seconds
Started Jan 24 02:41:26 PM PST 24
Finished Jan 24 02:41:35 PM PST 24
Peak memory 214564 kb
Host smart-a2929eb6-a7fe-4399-ad76-180a5d6945ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840321122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.840321122
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.406348730
Short name T704
Test name
Test status
Simulation time 64922976 ps
CPU time 2.32 seconds
Started Jan 24 02:41:32 PM PST 24
Finished Jan 24 02:41:42 PM PST 24
Peak memory 206004 kb
Host smart-5fdfd93c-c123-4fcf-9593-e9fe150542db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406348730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.406348730
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.260673047
Short name T630
Test name
Test status
Simulation time 85345331 ps
CPU time 3.14 seconds
Started Jan 24 02:41:37 PM PST 24
Finished Jan 24 02:41:47 PM PST 24
Peak memory 208844 kb
Host smart-b4ce68fb-ef38-4bc9-95c1-d6b4f99d1c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260673047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.260673047
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3455529745
Short name T981
Test name
Test status
Simulation time 3753110861 ps
CPU time 8.74 seconds
Started Jan 24 02:41:39 PM PST 24
Finished Jan 24 02:41:56 PM PST 24
Peak memory 222244 kb
Host smart-df3e1378-a5d1-4d1f-b415-f99c3d1cb147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455529745 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3455529745
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3476712027
Short name T256
Test name
Test status
Simulation time 1113350501 ps
CPU time 11.71 seconds
Started Jan 24 02:41:28 PM PST 24
Finished Jan 24 02:41:48 PM PST 24
Peak memory 206784 kb
Host smart-aabef102-0eb9-47d5-a8ad-89d739654ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476712027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3476712027
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.776813889
Short name T582
Test name
Test status
Simulation time 353621070 ps
CPU time 3.39 seconds
Started Jan 24 02:41:41 PM PST 24
Finished Jan 24 02:41:53 PM PST 24
Peak memory 209396 kb
Host smart-60b7f56f-6348-4765-8ffd-6ed50af95c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776813889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.776813889
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2833411531
Short name T412
Test name
Test status
Simulation time 12827122 ps
CPU time 0.9 seconds
Started Jan 24 02:41:53 PM PST 24
Finished Jan 24 02:41:59 PM PST 24
Peak memory 205360 kb
Host smart-9368b840-9dea-41f9-9644-c420e6f53736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833411531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2833411531
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3752536555
Short name T1087
Test name
Test status
Simulation time 59052802 ps
CPU time 4.08 seconds
Started Jan 24 02:41:42 PM PST 24
Finished Jan 24 02:41:53 PM PST 24
Peak memory 213844 kb
Host smart-798c4349-ccba-4f14-834f-9e09cf1bf38d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752536555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3752536555
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2438037669
Short name T1060
Test name
Test status
Simulation time 74245738 ps
CPU time 4.03 seconds
Started Jan 24 02:41:54 PM PST 24
Finished Jan 24 02:42:02 PM PST 24
Peak memory 209560 kb
Host smart-198ec037-34e5-45a1-b553-ce752ed88884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438037669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2438037669
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1520260591
Short name T969
Test name
Test status
Simulation time 51775537 ps
CPU time 2.8 seconds
Started Jan 24 02:55:58 PM PST 24
Finished Jan 24 02:56:06 PM PST 24
Peak memory 209476 kb
Host smart-3c34b1af-3a1c-4faf-b4b2-6b96958ff81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520260591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1520260591
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2240286056
Short name T907
Test name
Test status
Simulation time 262628689 ps
CPU time 3.37 seconds
Started Jan 24 02:41:53 PM PST 24
Finished Jan 24 02:42:01 PM PST 24
Peak memory 219928 kb
Host smart-38dc1f5b-af18-469e-894a-e1882271a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240286056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2240286056
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3906434303
Short name T942
Test name
Test status
Simulation time 1413306039 ps
CPU time 8.65 seconds
Started Jan 24 02:41:53 PM PST 24
Finished Jan 24 02:42:06 PM PST 24
Peak memory 213728 kb
Host smart-f4eed675-0ba4-432c-bec3-0850e6f18340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906434303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3906434303
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4010301500
Short name T395
Test name
Test status
Simulation time 156093832 ps
CPU time 4.16 seconds
Started Jan 24 02:41:48 PM PST 24
Finished Jan 24 02:41:59 PM PST 24
Peak memory 209100 kb
Host smart-3029ef05-3ba3-41a3-bbbf-1e1dd0993831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010301500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4010301500
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3158648605
Short name T988
Test name
Test status
Simulation time 72235868 ps
CPU time 3.6 seconds
Started Jan 24 02:41:39 PM PST 24
Finished Jan 24 02:41:50 PM PST 24
Peak memory 207880 kb
Host smart-5fd3536a-79e5-49df-b571-fa279261033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158648605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3158648605
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2079745186
Short name T771
Test name
Test status
Simulation time 2465056520 ps
CPU time 8.99 seconds
Started Jan 24 02:41:37 PM PST 24
Finished Jan 24 02:41:53 PM PST 24
Peak memory 207344 kb
Host smart-32f21281-4ac0-4640-beaa-f3ee5f4a77c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079745186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2079745186
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.759711780
Short name T958
Test name
Test status
Simulation time 559033070 ps
CPU time 4.97 seconds
Started Jan 24 02:41:41 PM PST 24
Finished Jan 24 02:41:54 PM PST 24
Peak memory 206120 kb
Host smart-5bbe8dd4-aac7-40de-924f-e32b6bc35a6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759711780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.759711780
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3567394589
Short name T912
Test name
Test status
Simulation time 219443785 ps
CPU time 6.8 seconds
Started Jan 24 02:41:39 PM PST 24
Finished Jan 24 02:41:54 PM PST 24
Peak memory 207904 kb
Host smart-32a2e5b1-0926-4aa5-9b3f-4b196cb3e920
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567394589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3567394589
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.7130330
Short name T881
Test name
Test status
Simulation time 174316890 ps
CPU time 3.87 seconds
Started Jan 24 03:10:59 PM PST 24
Finished Jan 24 03:11:07 PM PST 24
Peak memory 217644 kb
Host smart-98c7e979-2501-421c-a3cc-7cb383d8f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7130330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.7130330
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4019307903
Short name T596
Test name
Test status
Simulation time 460693199 ps
CPU time 2.52 seconds
Started Jan 24 02:41:41 PM PST 24
Finished Jan 24 02:41:51 PM PST 24
Peak memory 206032 kb
Host smart-585ce85b-4b98-498f-a3fc-5de8349e5c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019307903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4019307903
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2939697255
Short name T214
Test name
Test status
Simulation time 10630522065 ps
CPU time 188.13 seconds
Started Jan 24 02:41:53 PM PST 24
Finished Jan 24 02:45:06 PM PST 24
Peak memory 216000 kb
Host smart-be486cd3-f42e-4af8-bf94-04be15d9d712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939697255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2939697255
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3645020412
Short name T208
Test name
Test status
Simulation time 664078145 ps
CPU time 7.11 seconds
Started Jan 24 02:41:48 PM PST 24
Finished Jan 24 02:42:03 PM PST 24
Peak memory 222892 kb
Host smart-f4b3b242-032e-4efa-b086-c2a70b6e0f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645020412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3645020412
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3591206089
Short name T312
Test name
Test status
Simulation time 267660480 ps
CPU time 4.16 seconds
Started Jan 24 02:41:54 PM PST 24
Finished Jan 24 02:42:02 PM PST 24
Peak memory 217648 kb
Host smart-6e0825de-661b-467a-ac6e-613777fe0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591206089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3591206089
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.424869703
Short name T1067
Test name
Test status
Simulation time 279618770 ps
CPU time 4.25 seconds
Started Jan 24 03:02:29 PM PST 24
Finished Jan 24 03:02:42 PM PST 24
Peak memory 209088 kb
Host smart-d3ce643c-4886-4510-b1b8-9926cf9c8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424869703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.424869703
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.43478182
Short name T413
Test name
Test status
Simulation time 8450049 ps
CPU time 0.71 seconds
Started Jan 24 03:22:31 PM PST 24
Finished Jan 24 03:22:35 PM PST 24
Peak memory 205496 kb
Host smart-56f3ac8f-7f5e-416b-8f7d-387ec32835f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43478182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.43478182
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1010955148
Short name T403
Test name
Test status
Simulation time 40556067 ps
CPU time 2.95 seconds
Started Jan 24 02:42:05 PM PST 24
Finished Jan 24 02:42:13 PM PST 24
Peak memory 214332 kb
Host smart-de38dbb0-2ede-4534-ad41-030e7c70ef4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010955148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1010955148
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3906381401
Short name T682
Test name
Test status
Simulation time 155569354 ps
CPU time 5.47 seconds
Started Jan 24 02:42:02 PM PST 24
Finished Jan 24 02:42:12 PM PST 24
Peak memory 220864 kb
Host smart-cf3604d1-b2e6-4a05-829f-765efbf4a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906381401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3906381401
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3190515199
Short name T919
Test name
Test status
Simulation time 168451694 ps
CPU time 3.98 seconds
Started Jan 24 02:41:59 PM PST 24
Finished Jan 24 02:42:05 PM PST 24
Peak memory 209344 kb
Host smart-a75927ab-d296-4e6a-9cf6-6d34c505850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190515199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3190515199
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2654263255
Short name T778
Test name
Test status
Simulation time 759375734 ps
CPU time 8.23 seconds
Started Jan 24 02:55:07 PM PST 24
Finished Jan 24 02:55:22 PM PST 24
Peak memory 213848 kb
Host smart-04438401-a686-43da-ac2d-660b95abcfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654263255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2654263255
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.116076538
Short name T227
Test name
Test status
Simulation time 156602571 ps
CPU time 3.06 seconds
Started Jan 24 02:42:03 PM PST 24
Finished Jan 24 02:42:12 PM PST 24
Peak memory 213864 kb
Host smart-b5120914-9658-459a-af6f-f3b9713ac540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116076538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.116076538
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3016275253
Short name T786
Test name
Test status
Simulation time 1099146190 ps
CPU time 9.28 seconds
Started Jan 24 03:19:47 PM PST 24
Finished Jan 24 03:20:15 PM PST 24
Peak memory 206620 kb
Host smart-0b084d68-874d-45b5-8815-1440a7fd301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016275253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3016275253
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3817022941
Short name T990
Test name
Test status
Simulation time 170230895 ps
CPU time 2.77 seconds
Started Jan 24 05:50:45 PM PST 24
Finished Jan 24 05:50:48 PM PST 24
Peak memory 207876 kb
Host smart-816e1d89-92af-41ee-9c42-6ee792380b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817022941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3817022941
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.225031614
Short name T732
Test name
Test status
Simulation time 192910449 ps
CPU time 5.91 seconds
Started Jan 24 02:41:47 PM PST 24
Finished Jan 24 02:41:59 PM PST 24
Peak memory 208056 kb
Host smart-5fd11158-8805-40fe-9091-437c167b509a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225031614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.225031614
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3264172274
Short name T248
Test name
Test status
Simulation time 144317618 ps
CPU time 2.64 seconds
Started Jan 24 02:53:53 PM PST 24
Finished Jan 24 02:54:26 PM PST 24
Peak memory 207932 kb
Host smart-394596cc-bcd5-46c5-a82f-a24b34314305
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264172274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3264172274
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1962297723
Short name T364
Test name
Test status
Simulation time 450452133 ps
CPU time 13.01 seconds
Started Jan 24 02:42:04 PM PST 24
Finished Jan 24 02:42:22 PM PST 24
Peak memory 208880 kb
Host smart-10cb8b14-80f8-4554-8a27-2dffbd64d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962297723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1962297723
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.859341912
Short name T75
Test name
Test status
Simulation time 1843302780 ps
CPU time 18.2 seconds
Started Jan 24 02:41:49 PM PST 24
Finished Jan 24 02:42:14 PM PST 24
Peak memory 208292 kb
Host smart-031c0742-322b-437b-aa23-b0bb1eeff104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859341912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.859341912
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.667629218
Short name T44
Test name
Test status
Simulation time 1010481951 ps
CPU time 27.64 seconds
Started Jan 24 02:42:06 PM PST 24
Finished Jan 24 02:42:39 PM PST 24
Peak memory 220356 kb
Host smart-56d41a47-a4b7-4531-9d49-ae7358ca6523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667629218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.667629218
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3447035514
Short name T380
Test name
Test status
Simulation time 266195580 ps
CPU time 9.39 seconds
Started Jan 24 02:42:04 PM PST 24
Finished Jan 24 02:42:18 PM PST 24
Peak memory 222152 kb
Host smart-4d35ea8b-948d-49de-bd6c-5293f8d0e485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447035514 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3447035514
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.204670873
Short name T631
Test name
Test status
Simulation time 281111855 ps
CPU time 7.13 seconds
Started Jan 24 02:41:59 PM PST 24
Finished Jan 24 02:42:09 PM PST 24
Peak memory 207472 kb
Host smart-4a59e3cc-8908-47cc-b5e9-29fb7ac6eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204670873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.204670873
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.234146512
Short name T971
Test name
Test status
Simulation time 51127068 ps
CPU time 2.41 seconds
Started Jan 24 02:42:01 PM PST 24
Finished Jan 24 02:42:08 PM PST 24
Peak memory 209424 kb
Host smart-df833c43-8949-4e87-ad0e-91f951e85381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234146512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.234146512
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2688803893
Short name T933
Test name
Test status
Simulation time 66757290 ps
CPU time 0.85 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:23 PM PST 24
Peak memory 204920 kb
Host smart-b98eedd3-b084-4186-b660-7b9e77c83d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688803893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2688803893
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1337438286
Short name T245
Test name
Test status
Simulation time 45854566 ps
CPU time 3.4 seconds
Started Jan 24 02:42:17 PM PST 24
Finished Jan 24 02:42:29 PM PST 24
Peak memory 214064 kb
Host smart-6bc23a8c-854c-4d04-a359-87355d139b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337438286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1337438286
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4148028308
Short name T847
Test name
Test status
Simulation time 286719655 ps
CPU time 3.06 seconds
Started Jan 24 02:42:15 PM PST 24
Finished Jan 24 02:42:26 PM PST 24
Peak memory 207548 kb
Host smart-9b98ff15-c9ca-47a8-afca-91bce34d0cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148028308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4148028308
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.499570475
Short name T623
Test name
Test status
Simulation time 36942046 ps
CPU time 1.7 seconds
Started Jan 24 02:42:18 PM PST 24
Finished Jan 24 02:42:28 PM PST 24
Peak memory 213732 kb
Host smart-ce8ec632-d75e-4999-a5f9-63ae974b9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499570475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.499570475
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2120981913
Short name T91
Test name
Test status
Simulation time 1014946228 ps
CPU time 5.36 seconds
Started Jan 24 02:42:17 PM PST 24
Finished Jan 24 02:42:31 PM PST 24
Peak memory 213728 kb
Host smart-121830d4-631a-4289-90e9-1ecd274c3a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120981913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2120981913
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2775240365
Short name T834
Test name
Test status
Simulation time 111585544 ps
CPU time 4.72 seconds
Started Jan 24 02:42:18 PM PST 24
Finished Jan 24 02:42:32 PM PST 24
Peak memory 209156 kb
Host smart-12c2b417-f916-42ae-91d8-0de6b698c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775240365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2775240365
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.488311664
Short name T950
Test name
Test status
Simulation time 410028134 ps
CPU time 5.17 seconds
Started Jan 24 02:42:12 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 209488 kb
Host smart-f4681c1e-d9e2-480f-9adf-22a7d1dfb1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488311664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.488311664
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2682571394
Short name T661
Test name
Test status
Simulation time 84198218 ps
CPU time 2.7 seconds
Started Jan 24 02:42:02 PM PST 24
Finished Jan 24 02:42:09 PM PST 24
Peak memory 206136 kb
Host smart-6ca90db9-8153-4401-bba0-6558903a666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682571394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2682571394
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.994228056
Short name T743
Test name
Test status
Simulation time 128926529 ps
CPU time 2.5 seconds
Started Jan 24 02:42:10 PM PST 24
Finished Jan 24 02:42:20 PM PST 24
Peak memory 206068 kb
Host smart-7d69fe88-3326-4f34-aee3-30f72495d113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994228056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.994228056
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2843583439
Short name T385
Test name
Test status
Simulation time 109710474 ps
CPU time 2.39 seconds
Started Jan 24 02:42:04 PM PST 24
Finished Jan 24 02:42:12 PM PST 24
Peak memory 205996 kb
Host smart-cf4e3304-2896-4381-afaf-0e660d92af13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843583439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2843583439
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.293257805
Short name T837
Test name
Test status
Simulation time 261520595 ps
CPU time 6.02 seconds
Started Jan 24 02:42:11 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 207568 kb
Host smart-d42e1ca3-92b0-43ee-b19b-ea74f4a4b849
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293257805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.293257805
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2275560990
Short name T657
Test name
Test status
Simulation time 291672973 ps
CPU time 5.63 seconds
Started Jan 24 02:42:13 PM PST 24
Finished Jan 24 02:42:26 PM PST 24
Peak memory 208268 kb
Host smart-3b2cef06-1fb4-4618-899a-89d5aae97d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275560990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2275560990
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1518556714
Short name T1000
Test name
Test status
Simulation time 1379329747 ps
CPU time 21.4 seconds
Started Jan 24 02:42:06 PM PST 24
Finished Jan 24 02:42:32 PM PST 24
Peak memory 207540 kb
Host smart-5d29b09e-234c-4f8c-8999-f32f3598f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518556714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1518556714
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3367126441
Short name T664
Test name
Test status
Simulation time 692275539 ps
CPU time 10.67 seconds
Started Jan 24 02:42:13 PM PST 24
Finished Jan 24 02:42:31 PM PST 24
Peak memory 214596 kb
Host smart-a5fa9444-1efa-491a-9bf4-1b558fdb0065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367126441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3367126441
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2832599712
Short name T219
Test name
Test status
Simulation time 777292341 ps
CPU time 7.02 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:29 PM PST 24
Peak memory 221568 kb
Host smart-04262ba4-58ec-454e-a737-15795c2c0758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832599712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2832599712
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.568427467
Short name T277
Test name
Test status
Simulation time 798261037 ps
CPU time 6.76 seconds
Started Jan 24 02:42:11 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 208440 kb
Host smart-8e1007f6-5c8d-4378-b015-7c2777557b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568427467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.568427467
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4158452004
Short name T744
Test name
Test status
Simulation time 441970650 ps
CPU time 1.9 seconds
Started Jan 24 02:42:11 PM PST 24
Finished Jan 24 02:42:20 PM PST 24
Peak memory 209036 kb
Host smart-5b3108f3-4c83-4833-8b11-57eec4a53721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158452004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4158452004
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1961423760
Short name T998
Test name
Test status
Simulation time 8980523 ps
CPU time 0.7 seconds
Started Jan 24 02:42:23 PM PST 24
Finished Jan 24 02:42:35 PM PST 24
Peak memory 205504 kb
Host smart-da42c57d-10fb-4da6-85b1-ae315a7320bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961423760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1961423760
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1804796164
Short name T1034
Test name
Test status
Simulation time 481330562 ps
CPU time 21.1 seconds
Started Jan 24 02:42:22 PM PST 24
Finished Jan 24 02:42:55 PM PST 24
Peak memory 221652 kb
Host smart-15dfaf49-2b7f-4505-a0af-5ec92a628e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804796164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1804796164
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1040619603
Short name T779
Test name
Test status
Simulation time 175543199 ps
CPU time 4.93 seconds
Started Jan 24 02:42:22 PM PST 24
Finished Jan 24 02:42:37 PM PST 24
Peak memory 207284 kb
Host smart-d7b3b3b9-2dae-4083-8e9d-83b6bbd92607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040619603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1040619603
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3354465864
Short name T344
Test name
Test status
Simulation time 62289286 ps
CPU time 3.93 seconds
Started Jan 24 02:42:29 PM PST 24
Finished Jan 24 02:42:48 PM PST 24
Peak memory 211176 kb
Host smart-992f9df0-c569-4ed0-8886-a5564cfae2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354465864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3354465864
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1006356620
Short name T1073
Test name
Test status
Simulation time 147004221 ps
CPU time 4.82 seconds
Started Jan 24 02:42:24 PM PST 24
Finished Jan 24 02:42:41 PM PST 24
Peak memory 219404 kb
Host smart-6f92c091-ac8e-4579-82d8-49648ff02cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006356620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1006356620
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.641147031
Short name T647
Test name
Test status
Simulation time 153392288 ps
CPU time 4.57 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 208172 kb
Host smart-6aea2102-1bf1-4ab0-837b-389c30c4c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641147031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.641147031
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2302147340
Short name T192
Test name
Test status
Simulation time 86512891 ps
CPU time 3.62 seconds
Started Jan 24 02:42:18 PM PST 24
Finished Jan 24 02:42:30 PM PST 24
Peak memory 205944 kb
Host smart-dd11613d-70a0-4d0c-bea5-3a876c4af342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302147340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2302147340
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1872973646
Short name T1030
Test name
Test status
Simulation time 1860000719 ps
CPU time 65.49 seconds
Started Jan 24 02:42:12 PM PST 24
Finished Jan 24 02:43:25 PM PST 24
Peak memory 207712 kb
Host smart-27691c91-21cb-4944-9d3e-0ad2d82e7473
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872973646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1872973646
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1150908401
Short name T1004
Test name
Test status
Simulation time 738244510 ps
CPU time 5.3 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:26 PM PST 24
Peak memory 207880 kb
Host smart-3e8595c2-7f0b-41a7-85a6-d28c051fb958
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150908401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1150908401
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.435335120
Short name T698
Test name
Test status
Simulation time 95751942 ps
CPU time 4.07 seconds
Started Jan 24 02:42:17 PM PST 24
Finished Jan 24 02:42:29 PM PST 24
Peak memory 206096 kb
Host smart-682b8440-628f-4dc6-b877-2f2ac6ad76f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435335120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.435335120
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1799118787
Short name T286
Test name
Test status
Simulation time 90387652 ps
CPU time 3.69 seconds
Started Jan 24 02:42:30 PM PST 24
Finished Jan 24 02:42:48 PM PST 24
Peak memory 215508 kb
Host smart-3ff4e9d2-2bde-45bb-8e2f-02762f9a606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799118787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1799118787
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1935807533
Short name T1010
Test name
Test status
Simulation time 5715012406 ps
CPU time 19.49 seconds
Started Jan 24 02:42:14 PM PST 24
Finished Jan 24 02:42:41 PM PST 24
Peak memory 208024 kb
Host smart-2c82989d-35ca-41a0-bce3-d84f25510074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935807533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1935807533
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3620450481
Short name T1039
Test name
Test status
Simulation time 126736388 ps
CPU time 4.12 seconds
Started Jan 24 02:42:27 PM PST 24
Finished Jan 24 02:42:43 PM PST 24
Peak memory 222112 kb
Host smart-cb6cabc4-a921-4730-9707-9e0428e5a28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620450481 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3620450481
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2881780361
Short name T859
Test name
Test status
Simulation time 186719812 ps
CPU time 5.85 seconds
Started Jan 24 02:42:23 PM PST 24
Finished Jan 24 02:42:42 PM PST 24
Peak memory 213752 kb
Host smart-4a100d92-d2a4-4122-bd52-3b16c5277831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881780361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2881780361
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3954304036
Short name T162
Test name
Test status
Simulation time 151460994 ps
CPU time 2.07 seconds
Started Jan 24 02:42:31 PM PST 24
Finished Jan 24 02:42:47 PM PST 24
Peak memory 208968 kb
Host smart-8f77c9ab-dd30-4cb5-97b8-bb7cc75f9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954304036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3954304036
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.717080660
Short name T581
Test name
Test status
Simulation time 12148643 ps
CPU time 0.73 seconds
Started Jan 24 02:42:40 PM PST 24
Finished Jan 24 02:43:09 PM PST 24
Peak memory 205428 kb
Host smart-18f659eb-9011-4bfb-bba5-0fabd7843b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717080660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.717080660
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3633012260
Short name T32
Test name
Test status
Simulation time 162058748 ps
CPU time 4.1 seconds
Started Jan 24 02:42:41 PM PST 24
Finished Jan 24 02:43:12 PM PST 24
Peak memory 209272 kb
Host smart-8194921e-05d3-4ab4-8160-2310df1a30e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633012260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3633012260
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.8094283
Short name T2
Test name
Test status
Simulation time 46487990 ps
CPU time 2.35 seconds
Started Jan 24 02:42:37 PM PST 24
Finished Jan 24 02:43:02 PM PST 24
Peak memory 218000 kb
Host smart-8be88b1d-70f9-4ff8-894f-82fb61b116fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8094283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.8094283
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2145440987
Short name T24
Test name
Test status
Simulation time 124830058 ps
CPU time 2.7 seconds
Started Jan 24 02:42:41 PM PST 24
Finished Jan 24 02:43:10 PM PST 24
Peak memory 213676 kb
Host smart-423b2f59-94cc-4c3c-8d24-0dd4e10d6d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145440987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2145440987
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_random.1586205043
Short name T954
Test name
Test status
Simulation time 144730841 ps
CPU time 5.93 seconds
Started Jan 24 02:42:38 PM PST 24
Finished Jan 24 02:43:07 PM PST 24
Peak memory 217680 kb
Host smart-2e57a5db-cead-4bb7-8dce-3c00b67e1f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586205043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1586205043
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.457818920
Short name T356
Test name
Test status
Simulation time 216058896 ps
CPU time 3.85 seconds
Started Jan 24 02:42:26 PM PST 24
Finished Jan 24 02:42:43 PM PST 24
Peak memory 206024 kb
Host smart-e7141564-aba7-4e27-a2d9-0ceb82affcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457818920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.457818920
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.779574816
Short name T909
Test name
Test status
Simulation time 1970694561 ps
CPU time 7.74 seconds
Started Jan 24 02:42:29 PM PST 24
Finished Jan 24 02:42:52 PM PST 24
Peak memory 208216 kb
Host smart-355ab147-b6d5-474e-9782-22072685222b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779574816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.779574816
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3901932718
Short name T625
Test name
Test status
Simulation time 192285787 ps
CPU time 5.61 seconds
Started Jan 24 02:42:29 PM PST 24
Finished Jan 24 02:42:49 PM PST 24
Peak memory 207572 kb
Host smart-8b38bc95-0a09-4e94-8f6d-6a7fe2508df6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901932718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3901932718
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2506059084
Short name T373
Test name
Test status
Simulation time 184156995 ps
CPU time 2.71 seconds
Started Jan 24 02:42:32 PM PST 24
Finished Jan 24 02:42:48 PM PST 24
Peak memory 206504 kb
Host smart-40327929-337b-41ce-9699-2cca6ad5f230
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506059084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2506059084
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2134591278
Short name T799
Test name
Test status
Simulation time 886371347 ps
CPU time 11.18 seconds
Started Jan 24 02:42:34 PM PST 24
Finished Jan 24 02:43:02 PM PST 24
Peak memory 209120 kb
Host smart-b8c2da75-0be3-48d6-acf5-3448d0d29ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134591278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2134591278
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2007285940
Short name T610
Test name
Test status
Simulation time 35409167 ps
CPU time 2.38 seconds
Started Jan 24 02:42:25 PM PST 24
Finished Jan 24 02:42:39 PM PST 24
Peak memory 207944 kb
Host smart-d74884a8-e91a-4b38-a76d-6a69816d3cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007285940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2007285940
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2127135554
Short name T69
Test name
Test status
Simulation time 1543680330 ps
CPU time 20.27 seconds
Started Jan 24 02:42:40 PM PST 24
Finished Jan 24 02:43:27 PM PST 24
Peak memory 215536 kb
Host smart-015b4b03-3f46-4b5f-8ed5-134149b8d116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127135554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2127135554
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2001591924
Short name T209
Test name
Test status
Simulation time 178711485 ps
CPU time 5.76 seconds
Started Jan 24 02:42:39 PM PST 24
Finished Jan 24 02:43:12 PM PST 24
Peak memory 222104 kb
Host smart-77cf76d0-d398-4fe1-bed8-2263cea6e67a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001591924 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2001591924
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3399322518
Short name T793
Test name
Test status
Simulation time 104279525 ps
CPU time 4.95 seconds
Started Jan 24 02:42:40 PM PST 24
Finished Jan 24 02:43:12 PM PST 24
Peak memory 209644 kb
Host smart-c2646418-d72d-445e-8f60-af2767df46c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399322518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3399322518
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4283657635
Short name T711
Test name
Test status
Simulation time 74131796 ps
CPU time 0.84 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:31 PM PST 24
Peak memory 205484 kb
Host smart-975bf0a7-f937-417f-ba3a-e4d91eb9f9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283657635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4283657635
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.76791542
Short name T8
Test name
Test status
Simulation time 134330633 ps
CPU time 2.56 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:33 PM PST 24
Peak memory 215048 kb
Host smart-d5ffb0c6-0d6b-41f4-9a2c-cc78772e7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76791542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.76791542
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.508685584
Short name T64
Test name
Test status
Simulation time 459038891 ps
CPU time 2.99 seconds
Started Jan 24 02:42:45 PM PST 24
Finished Jan 24 02:43:19 PM PST 24
Peak memory 207944 kb
Host smart-d014736d-534b-416c-a2d0-6af5cc855578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508685584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.508685584
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2420050634
Short name T1051
Test name
Test status
Simulation time 348940440 ps
CPU time 4.56 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:34 PM PST 24
Peak memory 208720 kb
Host smart-ff397cdc-d1d5-4f0b-a30c-2ab3f335d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420050634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2420050634
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2951904603
Short name T197
Test name
Test status
Simulation time 180024405 ps
CPU time 4.93 seconds
Started Jan 24 02:42:47 PM PST 24
Finished Jan 24 02:43:28 PM PST 24
Peak memory 209992 kb
Host smart-77b1c945-425f-4532-a9c6-4a9d7ea821d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951904603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2951904603
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1328251700
Short name T690
Test name
Test status
Simulation time 114342422 ps
CPU time 5.03 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:35 PM PST 24
Peak memory 208212 kb
Host smart-77fafc52-6c28-42e9-a70b-dfeabf4844d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328251700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1328251700
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2537618008
Short name T369
Test name
Test status
Simulation time 14728637728 ps
CPU time 63.06 seconds
Started Jan 24 02:42:48 PM PST 24
Finished Jan 24 02:44:26 PM PST 24
Peak memory 217808 kb
Host smart-9f6fc7ab-c078-422b-9766-95f4dcf147b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537618008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2537618008
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.555321142
Short name T787
Test name
Test status
Simulation time 203069483 ps
CPU time 3.53 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:33 PM PST 24
Peak memory 205980 kb
Host smart-aa5715c7-8f84-4c64-83d7-4879d3d1d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555321142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.555321142
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2075966330
Short name T879
Test name
Test status
Simulation time 65156383 ps
CPU time 2.38 seconds
Started Jan 24 02:42:54 PM PST 24
Finished Jan 24 02:43:30 PM PST 24
Peak memory 206172 kb
Host smart-7d8e1530-ea5f-446a-9a3c-ea69e8a0ad8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075966330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2075966330
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.509011164
Short name T595
Test name
Test status
Simulation time 104508843 ps
CPU time 3.63 seconds
Started Jan 24 02:42:55 PM PST 24
Finished Jan 24 02:43:33 PM PST 24
Peak memory 207672 kb
Host smart-30c5301b-0c6e-45d2-9941-a508cfb5ebbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509011164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.509011164
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1893308723
Short name T1088
Test name
Test status
Simulation time 64283312 ps
CPU time 2.45 seconds
Started Jan 24 02:43:06 PM PST 24
Finished Jan 24 02:43:43 PM PST 24
Peak memory 206116 kb
Host smart-92284cbf-4473-4168-9d4a-fa4306d34404
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893308723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1893308723
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2803484564
Short name T728
Test name
Test status
Simulation time 56754586 ps
CPU time 2.6 seconds
Started Jan 24 02:42:50 PM PST 24
Finished Jan 24 02:43:28 PM PST 24
Peak memory 213884 kb
Host smart-b390967f-f6ac-4e6e-beea-8048b717ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803484564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2803484564
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3219365332
Short name T884
Test name
Test status
Simulation time 340487789 ps
CPU time 4.82 seconds
Started Jan 24 02:42:41 PM PST 24
Finished Jan 24 02:43:14 PM PST 24
Peak memory 207612 kb
Host smart-176c49fd-9061-4ee6-8a54-e1c4c2a5111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219365332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3219365332
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.549567837
Short name T833
Test name
Test status
Simulation time 4038376504 ps
CPU time 9.76 seconds
Started Jan 24 02:42:46 PM PST 24
Finished Jan 24 02:43:26 PM PST 24
Peak memory 222188 kb
Host smart-9b1da8c2-c4f9-4167-8ecf-117902177a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549567837 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.549567837
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1225650091
Short name T826
Test name
Test status
Simulation time 1221633910 ps
CPU time 8.84 seconds
Started Jan 24 02:42:51 PM PST 24
Finished Jan 24 02:43:33 PM PST 24
Peak memory 209240 kb
Host smart-7c99bae4-b3bc-4f95-b3f0-4a043e105a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225650091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1225650091
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.269917728
Short name T37
Test name
Test status
Simulation time 125867986 ps
CPU time 1.7 seconds
Started Jan 24 02:42:49 PM PST 24
Finished Jan 24 02:43:25 PM PST 24
Peak memory 209224 kb
Host smart-db89b537-e429-4a55-8fa1-626bfcb0579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269917728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.269917728
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2851454605
Short name T615
Test name
Test status
Simulation time 32544645 ps
CPU time 0.8 seconds
Started Jan 24 02:43:03 PM PST 24
Finished Jan 24 02:43:38 PM PST 24
Peak memory 205388 kb
Host smart-ea4bd842-cba6-4490-91f2-eba0156f2497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851454605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2851454605
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4248913665
Short name T341
Test name
Test status
Simulation time 39151716 ps
CPU time 3.06 seconds
Started Jan 24 02:43:02 PM PST 24
Finished Jan 24 02:43:39 PM PST 24
Peak memory 214272 kb
Host smart-16b73475-d838-445d-a35c-a72fcac64ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248913665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4248913665
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2718569820
Short name T666
Test name
Test status
Simulation time 217382698 ps
CPU time 2.97 seconds
Started Jan 24 02:43:05 PM PST 24
Finished Jan 24 02:43:42 PM PST 24
Peak memory 208392 kb
Host smart-a947961f-e47f-404f-bc9b-3b32b872814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718569820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2718569820
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3877917500
Short name T843
Test name
Test status
Simulation time 481497073 ps
CPU time 2.68 seconds
Started Jan 24 02:42:59 PM PST 24
Finished Jan 24 02:43:35 PM PST 24
Peak memory 207580 kb
Host smart-08e0f127-2e04-4fee-886a-1e3f730fede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877917500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3877917500
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2705797554
Short name T194
Test name
Test status
Simulation time 472022040 ps
CPU time 6.34 seconds
Started Jan 24 02:43:05 PM PST 24
Finished Jan 24 02:43:45 PM PST 24
Peak memory 213832 kb
Host smart-03c77fb8-768d-4e53-bc6c-9a1c73307b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705797554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2705797554
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2630287699
Short name T668
Test name
Test status
Simulation time 97722332 ps
CPU time 4.39 seconds
Started Jan 24 02:42:59 PM PST 24
Finished Jan 24 02:43:36 PM PST 24
Peak memory 208104 kb
Host smart-20b5def5-af5f-417a-b526-9ce1bb8ae679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630287699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2630287699
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1879570500
Short name T997
Test name
Test status
Simulation time 401030391 ps
CPU time 4.64 seconds
Started Jan 24 02:42:59 PM PST 24
Finished Jan 24 02:43:37 PM PST 24
Peak memory 207372 kb
Host smart-709faf9d-5787-4961-bb7d-e46dd8b60c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879570500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1879570500
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4140232134
Short name T350
Test name
Test status
Simulation time 160772006 ps
CPU time 3.24 seconds
Started Jan 24 02:42:47 PM PST 24
Finished Jan 24 02:43:23 PM PST 24
Peak memory 206084 kb
Host smart-0ab99352-874d-49d0-9987-98f884e699a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140232134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4140232134
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3579315134
Short name T1040
Test name
Test status
Simulation time 155758322 ps
CPU time 2.47 seconds
Started Jan 24 02:42:58 PM PST 24
Finished Jan 24 02:43:33 PM PST 24
Peak memory 206152 kb
Host smart-830fd680-36e1-49d9-9741-54e880832d01
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579315134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3579315134
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.77731627
Short name T621
Test name
Test status
Simulation time 40017107 ps
CPU time 1.68 seconds
Started Jan 24 02:43:05 PM PST 24
Finished Jan 24 02:43:41 PM PST 24
Peak memory 206096 kb
Host smart-dbb0a1a0-76bc-4cc9-882e-c3972baeddd8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77731627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.77731627
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3668217308
Short name T81
Test name
Test status
Simulation time 2012003925 ps
CPU time 21.2 seconds
Started Jan 24 02:42:56 PM PST 24
Finished Jan 24 02:43:52 PM PST 24
Peak memory 208272 kb
Host smart-35dd8b5d-364c-4b38-9932-e7fbbbdf709e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668217308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3668217308
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1570972248
Short name T585
Test name
Test status
Simulation time 190543504 ps
CPU time 2.83 seconds
Started Jan 24 02:42:58 PM PST 24
Finished Jan 24 02:43:34 PM PST 24
Peak memory 206160 kb
Host smart-7ccd82f0-915c-45a9-80b4-c5fb4b8a3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570972248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1570972248
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2361957290
Short name T848
Test name
Test status
Simulation time 38324350 ps
CPU time 2.43 seconds
Started Jan 24 02:42:48 PM PST 24
Finished Jan 24 02:43:26 PM PST 24
Peak memory 206596 kb
Host smart-108e7c7b-2314-45cd-ad70-7325d3401ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361957290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2361957290
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3590979507
Short name T67
Test name
Test status
Simulation time 14207688830 ps
CPU time 406.25 seconds
Started Jan 24 02:42:58 PM PST 24
Finished Jan 24 02:50:17 PM PST 24
Peak memory 222128 kb
Host smart-15b5280d-11ff-40d7-abfa-ea03ff1f978d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590979507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3590979507
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.107891491
Short name T1046
Test name
Test status
Simulation time 1138897707 ps
CPU time 7.08 seconds
Started Jan 24 02:43:03 PM PST 24
Finished Jan 24 02:43:44 PM PST 24
Peak memory 219824 kb
Host smart-648273d6-0ca2-437f-b412-a17e9b0846d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107891491 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.107891491
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2362338654
Short name T1029
Test name
Test status
Simulation time 131536433 ps
CPU time 3.03 seconds
Started Jan 24 02:42:57 PM PST 24
Finished Jan 24 02:43:34 PM PST 24
Peak memory 213776 kb
Host smart-dd32b30e-55aa-4539-af14-0444a918e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362338654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2362338654
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.974814571
Short name T676
Test name
Test status
Simulation time 229343026 ps
CPU time 3.15 seconds
Started Jan 24 02:43:04 PM PST 24
Finished Jan 24 02:43:41 PM PST 24
Peak memory 209408 kb
Host smart-ecc35b78-3bdc-454c-98b7-a15f4335bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974814571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.974814571
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.704615184
Short name T689
Test name
Test status
Simulation time 18710663 ps
CPU time 0.76 seconds
Started Jan 24 02:39:04 PM PST 24
Finished Jan 24 02:39:07 PM PST 24
Peak memory 205492 kb
Host smart-04151b31-ffe5-4568-81bd-0d69f85e9856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704615184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.704615184
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1499913289
Short name T392
Test name
Test status
Simulation time 131746645 ps
CPU time 2.91 seconds
Started Jan 24 02:39:08 PM PST 24
Finished Jan 24 02:39:22 PM PST 24
Peak memory 214056 kb
Host smart-32855685-17d4-42d1-bae0-9a9ba33505ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499913289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1499913289
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3770129676
Short name T687
Test name
Test status
Simulation time 3060816320 ps
CPU time 22.37 seconds
Started Jan 24 02:39:04 PM PST 24
Finished Jan 24 02:39:29 PM PST 24
Peak memory 208900 kb
Host smart-a5826799-1031-4bd1-98da-8509695551e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770129676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3770129676
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3543232939
Short name T264
Test name
Test status
Simulation time 9059860157 ps
CPU time 62.52 seconds
Started Jan 24 02:39:03 PM PST 24
Finished Jan 24 02:40:08 PM PST 24
Peak memory 220040 kb
Host smart-3f3d827e-19a6-4616-9b84-b5b2ca0915e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543232939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3543232939
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.84454914
Short name T325
Test name
Test status
Simulation time 159052713 ps
CPU time 4.1 seconds
Started Jan 24 02:39:03 PM PST 24
Finished Jan 24 02:39:09 PM PST 24
Peak memory 213856 kb
Host smart-7cdfd662-9345-4869-8e02-7df24459a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84454914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.84454914
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2201908017
Short name T712
Test name
Test status
Simulation time 1095297008 ps
CPU time 8.06 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:08 PM PST 24
Peak memory 208676 kb
Host smart-95749729-7f14-4f2e-a9ae-37446310f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201908017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2201908017
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1603520591
Short name T633
Test name
Test status
Simulation time 548732599 ps
CPU time 6.74 seconds
Started Jan 24 06:33:10 PM PST 24
Finished Jan 24 06:33:18 PM PST 24
Peak memory 207284 kb
Host smart-bcecf40a-0f0b-4fcb-ae7a-f18367ee72ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603520591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1603520591
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3108797484
Short name T315
Test name
Test status
Simulation time 274938702 ps
CPU time 3.52 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:04 PM PST 24
Peak memory 207508 kb
Host smart-e8aea201-5e39-415d-b328-ab5e6707c55e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108797484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3108797484
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3284570497
Short name T719
Test name
Test status
Simulation time 186981426 ps
CPU time 5.75 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:06 PM PST 24
Peak memory 207248 kb
Host smart-1546b68f-3fd3-495f-99fa-a31c101668cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284570497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3284570497
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4113391712
Short name T1090
Test name
Test status
Simulation time 71105954 ps
CPU time 3.41 seconds
Started Jan 24 02:39:08 PM PST 24
Finished Jan 24 02:39:23 PM PST 24
Peak memory 208944 kb
Host smart-aca9fd97-6d19-47b5-91d0-e3c7c8da7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113391712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4113391712
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1531917348
Short name T703
Test name
Test status
Simulation time 115445782 ps
CPU time 3.04 seconds
Started Jan 24 02:38:55 PM PST 24
Finished Jan 24 02:39:03 PM PST 24
Peak memory 207472 kb
Host smart-f448bd21-86bf-4719-8ba6-7d8f8cb444e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531917348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1531917348
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3122439719
Short name T68
Test name
Test status
Simulation time 67617706578 ps
CPU time 161.71 seconds
Started Jan 24 02:39:01 PM PST 24
Finished Jan 24 02:41:45 PM PST 24
Peak memory 217608 kb
Host smart-e93aaec6-554b-4921-8062-5a1f56802415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122439719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3122439719
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2088628113
Short name T215
Test name
Test status
Simulation time 151664658 ps
CPU time 7.93 seconds
Started Jan 24 02:39:03 PM PST 24
Finished Jan 24 02:39:13 PM PST 24
Peak memory 222064 kb
Host smart-6263e974-cfe2-4ad9-b965-50764896f47a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088628113 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2088628113
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2868818756
Short name T271
Test name
Test status
Simulation time 170053088 ps
CPU time 3.24 seconds
Started Jan 24 02:39:04 PM PST 24
Finished Jan 24 02:39:10 PM PST 24
Peak memory 217652 kb
Host smart-fbb2c895-a464-4a68-9bc8-292a10f4d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868818756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2868818756
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1124324422
Short name T708
Test name
Test status
Simulation time 104488961 ps
CPU time 1.67 seconds
Started Jan 24 02:39:04 PM PST 24
Finished Jan 24 02:39:08 PM PST 24
Peak memory 208836 kb
Host smart-5d92a628-f1be-4f42-8b39-f614642fa71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124324422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1124324422
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.413772951
Short name T864
Test name
Test status
Simulation time 107506042 ps
CPU time 0.81 seconds
Started Jan 24 03:24:49 PM PST 24
Finished Jan 24 03:25:08 PM PST 24
Peak memory 205492 kb
Host smart-23977f37-27da-453b-90c4-507f72dfcbe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413772951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.413772951
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.463599702
Short name T357
Test name
Test status
Simulation time 123248173 ps
CPU time 2.52 seconds
Started Jan 24 02:43:37 PM PST 24
Finished Jan 24 02:44:07 PM PST 24
Peak memory 208688 kb
Host smart-4255500a-05fb-46f9-bd3b-31bf159e4b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463599702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.463599702
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2029593063
Short name T924
Test name
Test status
Simulation time 620706603 ps
CPU time 5.11 seconds
Started Jan 24 02:43:37 PM PST 24
Finished Jan 24 02:44:09 PM PST 24
Peak memory 219500 kb
Host smart-32c69188-6f1d-4f1d-b5cd-dd59e82e9cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029593063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2029593063
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2525948566
Short name T244
Test name
Test status
Simulation time 59594161 ps
CPU time 3.47 seconds
Started Jan 24 02:43:37 PM PST 24
Finished Jan 24 02:44:07 PM PST 24
Peak memory 209708 kb
Host smart-6562d0d1-26d0-4292-a515-a008dc265966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525948566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2525948566
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.841820208
Short name T946
Test name
Test status
Simulation time 987581648 ps
CPU time 3.88 seconds
Started Jan 24 02:57:35 PM PST 24
Finished Jan 24 02:57:50 PM PST 24
Peak memory 213872 kb
Host smart-7d85c9ff-4c44-45c7-be47-0f2d8b7926c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841820208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.841820208
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3980141596
Short name T311
Test name
Test status
Simulation time 518451370 ps
CPU time 5.75 seconds
Started Jan 24 02:43:40 PM PST 24
Finished Jan 24 02:44:11 PM PST 24
Peak memory 209412 kb
Host smart-4cc90c92-6f0f-4f23-ac02-3048e86eb416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980141596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3980141596
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.790716984
Short name T1048
Test name
Test status
Simulation time 135311982 ps
CPU time 2.34 seconds
Started Jan 24 02:43:05 PM PST 24
Finished Jan 24 02:43:41 PM PST 24
Peak memory 205924 kb
Host smart-7c00e900-db5f-467a-8fe3-d3c27fb2a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790716984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.790716984
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1291626632
Short name T580
Test name
Test status
Simulation time 194456153 ps
CPU time 2.61 seconds
Started Jan 24 02:43:37 PM PST 24
Finished Jan 24 02:44:07 PM PST 24
Peak memory 205868 kb
Host smart-8fc4f739-ab12-4e85-9787-ee05fab8a7bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291626632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1291626632
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3570843937
Short name T756
Test name
Test status
Simulation time 90767326 ps
CPU time 3.38 seconds
Started Jan 24 03:52:21 PM PST 24
Finished Jan 24 03:52:26 PM PST 24
Peak memory 207808 kb
Host smart-3af327fd-954a-4ae2-9295-102c92fcb6c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570843937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3570843937
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2448008842
Short name T269
Test name
Test status
Simulation time 605843761 ps
CPU time 13.04 seconds
Started Jan 24 04:20:43 PM PST 24
Finished Jan 24 04:20:57 PM PST 24
Peak memory 207784 kb
Host smart-b57ec0cf-1b86-45b1-8337-9e4249cf31e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448008842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2448008842
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.816774740
Short name T619
Test name
Test status
Simulation time 116688204 ps
CPU time 3.79 seconds
Started Jan 24 02:43:51 PM PST 24
Finished Jan 24 02:44:14 PM PST 24
Peak memory 209388 kb
Host smart-4f5e584d-aaa8-4d43-8927-07d737fbf74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816774740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.816774740
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3124172897
Short name T635
Test name
Test status
Simulation time 111861194 ps
CPU time 2.55 seconds
Started Jan 24 02:42:59 PM PST 24
Finished Jan 24 02:43:35 PM PST 24
Peak memory 206340 kb
Host smart-7db35d9a-09e2-435e-b885-d849fed5e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124172897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3124172897
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3172984149
Short name T313
Test name
Test status
Simulation time 1215602025 ps
CPU time 38.42 seconds
Started Jan 24 02:43:50 PM PST 24
Finished Jan 24 02:44:48 PM PST 24
Peak memory 214700 kb
Host smart-2ac462ca-ad95-487c-aa03-f1fa30c5939e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172984149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3172984149
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2277993584
Short name T1086
Test name
Test status
Simulation time 160038887 ps
CPU time 4.85 seconds
Started Jan 24 02:43:58 PM PST 24
Finished Jan 24 02:44:19 PM PST 24
Peak memory 222144 kb
Host smart-bf8fb394-6858-462d-92db-4c290444ab02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277993584 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2277993584
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2871469818
Short name T767
Test name
Test status
Simulation time 2533473927 ps
CPU time 26.62 seconds
Started Jan 24 02:43:40 PM PST 24
Finished Jan 24 02:44:32 PM PST 24
Peak memory 210068 kb
Host smart-ed59bfd5-5bdd-427d-a3c5-a9315b703f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871469818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2871469818
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2234031782
Short name T1065
Test name
Test status
Simulation time 124698987 ps
CPU time 2.13 seconds
Started Jan 24 03:10:51 PM PST 24
Finished Jan 24 03:10:57 PM PST 24
Peak memory 209204 kb
Host smart-75d32b1e-cc97-43f8-89b2-4d4839dcc4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234031782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2234031782
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.460339472
Short name T632
Test name
Test status
Simulation time 22552007 ps
CPU time 0.76 seconds
Started Jan 24 02:44:01 PM PST 24
Finished Jan 24 02:44:17 PM PST 24
Peak memory 205408 kb
Host smart-014ed652-0cee-4ed2-a960-cb1971c392a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460339472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.460339472
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1152273230
Short name T400
Test name
Test status
Simulation time 70200669 ps
CPU time 2.81 seconds
Started Jan 24 02:44:05 PM PST 24
Finished Jan 24 02:44:21 PM PST 24
Peak memory 214172 kb
Host smart-0aec7384-16d4-400d-9e16-2963c9f84599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152273230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1152273230
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1401956624
Short name T35
Test name
Test status
Simulation time 608712146 ps
CPU time 5.23 seconds
Started Jan 24 02:44:02 PM PST 24
Finished Jan 24 02:44:22 PM PST 24
Peak memory 213812 kb
Host smart-ab47570c-d171-453f-ad37-9a82fc845d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401956624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1401956624
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.677043175
Short name T854
Test name
Test status
Simulation time 173633871 ps
CPU time 1.91 seconds
Started Jan 24 02:44:00 PM PST 24
Finished Jan 24 02:44:17 PM PST 24
Peak memory 207620 kb
Host smart-749c63a1-2d95-46f1-b318-45c41935a9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677043175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.677043175
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1108953039
Short name T720
Test name
Test status
Simulation time 149051890 ps
CPU time 2.81 seconds
Started Jan 24 02:44:08 PM PST 24
Finished Jan 24 02:44:23 PM PST 24
Peak memory 213780 kb
Host smart-0d1a3f87-e0bb-4218-a750-7ef3c1e91a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108953039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1108953039
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3600151733
Short name T260
Test name
Test status
Simulation time 196655335 ps
CPU time 5.11 seconds
Started Jan 24 02:44:04 PM PST 24
Finished Jan 24 02:44:23 PM PST 24
Peak memory 221816 kb
Host smart-e4a419ed-2547-47a8-ac65-abf4f4e3622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600151733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3600151733
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.116825039
Short name T281
Test name
Test status
Simulation time 205073005 ps
CPU time 5.05 seconds
Started Jan 24 02:44:08 PM PST 24
Finished Jan 24 02:44:25 PM PST 24
Peak memory 213844 kb
Host smart-f787e42c-2357-41e4-b0cc-86451f83e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116825039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.116825039
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4126675705
Short name T1049
Test name
Test status
Simulation time 314790839 ps
CPU time 5.17 seconds
Started Jan 24 02:43:59 PM PST 24
Finished Jan 24 02:44:20 PM PST 24
Peak memory 209048 kb
Host smart-9be3c7b5-b255-4182-adcb-044f77eb606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126675705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4126675705
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.262716016
Short name T663
Test name
Test status
Simulation time 234709994 ps
CPU time 2.62 seconds
Started Jan 24 02:43:51 PM PST 24
Finished Jan 24 02:44:13 PM PST 24
Peak memory 206016 kb
Host smart-c5dc0616-b3d7-4856-85bf-f6b9fdbeeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262716016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.262716016
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1277806455
Short name T656
Test name
Test status
Simulation time 87286615 ps
CPU time 2.46 seconds
Started Jan 24 02:44:08 PM PST 24
Finished Jan 24 02:44:23 PM PST 24
Peak memory 207216 kb
Host smart-eca55224-1007-426c-a3a2-f567e1e4ed2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277806455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1277806455
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3546748035
Short name T846
Test name
Test status
Simulation time 216016564 ps
CPU time 2.99 seconds
Started Jan 24 02:46:40 PM PST 24
Finished Jan 24 02:46:47 PM PST 24
Peak memory 207740 kb
Host smart-425f05cc-b78c-472d-9044-d8d7a29fb0a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546748035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3546748035
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2483713108
Short name T299
Test name
Test status
Simulation time 129093830 ps
CPU time 3.4 seconds
Started Jan 24 02:44:04 PM PST 24
Finished Jan 24 02:44:21 PM PST 24
Peak memory 208156 kb
Host smart-2912bc80-28fc-4fdf-9e72-06ff5475c094
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483713108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2483713108
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1030609608
Short name T193
Test name
Test status
Simulation time 549554780 ps
CPU time 3.33 seconds
Started Jan 24 02:44:06 PM PST 24
Finished Jan 24 02:44:22 PM PST 24
Peak memory 208448 kb
Host smart-54840e4d-020f-402d-99b0-eed9e58e1452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030609608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1030609608
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2890608985
Short name T602
Test name
Test status
Simulation time 47428896 ps
CPU time 2.03 seconds
Started Jan 24 02:43:53 PM PST 24
Finished Jan 24 02:44:13 PM PST 24
Peak memory 207728 kb
Host smart-c4566d8a-bd0f-4955-80a9-c91f9f178976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890608985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2890608985
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2309878823
Short name T65
Test name
Test status
Simulation time 31893411262 ps
CPU time 317.91 seconds
Started Jan 24 02:44:01 PM PST 24
Finished Jan 24 02:49:35 PM PST 24
Peak memory 219652 kb
Host smart-906cc918-06da-426e-b343-0489dcfecc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309878823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2309878823
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.993689366
Short name T213
Test name
Test status
Simulation time 355903108 ps
CPU time 5.72 seconds
Started Jan 24 02:44:01 PM PST 24
Finished Jan 24 02:44:22 PM PST 24
Peak memory 222080 kb
Host smart-a9348412-fe6d-4d7a-a7fc-edbbdbf5feb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993689366 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.993689366
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3744585563
Short name T321
Test name
Test status
Simulation time 704927779 ps
CPU time 8.63 seconds
Started Jan 24 02:44:05 PM PST 24
Finished Jan 24 02:44:27 PM PST 24
Peak memory 213768 kb
Host smart-38e5d974-4ce5-4fa7-b387-77fa2f5a0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744585563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3744585563
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3731271965
Short name T781
Test name
Test status
Simulation time 47125832 ps
CPU time 1.69 seconds
Started Jan 24 02:44:04 PM PST 24
Finished Jan 24 02:44:20 PM PST 24
Peak memory 209308 kb
Host smart-06cf347c-df94-4163-a4b8-21ea3bba01d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731271965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3731271965
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1342321313
Short name T586
Test name
Test status
Simulation time 47125058 ps
CPU time 0.74 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:45 PM PST 24
Peak memory 205484 kb
Host smart-b9282fc5-0675-4bd7-a8f9-a5929aeec5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342321313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1342321313
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1958010155
Short name T729
Test name
Test status
Simulation time 50824586 ps
CPU time 2.05 seconds
Started Jan 24 02:44:18 PM PST 24
Finished Jan 24 02:44:41 PM PST 24
Peak memory 206652 kb
Host smart-521f7eeb-c0c3-4222-a7fd-a196fc132a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958010155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1958010155
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.981616244
Short name T707
Test name
Test status
Simulation time 77776147 ps
CPU time 3.08 seconds
Started Jan 24 02:44:08 PM PST 24
Finished Jan 24 02:44:23 PM PST 24
Peak memory 222088 kb
Host smart-a3e89109-f4b3-45dd-9388-1f6c51f6d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981616244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.981616244
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3969230673
Short name T53
Test name
Test status
Simulation time 155835115 ps
CPU time 4.22 seconds
Started Jan 24 02:44:20 PM PST 24
Finished Jan 24 02:44:45 PM PST 24
Peak memory 209712 kb
Host smart-e3cee78f-1e4c-4c10-b022-cd4460f37351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969230673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3969230673
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.833482627
Short name T696
Test name
Test status
Simulation time 291851083 ps
CPU time 4.52 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:47 PM PST 24
Peak memory 209036 kb
Host smart-2fbae0b6-ac94-41f6-9576-2276654878f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833482627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.833482627
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3191589014
Short name T916
Test name
Test status
Simulation time 57608149 ps
CPU time 2.34 seconds
Started Jan 24 02:44:04 PM PST 24
Finished Jan 24 02:44:20 PM PST 24
Peak memory 208176 kb
Host smart-7930ab35-d598-42fb-8833-b1ee8a04e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191589014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3191589014
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1619047916
Short name T957
Test name
Test status
Simulation time 967245710 ps
CPU time 5.96 seconds
Started Jan 24 02:44:02 PM PST 24
Finished Jan 24 02:44:23 PM PST 24
Peak memory 207828 kb
Host smart-37c8c1ea-4b97-4814-9857-d24cb52acf1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619047916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1619047916
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3063378688
Short name T648
Test name
Test status
Simulation time 71367007 ps
CPU time 2.5 seconds
Started Jan 24 02:44:02 PM PST 24
Finished Jan 24 02:44:19 PM PST 24
Peak memory 205868 kb
Host smart-497e4e81-d93b-41ef-8681-d7fbc175ef79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063378688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3063378688
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2898226851
Short name T575
Test name
Test status
Simulation time 477652850 ps
CPU time 5.7 seconds
Started Jan 24 02:44:08 PM PST 24
Finished Jan 24 02:44:26 PM PST 24
Peak memory 207864 kb
Host smart-d12c44ac-f876-4416-a5e3-de9208e323b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898226851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2898226851
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.621540046
Short name T905
Test name
Test status
Simulation time 190754946 ps
CPU time 4.75 seconds
Started Jan 24 02:56:44 PM PST 24
Finished Jan 24 02:56:50 PM PST 24
Peak memory 209156 kb
Host smart-6c265ec1-917b-4d39-a68d-ae8f253f0549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621540046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.621540046
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2379252384
Short name T910
Test name
Test status
Simulation time 278383236 ps
CPU time 3.17 seconds
Started Jan 24 02:44:02 PM PST 24
Finished Jan 24 02:44:20 PM PST 24
Peak memory 206320 kb
Host smart-074e283f-5558-4f10-8849-30fbe169644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379252384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2379252384
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3558374699
Short name T867
Test name
Test status
Simulation time 3973801073 ps
CPU time 20.75 seconds
Started Jan 24 02:44:15 PM PST 24
Finished Jan 24 02:44:58 PM PST 24
Peak memory 216300 kb
Host smart-ee5b493f-3565-420d-ab11-164cfa95d491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558374699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3558374699
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2016589823
Short name T113
Test name
Test status
Simulation time 1065238227 ps
CPU time 8.55 seconds
Started Jan 24 02:44:17 PM PST 24
Finished Jan 24 02:44:47 PM PST 24
Peak memory 219328 kb
Host smart-456cdd77-cbf4-4d1b-b49c-10f5ad1192ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016589823 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2016589823
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1117468522
Short name T196
Test name
Test status
Simulation time 92670091 ps
CPU time 4.15 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:48 PM PST 24
Peak memory 208588 kb
Host smart-1c9f6e69-e785-409b-bdd9-64cd44e42d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117468522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1117468522
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1424581333
Short name T792
Test name
Test status
Simulation time 88943746 ps
CPU time 2.3 seconds
Started Jan 24 02:44:17 PM PST 24
Finished Jan 24 02:44:41 PM PST 24
Peak memory 208764 kb
Host smart-558bc9d0-28e0-4a44-aa55-2b46467250a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424581333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1424581333
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1519486264
Short name T101
Test name
Test status
Simulation time 17757515 ps
CPU time 0.78 seconds
Started Jan 24 02:44:25 PM PST 24
Finished Jan 24 02:44:45 PM PST 24
Peak memory 205440 kb
Host smart-52c9bc87-89c5-461a-9857-6648ab3ae725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519486264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1519486264
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3043353837
Short name T1066
Test name
Test status
Simulation time 528683143 ps
CPU time 9.7 seconds
Started Jan 24 02:44:28 PM PST 24
Finished Jan 24 02:44:53 PM PST 24
Peak memory 218836 kb
Host smart-4ddadeb0-7b73-4156-9174-f190981d46aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043353837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3043353837
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1983277969
Short name T1028
Test name
Test status
Simulation time 87251087 ps
CPU time 2.75 seconds
Started Jan 24 04:26:50 PM PST 24
Finished Jan 24 04:26:57 PM PST 24
Peak memory 208152 kb
Host smart-9488eb5e-a465-4a24-9100-43cce80e0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983277969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1983277969
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1238482801
Short name T87
Test name
Test status
Simulation time 312622031 ps
CPU time 2.84 seconds
Started Jan 24 02:44:23 PM PST 24
Finished Jan 24 02:44:49 PM PST 24
Peak memory 207696 kb
Host smart-30301413-2ee6-48c7-b698-45cce7ef3756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238482801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1238482801
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2193039084
Short name T897
Test name
Test status
Simulation time 1434376335 ps
CPU time 22.07 seconds
Started Jan 24 02:44:21 PM PST 24
Finished Jan 24 02:45:04 PM PST 24
Peak memory 213676 kb
Host smart-9e45224c-2bff-4ea0-9d33-89b86e3dcd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193039084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2193039084
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3429799657
Short name T212
Test name
Test status
Simulation time 56964962 ps
CPU time 3.58 seconds
Started Jan 24 02:44:25 PM PST 24
Finished Jan 24 02:44:47 PM PST 24
Peak memory 209588 kb
Host smart-aeb5143b-01db-42e7-ba45-2ee7d219c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429799657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3429799657
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2070337818
Short name T959
Test name
Test status
Simulation time 148679228 ps
CPU time 2.75 seconds
Started Jan 24 02:44:28 PM PST 24
Finished Jan 24 02:44:47 PM PST 24
Peak memory 206620 kb
Host smart-af23b13a-6ae3-4c28-ac08-990491bbcca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070337818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2070337818
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.837967368
Short name T268
Test name
Test status
Simulation time 44921130 ps
CPU time 2.03 seconds
Started Jan 24 02:44:20 PM PST 24
Finished Jan 24 02:44:43 PM PST 24
Peak memory 206684 kb
Host smart-d2a52cf2-6f24-4607-b3f4-746d44696025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837967368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.837967368
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.261777150
Short name T334
Test name
Test status
Simulation time 2375333632 ps
CPU time 24.99 seconds
Started Jan 24 02:44:28 PM PST 24
Finished Jan 24 02:45:09 PM PST 24
Peak memory 207376 kb
Host smart-7086e850-c75d-4a90-8883-eb61d748cf75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261777150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.261777150
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2531055364
Short name T568
Test name
Test status
Simulation time 145288115 ps
CPU time 4.56 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:52 PM PST 24
Peak memory 206040 kb
Host smart-ba391536-1dce-4349-a5c6-f9bfeb57d4fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531055364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2531055364
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1586858595
Short name T1024
Test name
Test status
Simulation time 1107619857 ps
CPU time 7.17 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:44:54 PM PST 24
Peak memory 207036 kb
Host smart-ec0a97e6-8659-41cf-a93d-54c29f95c455
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586858595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1586858595
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2783542120
Short name T973
Test name
Test status
Simulation time 287508559 ps
CPU time 3.44 seconds
Started Jan 24 04:14:21 PM PST 24
Finished Jan 24 04:14:29 PM PST 24
Peak memory 209312 kb
Host smart-420bb27c-b3e6-4fa2-a5a1-aedb54dd35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783542120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2783542120
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2940203698
Short name T629
Test name
Test status
Simulation time 5767642102 ps
CPU time 23.97 seconds
Started Jan 24 02:44:22 PM PST 24
Finished Jan 24 02:45:11 PM PST 24
Peak memory 207720 kb
Host smart-44a20b50-4272-4abf-966c-b3885ee0ddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940203698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2940203698
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1590421237
Short name T1022
Test name
Test status
Simulation time 86292507 ps
CPU time 4.76 seconds
Started Jan 24 02:44:23 PM PST 24
Finished Jan 24 02:44:51 PM PST 24
Peak memory 216056 kb
Host smart-67be5c28-5b53-432c-b3c5-29a69328c5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590421237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1590421237
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2217086923
Short name T124
Test name
Test status
Simulation time 268057596 ps
CPU time 6.97 seconds
Started Jan 24 02:44:28 PM PST 24
Finished Jan 24 02:44:51 PM PST 24
Peak memory 221952 kb
Host smart-a227b939-fb7a-4f64-b828-6f3d4e86f2c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217086923 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2217086923
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4100613400
Short name T845
Test name
Test status
Simulation time 8853396992 ps
CPU time 96.05 seconds
Started Jan 24 02:44:23 PM PST 24
Finished Jan 24 02:46:23 PM PST 24
Peak memory 207828 kb
Host smart-f883360e-ee5f-45e6-9ac5-2db23fa5d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100613400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4100613400
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2219588215
Short name T17
Test name
Test status
Simulation time 165786257 ps
CPU time 2.04 seconds
Started Jan 24 02:44:25 PM PST 24
Finished Jan 24 02:44:46 PM PST 24
Peak memory 208860 kb
Host smart-86c256c9-74af-4ab1-87c5-4bae1d91ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219588215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2219588215
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2719895306
Short name T807
Test name
Test status
Simulation time 13964607 ps
CPU time 0.73 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:44:55 PM PST 24
Peak memory 205480 kb
Host smart-58f30b16-2d39-41e6-bb12-57d91f6372aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719895306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2719895306
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3655313307
Short name T1089
Test name
Test status
Simulation time 421006686 ps
CPU time 2.64 seconds
Started Jan 24 02:44:38 PM PST 24
Finished Jan 24 02:44:55 PM PST 24
Peak memory 213812 kb
Host smart-ba3d8553-91fb-4b8a-a35c-6815e4756ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655313307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3655313307
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.130194730
Short name T917
Test name
Test status
Simulation time 123908086 ps
CPU time 3.12 seconds
Started Jan 24 02:44:37 PM PST 24
Finished Jan 24 02:44:54 PM PST 24
Peak memory 208536 kb
Host smart-3d1f0c05-ad32-4b7b-a1db-8bfa352cbb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130194730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.130194730
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.890274462
Short name T293
Test name
Test status
Simulation time 788159181 ps
CPU time 22.05 seconds
Started Jan 24 02:44:37 PM PST 24
Finished Jan 24 02:45:13 PM PST 24
Peak memory 209936 kb
Host smart-7ec05f2c-d531-4718-b616-9d546be0d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890274462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.890274462
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3351534899
Short name T38
Test name
Test status
Simulation time 597185434 ps
CPU time 3.63 seconds
Started Jan 24 02:44:34 PM PST 24
Finished Jan 24 02:44:50 PM PST 24
Peak memory 219080 kb
Host smart-17544358-738b-46ac-9ac6-8dd66a523661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351534899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3351534899
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2887543930
Short name T181
Test name
Test status
Simulation time 88533584 ps
CPU time 2.67 seconds
Started Jan 24 02:44:41 PM PST 24
Finished Jan 24 02:44:58 PM PST 24
Peak memory 213824 kb
Host smart-1e11a902-e35b-4128-9595-3728be2ce9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887543930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2887543930
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.522692558
Short name T251
Test name
Test status
Simulation time 38846781 ps
CPU time 2.43 seconds
Started Jan 24 02:44:28 PM PST 24
Finished Jan 24 02:44:46 PM PST 24
Peak memory 205964 kb
Host smart-3b9d0b67-7ddd-4f7d-a82a-f9808d4253f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522692558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.522692558
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.774322044
Short name T821
Test name
Test status
Simulation time 216836974 ps
CPU time 5.56 seconds
Started Jan 24 02:44:36 PM PST 24
Finished Jan 24 02:44:53 PM PST 24
Peak memory 207844 kb
Host smart-81dc7f2c-4d08-4d5e-9ba7-e3e5b571cd84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774322044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.774322044
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1364833298
Short name T714
Test name
Test status
Simulation time 100227314 ps
CPU time 3.7 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:44:59 PM PST 24
Peak memory 208140 kb
Host smart-7545f050-0bcd-4868-9db1-9651dc96ef23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364833298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1364833298
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.398935733
Short name T359
Test name
Test status
Simulation time 70947169 ps
CPU time 3.6 seconds
Started Jan 24 02:44:32 PM PST 24
Finished Jan 24 02:44:51 PM PST 24
Peak memory 208120 kb
Host smart-d27430c8-63df-4432-8079-7726aeb7e3d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398935733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.398935733
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3035934951
Short name T989
Test name
Test status
Simulation time 159650397 ps
CPU time 2.35 seconds
Started Jan 24 02:44:42 PM PST 24
Finished Jan 24 02:44:59 PM PST 24
Peak memory 208984 kb
Host smart-0b20f50b-7b43-44c3-9d3d-0d25b7b4512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035934951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3035934951
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.502565708
Short name T1023
Test name
Test status
Simulation time 5860600803 ps
CPU time 40.2 seconds
Started Jan 24 03:31:51 PM PST 24
Finished Jan 24 03:32:41 PM PST 24
Peak memory 207508 kb
Host smart-9bf33ed1-aeed-4cba-9dcf-f0b16a19e70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502565708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.502565708
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.417665722
Short name T56
Test name
Test status
Simulation time 172685347 ps
CPU time 7.52 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:45:02 PM PST 24
Peak memory 214320 kb
Host smart-c4fe84a2-83ab-45e8-89a7-14c0f691f91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417665722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.417665722
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2234177203
Short name T1019
Test name
Test status
Simulation time 186511722 ps
CPU time 7.23 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:45:01 PM PST 24
Peak memory 222176 kb
Host smart-53711020-de4f-4d1c-8b74-e693cd9e64fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234177203 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2234177203
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1752738397
Short name T1084
Test name
Test status
Simulation time 297990352 ps
CPU time 4.38 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:44:58 PM PST 24
Peak memory 209616 kb
Host smart-e1700280-d082-40cd-b187-b6dae80d5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752738397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1752738397
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3892901322
Short name T692
Test name
Test status
Simulation time 1145898437 ps
CPU time 29.44 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:45:23 PM PST 24
Peak memory 210184 kb
Host smart-e31cb886-c471-423e-ba93-df9394f07fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892901322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3892901322
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1820634066
Short name T606
Test name
Test status
Simulation time 15051509 ps
CPU time 0.79 seconds
Started Jan 24 02:45:10 PM PST 24
Finished Jan 24 02:45:31 PM PST 24
Peak memory 205488 kb
Host smart-f99e3ff9-7e78-4525-ac58-03a38660823e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820634066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1820634066
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2045169384
Short name T292
Test name
Test status
Simulation time 37759287 ps
CPU time 2.64 seconds
Started Jan 24 02:44:44 PM PST 24
Finished Jan 24 02:45:00 PM PST 24
Peak memory 222048 kb
Host smart-1659ed76-d167-4f52-ada9-a3ec34ec4c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045169384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2045169384
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1158808195
Short name T820
Test name
Test status
Simulation time 184838424 ps
CPU time 5.65 seconds
Started Jan 24 02:44:51 PM PST 24
Finished Jan 24 02:45:10 PM PST 24
Peak memory 207408 kb
Host smart-d2f72819-3dcb-4ba6-ae7f-8c386597dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158808195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1158808195
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2419817506
Short name T952
Test name
Test status
Simulation time 57855539 ps
CPU time 3.53 seconds
Started Jan 24 02:44:48 PM PST 24
Finished Jan 24 02:45:03 PM PST 24
Peak memory 208684 kb
Host smart-95d928d5-8163-4e80-acd6-d4453619f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419817506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2419817506
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4135386674
Short name T207
Test name
Test status
Simulation time 365508659 ps
CPU time 3.18 seconds
Started Jan 24 02:44:51 PM PST 24
Finished Jan 24 02:45:07 PM PST 24
Peak memory 213728 kb
Host smart-c3c27693-a924-4186-9384-e720503139c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135386674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4135386674
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4190550791
Short name T926
Test name
Test status
Simulation time 516386809 ps
CPU time 13.85 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:45:08 PM PST 24
Peak memory 213808 kb
Host smart-fb4f11ee-951c-4c5e-938d-772337b58e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190550791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4190550791
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1863745211
Short name T794
Test name
Test status
Simulation time 38002217 ps
CPU time 2.52 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:44:57 PM PST 24
Peak memory 207896 kb
Host smart-753aae15-284f-44fd-8327-eca42f83cc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863745211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1863745211
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.314587869
Short name T903
Test name
Test status
Simulation time 53203317 ps
CPU time 2.37 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:44:57 PM PST 24
Peak memory 206124 kb
Host smart-e6e1ff94-349c-4c83-a799-52cf0a1de3cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314587869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.314587869
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.732380393
Short name T874
Test name
Test status
Simulation time 60191835 ps
CPU time 3.15 seconds
Started Jan 24 02:44:42 PM PST 24
Finished Jan 24 02:45:00 PM PST 24
Peak memory 206124 kb
Host smart-48e890ab-51d7-491e-aca6-40244d21834b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732380393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.732380393
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.517481614
Short name T634
Test name
Test status
Simulation time 73047951 ps
CPU time 2.39 seconds
Started Jan 24 02:44:39 PM PST 24
Finished Jan 24 02:44:56 PM PST 24
Peak memory 206032 kb
Host smart-277c2357-6cb5-4081-b868-67ab5c66cc3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517481614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.517481614
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3557869537
Short name T273
Test name
Test status
Simulation time 74870778 ps
CPU time 3.05 seconds
Started Jan 24 02:44:42 PM PST 24
Finished Jan 24 02:45:00 PM PST 24
Peak memory 208912 kb
Host smart-3e887cc6-3928-4441-af32-20d7b430e738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557869537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3557869537
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4087600570
Short name T985
Test name
Test status
Simulation time 875782057 ps
CPU time 28.81 seconds
Started Jan 24 02:44:40 PM PST 24
Finished Jan 24 02:45:24 PM PST 24
Peak memory 207044 kb
Host smart-0babf90c-0c0f-4dd5-94c5-21ef0c350e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087600570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4087600570
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3843563397
Short name T317
Test name
Test status
Simulation time 12936609264 ps
CPU time 116.65 seconds
Started Jan 24 02:45:02 PM PST 24
Finished Jan 24 02:47:16 PM PST 24
Peak memory 221532 kb
Host smart-63d2dbc4-e23e-4cc7-804a-eeea463a1540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843563397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3843563397
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3681461222
Short name T1005
Test name
Test status
Simulation time 188071118 ps
CPU time 10.75 seconds
Started Jan 24 02:45:02 PM PST 24
Finished Jan 24 02:45:29 PM PST 24
Peak memory 223428 kb
Host smart-2e572e1f-4d07-4e21-86f3-0fc631894c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681461222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3681461222
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3559180366
Short name T839
Test name
Test status
Simulation time 1225605093 ps
CPU time 33.36 seconds
Started Jan 24 02:44:45 PM PST 24
Finished Jan 24 02:45:32 PM PST 24
Peak memory 209232 kb
Host smart-a0431935-4f95-4902-8a46-aa2bd97d0c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559180366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3559180366
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3822245875
Short name T597
Test name
Test status
Simulation time 109972404 ps
CPU time 2.77 seconds
Started Jan 24 02:44:43 PM PST 24
Finished Jan 24 02:44:59 PM PST 24
Peak memory 209364 kb
Host smart-ee22620c-b874-4ee2-a1d6-e2f956dff7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822245875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3822245875
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1670271852
Short name T638
Test name
Test status
Simulation time 11011617 ps
CPU time 0.89 seconds
Started Jan 24 02:45:36 PM PST 24
Finished Jan 24 02:45:48 PM PST 24
Peak memory 205440 kb
Host smart-7c328437-665a-42d1-979a-0d974f02df1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670271852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1670271852
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3269763528
Short name T394
Test name
Test status
Simulation time 105732867 ps
CPU time 2.64 seconds
Started Jan 24 02:45:10 PM PST 24
Finished Jan 24 02:45:33 PM PST 24
Peak memory 222004 kb
Host smart-2f715c86-d347-43a2-94e4-99cf281a9742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269763528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3269763528
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1011003280
Short name T772
Test name
Test status
Simulation time 90659965 ps
CPU time 4.47 seconds
Started Jan 24 02:45:13 PM PST 24
Finished Jan 24 02:45:41 PM PST 24
Peak memory 208532 kb
Host smart-6554d126-5bd0-47c0-a3ba-5a8d8be88f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011003280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1011003280
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1256544740
Short name T888
Test name
Test status
Simulation time 90718610 ps
CPU time 3.68 seconds
Started Jan 24 02:45:12 PM PST 24
Finished Jan 24 02:45:37 PM PST 24
Peak memory 207148 kb
Host smart-1dd6b1d9-49da-48c4-8afc-890cdf8f06f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256544740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1256544740
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1691509663
Short name T22
Test name
Test status
Simulation time 207379059 ps
CPU time 5.53 seconds
Started Jan 24 02:45:12 PM PST 24
Finished Jan 24 02:45:40 PM PST 24
Peak memory 219620 kb
Host smart-c33739d9-7016-4fd6-a773-7ffa14eb7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691509663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1691509663
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3769830432
Short name T223
Test name
Test status
Simulation time 106808216 ps
CPU time 3.77 seconds
Started Jan 24 02:45:08 PM PST 24
Finished Jan 24 02:45:32 PM PST 24
Peak memory 209572 kb
Host smart-2d0d9b6c-2902-4c1b-93ab-7d2aaf3fe474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769830432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3769830432
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.995232912
Short name T205
Test name
Test status
Simulation time 2111071297 ps
CPU time 21.67 seconds
Started Jan 24 02:45:09 PM PST 24
Finished Jan 24 02:45:51 PM PST 24
Peak memory 207568 kb
Host smart-64d3e78f-cfc6-4d1c-98a6-88070e7fc47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995232912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.995232912
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2954196557
Short name T806
Test name
Test status
Simulation time 335564774 ps
CPU time 3 seconds
Started Jan 24 02:45:10 PM PST 24
Finished Jan 24 02:45:33 PM PST 24
Peak memory 205928 kb
Host smart-75e56481-b46f-4159-bb13-93ad8c9378bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954196557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2954196557
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.705834548
Short name T640
Test name
Test status
Simulation time 50834904 ps
CPU time 2.73 seconds
Started Jan 24 03:03:58 PM PST 24
Finished Jan 24 03:04:20 PM PST 24
Peak memory 206128 kb
Host smart-b1437598-c4bc-4a73-8842-cd08c4185639
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705834548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.705834548
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1107155
Short name T1037
Test name
Test status
Simulation time 1181251426 ps
CPU time 35.92 seconds
Started Jan 24 02:54:02 PM PST 24
Finished Jan 24 02:55:07 PM PST 24
Peak memory 207364 kb
Host smart-843aa796-67b1-40a3-8169-0d5194dd5820
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1107155
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3732261188
Short name T570
Test name
Test status
Simulation time 819134797 ps
CPU time 16.91 seconds
Started Jan 24 02:45:10 PM PST 24
Finished Jan 24 02:45:47 PM PST 24
Peak memory 207332 kb
Host smart-c8b99fe3-2c2d-41ad-9087-9e359eac46b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732261188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3732261188
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4237424420
Short name T737
Test name
Test status
Simulation time 61148766 ps
CPU time 2.22 seconds
Started Jan 24 02:45:08 PM PST 24
Finished Jan 24 02:45:29 PM PST 24
Peak memory 207688 kb
Host smart-cce7a248-b843-470a-b9a9-6d9e9122f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237424420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4237424420
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.45975669
Short name T811
Test name
Test status
Simulation time 1679357456 ps
CPU time 4.91 seconds
Started Jan 24 02:45:08 PM PST 24
Finished Jan 24 02:45:32 PM PST 24
Peak memory 207656 kb
Host smart-318c4c30-934b-45ac-b3df-f7d37b7a558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45975669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.45975669
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.564680604
Short name T945
Test name
Test status
Simulation time 182470088 ps
CPU time 3.18 seconds
Started Jan 24 04:07:20 PM PST 24
Finished Jan 24 04:07:25 PM PST 24
Peak memory 209360 kb
Host smart-f53821f0-c5de-4f5a-b02d-8d575a73c291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564680604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.564680604
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1069243321
Short name T1006
Test name
Test status
Simulation time 178676623 ps
CPU time 8.41 seconds
Started Jan 24 02:45:06 PM PST 24
Finished Jan 24 02:45:33 PM PST 24
Peak memory 222080 kb
Host smart-474e51eb-2665-48d6-ba0e-f2c9ef151cbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069243321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1069243321
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2378444197
Short name T187
Test name
Test status
Simulation time 71758689 ps
CPU time 2.86 seconds
Started Jan 24 02:45:12 PM PST 24
Finished Jan 24 02:45:37 PM PST 24
Peak memory 207016 kb
Host smart-b55c79d9-a710-4dba-9ee9-3ece1bcbd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378444197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2378444197
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2836607101
Short name T702
Test name
Test status
Simulation time 92545464 ps
CPU time 0.73 seconds
Started Jan 24 03:46:24 PM PST 24
Finished Jan 24 03:46:27 PM PST 24
Peak memory 205468 kb
Host smart-a84548cd-e04a-4c7d-973a-1a6065043368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836607101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2836607101
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1226424729
Short name T861
Test name
Test status
Simulation time 199267009 ps
CPU time 8.29 seconds
Started Jan 24 02:45:39 PM PST 24
Finished Jan 24 02:45:56 PM PST 24
Peak memory 213828 kb
Host smart-688c2a59-3f1b-4c6a-a050-1dd9e4a59e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226424729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1226424729
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.445850933
Short name T572
Test name
Test status
Simulation time 731828995 ps
CPU time 3.97 seconds
Started Jan 24 02:45:34 PM PST 24
Finished Jan 24 02:45:50 PM PST 24
Peak memory 206588 kb
Host smart-5324e35d-c8ab-4750-a3b6-cb5bd00763e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445850933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.445850933
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.239476011
Short name T609
Test name
Test status
Simulation time 40961151 ps
CPU time 3.06 seconds
Started Jan 24 02:45:39 PM PST 24
Finished Jan 24 02:45:51 PM PST 24
Peak memory 208492 kb
Host smart-5c82d6a3-bac3-4c44-a0d7-9f78fa17174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239476011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.239476011
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3636342926
Short name T297
Test name
Test status
Simulation time 1459566968 ps
CPU time 51.34 seconds
Started Jan 24 02:52:09 PM PST 24
Finished Jan 24 02:53:05 PM PST 24
Peak memory 221988 kb
Host smart-54390a9a-df25-40a3-9ba2-56ba94f67279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636342926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3636342926
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3869449820
Short name T746
Test name
Test status
Simulation time 106786369 ps
CPU time 4.72 seconds
Started Jan 24 02:45:34 PM PST 24
Finished Jan 24 02:45:51 PM PST 24
Peak memory 209296 kb
Host smart-433789a5-e447-48fa-9ebb-23933a6a847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869449820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3869449820
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4105655420
Short name T651
Test name
Test status
Simulation time 17679366921 ps
CPU time 111.84 seconds
Started Jan 24 02:45:41 PM PST 24
Finished Jan 24 02:47:41 PM PST 24
Peak memory 217992 kb
Host smart-37952a28-534f-43ec-935c-8419d01996f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105655420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4105655420
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2232584574
Short name T742
Test name
Test status
Simulation time 148710532 ps
CPU time 3.56 seconds
Started Jan 24 02:45:33 PM PST 24
Finished Jan 24 02:45:50 PM PST 24
Peak memory 205528 kb
Host smart-5ddf33dd-7cfd-424a-a5bf-27d2025202c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232584574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2232584574
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2302639045
Short name T388
Test name
Test status
Simulation time 65794680 ps
CPU time 3.5 seconds
Started Jan 24 02:45:37 PM PST 24
Finished Jan 24 02:45:51 PM PST 24
Peak memory 206140 kb
Host smart-718dadba-20d0-45db-9be7-a96f24621b5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302639045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2302639045
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.905935732
Short name T815
Test name
Test status
Simulation time 166446698 ps
CPU time 5.27 seconds
Started Jan 24 04:41:47 PM PST 24
Finished Jan 24 04:41:59 PM PST 24
Peak memory 207188 kb
Host smart-1da25799-e505-4fc2-ad50-232c49a820a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905935732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.905935732
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3524616108
Short name T374
Test name
Test status
Simulation time 132120373 ps
CPU time 1.71 seconds
Started Jan 24 02:45:40 PM PST 24
Finished Jan 24 02:45:50 PM PST 24
Peak memory 205880 kb
Host smart-4d2cb61d-4211-4029-a706-9133a45f0013
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524616108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3524616108
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1657989892
Short name T887
Test name
Test status
Simulation time 134217476 ps
CPU time 2.51 seconds
Started Jan 24 03:14:05 PM PST 24
Finished Jan 24 03:14:26 PM PST 24
Peak memory 215196 kb
Host smart-0fbfaa5a-cb02-4f5f-8243-1955c4111fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657989892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1657989892
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1277241889
Short name T383
Test name
Test status
Simulation time 263006839 ps
CPU time 3.69 seconds
Started Jan 24 02:45:41 PM PST 24
Finished Jan 24 02:45:53 PM PST 24
Peak memory 205876 kb
Host smart-aeddbfb8-581a-47f5-a6ae-5975bdf489e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277241889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1277241889
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4239530314
Short name T885
Test name
Test status
Simulation time 1812777513 ps
CPU time 40.52 seconds
Started Jan 24 02:45:35 PM PST 24
Finished Jan 24 02:46:27 PM PST 24
Peak memory 220548 kb
Host smart-ba41fc12-d05d-491d-a547-e5bb040c6e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239530314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4239530314
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2895162559
Short name T686
Test name
Test status
Simulation time 276970570 ps
CPU time 7.71 seconds
Started Jan 24 03:26:09 PM PST 24
Finished Jan 24 03:26:31 PM PST 24
Peak memory 222136 kb
Host smart-3797f843-0549-40a0-b7a4-1fe67717c191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895162559 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2895162559
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.173270387
Short name T987
Test name
Test status
Simulation time 41500792 ps
CPU time 2.9 seconds
Started Jan 24 02:59:21 PM PST 24
Finished Jan 24 02:59:43 PM PST 24
Peak memory 209052 kb
Host smart-e69c6728-e8da-4457-ba04-4a9c9d837898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173270387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.173270387
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.215541591
Short name T636
Test name
Test status
Simulation time 120557220 ps
CPU time 2.93 seconds
Started Jan 24 02:45:40 PM PST 24
Finished Jan 24 02:45:51 PM PST 24
Peak memory 209332 kb
Host smart-8089f124-8f77-4c26-abcc-e447300a4574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215541591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.215541591
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4088812864
Short name T928
Test name
Test status
Simulation time 8700832 ps
CPU time 0.8 seconds
Started Jan 24 02:45:47 PM PST 24
Finished Jan 24 02:45:53 PM PST 24
Peak memory 205400 kb
Host smart-3db4a3d2-7a1a-49bc-aa25-9be632441e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088812864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4088812864
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3236396365
Short name T402
Test name
Test status
Simulation time 157283005 ps
CPU time 8.21 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:04 PM PST 24
Peak memory 213988 kb
Host smart-06e560c1-75ea-4ec3-b738-e8544b3daf48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236396365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3236396365
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2786322395
Short name T685
Test name
Test status
Simulation time 367778761 ps
CPU time 9.04 seconds
Started Jan 24 02:45:48 PM PST 24
Finished Jan 24 02:46:02 PM PST 24
Peak memory 222260 kb
Host smart-2d4c2622-388b-443d-bee4-5d8b688864bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786322395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2786322395
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2197842672
Short name T1059
Test name
Test status
Simulation time 28420947 ps
CPU time 2.05 seconds
Started Jan 24 02:45:48 PM PST 24
Finished Jan 24 02:45:56 PM PST 24
Peak memory 217572 kb
Host smart-6b802352-d9ef-4457-890c-9f5a3256a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197842672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2197842672
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4251818532
Short name T36
Test name
Test status
Simulation time 142822596 ps
CPU time 2.99 seconds
Started Jan 24 02:45:50 PM PST 24
Finished Jan 24 02:45:57 PM PST 24
Peak memory 221972 kb
Host smart-e22958c4-fbdb-4534-bbb4-2cb730551fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251818532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4251818532
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2597222723
Short name T974
Test name
Test status
Simulation time 263983371 ps
CPU time 4.18 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:00 PM PST 24
Peak memory 209048 kb
Host smart-15995d3a-d215-458c-997b-42c43ffe463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597222723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2597222723
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2157158791
Short name T365
Test name
Test status
Simulation time 239804464 ps
CPU time 3.98 seconds
Started Jan 24 02:45:48 PM PST 24
Finished Jan 24 02:45:57 PM PST 24
Peak memory 207436 kb
Host smart-aac5f18b-b449-4142-8988-cdf032840ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157158791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2157158791
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2535400129
Short name T944
Test name
Test status
Simulation time 93472944 ps
CPU time 2.64 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:45:59 PM PST 24
Peak memory 205960 kb
Host smart-9c5de6fe-f9df-4a0c-b80b-ed03d6c421e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535400129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2535400129
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3629960250
Short name T873
Test name
Test status
Simulation time 125308793 ps
CPU time 2.14 seconds
Started Jan 24 02:45:45 PM PST 24
Finished Jan 24 02:45:52 PM PST 24
Peak memory 208204 kb
Host smart-2574a845-fba3-4b2a-98db-d2d3670035c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629960250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3629960250
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.599957448
Short name T697
Test name
Test status
Simulation time 145738873 ps
CPU time 5.66 seconds
Started Jan 24 02:53:19 PM PST 24
Finished Jan 24 02:53:53 PM PST 24
Peak memory 207908 kb
Host smart-94332d58-d107-421f-baa8-13b5c91686a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599957448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.599957448
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3832678949
Short name T667
Test name
Test status
Simulation time 880660407 ps
CPU time 5.56 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:01 PM PST 24
Peak memory 207996 kb
Host smart-d0927683-b9c5-4e71-8d9a-16a5a6384550
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832678949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3832678949
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2602006226
Short name T791
Test name
Test status
Simulation time 292956228 ps
CPU time 3.57 seconds
Started Jan 24 02:45:50 PM PST 24
Finished Jan 24 02:45:58 PM PST 24
Peak memory 213832 kb
Host smart-1bf55d83-c165-411d-b1a9-a09f98f05e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602006226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2602006226
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1167648710
Short name T857
Test name
Test status
Simulation time 1322628850 ps
CPU time 14.15 seconds
Started Jan 24 02:45:35 PM PST 24
Finished Jan 24 02:46:01 PM PST 24
Peak memory 207860 kb
Host smart-1698d888-3092-466e-a11d-ebc2c5da942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167648710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1167648710
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.126020096
Short name T310
Test name
Test status
Simulation time 6630599701 ps
CPU time 39.08 seconds
Started Jan 24 02:45:48 PM PST 24
Finished Jan 24 02:46:33 PM PST 24
Peak memory 220056 kb
Host smart-0dbc81a6-3762-4f00-bfba-67d589066301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126020096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.126020096
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.4158932492
Short name T818
Test name
Test status
Simulation time 343916724 ps
CPU time 2.74 seconds
Started Jan 24 02:45:47 PM PST 24
Finished Jan 24 02:45:55 PM PST 24
Peak memory 222168 kb
Host smart-ff8c97f5-f6e6-4f51-b61f-a373bcabb1c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158932492 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.4158932492
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3755359089
Short name T1011
Test name
Test status
Simulation time 1366965875 ps
CPU time 7.1 seconds
Started Jan 24 02:45:47 PM PST 24
Finished Jan 24 02:45:59 PM PST 24
Peak memory 208664 kb
Host smart-79d6707a-c331-4500-a481-be3819446546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755359089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3755359089
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2014127280
Short name T589
Test name
Test status
Simulation time 53623552 ps
CPU time 2.25 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:45:58 PM PST 24
Peak memory 209080 kb
Host smart-c2360fde-7c5f-4c29-8d01-9c0fc98837c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014127280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2014127280
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.891024236
Short name T760
Test name
Test status
Simulation time 141153308 ps
CPU time 0.71 seconds
Started Jan 24 02:46:02 PM PST 24
Finished Jan 24 02:46:08 PM PST 24
Peak memory 205372 kb
Host smart-c0443f38-e948-4faf-acc2-edc9e432a199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891024236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.891024236
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.611903358
Short name T62
Test name
Test status
Simulation time 112190375 ps
CPU time 2.88 seconds
Started Jan 24 02:45:48 PM PST 24
Finished Jan 24 02:45:56 PM PST 24
Peak memory 217864 kb
Host smart-ffe375a7-ad15-4a7a-a3cd-076403a85abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611903358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.611903358
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1293820289
Short name T370
Test name
Test status
Simulation time 2388116339 ps
CPU time 56.45 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:52 PM PST 24
Peak memory 222124 kb
Host smart-b31a1024-412c-45c4-8241-1b08997141b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293820289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1293820289
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1767269672
Short name T785
Test name
Test status
Simulation time 164430015 ps
CPU time 4.93 seconds
Started Jan 24 02:45:54 PM PST 24
Finished Jan 24 02:46:03 PM PST 24
Peak memory 208540 kb
Host smart-d34b7d42-f800-4159-8b67-f305f4f491d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767269672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1767269672
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.732935541
Short name T654
Test name
Test status
Simulation time 373715161 ps
CPU time 7.9 seconds
Started Jan 24 02:46:04 PM PST 24
Finished Jan 24 02:46:18 PM PST 24
Peak memory 206552 kb
Host smart-2a038855-b703-4350-8636-5aa4654913a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732935541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.732935541
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.69399573
Short name T108
Test name
Test status
Simulation time 5887949946 ps
CPU time 60.67 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:57 PM PST 24
Peak memory 207672 kb
Host smart-8980bead-8e72-4fa0-a1fe-3567e8c04e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69399573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.69399573
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.237187800
Short name T788
Test name
Test status
Simulation time 78375735 ps
CPU time 1.9 seconds
Started Jan 24 02:45:53 PM PST 24
Finished Jan 24 02:46:00 PM PST 24
Peak memory 206184 kb
Host smart-891d250e-9f8c-4f51-a643-25cf06d8b1f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237187800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.237187800
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.369589779
Short name T71
Test name
Test status
Simulation time 2046151880 ps
CPU time 19.59 seconds
Started Jan 24 03:04:50 PM PST 24
Finished Jan 24 03:05:23 PM PST 24
Peak memory 208000 kb
Host smart-ac9228fd-b730-47c2-9abd-ccbbd570c51b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369589779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.369589779
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1179577149
Short name T79
Test name
Test status
Simulation time 1912950502 ps
CPU time 59.74 seconds
Started Jan 24 02:46:02 PM PST 24
Finished Jan 24 02:47:07 PM PST 24
Peak memory 207264 kb
Host smart-b073c339-175b-41a7-bd0e-85feaae97bee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179577149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1179577149
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4209860228
Short name T111
Test name
Test status
Simulation time 64078647 ps
CPU time 2.41 seconds
Started Jan 24 02:45:52 PM PST 24
Finished Jan 24 02:45:59 PM PST 24
Peak memory 207460 kb
Host smart-3106c899-1f95-43af-b183-cf3e93271e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209860228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4209860228
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2891356010
Short name T734
Test name
Test status
Simulation time 117191241 ps
CPU time 4.18 seconds
Started Jan 24 02:45:51 PM PST 24
Finished Jan 24 02:46:00 PM PST 24
Peak memory 205856 kb
Host smart-60b7f483-d049-46ed-a66f-d97a6c34c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891356010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2891356010
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2574477705
Short name T814
Test name
Test status
Simulation time 261550989 ps
CPU time 10.59 seconds
Started Jan 24 02:45:54 PM PST 24
Finished Jan 24 02:46:08 PM PST 24
Peak memory 222472 kb
Host smart-afa02752-b9fe-4ac2-ba4c-8a3f3fb000b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574477705 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2574477705
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2848524267
Short name T202
Test name
Test status
Simulation time 105547005 ps
CPU time 4.2 seconds
Started Jan 24 02:45:50 PM PST 24
Finished Jan 24 02:45:59 PM PST 24
Peak memory 209676 kb
Host smart-16cabbc3-1318-4e8f-a16b-79cfec30e556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848524267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2848524267
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3222854557
Short name T1075
Test name
Test status
Simulation time 18646919 ps
CPU time 0.91 seconds
Started Jan 24 02:39:29 PM PST 24
Finished Jan 24 02:39:46 PM PST 24
Peak memory 205468 kb
Host smart-1e99575e-7c57-42ab-acba-62d68c90dfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222854557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3222854557
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.300471571
Short name T61
Test name
Test status
Simulation time 630076777 ps
CPU time 2.14 seconds
Started Jan 24 02:39:32 PM PST 24
Finished Jan 24 02:39:55 PM PST 24
Peak memory 220448 kb
Host smart-8451f404-f148-48c2-9576-3f24c534bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300471571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.300471571
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1928231998
Short name T652
Test name
Test status
Simulation time 212610669 ps
CPU time 2.54 seconds
Started Jan 24 02:39:16 PM PST 24
Finished Jan 24 02:39:30 PM PST 24
Peak memory 217708 kb
Host smart-1427c5c4-920c-4494-b55d-aaedebeb1a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928231998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1928231998
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3713207387
Short name T947
Test name
Test status
Simulation time 463364893 ps
CPU time 4.22 seconds
Started Jan 24 02:39:22 PM PST 24
Finished Jan 24 02:39:43 PM PST 24
Peak memory 213764 kb
Host smart-9667fed0-7dcd-4330-88d4-f1a3f2224c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713207387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3713207387
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.165023385
Short name T198
Test name
Test status
Simulation time 282602264 ps
CPU time 9.15 seconds
Started Jan 24 02:39:18 PM PST 24
Finished Jan 24 02:39:40 PM PST 24
Peak memory 210604 kb
Host smart-8a49861d-263b-4926-9cbd-ae551a2b6a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165023385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.165023385
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2584127694
Short name T59
Test name
Test status
Simulation time 95554091 ps
CPU time 4.74 seconds
Started Jan 24 02:39:21 PM PST 24
Finished Jan 24 02:39:41 PM PST 24
Peak memory 208776 kb
Host smart-c935ba7f-9fec-47f9-826d-c791f00a3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584127694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2584127694
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.517568916
Short name T700
Test name
Test status
Simulation time 7527745817 ps
CPU time 61.96 seconds
Started Jan 24 02:39:21 PM PST 24
Finished Jan 24 02:40:38 PM PST 24
Peak memory 208016 kb
Host smart-074ce7e8-60c8-42ee-b385-ca99a605702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517568916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.517568916
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.65654584
Short name T11
Test name
Test status
Simulation time 2420759182 ps
CPU time 37.96 seconds
Started Jan 24 02:39:27 PM PST 24
Finished Jan 24 02:40:18 PM PST 24
Peak memory 235168 kb
Host smart-e88fd277-a4e3-4a5e-8e22-c1399e158322
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65654584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.65654584
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.335088373
Short name T349
Test name
Test status
Simulation time 344240395 ps
CPU time 6.14 seconds
Started Jan 24 02:39:22 PM PST 24
Finished Jan 24 02:39:44 PM PST 24
Peak memory 207816 kb
Host smart-adb2bc3a-87da-48b5-b274-b31f4852c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335088373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.335088373
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.254419093
Short name T965
Test name
Test status
Simulation time 62904209 ps
CPU time 3.13 seconds
Started Jan 24 02:39:22 PM PST 24
Finished Jan 24 02:39:39 PM PST 24
Peak memory 207360 kb
Host smart-b705d226-9b1b-42fa-872d-b9db8e818906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254419093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.254419093
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3571454815
Short name T1063
Test name
Test status
Simulation time 3642206658 ps
CPU time 45.5 seconds
Started Jan 24 02:39:19 PM PST 24
Finished Jan 24 02:40:17 PM PST 24
Peak memory 207572 kb
Host smart-5c82f62e-ad2a-40d5-96ed-5b00b1d01374
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571454815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3571454815
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1377245334
Short name T1013
Test name
Test status
Simulation time 1845718810 ps
CPU time 44.98 seconds
Started Jan 24 02:39:19 PM PST 24
Finished Jan 24 02:40:17 PM PST 24
Peak memory 207316 kb
Host smart-c813fae3-fd85-4d8b-a69f-2f9235483481
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377245334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1377245334
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3347168232
Short name T896
Test name
Test status
Simulation time 32720401 ps
CPU time 1.98 seconds
Started Jan 24 04:10:28 PM PST 24
Finished Jan 24 04:10:39 PM PST 24
Peak memory 213880 kb
Host smart-238744d4-07c0-4eb0-8730-8baf360dcd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347168232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3347168232
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.591428985
Short name T688
Test name
Test status
Simulation time 276679596 ps
CPU time 2.53 seconds
Started Jan 24 03:27:32 PM PST 24
Finished Jan 24 03:27:43 PM PST 24
Peak memory 206028 kb
Host smart-003e19bf-c595-4314-a0ad-79bc25983f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591428985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.591428985
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2861793180
Short name T235
Test name
Test status
Simulation time 23559130491 ps
CPU time 122.66 seconds
Started Jan 24 02:39:32 PM PST 24
Finished Jan 24 02:41:55 PM PST 24
Peak memory 216332 kb
Host smart-c1450222-3b1d-4573-bde0-a972c449557e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861793180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2861793180
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.922672420
Short name T776
Test name
Test status
Simulation time 47957526 ps
CPU time 1.91 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:52 PM PST 24
Peak memory 217132 kb
Host smart-e4b057c4-81d8-4cdd-8c16-05d0a33467da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922672420 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.922672420
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1815433878
Short name T715
Test name
Test status
Simulation time 297250523 ps
CPU time 4.04 seconds
Started Jan 24 02:39:17 PM PST 24
Finished Jan 24 02:39:33 PM PST 24
Peak memory 206856 kb
Host smart-fe07b181-bdab-4b23-b0f2-c19666d46ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815433878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1815433878
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3383272848
Short name T157
Test name
Test status
Simulation time 194075696 ps
CPU time 2.96 seconds
Started Jan 24 02:39:30 PM PST 24
Finished Jan 24 02:39:50 PM PST 24
Peak memory 209940 kb
Host smart-d71e588c-f5a2-4c8f-9b76-d4feb0d6a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383272848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3383272848
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1347639003
Short name T977
Test name
Test status
Simulation time 78815583 ps
CPU time 0.73 seconds
Started Jan 24 02:46:06 PM PST 24
Finished Jan 24 02:46:13 PM PST 24
Peak memory 205480 kb
Host smart-6415b296-b39b-4d55-945f-d8f82b058bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347639003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1347639003
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2848563727
Short name T270
Test name
Test status
Simulation time 560716589 ps
CPU time 8.36 seconds
Started Jan 24 02:46:07 PM PST 24
Finished Jan 24 02:46:21 PM PST 24
Peak memory 213840 kb
Host smart-c45b620f-a1b5-4c6b-aa40-f0a932396e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848563727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2848563727
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2838515309
Short name T920
Test name
Test status
Simulation time 1247737504 ps
CPU time 34.02 seconds
Started Jan 24 02:46:09 PM PST 24
Finished Jan 24 02:46:49 PM PST 24
Peak memory 221872 kb
Host smart-7343fa1c-2768-4396-b12c-e725b09a05e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838515309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2838515309
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4091141076
Short name T662
Test name
Test status
Simulation time 44246867 ps
CPU time 1.8 seconds
Started Jan 24 02:46:06 PM PST 24
Finished Jan 24 02:46:14 PM PST 24
Peak memory 221968 kb
Host smart-ee446fc9-9d57-45fb-ab3f-8edb37d69a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091141076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4091141076
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.847437819
Short name T1
Test name
Test status
Simulation time 483022404 ps
CPU time 3.83 seconds
Started Jan 24 02:55:59 PM PST 24
Finished Jan 24 02:56:07 PM PST 24
Peak memory 208252 kb
Host smart-54dee578-ff50-417e-991d-662d043b3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847437819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.847437819
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1889590810
Short name T189
Test name
Test status
Simulation time 1034403869 ps
CPU time 12.13 seconds
Started Jan 24 02:46:06 PM PST 24
Finished Jan 24 02:46:24 PM PST 24
Peak memory 213732 kb
Host smart-4ffe7b3f-0327-47d9-9bd4-aae9a9c66516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889590810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1889590810
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1839271521
Short name T54
Test name
Test status
Simulation time 538962764 ps
CPU time 5.33 seconds
Started Jan 24 02:46:07 PM PST 24
Finished Jan 24 02:46:17 PM PST 24
Peak memory 219300 kb
Host smart-a71d9a1b-cece-423b-954b-d0f9ba4ea27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839271521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1839271521
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1138555292
Short name T620
Test name
Test status
Simulation time 102065002 ps
CPU time 4.82 seconds
Started Jan 24 02:46:09 PM PST 24
Finished Jan 24 02:46:20 PM PST 24
Peak memory 206560 kb
Host smart-2bd367a8-ca61-41c0-8676-b2febe7249c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138555292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1138555292
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2688744183
Short name T1062
Test name
Test status
Simulation time 261049317 ps
CPU time 2.63 seconds
Started Jan 24 04:33:48 PM PST 24
Finished Jan 24 04:33:59 PM PST 24
Peak memory 206412 kb
Host smart-81892d99-a396-4587-ae7e-db1547b9c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688744183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2688744183
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1245250863
Short name T869
Test name
Test status
Simulation time 8083802823 ps
CPU time 25.75 seconds
Started Jan 24 02:46:02 PM PST 24
Finished Jan 24 02:46:33 PM PST 24
Peak memory 208528 kb
Host smart-cd85afca-121e-42e0-8a25-30006c726748
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245250863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1245250863
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2706070043
Short name T976
Test name
Test status
Simulation time 61042311 ps
CPU time 3.3 seconds
Started Jan 24 02:46:09 PM PST 24
Finished Jan 24 02:46:18 PM PST 24
Peak memory 206072 kb
Host smart-6c0d6b08-2ad3-4549-a98e-4640bb8aa271
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706070043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2706070043
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3646716190
Short name T999
Test name
Test status
Simulation time 528956819 ps
CPU time 5.96 seconds
Started Jan 24 03:15:23 PM PST 24
Finished Jan 24 03:15:32 PM PST 24
Peak memory 207900 kb
Host smart-1e462ff7-4603-4802-9cf0-5c7d4cc8a401
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646716190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3646716190
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.158710803
Short name T131
Test name
Test status
Simulation time 236655427 ps
CPU time 2.8 seconds
Started Jan 24 04:07:08 PM PST 24
Finished Jan 24 04:07:14 PM PST 24
Peak memory 207808 kb
Host smart-d8aa9b18-46c2-4374-a9cf-05c771943c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158710803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.158710803
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.587300867
Short name T643
Test name
Test status
Simulation time 414930720 ps
CPU time 1.85 seconds
Started Jan 24 02:46:04 PM PST 24
Finished Jan 24 02:46:11 PM PST 24
Peak memory 206076 kb
Host smart-f4f83cca-a0d9-4ced-8f36-7eae708bad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587300867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.587300867
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.615665244
Short name T302
Test name
Test status
Simulation time 3274474943 ps
CPU time 89.85 seconds
Started Jan 24 04:32:44 PM PST 24
Finished Jan 24 04:34:15 PM PST 24
Peak memory 215296 kb
Host smart-f1d54094-0e85-4871-b742-9c106b974dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615665244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.615665244
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3771857987
Short name T878
Test name
Test status
Simulation time 108557972 ps
CPU time 5.84 seconds
Started Jan 24 03:55:03 PM PST 24
Finished Jan 24 03:55:12 PM PST 24
Peak memory 219064 kb
Host smart-1f614291-2d65-4fd2-9f2f-9c30362cd7b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771857987 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3771857987
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1502175660
Short name T1080
Test name
Test status
Simulation time 1653039320 ps
CPU time 5.64 seconds
Started Jan 24 02:46:07 PM PST 24
Finished Jan 24 02:46:18 PM PST 24
Peak memory 213776 kb
Host smart-6cf02ac0-2ade-42c3-8a96-930c8b707549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502175660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1502175660
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.346293192
Short name T983
Test name
Test status
Simulation time 58513675 ps
CPU time 2.2 seconds
Started Jan 24 02:46:09 PM PST 24
Finished Jan 24 02:46:17 PM PST 24
Peak memory 209996 kb
Host smart-bab66246-46de-41b5-a2ea-823f9121279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346293192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.346293192
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1325649461
Short name T414
Test name
Test status
Simulation time 20047290 ps
CPU time 0.76 seconds
Started Jan 24 02:46:27 PM PST 24
Finished Jan 24 02:46:33 PM PST 24
Peak memory 205468 kb
Host smart-e846e052-808c-4b3c-b814-c77c03a1ed3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325649461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1325649461
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.850646091
Short name T254
Test name
Test status
Simulation time 271339011 ps
CPU time 7.71 seconds
Started Jan 24 03:53:26 PM PST 24
Finished Jan 24 03:53:43 PM PST 24
Peak memory 214704 kb
Host smart-2fd91d84-a448-4fd7-bc69-ca9dc6a9d91a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850646091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.850646091
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3689561535
Short name T9
Test name
Test status
Simulation time 798429410 ps
CPU time 5.6 seconds
Started Jan 24 04:05:24 PM PST 24
Finished Jan 24 04:05:31 PM PST 24
Peak memory 214148 kb
Host smart-61253564-5173-4baf-b7ad-b190821887d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689561535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3689561535
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.475138039
Short name T257
Test name
Test status
Simulation time 67531075 ps
CPU time 2.66 seconds
Started Jan 24 03:43:42 PM PST 24
Finished Jan 24 03:43:53 PM PST 24
Peak memory 213816 kb
Host smart-792bec0b-0213-49fe-966f-27526b35c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475138039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.475138039
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2419003602
Short name T106
Test name
Test status
Simulation time 751028798 ps
CPU time 6.56 seconds
Started Jan 24 02:46:29 PM PST 24
Finished Jan 24 02:46:42 PM PST 24
Peak memory 221244 kb
Host smart-3ce38182-5a7c-4892-b81b-fe5acfc913da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419003602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2419003602
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1046996839
Short name T211
Test name
Test status
Simulation time 63571239 ps
CPU time 3.33 seconds
Started Jan 24 02:46:24 PM PST 24
Finished Jan 24 02:46:32 PM PST 24
Peak memory 208808 kb
Host smart-3672c923-106b-49b6-86a6-e585309bf802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046996839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1046996839
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3547079195
Short name T1064
Test name
Test status
Simulation time 98718040 ps
CPU time 4.53 seconds
Started Jan 24 02:46:16 PM PST 24
Finished Jan 24 02:46:22 PM PST 24
Peak memory 207324 kb
Host smart-ce9769c5-ab0d-4bae-91fb-d65cf76a7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547079195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3547079195
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2786378256
Short name T925
Test name
Test status
Simulation time 195694477 ps
CPU time 2.73 seconds
Started Jan 24 02:46:18 PM PST 24
Finished Jan 24 02:46:23 PM PST 24
Peak memory 206060 kb
Host smart-4f9af821-4582-4c9d-aca8-b0ba93a02bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786378256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2786378256
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2842509560
Short name T674
Test name
Test status
Simulation time 2507496822 ps
CPU time 19.03 seconds
Started Jan 24 02:46:14 PM PST 24
Finished Jan 24 02:46:36 PM PST 24
Peak memory 207628 kb
Host smart-6492f54a-6016-4dc5-a789-8fe5d090bc65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842509560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2842509560
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3613586761
Short name T303
Test name
Test status
Simulation time 2468798590 ps
CPU time 29.48 seconds
Started Jan 24 02:46:16 PM PST 24
Finished Jan 24 02:46:47 PM PST 24
Peak memory 208288 kb
Host smart-b7d83efd-6e9c-4175-a837-3d0ac5199d34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613586761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3613586761
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.44199069
Short name T76
Test name
Test status
Simulation time 59268197 ps
CPU time 2.8 seconds
Started Jan 24 02:46:17 PM PST 24
Finished Jan 24 02:46:23 PM PST 24
Peak memory 206216 kb
Host smart-e556423b-f632-4280-a5d3-30ad92d3e54c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44199069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.44199069
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.176756138
Short name T203
Test name
Test status
Simulation time 77639544 ps
CPU time 3.36 seconds
Started Jan 24 02:46:23 PM PST 24
Finished Jan 24 02:46:31 PM PST 24
Peak memory 215256 kb
Host smart-0400d386-8b60-4f2d-a814-4a7c8ab3586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176756138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.176756138
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3436612262
Short name T220
Test name
Test status
Simulation time 493785177 ps
CPU time 9.54 seconds
Started Jan 24 04:06:23 PM PST 24
Finished Jan 24 04:06:33 PM PST 24
Peak memory 219532 kb
Host smart-ec5f41e7-9fd8-4440-b780-440e7b1d370c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436612262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3436612262
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2516700409
Short name T655
Test name
Test status
Simulation time 9429968685 ps
CPU time 108.63 seconds
Started Jan 24 03:55:20 PM PST 24
Finished Jan 24 03:57:10 PM PST 24
Peak memory 208816 kb
Host smart-ded941ff-bcea-4ac9-a3bb-6d07ddfe6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516700409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2516700409
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3077895826
Short name T808
Test name
Test status
Simulation time 518172066 ps
CPU time 9.15 seconds
Started Jan 24 03:40:02 PM PST 24
Finished Jan 24 03:40:17 PM PST 24
Peak memory 209920 kb
Host smart-cf26823d-6006-4a40-bd0c-9e17a6b3ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077895826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3077895826
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3959111135
Short name T677
Test name
Test status
Simulation time 50062566 ps
CPU time 0.75 seconds
Started Jan 24 02:46:42 PM PST 24
Finished Jan 24 02:46:47 PM PST 24
Peak memory 205480 kb
Host smart-560feaf2-ee01-42da-98b8-372aa6c82c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959111135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3959111135
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4183487235
Short name T31
Test name
Test status
Simulation time 147606208 ps
CPU time 4.43 seconds
Started Jan 24 02:46:38 PM PST 24
Finished Jan 24 02:46:46 PM PST 24
Peak memory 209692 kb
Host smart-22dd071c-8844-4cba-a1ea-d086c5df101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183487235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4183487235
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1410549988
Short name T362
Test name
Test status
Simulation time 327850945 ps
CPU time 3.06 seconds
Started Jan 24 02:46:27 PM PST 24
Finished Jan 24 02:46:36 PM PST 24
Peak memory 206732 kb
Host smart-2dbd88c2-048e-4820-bd0f-a7da8e4f1163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410549988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1410549988
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.733414116
Short name T750
Test name
Test status
Simulation time 32057775 ps
CPU time 2.25 seconds
Started Jan 24 03:55:09 PM PST 24
Finished Jan 24 03:55:15 PM PST 24
Peak memory 208012 kb
Host smart-1f53d48e-0e25-405f-97eb-258063e4d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733414116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.733414116
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2228683587
Short name T352
Test name
Test status
Simulation time 204434423 ps
CPU time 3.95 seconds
Started Jan 24 02:46:38 PM PST 24
Finished Jan 24 02:46:46 PM PST 24
Peak memory 213680 kb
Host smart-6bbc4bd6-5540-431b-ae14-7f1287b73164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228683587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2228683587
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3887331747
Short name T49
Test name
Test status
Simulation time 167729043 ps
CPU time 3.04 seconds
Started Jan 24 02:46:23 PM PST 24
Finished Jan 24 02:46:31 PM PST 24
Peak memory 219376 kb
Host smart-ac6bf154-f67b-4ec5-9d38-5420f537aad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887331747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3887331747
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3929225641
Short name T764
Test name
Test status
Simulation time 125358185 ps
CPU time 5.45 seconds
Started Jan 24 03:41:50 PM PST 24
Finished Jan 24 03:42:07 PM PST 24
Peak memory 207704 kb
Host smart-b04a4e3d-ae47-4918-955e-b4352b9c88db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929225641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3929225641
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1742627180
Short name T274
Test name
Test status
Simulation time 425713089 ps
CPU time 14.42 seconds
Started Jan 24 02:46:29 PM PST 24
Finished Jan 24 02:46:50 PM PST 24
Peak memory 207932 kb
Host smart-0ebc8e25-6061-427e-b3ac-e78d59da42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742627180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1742627180
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1606547676
Short name T1071
Test name
Test status
Simulation time 802236504 ps
CPU time 8.72 seconds
Started Jan 24 02:58:43 PM PST 24
Finished Jan 24 02:58:57 PM PST 24
Peak memory 207016 kb
Host smart-88f360ca-f0ea-47e3-bdea-8d72c102961a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606547676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1606547676
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3391202599
Short name T306
Test name
Test status
Simulation time 132092562 ps
CPU time 4.44 seconds
Started Jan 24 06:42:42 PM PST 24
Finished Jan 24 06:42:47 PM PST 24
Peak memory 206132 kb
Host smart-5ba6159b-f3fb-43e2-9376-574fb569e00a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391202599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3391202599
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2498637705
Short name T902
Test name
Test status
Simulation time 363149391 ps
CPU time 5 seconds
Started Jan 24 02:46:30 PM PST 24
Finished Jan 24 02:46:42 PM PST 24
Peak memory 207816 kb
Host smart-ea2af3b0-17b1-4b12-9f88-474ac5fa00bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498637705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2498637705
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1208373486
Short name T871
Test name
Test status
Simulation time 122309413 ps
CPU time 2.9 seconds
Started Jan 24 02:46:35 PM PST 24
Finished Jan 24 02:46:42 PM PST 24
Peak memory 209092 kb
Host smart-7157f7d8-0de8-4fa5-b912-0129b6890c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208373486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1208373486
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1732764619
Short name T937
Test name
Test status
Simulation time 238040878 ps
CPU time 3.13 seconds
Started Jan 24 02:51:17 PM PST 24
Finished Jan 24 02:51:30 PM PST 24
Peak memory 206044 kb
Host smart-cd0bac15-d9e3-4038-9edb-2ce07119e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732764619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1732764619
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4279013602
Short name T228
Test name
Test status
Simulation time 527243177 ps
CPU time 25.64 seconds
Started Jan 24 02:46:35 PM PST 24
Finished Jan 24 02:47:05 PM PST 24
Peak memory 214296 kb
Host smart-a9a2d791-c6d2-40ec-b5aa-7ea8e95d6690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279013602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4279013602
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1736263665
Short name T913
Test name
Test status
Simulation time 640923998 ps
CPU time 6.33 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:47:02 PM PST 24
Peak memory 222156 kb
Host smart-33a3e650-d9c9-4ae7-b140-12a44e15b01c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736263665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1736263665
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4268078361
Short name T921
Test name
Test status
Simulation time 917498555 ps
CPU time 6.59 seconds
Started Jan 24 02:46:28 PM PST 24
Finished Jan 24 02:46:42 PM PST 24
Peak memory 206496 kb
Host smart-e5de7eae-f04f-45eb-b86a-2b5a02c8a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268078361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4268078361
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1110687047
Short name T45
Test name
Test status
Simulation time 57057005 ps
CPU time 2.43 seconds
Started Jan 24 02:46:37 PM PST 24
Finished Jan 24 02:46:44 PM PST 24
Peak memory 209428 kb
Host smart-460640e8-f33c-4bc0-85a2-02316c20966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110687047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1110687047
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3167185771
Short name T672
Test name
Test status
Simulation time 11647208 ps
CPU time 0.78 seconds
Started Jan 24 02:46:50 PM PST 24
Finished Jan 24 02:46:59 PM PST 24
Peak memory 205488 kb
Host smart-72f55e76-204a-4167-aa0f-18fe215e8db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167185771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3167185771
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.606724104
Short name T949
Test name
Test status
Simulation time 341738834 ps
CPU time 2.72 seconds
Started Jan 24 02:46:52 PM PST 24
Finished Jan 24 02:47:13 PM PST 24
Peak memory 214096 kb
Host smart-c47506a0-1168-4268-8dc6-839c079860c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606724104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.606724104
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3328368900
Short name T25
Test name
Test status
Simulation time 227723480 ps
CPU time 3.84 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:01 PM PST 24
Peak memory 213772 kb
Host smart-4f68ba8e-9194-45e0-b2bd-a82dcf0cf317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328368900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3328368900
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2323090639
Short name T960
Test name
Test status
Simulation time 34832097 ps
CPU time 2.04 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:46:59 PM PST 24
Peak memory 208552 kb
Host smart-0f1ae36c-e442-41b6-b73b-6b242a844d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323090639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2323090639
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3015435616
Short name T930
Test name
Test status
Simulation time 81781163 ps
CPU time 3.78 seconds
Started Jan 24 02:46:53 PM PST 24
Finished Jan 24 02:47:14 PM PST 24
Peak memory 207748 kb
Host smart-efc56169-e0a3-4b2f-aaf5-1947d5a0f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015435616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3015435616
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1064321499
Short name T624
Test name
Test status
Simulation time 506065024 ps
CPU time 3.84 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:01 PM PST 24
Peak memory 208928 kb
Host smart-295e247a-091c-4165-82ef-28a089642cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064321499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1064321499
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.547138690
Short name T684
Test name
Test status
Simulation time 448415226 ps
CPU time 5.24 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:03 PM PST 24
Peak memory 209260 kb
Host smart-6be59a6b-d8c4-4def-9b22-062e9967e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547138690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.547138690
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.848120659
Short name T1061
Test name
Test status
Simulation time 53168211 ps
CPU time 2.8 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:46:58 PM PST 24
Peak memory 206140 kb
Host smart-45bb6624-a621-44d8-a8e4-6e62a7d8736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848120659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.848120659
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.356866692
Short name T617
Test name
Test status
Simulation time 4968574858 ps
CPU time 28.53 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:47:23 PM PST 24
Peak memory 207244 kb
Host smart-c9f32ddf-43e7-4090-8ea3-b94ddb8e242e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356866692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.356866692
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2941046298
Short name T749
Test name
Test status
Simulation time 199056693 ps
CPU time 3.07 seconds
Started Jan 24 02:46:52 PM PST 24
Finished Jan 24 02:47:12 PM PST 24
Peak memory 208068 kb
Host smart-1105420b-bd4b-48aa-ad6b-78f23fe7da80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941046298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2941046298
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2195848236
Short name T307
Test name
Test status
Simulation time 36872091 ps
CPU time 2.51 seconds
Started Jan 24 02:46:50 PM PST 24
Finished Jan 24 02:47:01 PM PST 24
Peak memory 206040 kb
Host smart-7cb86f94-5843-4564-8474-c013c5b83a6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195848236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2195848236
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.524997074
Short name T723
Test name
Test status
Simulation time 150235293 ps
CPU time 4.09 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:01 PM PST 24
Peak memory 209168 kb
Host smart-e9b6b3ce-1768-445b-a09a-3d9770ebafa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524997074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.524997074
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.582860567
Short name T828
Test name
Test status
Simulation time 40563929 ps
CPU time 2.34 seconds
Started Jan 24 02:46:37 PM PST 24
Finished Jan 24 02:46:43 PM PST 24
Peak memory 205912 kb
Host smart-a5980198-5f5a-4cbc-b78d-d2b7087b1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582860567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.582860567
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3395924834
Short name T955
Test name
Test status
Simulation time 4541109447 ps
CPU time 55.21 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:52 PM PST 24
Peak memory 215484 kb
Host smart-97581753-d571-444e-8e6b-df1c76147c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395924834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3395924834
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.146464624
Short name T103
Test name
Test status
Simulation time 225426466 ps
CPU time 6.61 seconds
Started Jan 24 03:15:56 PM PST 24
Finished Jan 24 03:16:03 PM PST 24
Peak memory 218696 kb
Host smart-b1044d5d-d47f-4931-aca5-8122903e71a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146464624 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.146464624
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2370030923
Short name T1018
Test name
Test status
Simulation time 1682390862 ps
CPU time 33.45 seconds
Started Jan 24 02:46:53 PM PST 24
Finished Jan 24 02:47:44 PM PST 24
Peak memory 208308 kb
Host smart-82ca7696-a054-4bdf-a7e8-7c11410bdc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370030923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2370030923
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3497518708
Short name T754
Test name
Test status
Simulation time 77668758 ps
CPU time 2.54 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:46:58 PM PST 24
Peak memory 208936 kb
Host smart-e1609264-12de-4bf0-b5d9-0d6733f903c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497518708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3497518708
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1986574379
Short name T616
Test name
Test status
Simulation time 9158870 ps
CPU time 0.82 seconds
Started Jan 24 02:47:06 PM PST 24
Finished Jan 24 02:47:30 PM PST 24
Peak memory 205464 kb
Host smart-8593c92e-7229-4995-a0ab-2ac7f4c4056b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986574379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1986574379
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3095951575
Short name T348
Test name
Test status
Simulation time 749765921 ps
CPU time 5.82 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:03 PM PST 24
Peak memory 213812 kb
Host smart-6191483d-1d36-4c7d-8793-2afcd6d014e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095951575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3095951575
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1973048990
Short name T627
Test name
Test status
Simulation time 594501740 ps
CPU time 4.29 seconds
Started Jan 24 02:46:52 PM PST 24
Finished Jan 24 02:47:13 PM PST 24
Peak memory 208292 kb
Host smart-a1ed42aa-20c5-4f4a-9b38-d3705683efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973048990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1973048990
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3965059608
Short name T927
Test name
Test status
Simulation time 496430400 ps
CPU time 6.76 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:04 PM PST 24
Peak memory 221664 kb
Host smart-a09fb133-90e3-46b0-81b5-ac0402eaafdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965059608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3965059608
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3802808336
Short name T671
Test name
Test status
Simulation time 233732940 ps
CPU time 3.21 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:46:59 PM PST 24
Peak memory 213840 kb
Host smart-59f88223-1769-43e0-b584-5d0d726b1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802808336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3802808336
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4227838392
Short name T253
Test name
Test status
Simulation time 701807411 ps
CPU time 4.25 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:01 PM PST 24
Peak memory 208440 kb
Host smart-c1da67ba-0cf0-4b0c-8ff2-c639536a4639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227838392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4227838392
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.135624458
Short name T1032
Test name
Test status
Simulation time 4167962434 ps
CPU time 45.82 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:43 PM PST 24
Peak memory 207384 kb
Host smart-ffbbc402-1cad-4491-9874-d7fa394d75e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135624458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.135624458
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1563260576
Short name T883
Test name
Test status
Simulation time 628471425 ps
CPU time 2.79 seconds
Started Jan 24 02:46:47 PM PST 24
Finished Jan 24 02:46:58 PM PST 24
Peak memory 205988 kb
Host smart-28a416c2-f801-48af-a031-3dd3b6617e59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563260576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1563260576
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4002918203
Short name T716
Test name
Test status
Simulation time 266427513 ps
CPU time 3.25 seconds
Started Jan 24 03:32:25 PM PST 24
Finished Jan 24 03:32:31 PM PST 24
Peak memory 206556 kb
Host smart-9b89b4ab-052f-40ec-93a6-38cb6dddfc6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002918203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4002918203
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3669368909
Short name T15
Test name
Test status
Simulation time 297336359 ps
CPU time 2.48 seconds
Started Jan 24 02:46:45 PM PST 24
Finished Jan 24 02:46:54 PM PST 24
Peak memory 206208 kb
Host smart-afea9901-2a23-4cee-9a53-19888a800344
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669368909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3669368909
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4242845161
Short name T382
Test name
Test status
Simulation time 228976705 ps
CPU time 2.79 seconds
Started Jan 24 02:56:40 PM PST 24
Finished Jan 24 02:56:45 PM PST 24
Peak memory 208188 kb
Host smart-def07851-2607-4818-a6c9-8c32554e0897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242845161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4242845161
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2666809754
Short name T831
Test name
Test status
Simulation time 134348455 ps
CPU time 3.56 seconds
Started Jan 24 02:46:52 PM PST 24
Finished Jan 24 02:47:12 PM PST 24
Peak memory 207960 kb
Host smart-2efd911b-275d-4760-b7eb-684d4c91c869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666809754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2666809754
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4156093574
Short name T237
Test name
Test status
Simulation time 12363943543 ps
CPU time 79 seconds
Started Jan 24 04:25:06 PM PST 24
Finished Jan 24 04:26:26 PM PST 24
Peak memory 216196 kb
Host smart-c3c450d2-dcef-40c1-b906-e5d0c9e24741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156093574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4156093574
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.249295899
Short name T870
Test name
Test status
Simulation time 194374312 ps
CPU time 2.98 seconds
Started Jan 24 03:32:12 PM PST 24
Finished Jan 24 03:32:17 PM PST 24
Peak memory 222048 kb
Host smart-c2a1f4ac-3232-4ab9-ba99-086c3abafe6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249295899 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.249295899
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3208390100
Short name T865
Test name
Test status
Simulation time 406721551 ps
CPU time 4.6 seconds
Started Jan 24 02:46:50 PM PST 24
Finished Jan 24 02:47:03 PM PST 24
Peak memory 208236 kb
Host smart-26f813e1-ce56-4d46-8d50-37c5b585bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208390100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3208390100
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.794026741
Short name T573
Test name
Test status
Simulation time 471087360 ps
CPU time 4.53 seconds
Started Jan 24 03:51:49 PM PST 24
Finished Jan 24 03:51:56 PM PST 24
Peak memory 209640 kb
Host smart-4c556bec-5622-413a-9ba2-69eb7b633fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794026741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.794026741
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2534124488
Short name T710
Test name
Test status
Simulation time 9634987 ps
CPU time 0.83 seconds
Started Jan 24 02:47:15 PM PST 24
Finished Jan 24 02:47:46 PM PST 24
Peak memory 205440 kb
Host smart-4eb01014-10b7-4cd2-8fdf-95023cc11fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534124488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2534124488
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3577627252
Short name T407
Test name
Test status
Simulation time 298282978 ps
CPU time 6.41 seconds
Started Jan 24 03:03:46 PM PST 24
Finished Jan 24 03:04:12 PM PST 24
Peak memory 213640 kb
Host smart-9e7a5678-6ffd-4a33-962c-c3d5ba893051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577627252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3577627252
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.654285973
Short name T28
Test name
Test status
Simulation time 97314257 ps
CPU time 2.82 seconds
Started Jan 24 02:47:16 PM PST 24
Finished Jan 24 02:47:50 PM PST 24
Peak memory 216816 kb
Host smart-0de75746-ef44-4cee-8b89-3ac4b1c74e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654285973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.654285973
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.902853332
Short name T337
Test name
Test status
Simulation time 139368735 ps
CPU time 4.49 seconds
Started Jan 24 02:47:15 PM PST 24
Finished Jan 24 02:47:50 PM PST 24
Peak memory 213772 kb
Host smart-a3d7d2bf-016d-42ab-83aa-e9dff6f6d441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902853332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.902853332
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.110565955
Short name T1068
Test name
Test status
Simulation time 187255157 ps
CPU time 3.84 seconds
Started Jan 24 02:47:15 PM PST 24
Finished Jan 24 02:47:49 PM PST 24
Peak memory 210772 kb
Host smart-bb8dbadd-daa7-440a-beaf-50bc7b4ca3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110565955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.110565955
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1305779591
Short name T276
Test name
Test status
Simulation time 110384852 ps
CPU time 4.05 seconds
Started Jan 24 02:47:13 PM PST 24
Finished Jan 24 02:47:45 PM PST 24
Peak memory 213836 kb
Host smart-2753f6cb-0dc1-4ba1-89cc-d7a8758abdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305779591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1305779591
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4075270925
Short name T827
Test name
Test status
Simulation time 44811437 ps
CPU time 2.59 seconds
Started Jan 24 02:47:01 PM PST 24
Finished Jan 24 02:47:29 PM PST 24
Peak memory 207048 kb
Host smart-eb5332ea-4cf4-4141-97ab-3aca33b2346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075270925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4075270925
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.375809115
Short name T628
Test name
Test status
Simulation time 4199113965 ps
CPU time 52.84 seconds
Started Jan 24 02:47:06 PM PST 24
Finished Jan 24 02:48:22 PM PST 24
Peak memory 207644 kb
Host smart-6d5f34c2-37a9-4282-b503-71ffc2b85a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375809115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.375809115
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2974568343
Short name T340
Test name
Test status
Simulation time 102725891 ps
CPU time 2.75 seconds
Started Jan 24 02:47:06 PM PST 24
Finished Jan 24 02:47:32 PM PST 24
Peak memory 205980 kb
Host smart-bd485ad2-bc95-4ca1-a5c2-ff902594c3fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974568343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2974568343
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3553370138
Short name T694
Test name
Test status
Simulation time 411957987 ps
CPU time 8.96 seconds
Started Jan 24 02:47:06 PM PST 24
Finished Jan 24 02:47:38 PM PST 24
Peak memory 207888 kb
Host smart-f9d619ee-49bd-47b1-b0bd-516570382671
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553370138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3553370138
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2812487507
Short name T331
Test name
Test status
Simulation time 10846418289 ps
CPU time 49.51 seconds
Started Jan 24 03:22:53 PM PST 24
Finished Jan 24 03:23:48 PM PST 24
Peak memory 207260 kb
Host smart-9d7d7758-713c-47a3-8a92-2355270dab76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812487507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2812487507
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2146685239
Short name T361
Test name
Test status
Simulation time 172997695 ps
CPU time 4.87 seconds
Started Jan 24 02:47:12 PM PST 24
Finished Jan 24 02:47:43 PM PST 24
Peak memory 213808 kb
Host smart-03491c0f-c6e9-4b93-874b-ef64410b0b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146685239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2146685239
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3076150727
Short name T19
Test name
Test status
Simulation time 561261811 ps
CPU time 3.19 seconds
Started Jan 24 02:47:06 PM PST 24
Finished Jan 24 02:47:32 PM PST 24
Peak memory 207892 kb
Host smart-e77b8125-5891-43cf-9501-f18f03a2bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076150727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3076150727
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2750092191
Short name T1025
Test name
Test status
Simulation time 511497057 ps
CPU time 10.5 seconds
Started Jan 24 02:47:14 PM PST 24
Finished Jan 24 02:47:54 PM PST 24
Peak memory 219444 kb
Host smart-91d5b606-f17f-4c74-8423-a19da43eca8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750092191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2750092191
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3378888228
Short name T1079
Test name
Test status
Simulation time 82666987 ps
CPU time 4.61 seconds
Started Jan 24 02:47:15 PM PST 24
Finished Jan 24 02:47:51 PM PST 24
Peak memory 218464 kb
Host smart-953adb87-6689-4c92-bb16-788a893782f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378888228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3378888228
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.555773956
Short name T351
Test name
Test status
Simulation time 245258443 ps
CPU time 6.02 seconds
Started Jan 24 02:47:13 PM PST 24
Finished Jan 24 02:47:48 PM PST 24
Peak memory 217884 kb
Host smart-af90101b-2f21-4114-acc0-5e5ef68a88ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555773956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.555773956
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3316270074
Short name T100
Test name
Test status
Simulation time 75779826 ps
CPU time 0.7 seconds
Started Jan 24 02:47:37 PM PST 24
Finished Jan 24 02:48:07 PM PST 24
Peak memory 205484 kb
Host smart-bfcbb38b-1830-4363-af99-05bfe3c8b4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316270074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3316270074
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2304721783
Short name T255
Test name
Test status
Simulation time 186725691 ps
CPU time 5.44 seconds
Started Jan 24 02:47:29 PM PST 24
Finished Jan 24 02:48:05 PM PST 24
Peak memory 213740 kb
Host smart-75eb8498-d16d-48e1-b063-39b39d3bc8c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304721783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2304721783
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.217415676
Short name T26
Test name
Test status
Simulation time 5788713727 ps
CPU time 32.11 seconds
Started Jan 24 03:33:16 PM PST 24
Finished Jan 24 03:33:53 PM PST 24
Peak memory 209924 kb
Host smart-66c878cd-0edc-49da-9f42-f6f2604b6662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217415676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.217415676
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2166295023
Short name T649
Test name
Test status
Simulation time 79324915 ps
CPU time 2.47 seconds
Started Jan 24 03:04:34 PM PST 24
Finished Jan 24 03:04:57 PM PST 24
Peak memory 208416 kb
Host smart-4b73b972-d555-4da8-939a-321c8a31fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166295023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2166295023
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1762074820
Short name T92
Test name
Test status
Simulation time 316249672 ps
CPU time 4.04 seconds
Started Jan 24 02:47:29 PM PST 24
Finished Jan 24 02:48:04 PM PST 24
Peak memory 208276 kb
Host smart-f620e16b-ce10-47da-a799-40f544c1bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762074820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1762074820
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.87671061
Short name T229
Test name
Test status
Simulation time 454732923 ps
CPU time 4.31 seconds
Started Jan 24 02:47:20 PM PST 24
Finished Jan 24 02:47:54 PM PST 24
Peak memory 208420 kb
Host smart-5967c7a0-f860-4816-a9c9-ec6ffa253d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87671061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.87671061
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3667208497
Short name T817
Test name
Test status
Simulation time 89856884 ps
CPU time 4.19 seconds
Started Jan 24 02:47:28 PM PST 24
Finished Jan 24 02:48:04 PM PST 24
Peak memory 207768 kb
Host smart-18379302-cb62-48de-9abd-94bd54301df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667208497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3667208497
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.468973332
Short name T1035
Test name
Test status
Simulation time 85657178 ps
CPU time 1.92 seconds
Started Jan 24 02:47:13 PM PST 24
Finished Jan 24 02:47:42 PM PST 24
Peak memory 206328 kb
Host smart-56780ca8-a959-489f-9bda-e81197f0f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468973332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.468973332
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4246314046
Short name T267
Test name
Test status
Simulation time 121147502 ps
CPU time 3.53 seconds
Started Jan 24 02:47:19 PM PST 24
Finished Jan 24 02:47:53 PM PST 24
Peak memory 207804 kb
Host smart-1eb7fe91-4eca-477c-89d1-6b5eadd76dbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246314046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4246314046
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3530784759
Short name T266
Test name
Test status
Simulation time 570145337 ps
CPU time 4.76 seconds
Started Jan 24 02:47:17 PM PST 24
Finished Jan 24 02:47:54 PM PST 24
Peak memory 207808 kb
Host smart-991f549c-6395-435f-8ac3-09145d72e34d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530784759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3530784759
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1113551986
Short name T762
Test name
Test status
Simulation time 1006084917 ps
CPU time 3.27 seconds
Started Jan 24 02:47:17 PM PST 24
Finished Jan 24 02:47:53 PM PST 24
Peak memory 208028 kb
Host smart-256d4ca7-5c47-4bca-b76b-6a4c2d3df482
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113551986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1113551986
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2890234225
Short name T283
Test name
Test status
Simulation time 102177907 ps
CPU time 4.29 seconds
Started Jan 24 02:55:00 PM PST 24
Finished Jan 24 02:55:14 PM PST 24
Peak memory 217820 kb
Host smart-b31c7e0e-bcba-445e-9000-07f442e42111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890234225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2890234225
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1899465792
Short name T613
Test name
Test status
Simulation time 198201718 ps
CPU time 2.21 seconds
Started Jan 24 02:47:11 PM PST 24
Finished Jan 24 02:47:39 PM PST 24
Peak memory 205860 kb
Host smart-8de38cc9-97b7-493c-9ce2-a9036d9a28ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899465792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1899465792
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1546085404
Short name T940
Test name
Test status
Simulation time 215827838 ps
CPU time 6.17 seconds
Started Jan 24 02:47:34 PM PST 24
Finished Jan 24 02:48:10 PM PST 24
Peak memory 218832 kb
Host smart-833f7a21-b7d1-4183-9991-06c6d51a87fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546085404 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1546085404
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.646033197
Short name T757
Test name
Test status
Simulation time 184382392 ps
CPU time 5.82 seconds
Started Jan 24 02:47:19 PM PST 24
Finished Jan 24 02:47:55 PM PST 24
Peak memory 208260 kb
Host smart-34a7d520-dd9b-473b-8756-a7e725943322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646033197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.646033197
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3500596137
Short name T50
Test name
Test status
Simulation time 150946752 ps
CPU time 3.44 seconds
Started Jan 24 03:47:44 PM PST 24
Finished Jan 24 03:47:50 PM PST 24
Peak memory 209444 kb
Host smart-f3860727-545e-4516-900c-152d0054aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500596137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3500596137
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3294173799
Short name T577
Test name
Test status
Simulation time 81620756 ps
CPU time 1.06 seconds
Started Jan 24 02:47:40 PM PST 24
Finished Jan 24 02:48:11 PM PST 24
Peak memory 205504 kb
Host smart-b60382a9-4159-4b71-8dfc-ae7de25c314b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294173799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3294173799
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1147939945
Short name T404
Test name
Test status
Simulation time 170548040 ps
CPU time 3.26 seconds
Started Jan 24 03:35:49 PM PST 24
Finished Jan 24 03:35:55 PM PST 24
Peak memory 213820 kb
Host smart-1cd8578a-9bf4-4a3d-9e47-da6815a218ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147939945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1147939945
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1691075956
Short name T358
Test name
Test status
Simulation time 133024012 ps
CPU time 3.09 seconds
Started Jan 24 02:47:34 PM PST 24
Finished Jan 24 02:48:07 PM PST 24
Peak memory 208444 kb
Host smart-10236511-0324-4f04-8b8d-714c29453d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691075956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1691075956
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1781760699
Short name T46
Test name
Test status
Simulation time 376642044 ps
CPU time 5.55 seconds
Started Jan 24 02:47:38 PM PST 24
Finished Jan 24 02:48:13 PM PST 24
Peak memory 213884 kb
Host smart-da170ffe-befc-457c-a65b-c40fee8eac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781760699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1781760699
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2389809825
Short name T93
Test name
Test status
Simulation time 244376140 ps
CPU time 5.28 seconds
Started Jan 24 02:47:31 PM PST 24
Finished Jan 24 02:48:07 PM PST 24
Peak memory 221892 kb
Host smart-2c83e081-d7a8-413c-b4ab-ac318266efaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389809825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2389809825
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3292011607
Short name T294
Test name
Test status
Simulation time 41856860 ps
CPU time 2.7 seconds
Started Jan 24 02:47:35 PM PST 24
Finished Jan 24 02:48:07 PM PST 24
Peak memory 209540 kb
Host smart-3ffad6fb-5aa0-4b82-a3ac-6f3b6bd5277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292011607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3292011607
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1153824504
Short name T58
Test name
Test status
Simulation time 238268286 ps
CPU time 3.69 seconds
Started Jan 24 02:47:41 PM PST 24
Finished Jan 24 02:48:14 PM PST 24
Peak memory 219380 kb
Host smart-660c2c1a-794b-4219-8ecb-6f14e6428932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153824504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1153824504
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2573602140
Short name T336
Test name
Test status
Simulation time 74635662 ps
CPU time 3.34 seconds
Started Jan 24 02:47:41 PM PST 24
Finished Jan 24 02:48:14 PM PST 24
Peak memory 207708 kb
Host smart-d42ef06b-05e5-47af-9fb5-a5147e4b0ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573602140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2573602140
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1477181094
Short name T1085
Test name
Test status
Simulation time 204505875 ps
CPU time 4.62 seconds
Started Jan 24 03:32:17 PM PST 24
Finished Jan 24 03:32:24 PM PST 24
Peak memory 207656 kb
Host smart-67593fd5-a8e8-4a0e-aee7-e465124fd387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477181094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1477181094
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.913158493
Short name T607
Test name
Test status
Simulation time 113009036 ps
CPU time 3.07 seconds
Started Jan 24 02:47:35 PM PST 24
Finished Jan 24 02:48:07 PM PST 24
Peak memory 207664 kb
Host smart-0830f977-ff66-4a35-bff4-4ff44fcdc959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913158493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.913158493
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2125729850
Short name T1083
Test name
Test status
Simulation time 185875156 ps
CPU time 2.75 seconds
Started Jan 24 02:47:37 PM PST 24
Finished Jan 24 02:48:09 PM PST 24
Peak memory 207836 kb
Host smart-812ab725-cd90-4839-85c4-446ac1fdee74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125729850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2125729850
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1820328224
Short name T705
Test name
Test status
Simulation time 269981591 ps
CPU time 2.66 seconds
Started Jan 24 02:47:41 PM PST 24
Finished Jan 24 02:48:14 PM PST 24
Peak memory 205976 kb
Host smart-a2e9fbbd-a4fe-4d3e-83ab-d66d2bfd3ff5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820328224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1820328224
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3356644370
Short name T583
Test name
Test status
Simulation time 266450909 ps
CPU time 3.08 seconds
Started Jan 24 02:47:36 PM PST 24
Finished Jan 24 02:48:08 PM PST 24
Peak memory 207360 kb
Host smart-65a7f60e-aa5e-4bf6-8fb4-3600eaa06b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356644370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3356644370
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2306794520
Short name T224
Test name
Test status
Simulation time 1115480987 ps
CPU time 17.41 seconds
Started Jan 24 02:47:45 PM PST 24
Finished Jan 24 02:48:33 PM PST 24
Peak memory 220912 kb
Host smart-35e55836-252f-4a83-ad82-9a081f93b726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306794520 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2306794520
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1895060311
Short name T1017
Test name
Test status
Simulation time 482770915 ps
CPU time 4.78 seconds
Started Jan 24 02:47:33 PM PST 24
Finished Jan 24 02:48:08 PM PST 24
Peak memory 207900 kb
Host smart-029df0cf-541d-4688-83e4-5f4ddfb630a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895060311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1895060311
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3054983024
Short name T840
Test name
Test status
Simulation time 39839998 ps
CPU time 1.65 seconds
Started Jan 24 02:47:42 PM PST 24
Finished Jan 24 02:48:14 PM PST 24
Peak memory 209344 kb
Host smart-b64cfaa8-67af-4230-a239-d9408626beed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054983024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3054983024
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1510032524
Short name T900
Test name
Test status
Simulation time 15189446 ps
CPU time 0.8 seconds
Started Jan 24 02:47:52 PM PST 24
Finished Jan 24 02:48:22 PM PST 24
Peak memory 205460 kb
Host smart-a9f38de8-6c38-4714-a9c5-3a3db60e8116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510032524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1510032524
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1718779265
Short name T20
Test name
Test status
Simulation time 433827157 ps
CPU time 4.79 seconds
Started Jan 24 02:47:52 PM PST 24
Finished Jan 24 02:48:26 PM PST 24
Peak memory 209512 kb
Host smart-8ad0295b-095b-4446-9727-088b93cd5f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718779265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1718779265
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2415567738
Short name T994
Test name
Test status
Simulation time 89382163 ps
CPU time 2.78 seconds
Started Jan 24 02:47:42 PM PST 24
Finished Jan 24 02:48:15 PM PST 24
Peak memory 206804 kb
Host smart-b89aa239-1c6e-4682-8587-0a968552940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415567738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2415567738
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.256799395
Short name T301
Test name
Test status
Simulation time 862723233 ps
CPU time 20.98 seconds
Started Jan 24 02:47:41 PM PST 24
Finished Jan 24 02:48:32 PM PST 24
Peak memory 221940 kb
Host smart-f08bdea8-9b23-4800-b800-92d422ff216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256799395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.256799395
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.650656742
Short name T318
Test name
Test status
Simulation time 177171751 ps
CPU time 4.92 seconds
Started Jan 24 02:47:53 PM PST 24
Finished Jan 24 02:48:26 PM PST 24
Peak memory 210796 kb
Host smart-0cfba133-caf5-47c7-938c-a834342d3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650656742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.650656742
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1553763802
Short name T112
Test name
Test status
Simulation time 130009025 ps
CPU time 3.14 seconds
Started Jan 24 02:47:47 PM PST 24
Finished Jan 24 02:48:20 PM PST 24
Peak memory 219160 kb
Host smart-2f2f588d-9e72-4845-a698-80142986886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553763802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1553763802
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3767071823
Short name T280
Test name
Test status
Simulation time 247776343 ps
CPU time 6.95 seconds
Started Jan 24 02:47:47 PM PST 24
Finished Jan 24 02:48:25 PM PST 24
Peak memory 209272 kb
Host smart-342327ff-1bbd-4b10-8623-af741f88fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767071823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3767071823
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3435521517
Short name T3
Test name
Test status
Simulation time 199609379 ps
CPU time 2.98 seconds
Started Jan 24 02:47:42 PM PST 24
Finished Jan 24 02:48:16 PM PST 24
Peak memory 207692 kb
Host smart-022975bf-d14c-4cd2-97dc-fc946ab0245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435521517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3435521517
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2941679633
Short name T576
Test name
Test status
Simulation time 492976424 ps
CPU time 4.12 seconds
Started Jan 24 02:47:46 PM PST 24
Finished Jan 24 02:48:21 PM PST 24
Peak memory 206136 kb
Host smart-a446f8bc-270b-4b24-be20-e502938064b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941679633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2941679633
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1616949747
Short name T339
Test name
Test status
Simulation time 1331699514 ps
CPU time 8.09 seconds
Started Jan 24 02:47:44 PM PST 24
Finished Jan 24 02:48:23 PM PST 24
Peak memory 207212 kb
Host smart-37fe21fd-c7a7-41af-b168-96a89fbb1655
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616949747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1616949747
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1214220282
Short name T706
Test name
Test status
Simulation time 341446369 ps
CPU time 3.74 seconds
Started Jan 24 02:47:44 PM PST 24
Finished Jan 24 02:48:19 PM PST 24
Peak memory 207080 kb
Host smart-a23bb3e0-084c-4c7e-a85f-3354c37f7d2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214220282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1214220282
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1879764313
Short name T866
Test name
Test status
Simulation time 208197012 ps
CPU time 2.98 seconds
Started Jan 24 02:47:52 PM PST 24
Finished Jan 24 02:48:24 PM PST 24
Peak memory 207264 kb
Host smart-5f805928-1d77-4dff-9af2-4421afcc1b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879764313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1879764313
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1556906907
Short name T618
Test name
Test status
Simulation time 194888964 ps
CPU time 2.71 seconds
Started Jan 24 02:47:46 PM PST 24
Finished Jan 24 02:48:20 PM PST 24
Peak memory 206016 kb
Host smart-8c647bd5-430b-46c8-88e7-0b25c2a636b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556906907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1556906907
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.515299820
Short name T783
Test name
Test status
Simulation time 772010557 ps
CPU time 6.66 seconds
Started Jan 24 02:47:42 PM PST 24
Finished Jan 24 02:48:20 PM PST 24
Peak memory 209440 kb
Host smart-e8e9503a-cb18-4091-9c5f-219335f9e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515299820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.515299820
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.296037851
Short name T13
Test name
Test status
Simulation time 79338204 ps
CPU time 2.91 seconds
Started Jan 24 02:47:51 PM PST 24
Finished Jan 24 02:48:24 PM PST 24
Peak memory 209596 kb
Host smart-f870d786-eb6c-4438-b85b-d23c840261fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296037851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.296037851
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3818474150
Short name T832
Test name
Test status
Simulation time 24381732 ps
CPU time 0.82 seconds
Started Jan 24 02:48:04 PM PST 24
Finished Jan 24 02:48:33 PM PST 24
Peak memory 205388 kb
Host smart-374b96fb-c8d9-4407-9cf1-f2488f0962a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818474150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3818474150
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3485517735
Short name T330
Test name
Test status
Simulation time 85044430 ps
CPU time 5.02 seconds
Started Jan 24 02:48:04 PM PST 24
Finished Jan 24 02:48:37 PM PST 24
Peak memory 213856 kb
Host smart-cd699638-b2b0-4623-9329-aafe50e39b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485517735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3485517735
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3426367669
Short name T29
Test name
Test status
Simulation time 1642043360 ps
CPU time 13.75 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:48:43 PM PST 24
Peak memory 220144 kb
Host smart-c3d7aaf1-d57e-43af-9210-8f601ae6afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426367669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3426367669
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3401957881
Short name T240
Test name
Test status
Simulation time 79007012 ps
CPU time 2.07 seconds
Started Jan 24 02:48:04 PM PST 24
Finished Jan 24 02:48:35 PM PST 24
Peak memory 207980 kb
Host smart-860ab198-e05c-4f0f-8e3a-945c25358f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401957881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3401957881
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3217665140
Short name T347
Test name
Test status
Simulation time 1070782290 ps
CPU time 29.79 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:48:59 PM PST 24
Peak memory 221960 kb
Host smart-b742085e-d561-4894-b8ef-2778755c1a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217665140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3217665140
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2862179456
Short name T278
Test name
Test status
Simulation time 3096533104 ps
CPU time 5.33 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:48:35 PM PST 24
Peak memory 222072 kb
Host smart-5801b794-68e1-4877-9f9d-5bc76aed41c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862179456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2862179456
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.327950526
Short name T804
Test name
Test status
Simulation time 767096998 ps
CPU time 9.22 seconds
Started Jan 24 02:48:03 PM PST 24
Finished Jan 24 02:48:39 PM PST 24
Peak memory 222056 kb
Host smart-4d62effa-7d99-44cc-8294-f758b5eebe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327950526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.327950526
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.852664237
Short name T915
Test name
Test status
Simulation time 138197621 ps
CPU time 6.46 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:48:36 PM PST 24
Peak memory 213696 kb
Host smart-7ffdaf66-f3cf-465f-b156-3591a23f55bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852664237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.852664237
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2542163310
Short name T819
Test name
Test status
Simulation time 151071902 ps
CPU time 2.85 seconds
Started Jan 24 02:48:00 PM PST 24
Finished Jan 24 02:48:31 PM PST 24
Peak memory 207824 kb
Host smart-9ae110c0-6c84-41f9-b9f7-5abaf594249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542163310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2542163310
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1074126507
Short name T701
Test name
Test status
Simulation time 30712467 ps
CPU time 2.28 seconds
Started Jan 24 02:47:59 PM PST 24
Finished Jan 24 02:48:29 PM PST 24
Peak memory 206008 kb
Host smart-a7d77a63-dfed-4e15-81af-7e705e52d36b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074126507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1074126507
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2829898958
Short name T691
Test name
Test status
Simulation time 82450386 ps
CPU time 3.88 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:48:33 PM PST 24
Peak memory 207964 kb
Host smart-f5f805c1-05e4-48c4-85b5-6f5375e466ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829898958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2829898958
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.787255062
Short name T943
Test name
Test status
Simulation time 1731115340 ps
CPU time 11.62 seconds
Started Jan 24 02:48:06 PM PST 24
Finished Jan 24 02:48:47 PM PST 24
Peak memory 207112 kb
Host smart-5fbce7b2-a2a5-42b1-83fd-408a36c11dda
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787255062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.787255062
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1681101542
Short name T284
Test name
Test status
Simulation time 994178100 ps
CPU time 7.87 seconds
Started Jan 24 02:48:03 PM PST 24
Finished Jan 24 02:48:38 PM PST 24
Peak memory 208088 kb
Host smart-6fcbd359-9714-4e4a-a8a4-247d7a2e5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681101542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1681101542
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4033698696
Short name T693
Test name
Test status
Simulation time 23534754 ps
CPU time 1.98 seconds
Started Jan 24 02:48:04 PM PST 24
Finished Jan 24 02:48:35 PM PST 24
Peak memory 207812 kb
Host smart-7d409c75-2059-4478-b318-21b42dcf09f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033698696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4033698696
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3156975675
Short name T1042
Test name
Test status
Simulation time 2486150442 ps
CPU time 74.79 seconds
Started Jan 24 02:48:02 PM PST 24
Finished Jan 24 02:49:44 PM PST 24
Peak memory 215496 kb
Host smart-0ffe452a-2661-435d-a82d-908111b59b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156975675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3156975675
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.640819872
Short name T939
Test name
Test status
Simulation time 194944716 ps
CPU time 11.01 seconds
Started Jan 24 02:48:03 PM PST 24
Finished Jan 24 02:48:42 PM PST 24
Peak memory 222464 kb
Host smart-4a3395f8-49ce-4ff7-befd-8bf49d0e0238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640819872 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.640819872
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.643167313
Short name T722
Test name
Test status
Simulation time 120643841 ps
CPU time 3.28 seconds
Started Jan 24 02:48:03 PM PST 24
Finished Jan 24 02:48:33 PM PST 24
Peak memory 206932 kb
Host smart-f013c79b-16cb-43dc-acc0-6f37dee8f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643167313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.643167313
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3889812034
Short name T765
Test name
Test status
Simulation time 341818528 ps
CPU time 3.71 seconds
Started Jan 24 02:48:06 PM PST 24
Finished Jan 24 02:48:39 PM PST 24
Peak memory 209636 kb
Host smart-064d752f-151d-4d74-bc03-da021997fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889812034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3889812034
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1937642644
Short name T797
Test name
Test status
Simulation time 45622753 ps
CPU time 0.85 seconds
Started Jan 24 02:39:46 PM PST 24
Finished Jan 24 02:39:59 PM PST 24
Peak memory 205460 kb
Host smart-b7621a16-12fe-4f2f-b594-32a49ed19b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937642644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1937642644
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3969415729
Short name T401
Test name
Test status
Simulation time 143214239 ps
CPU time 3.92 seconds
Started Jan 24 02:45:34 PM PST 24
Finished Jan 24 02:45:50 PM PST 24
Peak memory 213828 kb
Host smart-d410b690-8344-4b9f-8a40-fca681ca1e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969415729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3969415729
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3945269911
Short name T1002
Test name
Test status
Simulation time 130017823 ps
CPU time 3.06 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:53 PM PST 24
Peak memory 209288 kb
Host smart-4ea2af73-5962-445d-a4e3-4914a8e105a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945269911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3945269911
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3192822385
Short name T66
Test name
Test status
Simulation time 221164247 ps
CPU time 3.37 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:55 PM PST 24
Peak memory 209048 kb
Host smart-34a0e8b6-d4b5-4b07-9642-7c60916332c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192822385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3192822385
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1182848001
Short name T326
Test name
Test status
Simulation time 90775806 ps
CPU time 3.8 seconds
Started Jan 24 02:39:24 PM PST 24
Finished Jan 24 02:39:42 PM PST 24
Peak memory 221024 kb
Host smart-7b781cb3-4abe-4d45-9dd2-4bd53facbfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182848001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1182848001
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3550162186
Short name T188
Test name
Test status
Simulation time 350105585 ps
CPU time 6.45 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:58 PM PST 24
Peak memory 221912 kb
Host smart-dce91aa3-4035-4a79-bd8d-12465bee8d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550162186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3550162186
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4284662833
Short name T644
Test name
Test status
Simulation time 138505191 ps
CPU time 2.24 seconds
Started Jan 24 02:48:55 PM PST 24
Finished Jan 24 02:49:16 PM PST 24
Peak memory 214844 kb
Host smart-5f8adcb7-5411-44fd-bf73-d2682e620f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284662833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4284662833
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1308592466
Short name T200
Test name
Test status
Simulation time 1841643061 ps
CPU time 5.3 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:57 PM PST 24
Peak memory 209808 kb
Host smart-eb6e3839-173f-4af6-b75b-aadf459364b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308592466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1308592466
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.619583075
Short name T105
Test name
Test status
Simulation time 3522838347 ps
CPU time 12.24 seconds
Started Jan 24 02:39:39 PM PST 24
Finished Jan 24 02:40:08 PM PST 24
Peak memory 231428 kb
Host smart-ffcab40e-0025-4cbb-ba0d-1ad83fbd6c20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619583075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.619583075
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3665324171
Short name T327
Test name
Test status
Simulation time 321071369 ps
CPU time 4.08 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:39:55 PM PST 24
Peak memory 206656 kb
Host smart-e18b2d69-1bf2-4396-a8d4-48d11bbf49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665324171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3665324171
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1257480024
Short name T992
Test name
Test status
Simulation time 262938349 ps
CPU time 3.95 seconds
Started Jan 24 02:39:27 PM PST 24
Finished Jan 24 02:39:45 PM PST 24
Peak memory 207756 kb
Host smart-48c2c7ed-4ac3-4e59-b023-90d320e49bec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257480024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1257480024
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.329126656
Short name T74
Test name
Test status
Simulation time 13245996499 ps
CPU time 35.83 seconds
Started Jan 24 02:39:31 PM PST 24
Finished Jan 24 02:40:27 PM PST 24
Peak memory 208112 kb
Host smart-c60f5f94-9cf3-4aff-b383-adecf2cc3532
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329126656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.329126656
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.961564921
Short name T929
Test name
Test status
Simulation time 90003594 ps
CPU time 1.74 seconds
Started Jan 24 02:39:32 PM PST 24
Finished Jan 24 02:39:55 PM PST 24
Peak memory 206036 kb
Host smart-4cfd8e70-502a-4efa-ad1c-1490365db7fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961564921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.961564921
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.102043056
Short name T622
Test name
Test status
Simulation time 56600947 ps
CPU time 2.09 seconds
Started Jan 24 02:39:28 PM PST 24
Finished Jan 24 02:39:46 PM PST 24
Peak memory 207948 kb
Host smart-742c7496-8f67-45ee-b4da-1561774c9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102043056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.102043056
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2519055605
Short name T675
Test name
Test status
Simulation time 101260106 ps
CPU time 2.89 seconds
Started Jan 24 02:43:03 PM PST 24
Finished Jan 24 02:43:39 PM PST 24
Peak memory 206152 kb
Host smart-37dad75e-e07b-4b36-8ff8-08c614fe602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519055605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2519055605
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4057948102
Short name T727
Test name
Test status
Simulation time 165312035 ps
CPU time 5.38 seconds
Started Jan 24 02:39:38 PM PST 24
Finished Jan 24 02:40:01 PM PST 24
Peak memory 222192 kb
Host smart-40426e1d-0da7-46e7-ae59-6fde933fbfc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057948102 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4057948102
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.644783627
Short name T972
Test name
Test status
Simulation time 393122160 ps
CPU time 3.85 seconds
Started Jan 24 02:39:28 PM PST 24
Finished Jan 24 02:39:48 PM PST 24
Peak memory 207288 kb
Host smart-915b4bb4-fbdb-4574-960a-b973fb4993bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644783627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.644783627
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.732432242
Short name T381
Test name
Test status
Simulation time 403900192 ps
CPU time 4.8 seconds
Started Jan 24 02:39:25 PM PST 24
Finished Jan 24 02:39:43 PM PST 24
Peak memory 209668 kb
Host smart-ff432538-5b4c-4f89-ae48-12bad35ec101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732432242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.732432242
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4190868439
Short name T970
Test name
Test status
Simulation time 59793198 ps
CPU time 0.76 seconds
Started Jan 24 02:48:23 PM PST 24
Finished Jan 24 02:48:50 PM PST 24
Peak memory 205392 kb
Host smart-d284e07c-a539-4d99-839b-419feebf2758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190868439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4190868439
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1313688480
Short name T290
Test name
Test status
Simulation time 160300367 ps
CPU time 2.84 seconds
Started Jan 24 02:48:15 PM PST 24
Finished Jan 24 02:48:46 PM PST 24
Peak memory 213744 kb
Host smart-5a2ede11-2afd-4e1e-9300-8a17356d9a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313688480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1313688480
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1291454897
Short name T1069
Test name
Test status
Simulation time 43759115 ps
CPU time 1.45 seconds
Started Jan 24 02:57:23 PM PST 24
Finished Jan 24 02:57:40 PM PST 24
Peak memory 209032 kb
Host smart-2bdcaac0-a08b-42c5-b74c-7d95e28d90c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291454897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1291454897
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1434795361
Short name T868
Test name
Test status
Simulation time 519894972 ps
CPU time 5.48 seconds
Started Jan 24 02:48:15 PM PST 24
Finished Jan 24 02:48:49 PM PST 24
Peak memory 208408 kb
Host smart-54291fe3-dba5-4762-a922-c6bc10800ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434795361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1434795361
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1223330225
Short name T371
Test name
Test status
Simulation time 643678818 ps
CPU time 11.69 seconds
Started Jan 24 02:48:12 PM PST 24
Finished Jan 24 02:48:52 PM PST 24
Peak memory 218512 kb
Host smart-0d2b2ef6-760d-47c6-9cc8-3b2279920d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223330225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1223330225
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3902075085
Short name T914
Test name
Test status
Simulation time 2435368423 ps
CPU time 29.06 seconds
Started Jan 24 02:55:08 PM PST 24
Finished Jan 24 02:55:43 PM PST 24
Peak memory 222032 kb
Host smart-3931321d-b98e-4b84-8f9f-86924c62690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902075085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3902075085
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1272201310
Short name T218
Test name
Test status
Simulation time 236506384 ps
CPU time 3.42 seconds
Started Jan 24 02:48:14 PM PST 24
Finished Jan 24 02:48:46 PM PST 24
Peak memory 209016 kb
Host smart-81192859-50ab-4209-b37b-6a7c934437e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272201310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1272201310
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2101939109
Short name T107
Test name
Test status
Simulation time 241308006 ps
CPU time 3.14 seconds
Started Jan 24 02:48:16 PM PST 24
Finished Jan 24 02:48:47 PM PST 24
Peak memory 207940 kb
Host smart-73d3b97a-70dd-4c55-b028-c9db788bc5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101939109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2101939109
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1721105415
Short name T1081
Test name
Test status
Simulation time 190661270 ps
CPU time 7.02 seconds
Started Jan 24 03:47:03 PM PST 24
Finished Jan 24 03:47:12 PM PST 24
Peak memory 208020 kb
Host smart-9a0a1d27-b051-44a0-9384-9b6812d10124
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721105415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1721105415
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3641998584
Short name T1008
Test name
Test status
Simulation time 218636225 ps
CPU time 6.63 seconds
Started Jan 24 04:09:52 PM PST 24
Finished Jan 24 04:10:01 PM PST 24
Peak memory 207372 kb
Host smart-51bc1924-a7ea-42a4-a17f-5348c177810c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641998584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3641998584
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.535626998
Short name T411
Test name
Test status
Simulation time 79880034 ps
CPU time 2.32 seconds
Started Jan 24 02:48:15 PM PST 24
Finished Jan 24 02:48:46 PM PST 24
Peak memory 206064 kb
Host smart-5fa48d3d-556f-4023-906c-91e123035693
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535626998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.535626998
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.706456117
Short name T1058
Test name
Test status
Simulation time 80221296 ps
CPU time 3.47 seconds
Started Jan 24 02:48:23 PM PST 24
Finished Jan 24 02:48:52 PM PST 24
Peak memory 207924 kb
Host smart-dee6be16-0d93-40cc-8fcb-8d18fafaaf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706456117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.706456117
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1386094964
Short name T1021
Test name
Test status
Simulation time 955867573 ps
CPU time 6.42 seconds
Started Jan 24 02:48:06 PM PST 24
Finished Jan 24 02:48:42 PM PST 24
Peak memory 205996 kb
Host smart-5299467a-73f7-4cbd-b174-33ff4cde0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386094964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1386094964
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2888181912
Short name T114
Test name
Test status
Simulation time 896449442 ps
CPU time 9.15 seconds
Started Jan 24 02:48:25 PM PST 24
Finished Jan 24 02:49:00 PM PST 24
Peak memory 218364 kb
Host smart-0452c576-403a-41fd-ae57-dd8c3b9f9d9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888181912 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2888181912
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1773518305
Short name T653
Test name
Test status
Simulation time 38366414 ps
CPU time 2.68 seconds
Started Jan 24 02:48:14 PM PST 24
Finished Jan 24 02:48:45 PM PST 24
Peak memory 213592 kb
Host smart-c545aab5-52fa-4348-b309-4741211a2a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773518305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1773518305
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.487167449
Short name T753
Test name
Test status
Simulation time 257567087 ps
CPU time 3.08 seconds
Started Jan 24 03:11:51 PM PST 24
Finished Jan 24 03:12:06 PM PST 24
Peak memory 210100 kb
Host smart-d50f856a-fc5a-4b6a-a57d-56f7f5866f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487167449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.487167449
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.442874502
Short name T733
Test name
Test status
Simulation time 121790257 ps
CPU time 0.75 seconds
Started Jan 24 03:25:51 PM PST 24
Finished Jan 24 03:26:13 PM PST 24
Peak memory 205492 kb
Host smart-84c841ad-87a2-4198-bc39-d90a38e2a94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442874502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.442874502
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1356965574
Short name T410
Test name
Test status
Simulation time 365315491 ps
CPU time 3.71 seconds
Started Jan 24 02:48:31 PM PST 24
Finished Jan 24 02:48:58 PM PST 24
Peak memory 214160 kb
Host smart-58fa03ef-1682-48a4-99d7-a6db594489bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356965574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1356965574
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1019958358
Short name T852
Test name
Test status
Simulation time 42391688 ps
CPU time 2.28 seconds
Started Jan 24 02:48:38 PM PST 24
Finished Jan 24 02:49:00 PM PST 24
Peak memory 207960 kb
Host smart-46f17c56-b2dd-43ed-981c-af5ac7471829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019958358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1019958358
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2122502663
Short name T850
Test name
Test status
Simulation time 443306337 ps
CPU time 3.62 seconds
Started Jan 24 02:48:27 PM PST 24
Finished Jan 24 02:48:56 PM PST 24
Peak memory 217648 kb
Host smart-19eee1f0-884b-4175-a4a2-0e119a41a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122502663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2122502663
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4007891727
Short name T95
Test name
Test status
Simulation time 119874199 ps
CPU time 4.53 seconds
Started Jan 24 03:28:31 PM PST 24
Finished Jan 24 03:28:38 PM PST 24
Peak memory 221972 kb
Host smart-b109c68b-79a1-4411-8921-d612fa877bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007891727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4007891727
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1395851012
Short name T320
Test name
Test status
Simulation time 102395874 ps
CPU time 5.37 seconds
Started Jan 24 02:48:37 PM PST 24
Finished Jan 24 02:49:03 PM PST 24
Peak memory 209408 kb
Host smart-38d7255a-d2cd-4433-b92e-44b2d352da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395851012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1395851012
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3555567908
Short name T966
Test name
Test status
Simulation time 475481402 ps
CPU time 3.2 seconds
Started Jan 24 02:48:28 PM PST 24
Finished Jan 24 02:48:56 PM PST 24
Peak memory 209128 kb
Host smart-516d52ee-a9f3-4318-bf17-12c19d0da938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555567908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3555567908
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1517760200
Short name T724
Test name
Test status
Simulation time 450137563 ps
CPU time 7.56 seconds
Started Jan 24 03:46:35 PM PST 24
Finished Jan 24 03:46:47 PM PST 24
Peak memory 207868 kb
Host smart-d1a32583-059e-4a17-9022-1918f9d83204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517760200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1517760200
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2827516027
Short name T376
Test name
Test status
Simulation time 8120700376 ps
CPU time 41.95 seconds
Started Jan 24 02:48:33 PM PST 24
Finished Jan 24 02:49:38 PM PST 24
Peak memory 207724 kb
Host smart-57dbb0c7-f3fc-48d7-9c59-f67f95010e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827516027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2827516027
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2493805481
Short name T204
Test name
Test status
Simulation time 184426367 ps
CPU time 3.29 seconds
Started Jan 24 02:48:33 PM PST 24
Finished Jan 24 02:48:59 PM PST 24
Peak memory 205912 kb
Host smart-6b89e438-bd65-4786-9cc9-aca6ad71753d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493805481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2493805481
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.477617676
Short name T346
Test name
Test status
Simulation time 210929556 ps
CPU time 3.21 seconds
Started Jan 24 02:48:29 PM PST 24
Finished Jan 24 02:48:57 PM PST 24
Peak memory 207984 kb
Host smart-05786837-25ce-4912-9070-a882faae69c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477617676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.477617676
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.930973674
Short name T979
Test name
Test status
Simulation time 19086430 ps
CPU time 1.71 seconds
Started Jan 24 02:48:33 PM PST 24
Finished Jan 24 02:48:57 PM PST 24
Peak memory 205920 kb
Host smart-20470909-45ed-4377-9736-a7a51e4347b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930973674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.930973674
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1910747175
Short name T1076
Test name
Test status
Simulation time 29659083 ps
CPU time 2.39 seconds
Started Jan 24 02:48:38 PM PST 24
Finished Jan 24 02:49:01 PM PST 24
Peak memory 209212 kb
Host smart-f79230f7-9993-42d7-a0f6-bb774142d3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910747175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1910747175
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3597271307
Short name T389
Test name
Test status
Simulation time 142509374 ps
CPU time 2.31 seconds
Started Jan 24 04:01:19 PM PST 24
Finished Jan 24 04:01:23 PM PST 24
Peak memory 206084 kb
Host smart-c384ff5f-3954-4f16-91b5-39f9428e156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597271307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3597271307
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4174410288
Short name T275
Test name
Test status
Simulation time 321173481 ps
CPU time 11.58 seconds
Started Jan 24 02:48:34 PM PST 24
Finished Jan 24 02:49:07 PM PST 24
Peak memory 215372 kb
Host smart-807a3639-908d-4f5a-9bfc-6bc04754b7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174410288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4174410288
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1561148869
Short name T890
Test name
Test status
Simulation time 201321246 ps
CPU time 5.01 seconds
Started Jan 24 02:48:34 PM PST 24
Finished Jan 24 02:49:01 PM PST 24
Peak memory 219144 kb
Host smart-f2af7755-a4f8-41d2-8bcb-be1f943d5dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561148869 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1561148869
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.401471881
Short name T594
Test name
Test status
Simulation time 773914611 ps
CPU time 5.75 seconds
Started Jan 24 02:48:35 PM PST 24
Finished Jan 24 02:49:02 PM PST 24
Peak memory 207372 kb
Host smart-b631307f-2080-40bf-9679-1accace2e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401471881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.401471881
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.831755558
Short name T775
Test name
Test status
Simulation time 100924960 ps
CPU time 2.4 seconds
Started Jan 24 02:48:39 PM PST 24
Finished Jan 24 02:49:01 PM PST 24
Peak memory 209264 kb
Host smart-3f7f22f3-390c-4377-bb16-62d988fc9f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831755558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.831755558
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4227930202
Short name T1003
Test name
Test status
Simulation time 104205571 ps
CPU time 0.86 seconds
Started Jan 24 02:48:52 PM PST 24
Finished Jan 24 02:49:13 PM PST 24
Peak memory 205460 kb
Host smart-c96c7c76-0285-49b5-b073-1a8ef5802475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227930202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4227930202
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2401419446
Short name T236
Test name
Test status
Simulation time 1625849761 ps
CPU time 38.16 seconds
Started Jan 24 02:48:49 PM PST 24
Finished Jan 24 02:49:46 PM PST 24
Peak memory 213768 kb
Host smart-cf10ecec-b54a-4b45-add7-f3f49aeeeec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401419446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2401419446
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4025797508
Short name T893
Test name
Test status
Simulation time 385299109 ps
CPU time 7.47 seconds
Started Jan 24 02:48:46 PM PST 24
Finished Jan 24 02:49:14 PM PST 24
Peak memory 207700 kb
Host smart-64441d34-1000-4e19-b7bb-bb9841afca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025797508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4025797508
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2224705036
Short name T968
Test name
Test status
Simulation time 72433575 ps
CPU time 2.91 seconds
Started Jan 24 02:48:45 PM PST 24
Finished Jan 24 02:49:08 PM PST 24
Peak memory 219704 kb
Host smart-de4f0258-251f-4525-8733-c2f725dd3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224705036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2224705036
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3626161364
Short name T669
Test name
Test status
Simulation time 248898094 ps
CPU time 4.61 seconds
Started Jan 24 02:48:48 PM PST 24
Finished Jan 24 02:49:13 PM PST 24
Peak memory 208092 kb
Host smart-225c90ed-3f80-47ae-918f-357db84c8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626161364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3626161364
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1783417580
Short name T995
Test name
Test status
Simulation time 1557659649 ps
CPU time 39.41 seconds
Started Jan 24 02:48:48 PM PST 24
Finished Jan 24 02:49:47 PM PST 24
Peak memory 207932 kb
Host smart-aede94a2-46b8-4939-80aa-532a05ecc8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783417580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1783417580
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4225777671
Short name T1038
Test name
Test status
Simulation time 456369692 ps
CPU time 5.68 seconds
Started Jan 24 02:48:45 PM PST 24
Finished Jan 24 02:49:11 PM PST 24
Peak memory 208096 kb
Host smart-5f87a8d0-c72c-4229-bd64-d5c8e6504b7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225777671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4225777671
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3860157890
Short name T646
Test name
Test status
Simulation time 463281827 ps
CPU time 3.88 seconds
Started Jan 24 02:48:44 PM PST 24
Finished Jan 24 02:49:08 PM PST 24
Peak memory 205992 kb
Host smart-8e859d5e-b86f-4d54-9b47-92a5a9613aac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860157890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3860157890
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1638457575
Short name T1044
Test name
Test status
Simulation time 66773881 ps
CPU time 3.34 seconds
Started Jan 24 02:48:45 PM PST 24
Finished Jan 24 02:49:08 PM PST 24
Peak memory 206128 kb
Host smart-35851129-80fe-49b6-8edf-689b807c3413
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638457575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1638457575
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2480719162
Short name T1031
Test name
Test status
Simulation time 1325784874 ps
CPU time 5.34 seconds
Started Jan 24 02:48:48 PM PST 24
Finished Jan 24 02:49:13 PM PST 24
Peak memory 209340 kb
Host smart-7a7f81be-6cba-4b1e-a40f-d9a8c423393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480719162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2480719162
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.163667145
Short name T699
Test name
Test status
Simulation time 1919703328 ps
CPU time 19.32 seconds
Started Jan 24 02:48:43 PM PST 24
Finished Jan 24 02:49:23 PM PST 24
Peak memory 207256 kb
Host smart-5924b9a6-a9ca-4bad-9697-85c74c8f360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163667145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.163667145
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1014043647
Short name T252
Test name
Test status
Simulation time 507041360 ps
CPU time 22.39 seconds
Started Jan 24 02:57:46 PM PST 24
Finished Jan 24 02:58:13 PM PST 24
Peak memory 214272 kb
Host smart-c0991ac2-9d6a-47de-ac78-7c03fdc4179d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014043647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1014043647
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1952539539
Short name T246
Test name
Test status
Simulation time 394928687 ps
CPU time 25.48 seconds
Started Jan 24 02:56:35 PM PST 24
Finished Jan 24 02:57:02 PM PST 24
Peak memory 220400 kb
Host smart-f73a4d1f-e552-4938-8522-76df9fa6dc09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952539539 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1952539539
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3218157314
Short name T338
Test name
Test status
Simulation time 107214425 ps
CPU time 3.19 seconds
Started Jan 24 02:48:44 PM PST 24
Finished Jan 24 02:49:07 PM PST 24
Peak memory 207372 kb
Host smart-b32a0d93-1013-4e2a-b481-7512bd457a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218157314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3218157314
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4271932175
Short name T739
Test name
Test status
Simulation time 124318444 ps
CPU time 1.79 seconds
Started Jan 24 02:48:55 PM PST 24
Finished Jan 24 02:49:15 PM PST 24
Peak memory 208972 kb
Host smart-09722126-9fe9-449f-979e-7b0f9c32f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271932175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4271932175
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3487531148
Short name T938
Test name
Test status
Simulation time 10085038 ps
CPU time 0.76 seconds
Started Jan 24 02:48:59 PM PST 24
Finished Jan 24 02:49:18 PM PST 24
Peak memory 205468 kb
Host smart-3a182e7c-959f-4abd-8e5c-7756357d04b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487531148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3487531148
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.275671437
Short name T695
Test name
Test status
Simulation time 134352076 ps
CPU time 3 seconds
Started Jan 24 02:49:05 PM PST 24
Finished Jan 24 02:49:24 PM PST 24
Peak memory 209584 kb
Host smart-9efdce39-7eb1-4380-a19f-2d5e6351ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275671437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.275671437
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3662547987
Short name T1016
Test name
Test status
Simulation time 534804406 ps
CPU time 2.86 seconds
Started Jan 24 02:49:00 PM PST 24
Finished Jan 24 02:49:21 PM PST 24
Peak memory 206940 kb
Host smart-21976ce5-6beb-42a1-a5a7-708d8a5b0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662547987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3662547987
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3843838656
Short name T83
Test name
Test status
Simulation time 64902245 ps
CPU time 3.48 seconds
Started Jan 24 02:49:05 PM PST 24
Finished Jan 24 02:49:24 PM PST 24
Peak memory 217796 kb
Host smart-18604233-8507-4e10-a24b-a798fb386bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843838656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3843838656
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2960075222
Short name T390
Test name
Test status
Simulation time 408353330 ps
CPU time 4.82 seconds
Started Jan 24 02:49:01 PM PST 24
Finished Jan 24 02:49:23 PM PST 24
Peak memory 213832 kb
Host smart-bd737e92-0ffc-4d96-a02e-11da4b15975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960075222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2960075222
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1817949708
Short name T906
Test name
Test status
Simulation time 307227651 ps
CPU time 8.95 seconds
Started Jan 24 02:48:59 PM PST 24
Finished Jan 24 02:49:25 PM PST 24
Peak memory 207144 kb
Host smart-25032df9-9349-42a1-b068-c19210ea128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817949708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1817949708
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1612716034
Short name T709
Test name
Test status
Simulation time 568624693 ps
CPU time 4.86 seconds
Started Jan 24 02:48:56 PM PST 24
Finished Jan 24 02:49:19 PM PST 24
Peak memory 207884 kb
Host smart-de31ae47-032f-49d0-8465-660a36caca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612716034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1612716034
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.495890634
Short name T665
Test name
Test status
Simulation time 264290104 ps
CPU time 6.63 seconds
Started Jan 24 02:48:52 PM PST 24
Finished Jan 24 02:49:18 PM PST 24
Peak memory 207896 kb
Host smart-b8bb42dc-454c-4bff-9423-3aac82a16eaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495890634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.495890634
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.139293107
Short name T323
Test name
Test status
Simulation time 184222847 ps
CPU time 6.14 seconds
Started Jan 24 02:48:56 PM PST 24
Finished Jan 24 02:49:21 PM PST 24
Peak memory 207960 kb
Host smart-4dabef67-d0cb-431b-99af-cce7eb17b639
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139293107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.139293107
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1290153419
Short name T894
Test name
Test status
Simulation time 99246944 ps
CPU time 2.1 seconds
Started Jan 24 02:49:01 PM PST 24
Finished Jan 24 02:49:20 PM PST 24
Peak memory 207300 kb
Host smart-d2712ab2-88d1-4f2b-b545-145ede2799b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290153419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1290153419
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3461154742
Short name T670
Test name
Test status
Simulation time 226339836 ps
CPU time 2.99 seconds
Started Jan 24 02:48:56 PM PST 24
Finished Jan 24 02:49:18 PM PST 24
Peak memory 206012 kb
Host smart-37b91a00-0189-480d-bc4e-a34358eae05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461154742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3461154742
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.751965026
Short name T766
Test name
Test status
Simulation time 3743087649 ps
CPU time 23.01 seconds
Started Jan 24 02:49:05 PM PST 24
Finished Jan 24 02:49:44 PM PST 24
Peak memory 207060 kb
Host smart-c702e0c4-6eb2-4fd6-92c9-298fd7f4c634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751965026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.751965026
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1156491237
Short name T953
Test name
Test status
Simulation time 65349248 ps
CPU time 4.14 seconds
Started Jan 24 02:48:59 PM PST 24
Finished Jan 24 02:49:21 PM PST 24
Peak memory 222248 kb
Host smart-76fea7f5-f744-46b0-826f-b5021354cce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156491237 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1156491237
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2174880398
Short name T964
Test name
Test status
Simulation time 621793090 ps
CPU time 11.46 seconds
Started Jan 24 02:49:02 PM PST 24
Finished Jan 24 02:49:30 PM PST 24
Peak memory 207472 kb
Host smart-f9a1bdc5-39b5-4beb-a3d9-e643ef9d9032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174880398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2174880398
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4264057180
Short name T736
Test name
Test status
Simulation time 23582830 ps
CPU time 0.81 seconds
Started Jan 24 02:49:22 PM PST 24
Finished Jan 24 02:49:35 PM PST 24
Peak memory 205496 kb
Host smart-bce56584-0a40-485c-b6ef-7fba92cec5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264057180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4264057180
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1619690963
Short name T272
Test name
Test status
Simulation time 170432685 ps
CPU time 9.56 seconds
Started Jan 24 02:49:11 PM PST 24
Finished Jan 24 02:49:36 PM PST 24
Peak memory 214800 kb
Host smart-861b6027-65b1-46b1-8bc6-a3a440f3e8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619690963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1619690963
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2590976131
Short name T1041
Test name
Test status
Simulation time 46998707 ps
CPU time 3.22 seconds
Started Jan 24 02:49:26 PM PST 24
Finished Jan 24 02:49:41 PM PST 24
Peak memory 209380 kb
Host smart-d27c32da-f9fa-488a-a483-f5ac0c7c20e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590976131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2590976131
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3920807491
Short name T57
Test name
Test status
Simulation time 2791997935 ps
CPU time 31.11 seconds
Started Jan 24 02:49:10 PM PST 24
Finished Jan 24 02:49:56 PM PST 24
Peak memory 213968 kb
Host smart-523bf7bf-5b8b-463d-9689-42e85ada2c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920807491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3920807491
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2857991112
Short name T355
Test name
Test status
Simulation time 602436042 ps
CPU time 8.04 seconds
Started Jan 24 02:49:12 PM PST 24
Finished Jan 24 02:49:35 PM PST 24
Peak memory 208356 kb
Host smart-70b99fe0-2b76-482b-8d52-3d538a81b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857991112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2857991112
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3726621995
Short name T102
Test name
Test status
Simulation time 1211773394 ps
CPU time 4.17 seconds
Started Jan 24 02:49:22 PM PST 24
Finished Jan 24 02:49:39 PM PST 24
Peak memory 221940 kb
Host smart-6ce2bf5e-9bc7-40bd-b926-74e40c9243a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726621995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3726621995
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2317681302
Short name T626
Test name
Test status
Simulation time 292433353 ps
CPU time 3.69 seconds
Started Jan 24 02:49:09 PM PST 24
Finished Jan 24 02:49:28 PM PST 24
Peak memory 208732 kb
Host smart-6a33559a-67a3-4193-aae7-389ec216e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317681302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2317681302
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1760568218
Short name T810
Test name
Test status
Simulation time 45806301 ps
CPU time 3.03 seconds
Started Jan 24 02:54:27 PM PST 24
Finished Jan 24 02:54:52 PM PST 24
Peak memory 206552 kb
Host smart-456a4a9a-10df-4b17-8423-24951b5d5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760568218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1760568218
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1522195501
Short name T835
Test name
Test status
Simulation time 205238615 ps
CPU time 4.77 seconds
Started Jan 24 02:49:01 PM PST 24
Finished Jan 24 02:49:23 PM PST 24
Peak memory 205980 kb
Host smart-cfe36076-ced9-4aa2-8460-2f8351bb0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522195501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1522195501
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3789064185
Short name T599
Test name
Test status
Simulation time 377091270 ps
CPU time 3.51 seconds
Started Jan 24 02:49:10 PM PST 24
Finished Jan 24 02:49:29 PM PST 24
Peak memory 207776 kb
Host smart-af2e7725-aaf2-448f-a06d-78afe7300429
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789064185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3789064185
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1253696988
Short name T738
Test name
Test status
Simulation time 48940590 ps
CPU time 2.74 seconds
Started Jan 24 02:49:11 PM PST 24
Finished Jan 24 02:49:29 PM PST 24
Peak memory 206124 kb
Host smart-ce635863-7094-4ce6-89e4-a057aa21b865
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253696988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1253696988
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.629962899
Short name T858
Test name
Test status
Simulation time 638389539 ps
CPU time 7.65 seconds
Started Jan 24 02:49:10 PM PST 24
Finished Jan 24 02:49:33 PM PST 24
Peak memory 207160 kb
Host smart-36f5b34f-1922-4e7a-af2c-35ebc579f0c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629962899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.629962899
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4203904260
Short name T590
Test name
Test status
Simulation time 73068170 ps
CPU time 2.79 seconds
Started Jan 24 02:49:19 PM PST 24
Finished Jan 24 02:49:35 PM PST 24
Peak memory 208372 kb
Host smart-a02b03da-a110-4363-9a37-3c6ec7fc86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203904260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4203904260
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1588225052
Short name T191
Test name
Test status
Simulation time 216279863 ps
CPU time 3.26 seconds
Started Jan 24 02:49:05 PM PST 24
Finished Jan 24 02:49:25 PM PST 24
Peak memory 207600 kb
Host smart-f318dcc0-76d3-4984-bb3d-89c2f11366c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588225052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1588225052
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3659271771
Short name T614
Test name
Test status
Simulation time 393162318 ps
CPU time 4.75 seconds
Started Jan 24 04:16:46 PM PST 24
Finished Jan 24 04:16:52 PM PST 24
Peak memory 208992 kb
Host smart-10713638-fc92-4240-902e-6feb1ae7fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659271771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3659271771
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2451338703
Short name T1074
Test name
Test status
Simulation time 110162937 ps
CPU time 2.31 seconds
Started Jan 24 02:49:22 PM PST 24
Finished Jan 24 02:49:37 PM PST 24
Peak memory 209488 kb
Host smart-b608a170-53f1-4f27-8a98-e64e206ded50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451338703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2451338703
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1593090801
Short name T603
Test name
Test status
Simulation time 16479611 ps
CPU time 0.77 seconds
Started Jan 24 02:49:37 PM PST 24
Finished Jan 24 02:49:55 PM PST 24
Peak memory 205468 kb
Host smart-653479f3-e842-4495-bf86-836fc8c705b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593090801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1593090801
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1177906409
Short name T1007
Test name
Test status
Simulation time 378786039 ps
CPU time 7.67 seconds
Started Jan 24 02:49:31 PM PST 24
Finished Jan 24 02:49:53 PM PST 24
Peak memory 209304 kb
Host smart-a53c1fdf-6139-4696-a025-d3256be5fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177906409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1177906409
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2212545510
Short name T872
Test name
Test status
Simulation time 406920092 ps
CPU time 4.19 seconds
Started Jan 24 02:49:30 PM PST 24
Finished Jan 24 02:49:49 PM PST 24
Peak memory 213776 kb
Host smart-c34c0a7c-2a52-4c4f-b39e-a39e548e9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212545510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2212545510
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1648159475
Short name T1070
Test name
Test status
Simulation time 347111529 ps
CPU time 5.86 seconds
Started Jan 24 02:49:37 PM PST 24
Finished Jan 24 02:50:01 PM PST 24
Peak memory 210328 kb
Host smart-3768b357-edf3-40c9-880a-f7e191b6a923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648159475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1648159475
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2906859160
Short name T216
Test name
Test status
Simulation time 119723706 ps
CPU time 3.54 seconds
Started Jan 24 02:49:34 PM PST 24
Finished Jan 24 02:49:54 PM PST 24
Peak memory 208524 kb
Host smart-f871fa1e-ff38-4062-be2f-9b775bc69e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906859160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2906859160
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2884444013
Short name T1054
Test name
Test status
Simulation time 881454869 ps
CPU time 5.44 seconds
Started Jan 24 02:49:32 PM PST 24
Finished Jan 24 02:49:52 PM PST 24
Peak memory 208328 kb
Host smart-95eaa202-f757-438f-aaa9-7ee12839c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884444013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2884444013
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1864821819
Short name T882
Test name
Test status
Simulation time 39117819 ps
CPU time 1.79 seconds
Started Jan 24 02:49:23 PM PST 24
Finished Jan 24 02:49:37 PM PST 24
Peak memory 206040 kb
Host smart-1a9b3730-adc8-4b2d-96c5-29b11a7634ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864821819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1864821819
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2565427684
Short name T1027
Test name
Test status
Simulation time 97980336 ps
CPU time 3.35 seconds
Started Jan 24 02:49:31 PM PST 24
Finished Jan 24 02:49:49 PM PST 24
Peak memory 207028 kb
Host smart-2a2427e4-c84d-4125-bf5d-17474f3bc6fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565427684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2565427684
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.4002888040
Short name T863
Test name
Test status
Simulation time 52573085 ps
CPU time 2.99 seconds
Started Jan 24 02:49:37 PM PST 24
Finished Jan 24 02:49:58 PM PST 24
Peak memory 206204 kb
Host smart-5e57884e-668b-43eb-a83f-148c7f62b598
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002888040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.4002888040
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1997441969
Short name T802
Test name
Test status
Simulation time 62066867 ps
CPU time 3.24 seconds
Started Jan 24 02:49:33 PM PST 24
Finished Jan 24 02:49:53 PM PST 24
Peak memory 206016 kb
Host smart-4d72e33f-7400-47be-8dc7-b790c49469ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997441969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1997441969
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1036071094
Short name T844
Test name
Test status
Simulation time 39465646 ps
CPU time 2.48 seconds
Started Jan 24 04:28:05 PM PST 24
Finished Jan 24 04:28:14 PM PST 24
Peak memory 209016 kb
Host smart-167b0f27-de74-4c45-9789-94e15087291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036071094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1036071094
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3319982571
Short name T384
Test name
Test status
Simulation time 254047245 ps
CPU time 6.22 seconds
Started Jan 24 02:49:25 PM PST 24
Finished Jan 24 02:49:44 PM PST 24
Peak memory 207740 kb
Host smart-f61a1877-1a0b-4413-bacd-e1f31c2b9b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319982571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3319982571
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2698361699
Short name T777
Test name
Test status
Simulation time 2075744873 ps
CPU time 46.4 seconds
Started Jan 24 02:49:31 PM PST 24
Finished Jan 24 02:50:32 PM PST 24
Peak memory 220612 kb
Host smart-f1e0989a-4f97-4d6a-9c09-48510bfa3b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698361699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2698361699
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2475655890
Short name T42
Test name
Test status
Simulation time 232423313 ps
CPU time 4.12 seconds
Started Jan 24 04:09:48 PM PST 24
Finished Jan 24 04:09:53 PM PST 24
Peak memory 222180 kb
Host smart-ff0ae9a5-c83f-4d93-83f4-44d006f9a283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475655890 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2475655890
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3773933643
Short name T853
Test name
Test status
Simulation time 112689163 ps
CPU time 4.54 seconds
Started Jan 24 02:49:40 PM PST 24
Finished Jan 24 02:50:01 PM PST 24
Peak memory 206504 kb
Host smart-34af70e9-7c2b-40f3-b641-6a7ffbf7fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773933643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3773933643
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1684794294
Short name T154
Test name
Test status
Simulation time 44599389 ps
CPU time 1.5 seconds
Started Jan 24 02:49:32 PM PST 24
Finished Jan 24 02:49:49 PM PST 24
Peak memory 208776 kb
Host smart-4ac8bbe8-99b8-47be-be02-c9e18599737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684794294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1684794294
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3559939899
Short name T645
Test name
Test status
Simulation time 19090722 ps
CPU time 1.01 seconds
Started Jan 24 02:49:53 PM PST 24
Finished Jan 24 02:50:17 PM PST 24
Peak memory 205452 kb
Host smart-3563ec47-ac5b-48c9-ad39-eb7d3fa20ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559939899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3559939899
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3575936889
Short name T175
Test name
Test status
Simulation time 158153562 ps
CPU time 7.91 seconds
Started Jan 24 04:32:02 PM PST 24
Finished Jan 24 04:32:10 PM PST 24
Peak memory 217196 kb
Host smart-ceadc5ad-e912-4ab4-b271-441659f15ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575936889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3575936889
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3348293192
Short name T841
Test name
Test status
Simulation time 9216368087 ps
CPU time 12.4 seconds
Started Jan 24 03:33:47 PM PST 24
Finished Jan 24 03:34:03 PM PST 24
Peak memory 207468 kb
Host smart-a77572ac-0a49-4d33-931d-6b578cfc6a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348293192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3348293192
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.830821797
Short name T1009
Test name
Test status
Simulation time 569363610 ps
CPU time 7.73 seconds
Started Jan 24 03:54:12 PM PST 24
Finished Jan 24 03:54:29 PM PST 24
Peak memory 213800 kb
Host smart-c4a00c7e-3b85-43c7-ae31-67dcfb98de9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830821797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.830821797
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.931016598
Short name T190
Test name
Test status
Simulation time 244096384 ps
CPU time 4.4 seconds
Started Jan 24 02:49:53 PM PST 24
Finished Jan 24 02:50:20 PM PST 24
Peak memory 213668 kb
Host smart-967b559d-6e7d-4af1-add8-dbaa76a538d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931016598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.931016598
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2812400193
Short name T780
Test name
Test status
Simulation time 409830776 ps
CPU time 4.86 seconds
Started Jan 24 04:18:44 PM PST 24
Finished Jan 24 04:18:50 PM PST 24
Peak memory 207992 kb
Host smart-40fb712d-b12e-4d40-b71d-f1eb771c694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812400193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2812400193
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1999643075
Short name T809
Test name
Test status
Simulation time 670263860 ps
CPU time 13.55 seconds
Started Jan 24 02:49:44 PM PST 24
Finished Jan 24 02:50:16 PM PST 24
Peak memory 208064 kb
Host smart-f80e57f9-6506-45d2-81ce-72d8e0186d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999643075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1999643075
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2556333087
Short name T984
Test name
Test status
Simulation time 1782642123 ps
CPU time 18.6 seconds
Started Jan 24 02:49:33 PM PST 24
Finished Jan 24 02:50:08 PM PST 24
Peak memory 208012 kb
Host smart-86f4fdcd-198e-444c-8954-515c4e44d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556333087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2556333087
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2688353551
Short name T379
Test name
Test status
Simulation time 53378146 ps
CPU time 2.92 seconds
Started Jan 24 02:49:48 PM PST 24
Finished Jan 24 02:50:12 PM PST 24
Peak memory 205984 kb
Host smart-f839ba69-8035-4704-8471-21e61d02e266
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688353551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2688353551
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2756712432
Short name T314
Test name
Test status
Simulation time 263137807 ps
CPU time 6.5 seconds
Started Jan 24 02:49:43 PM PST 24
Finished Jan 24 02:50:07 PM PST 24
Peak memory 207628 kb
Host smart-efcfea14-ed6c-48bf-98bd-59121abefbe9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756712432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2756712432
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.831165764
Short name T855
Test name
Test status
Simulation time 329454389 ps
CPU time 3.93 seconds
Started Jan 24 03:23:36 PM PST 24
Finished Jan 24 03:23:43 PM PST 24
Peak memory 208224 kb
Host smart-ea3d1e91-a584-4f8c-a1fa-85ccc0ccd5f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831165764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.831165764
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3870995817
Short name T660
Test name
Test status
Simulation time 110377318 ps
CPU time 2.34 seconds
Started Jan 24 03:51:46 PM PST 24
Finished Jan 24 03:51:51 PM PST 24
Peak memory 214732 kb
Host smart-fff96f74-1af6-4a73-9114-5ee79f49ff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870995817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3870995817
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.926503176
Short name T578
Test name
Test status
Simulation time 304993484 ps
CPU time 2.1 seconds
Started Jan 24 02:49:37 PM PST 24
Finished Jan 24 02:49:57 PM PST 24
Peak memory 207772 kb
Host smart-a96e7924-eb09-4e82-9624-bc267f378694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926503176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.926503176
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1970245942
Short name T789
Test name
Test status
Simulation time 79930460 ps
CPU time 2.93 seconds
Started Jan 24 02:49:49 PM PST 24
Finished Jan 24 02:50:13 PM PST 24
Peak memory 222092 kb
Host smart-7edd0a90-2a50-49f6-bc26-2c2cda22a08d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970245942 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1970245942
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3690628704
Short name T598
Test name
Test status
Simulation time 482864900 ps
CPU time 13.31 seconds
Started Jan 24 02:49:49 PM PST 24
Finished Jan 24 02:50:24 PM PST 24
Peak memory 213720 kb
Host smart-e80639e9-f5bc-4338-ae2e-29cbcb8f7e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690628704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3690628704
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1829064652
Short name T823
Test name
Test status
Simulation time 539511606 ps
CPU time 1.96 seconds
Started Jan 24 06:42:35 PM PST 24
Finished Jan 24 06:42:38 PM PST 24
Peak memory 209308 kb
Host smart-9486cfd6-d461-4a30-acd9-2a5681a6349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829064652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1829064652
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2664876434
Short name T763
Test name
Test status
Simulation time 13804931 ps
CPU time 0.72 seconds
Started Jan 24 02:50:03 PM PST 24
Finished Jan 24 02:50:24 PM PST 24
Peak memory 205496 kb
Host smart-5fef39c8-6212-4231-b1d7-d8d945dc84e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664876434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2664876434
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.166869680
Short name T1082
Test name
Test status
Simulation time 57628941 ps
CPU time 2.36 seconds
Started Jan 24 02:49:53 PM PST 24
Finished Jan 24 02:50:18 PM PST 24
Peak memory 214120 kb
Host smart-3c2793ee-d52f-42b8-9497-eb2911dcffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166869680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.166869680
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3588144431
Short name T803
Test name
Test status
Simulation time 79782312 ps
CPU time 3.21 seconds
Started Jan 24 02:49:53 PM PST 24
Finished Jan 24 02:50:19 PM PST 24
Peak memory 217716 kb
Host smart-158147c3-a218-41bf-9f7f-1d62356e37ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588144431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3588144431
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3009318994
Short name T345
Test name
Test status
Simulation time 133166524 ps
CPU time 5.53 seconds
Started Jan 24 03:12:48 PM PST 24
Finished Jan 24 03:13:04 PM PST 24
Peak memory 219956 kb
Host smart-763e0a7b-0304-4d5b-9bcb-3034df82248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009318994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3009318994
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1893552552
Short name T97
Test name
Test status
Simulation time 660951404 ps
CPU time 8.4 seconds
Started Jan 24 02:49:54 PM PST 24
Finished Jan 24 02:50:24 PM PST 24
Peak memory 221764 kb
Host smart-4fd54010-f4b9-4a0e-9835-dd5cdcf96c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893552552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1893552552
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1129480945
Short name T1057
Test name
Test status
Simulation time 203258490 ps
CPU time 3.71 seconds
Started Jan 24 02:49:49 PM PST 24
Finished Jan 24 02:50:14 PM PST 24
Peak memory 209148 kb
Host smart-347ad4ff-c6f4-4c9b-83b4-df7695058ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129480945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1129480945
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.600063534
Short name T759
Test name
Test status
Simulation time 5015630587 ps
CPU time 36.24 seconds
Started Jan 24 03:17:53 PM PST 24
Finished Jan 24 03:18:32 PM PST 24
Peak memory 209572 kb
Host smart-bece445f-cf06-4d5d-b5dc-a339324afaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600063534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.600063534
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3938451202
Short name T72
Test name
Test status
Simulation time 60858950 ps
CPU time 2.61 seconds
Started Jan 24 02:49:50 PM PST 24
Finished Jan 24 02:50:14 PM PST 24
Peak memory 206164 kb
Host smart-ee84391b-6cfd-41b5-bbd2-39722cc0fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938451202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3938451202
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.760187156
Short name T730
Test name
Test status
Simulation time 14587977664 ps
CPU time 43.55 seconds
Started Jan 24 02:49:50 PM PST 24
Finished Jan 24 02:50:55 PM PST 24
Peak memory 207872 kb
Host smart-56c45117-85b7-4562-8286-651b2a265e7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760187156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.760187156
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2122127071
Short name T908
Test name
Test status
Simulation time 4240650571 ps
CPU time 31.15 seconds
Started Jan 24 02:49:49 PM PST 24
Finished Jan 24 02:50:42 PM PST 24
Peak memory 207716 kb
Host smart-e824a194-a086-4ab7-af38-c34db8d019f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122127071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2122127071
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.612952706
Short name T931
Test name
Test status
Simulation time 490772325 ps
CPU time 5.88 seconds
Started Jan 24 02:49:48 PM PST 24
Finished Jan 24 02:50:15 PM PST 24
Peak memory 208188 kb
Host smart-a576bd26-3f53-4cc3-a994-7d5d6321f347
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612952706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.612952706
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1767897913
Short name T829
Test name
Test status
Simulation time 59104782 ps
CPU time 2.82 seconds
Started Jan 24 03:02:41 PM PST 24
Finished Jan 24 03:02:50 PM PST 24
Peak memory 207948 kb
Host smart-786ad960-e567-4535-bf81-23d6a18736f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767897913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1767897913
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.362099419
Short name T574
Test name
Test status
Simulation time 239533388 ps
CPU time 2.66 seconds
Started Jan 24 02:49:54 PM PST 24
Finished Jan 24 02:50:19 PM PST 24
Peak memory 206028 kb
Host smart-f1bc8108-bba0-4e1e-b803-17478315d3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362099419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.362099419
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1496692820
Short name T1072
Test name
Test status
Simulation time 416795459 ps
CPU time 10.84 seconds
Started Jan 24 02:49:57 PM PST 24
Finished Jan 24 02:50:30 PM PST 24
Peak memory 215712 kb
Host smart-ec2b0193-6de0-4f0f-9d95-b0849da6ee6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496692820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1496692820
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.4155807766
Short name T210
Test name
Test status
Simulation time 74972335 ps
CPU time 5.56 seconds
Started Jan 24 02:49:59 PM PST 24
Finished Jan 24 02:50:27 PM PST 24
Peak memory 218736 kb
Host smart-995a55be-0d0a-4d91-a7f2-7cb3aa0afe5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155807766 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.4155807766
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2961593920
Short name T680
Test name
Test status
Simulation time 9051966725 ps
CPU time 90.08 seconds
Started Jan 24 02:49:48 PM PST 24
Finished Jan 24 02:51:39 PM PST 24
Peak memory 218048 kb
Host smart-abc2f611-a077-45a0-b3fa-01ca99ec9ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961593920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2961593920
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.23271950
Short name T14
Test name
Test status
Simulation time 537150677 ps
CPU time 10.98 seconds
Started Jan 24 02:50:06 PM PST 24
Finished Jan 24 02:50:35 PM PST 24
Peak memory 209764 kb
Host smart-6834b018-ad78-49dd-b5ec-7fd6ae37dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23271950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.23271950
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2567867858
Short name T934
Test name
Test status
Simulation time 23329437 ps
CPU time 0.85 seconds
Started Jan 24 02:50:17 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 205388 kb
Host smart-93312931-a2d0-483a-b076-1a8e52261836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567867858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2567867858
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2191505431
Short name T27
Test name
Test status
Simulation time 194877730 ps
CPU time 8.19 seconds
Started Jan 24 02:50:09 PM PST 24
Finished Jan 24 02:50:33 PM PST 24
Peak memory 216292 kb
Host smart-ebe7e5d0-e9cd-4604-99f1-98de1768ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191505431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2191505431
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2989555625
Short name T673
Test name
Test status
Simulation time 127112676 ps
CPU time 1.98 seconds
Started Jan 24 02:49:57 PM PST 24
Finished Jan 24 02:50:22 PM PST 24
Peak memory 208104 kb
Host smart-bc518ac0-0bdd-4211-8df2-c4d36c0f80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989555625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2989555625
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2686436520
Short name T279
Test name
Test status
Simulation time 176340403 ps
CPU time 6.11 seconds
Started Jan 24 02:50:09 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 210276 kb
Host smart-5057b9b2-3c1a-49ae-a337-a00fdb1215cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686436520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2686436520
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.3013035723
Short name T77
Test name
Test status
Simulation time 385225461 ps
CPU time 4.46 seconds
Started Jan 24 02:49:59 PM PST 24
Finished Jan 24 02:50:26 PM PST 24
Peak memory 206648 kb
Host smart-2b97e7ae-40b6-4aff-9d54-db6869c64367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013035723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3013035723
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3013699352
Short name T363
Test name
Test status
Simulation time 44333313 ps
CPU time 1.92 seconds
Started Jan 24 02:50:01 PM PST 24
Finished Jan 24 02:50:24 PM PST 24
Peak memory 205928 kb
Host smart-5f9a2f7a-c06a-4fbf-8e63-041ca21f37b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013699352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3013699352
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.142932180
Short name T922
Test name
Test status
Simulation time 544457911 ps
CPU time 6.3 seconds
Started Jan 24 03:46:42 PM PST 24
Finished Jan 24 03:46:51 PM PST 24
Peak memory 207860 kb
Host smart-e22c7b5f-05ad-4438-87c2-cf617885dafb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142932180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.142932180
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.19424862
Short name T769
Test name
Test status
Simulation time 614374937 ps
CPU time 4.42 seconds
Started Jan 24 02:50:00 PM PST 24
Finished Jan 24 02:50:27 PM PST 24
Peak memory 208336 kb
Host smart-2d7d2c06-4daa-49b5-a73e-a38b23d5ef7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19424862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.19424862
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.988259489
Short name T824
Test name
Test status
Simulation time 239366511 ps
CPU time 2.62 seconds
Started Jan 24 02:50:01 PM PST 24
Finished Jan 24 02:50:25 PM PST 24
Peak memory 208088 kb
Host smart-7191faa4-d19d-498c-9753-f603edf321d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988259489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.988259489
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4230643105
Short name T1036
Test name
Test status
Simulation time 178351558 ps
CPU time 4.82 seconds
Started Jan 24 02:50:05 PM PST 24
Finished Jan 24 02:50:28 PM PST 24
Peak memory 208988 kb
Host smart-670a2b84-385b-4140-8335-fb5184deeda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230643105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4230643105
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.978042509
Short name T935
Test name
Test status
Simulation time 57698954 ps
CPU time 2.4 seconds
Started Jan 24 02:49:59 PM PST 24
Finished Jan 24 02:50:24 PM PST 24
Peak memory 207448 kb
Host smart-aaa8a281-8312-4081-abdf-1cb6842466dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978042509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.978042509
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3759143545
Short name T231
Test name
Test status
Simulation time 3260485167 ps
CPU time 37.2 seconds
Started Jan 24 02:50:08 PM PST 24
Finished Jan 24 02:51:01 PM PST 24
Peak memory 216012 kb
Host smart-23cb4b31-38f6-435f-9bd9-fd79e3f2911e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759143545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3759143545
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.136708024
Short name T825
Test name
Test status
Simulation time 860746240 ps
CPU time 8.16 seconds
Started Jan 24 02:50:12 PM PST 24
Finished Jan 24 02:50:35 PM PST 24
Peak memory 219000 kb
Host smart-f1a5c049-34f4-447e-9302-3965953e6479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136708024 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.136708024
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2682392108
Short name T982
Test name
Test status
Simulation time 88743311 ps
CPU time 4.11 seconds
Started Jan 24 02:50:12 PM PST 24
Finished Jan 24 02:50:30 PM PST 24
Peak memory 209252 kb
Host smart-f186e7eb-6657-4daf-90da-5b1e7dcedab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682392108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2682392108
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.53237481
Short name T155
Test name
Test status
Simulation time 320952900 ps
CPU time 9.86 seconds
Started Jan 24 02:50:06 PM PST 24
Finished Jan 24 02:50:34 PM PST 24
Peak memory 210012 kb
Host smart-729f79bf-520e-4c77-a82f-fffd94051b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53237481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.53237481
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2393604871
Short name T986
Test name
Test status
Simulation time 71824348 ps
CPU time 0.84 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:50:51 PM PST 24
Peak memory 205468 kb
Host smart-920a5837-6f07-45a2-a934-9106706b17ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393604871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2393604871
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1353399321
Short name T233
Test name
Test status
Simulation time 528689183 ps
CPU time 7.46 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:50:58 PM PST 24
Peak memory 213852 kb
Host smart-a9b1b973-eeeb-4364-8233-783b8a992a51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353399321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1353399321
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1446827071
Short name T880
Test name
Test status
Simulation time 70692363 ps
CPU time 3.72 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:50:54 PM PST 24
Peak memory 222308 kb
Host smart-10ee19a4-decd-46ca-a059-4a328a04fafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446827071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1446827071
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1014346520
Short name T683
Test name
Test status
Simulation time 109457345 ps
CPU time 3.05 seconds
Started Jan 24 02:50:48 PM PST 24
Finished Jan 24 02:51:10 PM PST 24
Peak memory 209296 kb
Host smart-91fdeee2-d589-4c7f-b899-3f23502dc3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014346520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1014346520
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.92134297
Short name T86
Test name
Test status
Simulation time 51866747 ps
CPU time 3.25 seconds
Started Jan 24 02:50:39 PM PST 24
Finished Jan 24 02:50:52 PM PST 24
Peak memory 213772 kb
Host smart-45f36059-fd50-4db5-9d32-a8b07b44bc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92134297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.92134297
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1148089811
Short name T295
Test name
Test status
Simulation time 3201939312 ps
CPU time 6.57 seconds
Started Jan 24 02:50:48 PM PST 24
Finished Jan 24 02:51:13 PM PST 24
Peak memory 222040 kb
Host smart-f524e78d-e651-40a8-b6b3-abac5e9cd1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148089811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1148089811
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1862210961
Short name T740
Test name
Test status
Simulation time 276035654 ps
CPU time 3.84 seconds
Started Jan 24 02:50:38 PM PST 24
Finished Jan 24 02:50:52 PM PST 24
Peak memory 209112 kb
Host smart-572c3f22-0a35-4ecf-a140-3a33a2edb910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862210961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1862210961
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2616919105
Short name T304
Test name
Test status
Simulation time 2396459617 ps
CPU time 33.95 seconds
Started Jan 24 02:50:48 PM PST 24
Finished Jan 24 02:51:41 PM PST 24
Peak memory 209440 kb
Host smart-13f49d83-480b-49a4-9527-0050928ff1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616919105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2616919105
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1575692264
Short name T309
Test name
Test status
Simulation time 425858523 ps
CPU time 3.8 seconds
Started Jan 24 02:50:13 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 205780 kb
Host smart-fa30e055-5772-4dd0-b44a-4052ae985666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575692264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1575692264
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2493778653
Short name T1052
Test name
Test status
Simulation time 5389398020 ps
CPU time 58.58 seconds
Started Jan 24 02:50:07 PM PST 24
Finished Jan 24 02:51:23 PM PST 24
Peak memory 207872 kb
Host smart-eadb8b96-f319-4e2a-890a-f9937dcc91e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493778653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2493778653
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2106875626
Short name T354
Test name
Test status
Simulation time 28515790 ps
CPU time 2.21 seconds
Started Jan 24 02:50:10 PM PST 24
Finished Jan 24 02:50:27 PM PST 24
Peak memory 208276 kb
Host smart-7a3f6e37-7ea7-400c-8772-cdacb1e4b5e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106875626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2106875626
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2858752085
Short name T713
Test name
Test status
Simulation time 260333615 ps
CPU time 8.73 seconds
Started Jan 24 02:50:17 PM PST 24
Finished Jan 24 02:50:39 PM PST 24
Peak memory 207896 kb
Host smart-6592493a-468c-426e-86a3-bb13fc98e857
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858752085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2858752085
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2395655232
Short name T761
Test name
Test status
Simulation time 478380531 ps
CPU time 4.93 seconds
Started Jan 24 02:50:44 PM PST 24
Finished Jan 24 02:51:04 PM PST 24
Peak memory 207620 kb
Host smart-a9695c25-3b7f-4349-b114-6cec2a4bfefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395655232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2395655232
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.447399935
Short name T378
Test name
Test status
Simulation time 255838713 ps
CPU time 2.05 seconds
Started Jan 24 02:50:16 PM PST 24
Finished Jan 24 02:50:31 PM PST 24
Peak memory 207696 kb
Host smart-dc605563-bf6a-4a1a-b396-c174b33b70af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447399935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.447399935
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2268018281
Short name T923
Test name
Test status
Simulation time 1161159957 ps
CPU time 7.21 seconds
Started Jan 24 02:50:48 PM PST 24
Finished Jan 24 02:51:14 PM PST 24
Peak memory 222048 kb
Host smart-82013196-ac85-4207-b012-168ab6b927b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268018281 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2268018281
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4162191688
Short name T877
Test name
Test status
Simulation time 106013928 ps
CPU time 4.85 seconds
Started Jan 24 02:50:40 PM PST 24
Finished Jan 24 02:50:55 PM PST 24
Peak memory 206588 kb
Host smart-cdcc4d29-44d7-427f-b94a-81028ddae79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162191688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4162191688
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1718850382
Short name T587
Test name
Test status
Simulation time 82426509 ps
CPU time 3.16 seconds
Started Jan 24 02:50:41 PM PST 24
Finished Jan 24 02:50:54 PM PST 24
Peak memory 209352 kb
Host smart-2faa1711-e9f3-44bf-8af1-ddfed17b0730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718850382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1718850382
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3004614970
Short name T812
Test name
Test status
Simulation time 113062851 ps
CPU time 0.76 seconds
Started Jan 24 02:39:57 PM PST 24
Finished Jan 24 02:40:09 PM PST 24
Peak memory 205468 kb
Host smart-29eeaf60-9661-4300-bd09-82e8475797d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004614970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3004614970
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1324022124
Short name T409
Test name
Test status
Simulation time 50829661 ps
CPU time 3.95 seconds
Started Jan 24 02:39:40 PM PST 24
Finished Jan 24 02:40:00 PM PST 24
Peak memory 214116 kb
Host smart-caa5e9f4-a03a-4437-afdb-15b39150fd1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324022124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1324022124
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.232686632
Short name T751
Test name
Test status
Simulation time 235174538 ps
CPU time 4.77 seconds
Started Jan 24 02:39:48 PM PST 24
Finished Jan 24 02:40:03 PM PST 24
Peak memory 222320 kb
Host smart-ede50a07-aea9-4837-84a1-b16f19f7c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232686632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.232686632
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.829276182
Short name T1047
Test name
Test status
Simulation time 363905708 ps
CPU time 7.67 seconds
Started Jan 24 02:39:44 PM PST 24
Finished Jan 24 02:40:05 PM PST 24
Peak memory 221016 kb
Host smart-80094595-a424-41d4-9cf9-fce97636efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829276182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.829276182
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3121255791
Short name T993
Test name
Test status
Simulation time 240976824 ps
CPU time 6.01 seconds
Started Jan 24 02:39:49 PM PST 24
Finished Jan 24 02:40:04 PM PST 24
Peak memory 213744 kb
Host smart-0ed5ad10-cf3f-45bc-884f-4ad54393a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121255791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3121255791
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1876518545
Short name T642
Test name
Test status
Simulation time 45048358 ps
CPU time 2.01 seconds
Started Jan 24 02:39:40 PM PST 24
Finished Jan 24 02:39:58 PM PST 24
Peak memory 213564 kb
Host smart-cf6b20c3-92b2-4cf3-88a0-df282fcdc6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876518545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1876518545
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1795186311
Short name T681
Test name
Test status
Simulation time 436587618 ps
CPU time 4.56 seconds
Started Jan 24 02:39:43 PM PST 24
Finished Jan 24 02:40:02 PM PST 24
Peak memory 208076 kb
Host smart-44146a07-afb9-4d44-8fc3-d12a41046d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795186311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1795186311
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4084908598
Short name T755
Test name
Test status
Simulation time 22011345 ps
CPU time 1.83 seconds
Started Jan 24 04:17:01 PM PST 24
Finished Jan 24 04:17:04 PM PST 24
Peak memory 206148 kb
Host smart-5b061c23-49cc-44a7-a242-151249d6d593
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084908598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4084908598
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2388931597
Short name T593
Test name
Test status
Simulation time 30182632 ps
CPU time 2.15 seconds
Started Jan 24 02:39:43 PM PST 24
Finished Jan 24 02:39:59 PM PST 24
Peak memory 206112 kb
Host smart-0ca62cca-c717-451d-8353-5894f70788ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388931597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2388931597
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2401233031
Short name T895
Test name
Test status
Simulation time 236263018 ps
CPU time 3.28 seconds
Started Jan 24 02:39:39 PM PST 24
Finished Jan 24 02:39:59 PM PST 24
Peak memory 206116 kb
Host smart-f7455a78-7558-4818-a27c-3c0fdcf460c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401233031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2401233031
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2195052700
Short name T963
Test name
Test status
Simulation time 99627683 ps
CPU time 2.55 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:11 PM PST 24
Peak memory 209084 kb
Host smart-efcd5139-2dc9-435e-ab57-0ed215018a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195052700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2195052700
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2400113556
Short name T813
Test name
Test status
Simulation time 286843971 ps
CPU time 4.35 seconds
Started Jan 24 02:39:40 PM PST 24
Finished Jan 24 02:40:00 PM PST 24
Peak memory 206012 kb
Host smart-3ddc1d01-73c6-41a2-b1f4-156f24f0e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400113556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2400113556
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1116489797
Short name T1043
Test name
Test status
Simulation time 73958323 ps
CPU time 6.14 seconds
Started Jan 24 02:39:44 PM PST 24
Finished Jan 24 02:40:03 PM PST 24
Peak memory 220340 kb
Host smart-60407d13-e53a-4996-9040-7a8edd8bb86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116489797 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1116489797
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3253138316
Short name T774
Test name
Test status
Simulation time 165350380 ps
CPU time 4.09 seconds
Started Jan 24 03:43:47 PM PST 24
Finished Jan 24 03:43:56 PM PST 24
Peak memory 207332 kb
Host smart-a1559f55-a025-4a9a-9f11-619ccbfbf8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253138316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3253138316
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4284824468
Short name T899
Test name
Test status
Simulation time 59429864 ps
CPU time 2.88 seconds
Started Jan 24 02:39:49 PM PST 24
Finished Jan 24 02:40:01 PM PST 24
Peak memory 209320 kb
Host smart-f0f5b753-2ff0-489d-acb8-2eaeeb936026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284824468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4284824468
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.101957065
Short name T1055
Test name
Test status
Simulation time 17712217 ps
CPU time 0.75 seconds
Started Jan 24 03:50:03 PM PST 24
Finished Jan 24 03:50:09 PM PST 24
Peak memory 205492 kb
Host smart-e7c1713e-cb48-4e99-8193-04c1abb480eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101957065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.101957065
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1937245816
Short name T289
Test name
Test status
Simulation time 53497535 ps
CPU time 3.81 seconds
Started Jan 24 02:39:52 PM PST 24
Finished Jan 24 02:40:03 PM PST 24
Peak memory 222068 kb
Host smart-b49b3779-ef6f-487e-b16b-772bf010403a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937245816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1937245816
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.40009292
Short name T34
Test name
Test status
Simulation time 697956774 ps
CPU time 9 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:20 PM PST 24
Peak memory 217436 kb
Host smart-c3b60eef-ef9d-4f72-83d0-e0fa07dc0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40009292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.40009292
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1585739910
Short name T397
Test name
Test status
Simulation time 30190156 ps
CPU time 2.1 seconds
Started Jan 24 02:39:59 PM PST 24
Finished Jan 24 02:40:16 PM PST 24
Peak memory 213836 kb
Host smart-a3bee474-3f2a-421e-bbb0-11670d2bb633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585739910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1585739910
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4262157729
Short name T82
Test name
Test status
Simulation time 1850997142 ps
CPU time 21.74 seconds
Started Jan 24 02:39:59 PM PST 24
Finished Jan 24 02:40:35 PM PST 24
Peak memory 221780 kb
Host smart-f4d74fa6-b5f6-46c6-847e-580f4b3ad11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262157729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4262157729
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.18123490
Short name T261
Test name
Test status
Simulation time 301891620 ps
CPU time 7.3 seconds
Started Jan 24 02:40:00 PM PST 24
Finished Jan 24 02:40:21 PM PST 24
Peak memory 221868 kb
Host smart-796464b6-2c60-46be-bc0c-a2b45db20c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18123490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.18123490
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4175881152
Short name T659
Test name
Test status
Simulation time 295935784 ps
CPU time 2.36 seconds
Started Jan 24 02:40:01 PM PST 24
Finished Jan 24 02:40:19 PM PST 24
Peak memory 206820 kb
Host smart-9f87c8e1-860c-432b-98b2-6aedef6a6827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175881152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4175881152
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2130595381
Short name T110
Test name
Test status
Simulation time 350920584 ps
CPU time 4.26 seconds
Started Jan 24 02:39:49 PM PST 24
Finished Jan 24 02:40:03 PM PST 24
Peak memory 208640 kb
Host smart-e72f8fcd-5a1d-4d90-994c-136888df059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130595381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2130595381
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2581829931
Short name T830
Test name
Test status
Simulation time 623433190 ps
CPU time 6.68 seconds
Started Jan 24 02:39:52 PM PST 24
Finished Jan 24 02:40:06 PM PST 24
Peak memory 207312 kb
Host smart-979e90ad-2f3f-4f90-b752-a87dfe63c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581829931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2581829931
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2761556484
Short name T679
Test name
Test status
Simulation time 183664627 ps
CPU time 5.57 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:15 PM PST 24
Peak memory 207248 kb
Host smart-e5c47048-eb39-4fe1-8f2a-9826fa5b75f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761556484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2761556484
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3957185567
Short name T805
Test name
Test status
Simulation time 301234765 ps
CPU time 4.67 seconds
Started Jan 24 02:39:52 PM PST 24
Finished Jan 24 02:40:04 PM PST 24
Peak memory 208128 kb
Host smart-432ff5c1-9c1d-42b4-8de6-dffe38160434
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957185567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3957185567
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4182525418
Short name T747
Test name
Test status
Simulation time 12835209596 ps
CPU time 59.33 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:41:08 PM PST 24
Peak memory 208080 kb
Host smart-50972755-0d38-40c2-ab10-68147a6856ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182525418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4182525418
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.671280981
Short name T980
Test name
Test status
Simulation time 26890886 ps
CPU time 2.22 seconds
Started Jan 24 02:40:04 PM PST 24
Finished Jan 24 02:40:24 PM PST 24
Peak memory 206792 kb
Host smart-60ee28a0-0839-45cf-9fd7-5915d44df7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671280981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.671280981
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.471011857
Short name T784
Test name
Test status
Simulation time 34669672 ps
CPU time 2.02 seconds
Started Jan 24 02:39:48 PM PST 24
Finished Jan 24 02:40:00 PM PST 24
Peak memory 207824 kb
Host smart-0812a920-5abf-49e9-b5de-333d5d6649cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471011857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.471011857
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1113752802
Short name T60
Test name
Test status
Simulation time 1358179770 ps
CPU time 17.39 seconds
Started Jan 24 02:40:04 PM PST 24
Finished Jan 24 02:40:39 PM PST 24
Peak memory 221324 kb
Host smart-b90ca1f7-efcf-42a4-9b0e-f8e4a5027992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113752802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1113752802
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2395616126
Short name T941
Test name
Test status
Simulation time 142039978 ps
CPU time 2.82 seconds
Started Jan 24 04:32:10 PM PST 24
Finished Jan 24 04:32:14 PM PST 24
Peak memory 214132 kb
Host smart-b95848d6-19f8-4210-a97f-9690c827fcdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395616126 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2395616126
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1264542854
Short name T911
Test name
Test status
Simulation time 95448207 ps
CPU time 4.47 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:15 PM PST 24
Peak memory 209064 kb
Host smart-ee009c70-1128-49f8-831a-bfec6c0e17c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264542854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1264542854
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4062536542
Short name T1033
Test name
Test status
Simulation time 75531774 ps
CPU time 2.99 seconds
Started Jan 24 02:39:58 PM PST 24
Finished Jan 24 02:40:13 PM PST 24
Peak memory 209232 kb
Host smart-5e0661ef-cdbf-46d2-8776-3b5a2317f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062536542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4062536542
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2494135511
Short name T718
Test name
Test status
Simulation time 12733867 ps
CPU time 0.73 seconds
Started Jan 24 02:40:32 PM PST 24
Finished Jan 24 02:40:46 PM PST 24
Peak memory 205488 kb
Host smart-c418cb93-67c7-4998-8880-f0324f30eb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494135511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2494135511
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2181897822
Short name T285
Test name
Test status
Simulation time 122073360 ps
CPU time 2.93 seconds
Started Jan 24 02:40:11 PM PST 24
Finished Jan 24 02:40:29 PM PST 24
Peak memory 214212 kb
Host smart-559caf04-0285-4701-b8e5-92191404c8f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181897822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2181897822
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2396696429
Short name T592
Test name
Test status
Simulation time 59811121 ps
CPU time 2.92 seconds
Started Jan 24 02:48:14 PM PST 24
Finished Jan 24 02:48:45 PM PST 24
Peak memory 208880 kb
Host smart-82ce2c79-620f-4baf-82a2-1117d63a243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396696429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2396696429
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.920697736
Short name T862
Test name
Test status
Simulation time 223183928 ps
CPU time 5.83 seconds
Started Jan 24 02:40:09 PM PST 24
Finished Jan 24 02:40:30 PM PST 24
Peak memory 208584 kb
Host smart-b59010b0-f33b-4f6c-8738-1d8c3d8007d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920697736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.920697736
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2507567829
Short name T991
Test name
Test status
Simulation time 1212743079 ps
CPU time 5.17 seconds
Started Jan 24 02:40:33 PM PST 24
Finished Jan 24 02:40:51 PM PST 24
Peak memory 211720 kb
Host smart-ba22f9d1-702d-46aa-8e80-80d272f5c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507567829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2507567829
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1839305034
Short name T838
Test name
Test status
Simulation time 76587396 ps
CPU time 2.13 seconds
Started Jan 24 02:40:15 PM PST 24
Finished Jan 24 02:40:31 PM PST 24
Peak memory 213852 kb
Host smart-528fe040-ef66-4e7c-a48e-ce04a0035a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839305034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1839305034
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2288497040
Short name T291
Test name
Test status
Simulation time 343120733 ps
CPU time 4.41 seconds
Started Jan 24 02:40:11 PM PST 24
Finished Jan 24 02:40:31 PM PST 24
Peak memory 208060 kb
Host smart-4e05f888-2453-4ee0-8d48-8dcf53df8445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288497040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2288497040
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1130812029
Short name T770
Test name
Test status
Simulation time 333008491 ps
CPU time 7.26 seconds
Started Jan 24 02:40:11 PM PST 24
Finished Jan 24 02:40:33 PM PST 24
Peak memory 205864 kb
Host smart-ea7d1a67-739a-45e8-b811-cafe339f0905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130812029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1130812029
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3150790513
Short name T78
Test name
Test status
Simulation time 228153025 ps
CPU time 6.65 seconds
Started Jan 24 02:40:08 PM PST 24
Finished Jan 24 02:40:30 PM PST 24
Peak memory 208048 kb
Host smart-f1825920-b195-4c93-84e3-dfd49d11ddb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150790513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3150790513
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2821041247
Short name T717
Test name
Test status
Simulation time 49651244 ps
CPU time 2.82 seconds
Started Jan 24 03:11:24 PM PST 24
Finished Jan 24 03:11:30 PM PST 24
Peak memory 206188 kb
Host smart-ebe007cf-6ee9-47c6-86e2-1deae83e5b68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821041247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2821041247
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.377056731
Short name T816
Test name
Test status
Simulation time 60295186 ps
CPU time 1.97 seconds
Started Jan 24 02:40:35 PM PST 24
Finished Jan 24 02:40:49 PM PST 24
Peak memory 207892 kb
Host smart-23689584-3cbe-4a76-96bd-ccf75172fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377056731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.377056731
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1881920766
Short name T752
Test name
Test status
Simulation time 66114192 ps
CPU time 2.88 seconds
Started Jan 24 02:57:26 PM PST 24
Finished Jan 24 02:57:46 PM PST 24
Peak memory 206668 kb
Host smart-0bfe2adc-ffa0-4e5e-9f4b-c15d7b9dae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881920766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1881920766
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2886797618
Short name T387
Test name
Test status
Simulation time 55748533 ps
CPU time 2.91 seconds
Started Jan 24 02:40:35 PM PST 24
Finished Jan 24 02:40:50 PM PST 24
Peak memory 207608 kb
Host smart-cba5e529-bb12-49c0-8612-1e3a0ea3deb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886797618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2886797618
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3921457596
Short name T886
Test name
Test status
Simulation time 476069517 ps
CPU time 7.9 seconds
Started Jan 24 02:40:32 PM PST 24
Finished Jan 24 02:40:52 PM PST 24
Peak memory 219356 kb
Host smart-d907ca62-4bd1-43ae-83e0-f0abe7f2967c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921457596 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3921457596
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1364400274
Short name T836
Test name
Test status
Simulation time 86467980 ps
CPU time 4.66 seconds
Started Jan 24 02:40:15 PM PST 24
Finished Jan 24 02:40:33 PM PST 24
Peak memory 208064 kb
Host smart-3082a565-d26c-4f62-8dab-3cd0c03d4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364400274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1364400274
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4121062241
Short name T372
Test name
Test status
Simulation time 190506615 ps
CPU time 1.9 seconds
Started Jan 24 02:40:32 PM PST 24
Finished Jan 24 02:40:47 PM PST 24
Peak memory 209468 kb
Host smart-ebe7b4f0-1646-493e-94f5-8c8bef049bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121062241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4121062241
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1923847429
Short name T822
Test name
Test status
Simulation time 19163376 ps
CPU time 0.82 seconds
Started Jan 24 02:40:51 PM PST 24
Finished Jan 24 02:41:06 PM PST 24
Peak memory 205460 kb
Host smart-d4ea2fb4-4308-46c6-8ead-924ba662a159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923847429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1923847429
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.93761565
Short name T239
Test name
Test status
Simulation time 77695684 ps
CPU time 2.28 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:55 PM PST 24
Peak memory 207032 kb
Host smart-70a66971-7529-4814-817d-5da12327e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93761565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.93761565
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1012573881
Short name T768
Test name
Test status
Simulation time 95656999 ps
CPU time 3.93 seconds
Started Jan 24 02:40:41 PM PST 24
Finished Jan 24 02:40:55 PM PST 24
Peak memory 213804 kb
Host smart-68ac27fc-1de4-44df-b998-94381e6baf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012573881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1012573881
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3532864887
Short name T201
Test name
Test status
Simulation time 3658050896 ps
CPU time 27.74 seconds
Started Jan 24 02:56:38 PM PST 24
Finished Jan 24 02:57:07 PM PST 24
Peak memory 216208 kb
Host smart-d19ef8cb-c9b6-416b-824b-3133573b005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532864887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3532864887
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3971023094
Short name T918
Test name
Test status
Simulation time 689552618 ps
CPU time 7.15 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:59 PM PST 24
Peak memory 213840 kb
Host smart-17a7dc05-7493-4b54-b86a-5531d4e47e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971023094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3971023094
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1795153005
Short name T1045
Test name
Test status
Simulation time 116353892 ps
CPU time 2.47 seconds
Started Jan 24 02:40:44 PM PST 24
Finished Jan 24 02:40:57 PM PST 24
Peak memory 208044 kb
Host smart-fa7990c1-4b69-41cd-af20-7078e9a0c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795153005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1795153005
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2601188195
Short name T860
Test name
Test status
Simulation time 859853760 ps
CPU time 3.45 seconds
Started Jan 24 02:40:44 PM PST 24
Finished Jan 24 02:40:59 PM PST 24
Peak memory 207876 kb
Host smart-af0094c7-67d7-478c-8176-66eb04de7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601188195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2601188195
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1489466280
Short name T588
Test name
Test status
Simulation time 489745654 ps
CPU time 6.41 seconds
Started Jan 24 02:52:23 PM PST 24
Finished Jan 24 02:52:40 PM PST 24
Peak memory 207864 kb
Host smart-671a5bbf-269b-4cb0-a9d5-82c3ccf6cfbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489466280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1489466280
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.911488243
Short name T735
Test name
Test status
Simulation time 526675461 ps
CPU time 18.82 seconds
Started Jan 24 02:40:41 PM PST 24
Finished Jan 24 02:41:10 PM PST 24
Peak memory 207920 kb
Host smart-6ba96272-bb02-4a66-8ffe-adab405dacb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911488243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.911488243
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3583014180
Short name T962
Test name
Test status
Simulation time 425319055 ps
CPU time 7.38 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:41:00 PM PST 24
Peak memory 208108 kb
Host smart-94a4238b-c79b-4815-94b4-7fb0224baca2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583014180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3583014180
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.26986204
Short name T956
Test name
Test status
Simulation time 240231145 ps
CPU time 3.15 seconds
Started Jan 24 02:40:45 PM PST 24
Finished Jan 24 02:40:59 PM PST 24
Peak memory 208492 kb
Host smart-b636323c-1969-4f89-82ba-f03819c0ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26986204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.26986204
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3308158255
Short name T1015
Test name
Test status
Simulation time 1707361744 ps
CPU time 36 seconds
Started Jan 24 02:40:32 PM PST 24
Finished Jan 24 02:41:21 PM PST 24
Peak memory 207516 kb
Host smart-0c39b668-805a-47ba-988a-b0423816fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308158255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3308158255
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1121747272
Short name T375
Test name
Test status
Simulation time 761204910 ps
CPU time 5.5 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:57 PM PST 24
Peak memory 221076 kb
Host smart-b0d9ee0b-3c43-415c-b3da-8ae88c2a2421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121747272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1121747272
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2284830830
Short name T975
Test name
Test status
Simulation time 239905586 ps
CPU time 5.02 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:57 PM PST 24
Peak memory 206980 kb
Host smart-fedea419-32c5-4632-98ad-582681c7c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284830830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2284830830
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4288687639
Short name T391
Test name
Test status
Simulation time 1741003143 ps
CPU time 2.5 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:54 PM PST 24
Peak memory 210076 kb
Host smart-7d08935e-f3f0-429e-9794-a12ce005d64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288687639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4288687639
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1494791560
Short name T569
Test name
Test status
Simulation time 42475273 ps
CPU time 0.85 seconds
Started Jan 24 02:40:50 PM PST 24
Finished Jan 24 02:41:05 PM PST 24
Peak memory 205388 kb
Host smart-03b31a2c-83a4-46ce-b286-985d26f949c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494791560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1494791560
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2305291338
Short name T70
Test name
Test status
Simulation time 271711555 ps
CPU time 4.28 seconds
Started Jan 24 02:40:52 PM PST 24
Finished Jan 24 02:41:11 PM PST 24
Peak memory 213720 kb
Host smart-6ce62510-d969-42e4-8117-21dfd78ef148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305291338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2305291338
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2187736824
Short name T1078
Test name
Test status
Simulation time 1013455602 ps
CPU time 4.63 seconds
Started Jan 24 02:40:57 PM PST 24
Finished Jan 24 02:41:16 PM PST 24
Peak memory 220560 kb
Host smart-a295fdc2-89ef-41cb-8fab-8adc16ec495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187736824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2187736824
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3252847260
Short name T265
Test name
Test status
Simulation time 353472527 ps
CPU time 3.88 seconds
Started Jan 24 02:40:57 PM PST 24
Finished Jan 24 02:41:16 PM PST 24
Peak memory 209844 kb
Host smart-732beeec-ec96-43db-b9ac-9295cfd8ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252847260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3252847260
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.4076643686
Short name T798
Test name
Test status
Simulation time 166976945 ps
CPU time 5.15 seconds
Started Jan 24 02:40:49 PM PST 24
Finished Jan 24 02:41:08 PM PST 24
Peak memory 213724 kb
Host smart-a03038bd-a1f7-4846-8330-39439601461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076643686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.4076643686
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2251921249
Short name T88
Test name
Test status
Simulation time 103477625 ps
CPU time 2.47 seconds
Started Jan 24 02:40:57 PM PST 24
Finished Jan 24 02:41:14 PM PST 24
Peak memory 208864 kb
Host smart-1f3f3800-901f-4821-add7-4a864faad9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251921249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2251921249
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.140799073
Short name T748
Test name
Test status
Simulation time 59764719 ps
CPU time 2.41 seconds
Started Jan 24 03:01:13 PM PST 24
Finished Jan 24 03:01:30 PM PST 24
Peak memory 206664 kb
Host smart-24be013c-ef09-4553-9a31-7cc1068f3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140799073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.140799073
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.701256118
Short name T328
Test name
Test status
Simulation time 119976803 ps
CPU time 3.26 seconds
Started Jan 24 04:32:00 PM PST 24
Finished Jan 24 04:32:04 PM PST 24
Peak memory 207992 kb
Host smart-ccaf7a04-4922-4b7d-a22c-293fee405455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701256118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.701256118
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.839793080
Short name T856
Test name
Test status
Simulation time 2076844619 ps
CPU time 7.76 seconds
Started Jan 24 03:51:29 PM PST 24
Finished Jan 24 03:51:38 PM PST 24
Peak memory 207852 kb
Host smart-a70c7dc6-ba28-489f-8a8b-76ffc2a774b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839793080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.839793080
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1945933900
Short name T1050
Test name
Test status
Simulation time 21069501 ps
CPU time 1.8 seconds
Started Jan 24 02:40:50 PM PST 24
Finished Jan 24 02:41:06 PM PST 24
Peak memory 206104 kb
Host smart-042e4799-e320-4182-87e6-c2cb7bed1f2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945933900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1945933900
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.4168780107
Short name T800
Test name
Test status
Simulation time 237355861 ps
CPU time 3.1 seconds
Started Jan 24 02:40:54 PM PST 24
Finished Jan 24 02:41:11 PM PST 24
Peak memory 206132 kb
Host smart-7446099b-185d-4579-8a23-efc0edf78616
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168780107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4168780107
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3307063653
Short name T978
Test name
Test status
Simulation time 608732133 ps
CPU time 5.9 seconds
Started Jan 24 02:40:53 PM PST 24
Finished Jan 24 02:41:13 PM PST 24
Peak memory 208944 kb
Host smart-08bd8218-b1fc-4eed-9f6d-31ad62a89ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307063653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3307063653
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3964872110
Short name T678
Test name
Test status
Simulation time 753019364 ps
CPU time 8.38 seconds
Started Jan 24 02:40:52 PM PST 24
Finished Jan 24 02:41:14 PM PST 24
Peak memory 205968 kb
Host smart-14364b5b-5b3e-4e4f-b36b-a104a5fd727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964872110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3964872110
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2536971341
Short name T305
Test name
Test status
Simulation time 466268275 ps
CPU time 18.45 seconds
Started Jan 24 03:33:15 PM PST 24
Finished Jan 24 03:33:35 PM PST 24
Peak memory 221976 kb
Host smart-d407c4f6-35ac-47e1-962b-5e769a4ac408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536971341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2536971341
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2334267765
Short name T875
Test name
Test status
Simulation time 167481036 ps
CPU time 10.48 seconds
Started Jan 24 02:40:52 PM PST 24
Finished Jan 24 02:41:17 PM PST 24
Peak memory 223084 kb
Host smart-9dee7104-33d3-42a3-b34c-e6cae3d88b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334267765 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2334267765
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1436979106
Short name T262
Test name
Test status
Simulation time 380789689 ps
CPU time 4.66 seconds
Started Jan 24 02:40:53 PM PST 24
Finished Jan 24 02:41:12 PM PST 24
Peak memory 213860 kb
Host smart-e9b90a72-ce31-4a38-aa83-32066aa632e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436979106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1436979106
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4253219907
Short name T1001
Test name
Test status
Simulation time 127704390 ps
CPU time 3.18 seconds
Started Jan 24 02:40:57 PM PST 24
Finished Jan 24 02:41:15 PM PST 24
Peak memory 209120 kb
Host smart-ff61aad3-b5ff-42a6-8c9a-effa3fca8a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253219907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4253219907
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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