SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[FlashOwnerSeedInvalid] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 780 | 1 | T25 | 20 | T27 | 20 | T28 | 40 | ||||
auto[OtpRootKeyValidLow] | 162 | 1 | T25 | 7 | T27 | 7 | T28 | 7 | ||||
auto[LcStateInvalid] | 36 | 1 | T288 | 12 | T365 | 24 | - | - | ||||
auto[OtpDevIdInvalid] | 144 | 1 | T91 | 72 | T95 | 12 | T365 | 12 | ||||
auto[RomDigestInvalid] | 8 | 1 | T366 | 8 | - | - | - | - | ||||
auto[RomDigestValidLow] | 36 | 1 | T91 | 12 | T367 | 24 | - | - | ||||
auto[FlashCreatorSeedInvalid] | 108 | 1 | T87 | 84 | T88 | 24 | - | - |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |