Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10896

1

T1

14

T2

57

T3

4

auto[Attestation]

7376

1

T1

10

T2

49

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2741	1			T1	6		T2	20		T3	1
auto[Aes]	3285	1			T1	2		T2	14		T3	1
auto[Kmac]	3313	1			T1	5		T2	6		T14	1
auto[Otbn]	3210	1			T1	4		T2	19		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7253	1			T1	8		T2	51		T3	8
auto[OpGenId]	5723	1			T1	7		T2	47		T3	4
auto[OpGenSwOut]	5710	1			T1	10		T2	43		T3	4
auto[OpGenHwOut]	6839	1			T1	7		T2	16		T4	14
auto[OpDisable]	113	1			T46	1		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9493

1

T1

6

T2

64

T3

8

auto[OpDoneFail]

16145

1

T1

26

T2

93

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6080	1			T1	10		T2	49		T3	1
auto[StInit]	3977	1			T1	6		T2	17		T3	2
auto[StCreatorRootKey]	2786	1			T1	2		T2	20		T3	2
auto[StOwnerIntKey]	2527	1			T1	1		T2	16		T3	2
auto[StOwnerKey]	2165	1			T1	1		T2	14		T3	2
auto[StDisabled]	7092	1			T1	12		T2	41		T3	7
auto[StInvalid]	1011	1			T52	25		T53	19		T97	26

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	311	1			T2	4		T41	2		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T1	1		T14	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T34	1		T101	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T2	1		T43	1		T120	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T196	1		T54	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	186	1			T42	1		T193	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	42	1			T52	1		T53	3		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	313	1			T2	3		T43	1		T196	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T7	1		T54	3		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	67	1			T34	1		T48	1		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T2	2		T43	1		T170	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	50	1			T54	2		T197	1		T147	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	199	1			T2	3		T3	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T62	2		T198	2		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	308	1			T2	1		T41	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T170	1		T19	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T1	1		T2	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T120	1		T54	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T34	1		T54	2		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	183	1			T41	1		T43	2		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	19	1			T201	2		T202	1		T203	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	309	1			T2	2		T43	3		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T2	1		T14	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T16	1		T134	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T14	1		T47	1		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T41	1		T54	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	176	1			T1	2		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	26	1			T52	1		T199	2		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T2	3		T170	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T196	1		T170	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T2	1		T101	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T140	1		T54	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T2	1		T16	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	190	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	31	1			T53	1		T97	2		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	58	1			T2	2		T170	3		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T18	1		T41	1		T25	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T2	1		T46	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	53	1			T54	1		T61	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	45	1			T2	1		T170	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	187	1			T16	2		T196	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T52	1		T53	1		T97	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	76	1			T2	1		T170	2		T54	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T1	1		T14	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T55	1		T33	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T16	1		T18	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	59	1			T2	1		T140	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	192	1			T1	2		T2	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T52	1		T97	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T2	5		T54	4		T102	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T1	1		T2	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T2	1		T14	1		T54	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	48	1			T2	1		T120	1		T160	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	49	1			T2	1		T42	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	206	1			T2	1		T41	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	24	1			T52	1		T53	1		T97	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	269	1			T1	2		T43	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T54	4		T27	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T2	2		T18	1		T54	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T196	1		T54	1		T160	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T61	1		T57	1		T70	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	209	1			T2	1		T18	1		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	20	1			T62	1		T198	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	448	1			T1	2		T17	8		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T17	1		T115	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T2	1		T120	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T34	1		T115	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T115	1		T135	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	253	1			T17	2		T41	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	34	1			T52	2		T62	1		T198	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	481	1			T1	1		T41	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	121	1			T15	1		T47	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T134	1		T120	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T18	1		T196	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T207	1		T140	2		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	250	1			T2	1		T42	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	39	1			T52	2		T53	1		T62	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	391	1			T2	2		T4	6		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T2	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T13	1		T14	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T18	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	77	1			T4	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	292	1			T2	1		T4	2		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	25	1			T52	1		T199	1		T202	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	47	1			T2	2		T54	4		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T2	1		T35	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T193	1		T137	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	51	1			T34	1		T19	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T2	1		T54	3		T160	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T1	1		T2	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T52	1		T97	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T54	4		T102	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T43	2		T135	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T17	1		T43	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	85	1			T2	1		T17	1		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	98	1			T17	1		T34	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	264	1			T17	2		T41	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T62	1		T199	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	55	1			T54	3		T102	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T34	1		T207	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T46	1		T43	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T46	1		T54	4		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T18	1		T42	1		T196	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	253	1			T196	1		T207	3		T208	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T52	1		T53	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	42	1			T2	1		T54	3		T102	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T54	1		T210	1		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T4	1		T134	1		T211	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T4	1		T13	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T170	2		T54	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	252	1			T1	1		T4	2		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T53	2		T97	3		T198	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	190	1			T2	1		T34	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	681	1			T1	1		T2	4		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	187	1			T2	2		T34	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	661	1			T2	6		T3	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T1	1		T2	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	624	1			T2	1		T41	2		T43	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T14	1		T16	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	632	1			T1	2		T2	4		T3	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	190	1			T2	2		T16	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	376	1			T1	2		T2	5		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	179	1			T2	2		T46	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	409	1			T2	2		T16	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T2	1		T16	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	432	1			T1	3		T2	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	157	1			T2	3		T14	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	429	1			T1	1		T2	7		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	161	1			T2	2		T18	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	620	1			T1	2		T2	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	228	1			T2	1		T34	1		T115	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	884	1			T1	2		T17	11		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T134	1		T196	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	903	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	253	1			T4	1		T13	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	852	1			T2	4		T4	9		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	150	1			T2	1		T34	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	373	1			T1	1		T2	4		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	255	1			T2	1		T17	3		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	482	1			T17	2		T41	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	225	1			T18	1		T42	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	474	1			T34	1		T196	1		T207	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	244	1			T4	2		T13	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	462	1			T1	1		T2	1		T4	2