Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29497

1

T1

37

T2

179

T3

22

auto[1]

284

1

T120

7

T159

2

T310

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	29504	1			T1	37		T2	179		T3	22
auto[134217728:268435455]	17	1			T120	1		T363	1		T381	1
auto[268435456:402653183]	8	1			T382	1		T383	1		T358	1
auto[402653184:536870911]	10	1			T271	1		T381	1		T343	1
auto[536870912:671088639]	9	1			T360	1		T370	1		T384	1
auto[671088640:805306367]	7	1			T370	1		T384	2		T281	1
auto[805306368:939524095]	12	1			T120	1		T271	1		T370	1
auto[939524096:1073741823]	8	1			T120	1		T382	2		T314	1
auto[1073741824:1207959551]	11	1			T120	1		T159	1		T310	1
auto[1207959552:1342177279]	5	1			T385	1		T384	1		T363	1
auto[1342177280:1476395007]	7	1			T239	1		T386	1		T236	1
auto[1476395008:1610612735]	10	1			T360	2		T384	1		T382	1
auto[1610612736:1744830463]	10	1			T370	1		T351	1		T381	1
auto[1744830464:1879048191]	10	1			T351	3		T364	1		T382	1
auto[1879048192:2013265919]	7	1			T370	1		T387	2		T236	1
auto[2013265920:2147483647]	11	1			T310	1		T360	1		T385	1
auto[2147483648:2281701375]	11	1			T310	1		T360	1		T363	1
auto[2281701376:2415919103]	7	1			T351	2		T358	2		T388	1
auto[2415919104:2550136831]	10	1			T111	1		T343	1		T389	2
auto[2550136832:2684354559]	5	1			T271	1		T370	1		T314	1
auto[2684354560:2818572287]	7	1			T120	1		T280	1		T271	1
auto[2818572288:2952790015]	8	1			T370	2		T384	1		T387	1
auto[2952790016:3087007743]	10	1			T280	1		T360	1		T281	2
auto[3087007744:3221225471]	9	1			T310	2		T387	1		T254	1
auto[3221225472:3355443199]	9	1			T120	1		T360	1		T383	2
auto[3355443200:3489660927]	10	1			T373	1		T364	1		T111	1
auto[3489660928:3623878655]	8	1			T385	1		T351	1		T239	1
auto[3623878656:3758096383]	10	1			T370	1		T111	1		T281	1
auto[3758096384:3892314111]	7	1			T239	1		T111	1		T382	1
auto[3892314112:4026531839]	9	1			T120	1		T271	1		T384	1
auto[4026531840:4160749567]	5	1			T364	1		T111	1		T387	1
auto[4160749568:4294967295]	10	1			T159	1		T111	1		T390	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29497	1			T1	37		T2	179		T3	22
auto[0:134217727]	auto[1]	7	1			T389	1		T358	2		T388	2
auto[134217728:268435455]	auto[1]	17	1			T120	1		T363	1		T381	1
auto[268435456:402653183]	auto[1]	8	1			T382	1		T383	1		T358	1
auto[402653184:536870911]	auto[1]	10	1			T271	1		T381	1		T343	1
auto[536870912:671088639]	auto[1]	9	1			T360	1		T370	1		T384	1
auto[671088640:805306367]	auto[1]	7	1			T370	1		T384	2		T281	1
auto[805306368:939524095]	auto[1]	12	1			T120	1		T271	1		T370	1
auto[939524096:1073741823]	auto[1]	8	1			T120	1		T382	2		T314	1
auto[1073741824:1207959551]	auto[1]	11	1			T120	1		T159	1		T310	1
auto[1207959552:1342177279]	auto[1]	5	1			T385	1		T384	1		T363	1
auto[1342177280:1476395007]	auto[1]	7	1			T239	1		T386	1		T236	1
auto[1476395008:1610612735]	auto[1]	10	1			T360	2		T384	1		T382	1
auto[1610612736:1744830463]	auto[1]	10	1			T370	1		T351	1		T381	1
auto[1744830464:1879048191]	auto[1]	10	1			T351	3		T364	1		T382	1
auto[1879048192:2013265919]	auto[1]	7	1			T370	1		T387	2		T236	1
auto[2013265920:2147483647]	auto[1]	11	1			T310	1		T360	1		T385	1
auto[2147483648:2281701375]	auto[1]	11	1			T310	1		T360	1		T363	1
auto[2281701376:2415919103]	auto[1]	7	1			T351	2		T358	2		T388	1
auto[2415919104:2550136831]	auto[1]	10	1			T111	1		T343	1		T389	2
auto[2550136832:2684354559]	auto[1]	5	1			T271	1		T370	1		T314	1
auto[2684354560:2818572287]	auto[1]	7	1			T120	1		T280	1		T271	1
auto[2818572288:2952790015]	auto[1]	8	1			T370	2		T384	1		T387	1
auto[2952790016:3087007743]	auto[1]	10	1			T280	1		T360	1		T281	2
auto[3087007744:3221225471]	auto[1]	9	1			T310	2		T387	1		T254	1
auto[3221225472:3355443199]	auto[1]	9	1			T120	1		T360	1		T383	2
auto[3355443200:3489660927]	auto[1]	10	1			T373	1		T364	1		T111	1
auto[3489660928:3623878655]	auto[1]	8	1			T385	1		T351	1		T239	1
auto[3623878656:3758096383]	auto[1]	10	1			T370	1		T111	1		T281	1
auto[3758096384:3892314111]	auto[1]	7	1			T239	1		T111	1		T382	1
auto[3892314112:4026531839]	auto[1]	9	1			T120	1		T271	1		T384	1
auto[4026531840:4160749567]	auto[1]	5	1			T364	1		T111	1		T387	1
auto[4160749568:4294967295]	auto[1]	10	1			T159	1		T111	1		T390	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1409

1

T1

5

T2

4

T15

4

auto[1]

1583

1

T1

2

T2

8

T18

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T101	1		T54	4		T19	1
auto[134217728:268435455]	86	1			T1	1		T2	1		T42	1
auto[268435456:402653183]	80	1			T7	1		T196	1		T120	1
auto[402653184:536870911]	100	1			T15	1		T54	1		T27	1
auto[536870912:671088639]	102	1			T140	1		T25	1		T26	1
auto[671088640:805306367]	101	1			T41	1		T101	1		T54	3
auto[805306368:939524095]	99	1			T1	1		T43	1		T134	1
auto[939524096:1073741823]	95	1			T18	1		T43	1		T54	2
auto[1073741824:1207959551]	103	1			T101	1		T7	1		T134	1
auto[1207959552:1342177279]	82	1			T2	4		T42	1		T47	1
auto[1342177280:1476395007]	97	1			T1	1		T2	2		T43	2
auto[1476395008:1610612735]	107	1			T54	1		T269	1		T27	2
auto[1610612736:1744830463]	94	1			T54	3		T6	2		T61	2
auto[1744830464:1879048191]	78	1			T1	1		T2	1		T54	1
auto[1879048192:2013265919]	83	1			T1	1		T54	1		T26	1
auto[2013265920:2147483647]	107	1			T2	1		T43	1		T196	1
auto[2147483648:2281701375]	102	1			T2	1		T46	1		T237	1
auto[2281701376:2415919103]	82	1			T120	1		T54	1		T33	1
auto[2415919104:2550136831]	91	1			T1	1		T43	1		T101	1
auto[2550136832:2684354559]	82	1			T43	1		T54	1		T60	1
auto[2684354560:2818572287]	84	1			T54	1		T102	1		T159	1
auto[2818572288:2952790015]	106	1			T15	1		T170	2		T48	1
auto[2952790016:3087007743]	78	1			T41	1		T54	2		T269	1
auto[3087007744:3221225471]	111	1			T18	2		T54	1		T237	1
auto[3221225472:3355443199]	92	1			T41	1		T43	1		T54	2
auto[3355443200:3489660927]	82	1			T2	1		T41	1		T54	1
auto[3489660928:3623878655]	94	1			T1	1		T42	1		T8	1
auto[3623878656:3758096383]	101	1			T15	1		T41	1		T120	1
auto[3758096384:3892314111]	90	1			T15	1		T41	2		T47	1
auto[3892314112:4026531839]	106	1			T42	1		T7	1		T54	2
auto[4026531840:4160749567]	96	1			T2	1		T101	1		T54	3
auto[4160749568:4294967295]	86	1			T18	1		T120	1		T54	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T101	1		T54	3		T137	1
auto[0:134217727]	auto[1]	45	1			T54	1		T19	1		T144	1
auto[134217728:268435455]	auto[0]	32	1			T1	1		T2	1		T211	1
auto[134217728:268435455]	auto[1]	54	1			T42	1		T43	1		T159	1
auto[268435456:402653183]	auto[0]	32	1			T7	1		T67	1		T57	1
auto[268435456:402653183]	auto[1]	48	1			T196	1		T120	1		T54	1
auto[402653184:536870911]	auto[0]	46	1			T15	1		T54	1		T27	1
auto[402653184:536870911]	auto[1]	54	1			T61	1		T270	1		T212	1
auto[536870912:671088639]	auto[0]	51	1			T140	1		T61	1		T198	1
auto[536870912:671088639]	auto[1]	51	1			T25	1		T26	1		T44	1
auto[671088640:805306367]	auto[0]	50	1			T41	1		T54	1		T44	1
auto[671088640:805306367]	auto[1]	51	1			T101	1		T54	2		T159	1
auto[805306368:939524095]	auto[0]	53	1			T43	1		T196	1		T5	2
auto[805306368:939524095]	auto[1]	46	1			T1	1		T134	1		T54	2
auto[939524096:1073741823]	auto[0]	42	1			T43	1		T6	1		T391	1
auto[939524096:1073741823]	auto[1]	53	1			T18	1		T54	2		T33	1
auto[1073741824:1207959551]	auto[0]	43	1			T7	1		T52	1		T5	1
auto[1073741824:1207959551]	auto[1]	60	1			T101	1		T134	1		T120	1
auto[1207959552:1342177279]	auto[0]	34	1			T2	2		T44	1		T45	1
auto[1207959552:1342177279]	auto[1]	48	1			T2	2		T42	1		T47	1
auto[1342177280:1476395007]	auto[0]	54	1			T2	1		T43	1		T136	1
auto[1342177280:1476395007]	auto[1]	43	1			T1	1		T2	1		T43	1
auto[1476395008:1610612735]	auto[0]	52	1			T54	1		T27	1		T45	1
auto[1476395008:1610612735]	auto[1]	55	1			T269	1		T27	1		T159	1
auto[1610612736:1744830463]	auto[0]	41	1			T61	1		T65	1		T20	1
auto[1610612736:1744830463]	auto[1]	53	1			T54	3		T6	2		T61	1
auto[1744830464:1879048191]	auto[0]	37	1			T1	1		T45	1		T57	1
auto[1744830464:1879048191]	auto[1]	41	1			T2	1		T54	1		T19	1
auto[1879048192:2013265919]	auto[0]	31	1			T1	1		T54	1		T102	1
auto[1879048192:2013265919]	auto[1]	52	1			T26	1		T5	1		T38	1
auto[2013265920:2147483647]	auto[0]	56	1			T196	1		T54	1		T237	1
auto[2013265920:2147483647]	auto[1]	51	1			T2	1		T43	1		T54	2
auto[2147483648:2281701375]	auto[0]	53	1			T26	1		T44	1		T5	2
auto[2147483648:2281701375]	auto[1]	49	1			T2	1		T46	1		T237	1
auto[2281701376:2415919103]	auto[0]	36	1			T54	1		T391	1		T392	1
auto[2281701376:2415919103]	auto[1]	46	1			T120	1		T33	1		T6	1
auto[2415919104:2550136831]	auto[0]	43	1			T1	1		T43	1		T136	1
auto[2415919104:2550136831]	auto[1]	48	1			T101	1		T33	1		T6	1
auto[2550136832:2684354559]	auto[0]	39	1			T43	1		T54	1		T6	1
auto[2550136832:2684354559]	auto[1]	43	1			T60	1		T6	2		T96	1
auto[2684354560:2818572287]	auto[0]	49	1			T54	1		T102	1		T145	1
auto[2684354560:2818572287]	auto[1]	35	1			T159	1		T240	1		T214	1
auto[2818572288:2952790015]	auto[0]	49	1			T15	1		T170	1		T54	2
auto[2818572288:2952790015]	auto[1]	57	1			T170	1		T48	1		T54	1
auto[2952790016:3087007743]	auto[0]	40	1			T41	1		T54	1		T269	1
auto[2952790016:3087007743]	auto[1]	38	1			T54	1		T6	1		T70	1
auto[3087007744:3221225471]	auto[0]	50	1			T18	1		T44	1		T211	1
auto[3087007744:3221225471]	auto[1]	61	1			T18	1		T54	1		T237	1
auto[3221225472:3355443199]	auto[0]	40	1			T102	1		T145	1		T30	1
auto[3221225472:3355443199]	auto[1]	52	1			T41	1		T43	1		T54	2
auto[3355443200:3489660927]	auto[0]	42	1			T41	1		T57	1		T214	1
auto[3355443200:3489660927]	auto[1]	40	1			T2	1		T54	1		T215	1
auto[3489660928:3623878655]	auto[0]	33	1			T1	1		T54	2		T198	1
auto[3489660928:3623878655]	auto[1]	61	1			T42	1		T8	1		T54	2
auto[3623878656:3758096383]	auto[0]	50	1			T15	1		T41	1		T120	1
auto[3623878656:3758096383]	auto[1]	51	1			T140	1		T25	1		T48	1
auto[3758096384:3892314111]	auto[0]	47	1			T15	1		T41	1		T269	1
auto[3758096384:3892314111]	auto[1]	43	1			T41	1		T47	1		T5	2
auto[3892314112:4026531839]	auto[0]	53	1			T7	1		T54	1		T27	1
auto[3892314112:4026531839]	auto[1]	53	1			T42	1		T54	1		T45	1
auto[4026531840:4160749567]	auto[0]	42	1			T54	2		T52	2		T137	1
auto[4026531840:4160749567]	auto[1]	54	1			T2	1		T101	1		T54	1
auto[4160749568:4294967295]	auto[0]	39	1			T54	1		T391	1		T93	1
auto[4160749568:4294967295]	auto[1]	47	1			T18	1		T120	1		T159	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1441

1

T1

6

T2

5

T15

3

auto[1]

1537

1

T1

1

T2

7

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T43	1		T54	3		T237	1
auto[134217728:268435455]	89	1			T43	1		T25	1		T102	1
auto[268435456:402653183]	89	1			T5	2		T160	1		T33	1
auto[402653184:536870911]	86	1			T54	1		T136	1		T5	1
auto[536870912:671088639]	94	1			T54	2		T44	1		T6	1
auto[671088640:805306367]	86	1			T54	2		T5	3		T6	1
auto[805306368:939524095]	86	1			T1	1		T42	1		T269	1
auto[939524096:1073741823]	84	1			T2	2		T42	1		T8	1
auto[1073741824:1207959551]	95	1			T42	1		T101	1		T47	1
auto[1207959552:1342177279]	98	1			T54	1		T137	1		T5	1
auto[1342177280:1476395007]	92	1			T15	1		T41	1		T120	1
auto[1476395008:1610612735]	81	1			T2	1		T170	1		T54	4
auto[1610612736:1744830463]	82	1			T18	1		T41	1		T54	4
auto[1744830464:1879048191]	106	1			T1	1		T7	1		T196	1
auto[1879048192:2013265919]	105	1			T43	1		T170	1		T54	1
auto[2013265920:2147483647]	102	1			T1	1		T18	1		T42	1
auto[2147483648:2281701375]	86	1			T2	1		T15	1		T41	1
auto[2281701376:2415919103]	94	1			T1	2		T2	2		T41	1
auto[2415919104:2550136831]	102	1			T2	1		T7	1		T25	1
auto[2550136832:2684354559]	121	1			T1	1		T43	1		T7	1
auto[2684354560:2818572287]	83	1			T15	1		T43	1		T48	1
auto[2818572288:2952790015]	80	1			T120	1		T54	2		T52	1
auto[2952790016:3087007743]	110	1			T15	1		T41	2		T43	1
auto[3087007744:3221225471]	106	1			T2	1		T101	2		T54	2
auto[3221225472:3355443199]	103	1			T1	1		T41	1		T43	1
auto[3355443200:3489660927]	81	1			T2	1		T120	1		T54	2
auto[3489660928:3623878655]	83	1			T2	2		T101	1		T196	1
auto[3623878656:3758096383]	100	1			T46	1		T43	1		T54	1
auto[3758096384:3892314111]	91	1			T18	1		T140	1		T54	2
auto[3892314112:4026531839]	81	1			T137	1		T45	1		T61	1
auto[4026531840:4160749567]	96	1			T2	1		T196	1		T120	1
auto[4160749568:4294967295]	89	1			T18	1		T43	1		T44	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T43	1		T54	2		T237	1
auto[0:134217727]	auto[1]	52	1			T54	1		T26	1		T159	1
auto[134217728:268435455]	auto[0]	42	1			T43	1		T102	1		T45	1
auto[134217728:268435455]	auto[1]	47	1			T25	1		T55	1		T160	1
auto[268435456:402653183]	auto[0]	43	1			T5	2		T33	1		T61	2
auto[268435456:402653183]	auto[1]	46	1			T160	1		T70	2		T280	1
auto[402653184:536870911]	auto[0]	35	1			T136	1		T5	1		T160	1
auto[402653184:536870911]	auto[1]	51	1			T54	1		T6	2		T61	1
auto[536870912:671088639]	auto[0]	46	1			T54	2		T6	1		T57	1
auto[536870912:671088639]	auto[1]	48	1			T44	1		T61	3		T70	1
auto[671088640:805306367]	auto[0]	39	1			T54	1		T6	1		T61	1
auto[671088640:805306367]	auto[1]	47	1			T54	1		T5	3		T61	1
auto[805306368:939524095]	auto[0]	32	1			T269	1		T102	1		T6	1
auto[805306368:939524095]	auto[1]	54	1			T1	1		T42	1		T44	1
auto[939524096:1073741823]	auto[0]	38	1			T8	1		T170	1		T33	1
auto[939524096:1073741823]	auto[1]	46	1			T2	2		T42	1		T48	1
auto[1073741824:1207959551]	auto[0]	46	1			T101	1		T103	1		T60	1
auto[1073741824:1207959551]	auto[1]	49	1			T42	1		T47	1		T214	1
auto[1207959552:1342177279]	auto[0]	49	1			T137	1		T5	1		T145	1
auto[1207959552:1342177279]	auto[1]	49	1			T54	1		T160	1		T284	1
auto[1342177280:1476395007]	auto[0]	47	1			T15	1		T120	1		T53	1
auto[1342177280:1476395007]	auto[1]	45	1			T41	1		T47	1		T136	1
auto[1476395008:1610612735]	auto[0]	37	1			T54	3		T136	2		T211	1
auto[1476395008:1610612735]	auto[1]	44	1			T2	1		T170	1		T54	1
auto[1610612736:1744830463]	auto[0]	44	1			T41	1		T54	1		T45	1
auto[1610612736:1744830463]	auto[1]	38	1			T18	1		T54	3		T137	1
auto[1744830464:1879048191]	auto[0]	54	1			T1	1		T7	1		T196	1
auto[1744830464:1879048191]	auto[1]	52	1			T120	1		T54	2		T102	1
auto[1879048192:2013265919]	auto[0]	46	1			T43	1		T170	1		T61	2
auto[1879048192:2013265919]	auto[1]	59	1			T54	1		T237	1		T6	2
auto[2013265920:2147483647]	auto[0]	59	1			T1	1		T269	1		T52	1
auto[2013265920:2147483647]	auto[1]	43	1			T18	1		T42	1		T54	1
auto[2147483648:2281701375]	auto[0]	40	1			T2	1		T15	1		T26	1
auto[2147483648:2281701375]	auto[1]	46	1			T41	1		T134	1		T54	1
auto[2281701376:2415919103]	auto[0]	39	1			T1	2		T2	1		T41	1
auto[2281701376:2415919103]	auto[1]	55	1			T2	1		T8	1		T237	1
auto[2415919104:2550136831]	auto[0]	50	1			T7	1		T19	1		T5	2
auto[2415919104:2550136831]	auto[1]	52	1			T2	1		T25	1		T54	1
auto[2550136832:2684354559]	auto[0]	65	1			T1	1		T43	1		T7	1
auto[2550136832:2684354559]	auto[1]	56	1			T54	1		T5	1		T33	1
auto[2684354560:2818572287]	auto[0]	43	1			T54	2		T44	1		T55	1
auto[2684354560:2818572287]	auto[1]	40	1			T15	1		T43	1		T48	1
auto[2818572288:2952790015]	auto[0]	34	1			T54	1		T52	1		T61	1
auto[2818572288:2952790015]	auto[1]	46	1			T120	1		T54	1		T103	1
auto[2952790016:3087007743]	auto[0]	58	1			T15	1		T41	1		T5	1
auto[2952790016:3087007743]	auto[1]	52	1			T41	1		T43	1		T54	1
auto[3087007744:3221225471]	auto[0]	52	1			T54	1		T211	1		T61	1
auto[3087007744:3221225471]	auto[1]	54	1			T2	1		T101	2		T54	1
auto[3221225472:3355443199]	auto[0]	49	1			T1	1		T41	1		T54	2
auto[3221225472:3355443199]	auto[1]	54	1			T43	1		T134	1		T26	1
auto[3355443200:3489660927]	auto[0]	44	1			T2	1		T52	1		T44	1
auto[3355443200:3489660927]	auto[1]	37	1			T120	1		T54	2		T137	1
auto[3489660928:3623878655]	auto[0]	43	1			T2	2		T196	1		T54	1
auto[3489660928:3623878655]	auto[1]	40	1			T101	1		T5	1		T160	1
auto[3623878656:3758096383]	auto[0]	51	1			T43	1		T27	1		T137	1
auto[3623878656:3758096383]	auto[1]	49	1			T46	1		T54	1		T6	1
auto[3758096384:3892314111]	auto[0]	40	1			T140	1		T54	1		T6	2
auto[3758096384:3892314111]	auto[1]	51	1			T18	1		T54	1		T159	1
auto[3892314112:4026531839]	auto[0]	39	1			T137	1		T45	1		T391	1
auto[3892314112:4026531839]	auto[1]	42	1			T61	1		T97	1		T20	1
auto[4026531840:4160749567]	auto[0]	47	1			T140	1		T54	1		T27	1
auto[4026531840:4160749567]	auto[1]	49	1			T2	1		T196	1		T120	1
auto[4160749568:4294967295]	auto[0]	45	1			T43	1		T44	2		T61	2
auto[4160749568:4294967295]	auto[1]	44	1			T18	1		T5	1		T147	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1423

1

T1

5

T2

5

T15

3

auto[1]

1557

1

T1

2

T2

7

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T2	1		T54	1		T102	1
auto[134217728:268435455]	84	1			T54	1		T237	1		T19	1
auto[268435456:402653183]	85	1			T1	1		T54	1		T237	1
auto[402653184:536870911]	97	1			T120	2		T140	1		T54	2
auto[536870912:671088639]	105	1			T1	2		T2	2		T15	2
auto[671088640:805306367]	77	1			T18	1		T41	1		T42	1
auto[805306368:939524095]	88	1			T2	1		T120	1		T25	1
auto[939524096:1073741823]	102	1			T18	1		T43	2		T101	1
auto[1073741824:1207959551]	120	1			T101	1		T54	3		T27	2
auto[1207959552:1342177279]	87	1			T2	1		T41	1		T5	2
auto[1342177280:1476395007]	102	1			T1	1		T41	1		T101	1
auto[1476395008:1610612735]	78	1			T18	1		T43	1		T269	1
auto[1610612736:1744830463]	81	1			T42	1		T54	1		T269	1
auto[1744830464:1879048191]	81	1			T48	1		T54	1		T160	1
auto[1879048192:2013265919]	77	1			T2	1		T134	1		T120	1
auto[2013265920:2147483647]	96	1			T15	1		T134	1		T54	2
auto[2147483648:2281701375]	103	1			T2	1		T54	3		T269	1
auto[2281701376:2415919103]	103	1			T42	1		T7	1		T54	1
auto[2415919104:2550136831]	80	1			T46	1		T43	1		T54	1
auto[2550136832:2684354559]	98	1			T2	1		T41	1		T43	1
auto[2684354560:2818572287]	86	1			T18	1		T43	1		T101	1
auto[2818572288:2952790015]	98	1			T41	1		T54	1		T159	1
auto[2952790016:3087007743]	88	1			T1	1		T41	1		T137	1
auto[3087007744:3221225471]	108	1			T47	1		T54	1		T26	1
auto[3221225472:3355443199]	96	1			T15	1		T25	1		T136	1
auto[3355443200:3489660927]	80	1			T1	1		T2	2		T8	2
auto[3489660928:3623878655]	112	1			T2	1		T41	1		T43	1
auto[3623878656:3758096383]	101	1			T54	3		T237	1		T26	1
auto[3758096384:3892314111]	91	1			T42	1		T101	1		T140	1
auto[3892314112:4026531839]	98	1			T7	1		T196	1		T102	1
auto[4026531840:4160749567]	86	1			T2	1		T43	1		T196	1
auto[4160749568:4294967295]	96	1			T1	1		T7	1		T54	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	37	1			T6	1		T61	1		T70	2
auto[0:134217727]	auto[1]	59	1			T2	1		T54	1		T102	1
auto[134217728:268435455]	auto[0]	36	1			T237	1		T19	1		T26	1
auto[134217728:268435455]	auto[1]	48	1			T54	1		T6	1		T260	1
auto[268435456:402653183]	auto[0]	39	1			T1	1		T54	1		T44	1
auto[268435456:402653183]	auto[1]	46	1			T237	1		T44	1		T5	1
auto[402653184:536870911]	auto[0]	41	1			T52	1		T55	1		T5	1
auto[402653184:536870911]	auto[1]	56	1			T120	2		T140	1		T54	2
auto[536870912:671088639]	auto[0]	41	1			T1	1		T15	1		T43	1
auto[536870912:671088639]	auto[1]	64	1			T1	1		T2	2		T15	1
auto[671088640:805306367]	auto[0]	42	1			T42	1		T102	1		T213	1
auto[671088640:805306367]	auto[1]	35	1			T18	1		T41	1		T47	1
auto[805306368:939524095]	auto[0]	43	1			T170	1		T127	1		T61	1
auto[805306368:939524095]	auto[1]	45	1			T2	1		T120	1		T25	1
auto[939524096:1073741823]	auto[0]	51	1			T18	1		T43	2		T6	1
auto[939524096:1073741823]	auto[1]	51	1			T101	1		T54	3		T19	1
auto[1073741824:1207959551]	auto[0]	63	1			T101	1		T54	1		T27	2
auto[1073741824:1207959551]	auto[1]	57	1			T54	2		T61	4		T70	3
auto[1207959552:1342177279]	auto[0]	43	1			T41	1		T145	1		T147	1
auto[1207959552:1342177279]	auto[1]	44	1			T2	1		T5	2		T160	1
auto[1342177280:1476395007]	auto[0]	43	1			T1	1		T41	1		T44	1
auto[1342177280:1476395007]	auto[1]	59	1			T101	1		T120	1		T48	1
auto[1476395008:1610612735]	auto[0]	44	1			T269	1		T27	1		T284	1
auto[1476395008:1610612735]	auto[1]	34	1			T18	1		T43	1		T5	1
auto[1610612736:1744830463]	auto[0]	35	1			T269	1		T44	1		T5	1
auto[1610612736:1744830463]	auto[1]	46	1			T42	1		T54	1		T5	2
auto[1744830464:1879048191]	auto[0]	40	1			T160	1		T28	1		T93	1
auto[1744830464:1879048191]	auto[1]	41	1			T48	1		T54	1		T70	2
auto[1879048192:2013265919]	auto[0]	42	1			T2	1		T120	1		T54	3
auto[1879048192:2013265919]	auto[1]	35	1			T134	1		T170	1		T54	1
auto[2013265920:2147483647]	auto[0]	46	1			T15	1		T54	1		T159	1
auto[2013265920:2147483647]	auto[1]	50	1			T134	1		T54	1		T6	1
auto[2147483648:2281701375]	auto[0]	52	1			T2	1		T54	1		T269	1
auto[2147483648:2281701375]	auto[1]	51	1			T54	2		T160	1		T61	1
auto[2281701376:2415919103]	auto[0]	53	1			T7	1		T54	1		T269	1
auto[2281701376:2415919103]	auto[1]	50	1			T42	1		T102	1		T5	1
auto[2415919104:2550136831]	auto[0]	34	1			T46	1		T54	1		T6	1
auto[2415919104:2550136831]	auto[1]	46	1			T43	1		T33	1		T61	1
auto[2550136832:2684354559]	auto[0]	47	1			T2	1		T41	1		T52	1
auto[2550136832:2684354559]	auto[1]	51	1			T43	1		T237	1		T144	1
auto[2684354560:2818572287]	auto[0]	47	1			T43	1		T54	1		T102	1
auto[2684354560:2818572287]	auto[1]	39	1			T18	1		T101	1		T54	1
auto[2818572288:2952790015]	auto[0]	33	1			T45	1		T53	1		T70	2
auto[2818572288:2952790015]	auto[1]	65	1			T41	1		T54	1		T159	1
auto[2952790016:3087007743]	auto[0]	39	1			T1	1		T41	1		T103	1
auto[2952790016:3087007743]	auto[1]	49	1			T137	1		T5	1		T103	1
auto[3087007744:3221225471]	auto[0]	53	1			T137	2		T160	1		T6	2
auto[3087007744:3221225471]	auto[1]	55	1			T47	1		T54	1		T26	1
auto[3221225472:3355443199]	auto[0]	46	1			T15	1		T136	1		T5	2
auto[3221225472:3355443199]	auto[1]	50	1			T25	1		T147	1		T33	1
auto[3355443200:3489660927]	auto[0]	43	1			T1	1		T2	1		T8	1
auto[3355443200:3489660927]	auto[1]	37	1			T2	1		T8	1		T54	1
auto[3489660928:3623878655]	auto[0]	60	1			T2	1		T41	1		T170	1
auto[3489660928:3623878655]	auto[1]	52	1			T43	1		T54	2		T159	2
auto[3623878656:3758096383]	auto[0]	46	1			T54	1		T237	1		T6	2
auto[3623878656:3758096383]	auto[1]	55	1			T54	2		T26	1		T137	1
auto[3758096384:3892314111]	auto[0]	42	1			T140	1		T54	1		T44	1
auto[3758096384:3892314111]	auto[1]	49	1			T42	1		T101	1		T54	1
auto[3892314112:4026531839]	auto[0]	51	1			T7	1		T196	1		T102	1
auto[3892314112:4026531839]	auto[1]	47	1			T5	1		T61	2		T270	1
auto[4026531840:4160749567]	auto[0]	49	1			T43	1		T196	1		T54	2
auto[4026531840:4160749567]	auto[1]	37	1			T2	1		T54	1		T144	1
auto[4160749568:4294967295]	auto[0]	42	1			T7	1		T137	1		T6	1
auto[4160749568:4294967295]	auto[1]	54	1			T1	1		T54	1		T5	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1433

1

T1

6

T2

6

T15

3

auto[1]

1554

1

T1

1

T2

6

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	81	1			T41	1		T43	1		T196	1
auto[134217728:268435455]	91	1			T2	1		T237	1		T269	1
auto[268435456:402653183]	87	1			T101	1		T170	1		T54	2
auto[402653184:536870911]	107	1			T54	1		T237	1		T27	1
auto[536870912:671088639]	93	1			T1	1		T46	1		T101	1
auto[671088640:805306367]	92	1			T42	1		T7	1		T8	1
auto[805306368:939524095]	97	1			T120	1		T54	3		T136	1
auto[939524096:1073741823]	111	1			T1	1		T15	1		T54	3
auto[1073741824:1207959551]	98	1			T41	1		T43	1		T101	1
auto[1207959552:1342177279]	80	1			T54	1		T137	2		T5	1
auto[1342177280:1476395007]	95	1			T2	1		T18	1		T43	1
auto[1476395008:1610612735]	79	1			T2	2		T15	2		T25	1
auto[1610612736:1744830463]	93	1			T2	1		T41	1		T101	1
auto[1744830464:1879048191]	98	1			T1	1		T41	1		T170	1
auto[1879048192:2013265919]	93	1			T43	1		T134	1		T54	1
auto[2013265920:2147483647]	97	1			T1	1		T41	1		T7	1
auto[2147483648:2281701375]	86	1			T54	1		T237	1		T159	1
auto[2281701376:2415919103]	95	1			T2	3		T42	1		T120	1
auto[2415919104:2550136831]	100	1			T43	1		T26	1		T211	1
auto[2550136832:2684354559]	99	1			T140	2		T54	4		T27	1
auto[2684354560:2818572287]	107	1			T1	1		T43	1		T120	1
auto[2818572288:2952790015]	91	1			T54	1		T27	1		T44	1
auto[2952790016:3087007743]	98	1			T1	2		T18	1		T43	1
auto[3087007744:3221225471]	88	1			T43	1		T7	1		T47	1
auto[3221225472:3355443199]	90	1			T2	1		T18	1		T120	1
auto[3355443200:3489660927]	85	1			T41	1		T42	1		T47	1
auto[3489660928:3623878655]	88	1			T120	1		T54	1		T52	1
auto[3623878656:3758096383]	92	1			T42	1		T54	1		T26	1
auto[3758096384:3892314111]	88	1			T2	2		T54	3		T269	1
auto[3892314112:4026531839]	93	1			T18	1		T41	1		T101	1
auto[4026531840:4160749567]	96	1			T2	1		T15	1		T196	1
auto[4160749568:4294967295]	99	1			T43	1		T54	1		T45	1