Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1422

1

T1

6

T2

4

T15

3

auto[1]

1564

1

T1

1

T2

8

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T1	1		T43	1		T54	3
auto[134217728:268435455]	95	1			T2	2		T41	1		T8	1
auto[268435456:402653183]	104	1			T2	1		T18	1		T42	1
auto[402653184:536870911]	74	1			T43	1		T101	1		T54	1
auto[536870912:671088639]	102	1			T2	1		T7	1		T25	1
auto[671088640:805306367]	92	1			T120	2		T5	1		T61	4
auto[805306368:939524095]	98	1			T2	2		T41	1		T43	1
auto[939524096:1073741823]	91	1			T41	1		T43	1		T101	1
auto[1073741824:1207959551]	90	1			T101	1		T134	1		T170	1
auto[1207959552:1342177279]	77	1			T1	1		T2	1		T136	1
auto[1342177280:1476395007]	94	1			T15	1		T41	1		T54	1
auto[1476395008:1610612735]	100	1			T134	1		T54	2		T44	1
auto[1610612736:1744830463]	96	1			T54	1		T5	2		T145	1
auto[1744830464:1879048191]	91	1			T101	1		T52	1		T102	1
auto[1879048192:2013265919]	97	1			T1	1		T101	1		T54	2
auto[2013265920:2147483647]	79	1			T15	1		T41	1		T43	1
auto[2147483648:2281701375]	79	1			T140	1		T48	1		T54	1
auto[2281701376:2415919103]	89	1			T102	1		T61	2		T240	1
auto[2415919104:2550136831]	91	1			T1	1		T120	1		T47	1
auto[2550136832:2684354559]	98	1			T41	1		T5	1		T33	1
auto[2684354560:2818572287]	96	1			T237	1		T26	1		T145	1
auto[2818572288:2952790015]	96	1			T2	1		T42	1		T196	1
auto[2952790016:3087007743]	116	1			T2	1		T15	1		T26	1
auto[3087007744:3221225471]	91	1			T1	1		T46	1		T120	1
auto[3221225472:3355443199]	77	1			T54	5		T33	1		T6	1
auto[3355443200:3489660927]	106	1			T1	1		T2	2		T15	1
auto[3489660928:3623878655]	100	1			T7	1		T54	3		T237	1
auto[3623878656:3758096383]	110	1			T1	1		T2	1		T43	1
auto[3758096384:3892314111]	85	1			T18	1		T7	1		T120	1
auto[3892314112:4026531839]	103	1			T18	1		T43	1		T25	1
auto[4026531840:4160749567]	84	1			T44	1		T5	1		T147	1
auto[4160749568:4294967295]	89	1			T41	1		T42	2		T54	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T1	1		T43	1		T54	2
auto[0:134217727]	auto[1]	50	1			T54	1		T44	1		T6	1
auto[134217728:268435455]	auto[0]	48	1			T2	1		T41	1		T170	1
auto[134217728:268435455]	auto[1]	47	1			T2	1		T8	1		T137	1
auto[268435456:402653183]	auto[0]	48	1			T43	1		T269	1		T52	1
auto[268435456:402653183]	auto[1]	56	1			T2	1		T18	1		T42	1
auto[402653184:536870911]	auto[0]	27	1			T43	1		T45	1		T96	1
auto[402653184:536870911]	auto[1]	47	1			T101	1		T54	1		T5	1
auto[536870912:671088639]	auto[0]	51	1			T7	1		T54	1		T27	2
auto[536870912:671088639]	auto[1]	51	1			T2	1		T25	1		T19	1
auto[671088640:805306367]	auto[0]	44	1			T5	1		T61	2		T198	1
auto[671088640:805306367]	auto[1]	48	1			T120	2		T61	2		T96	1
auto[805306368:939524095]	auto[0]	51	1			T2	2		T43	1		T196	2
auto[805306368:939524095]	auto[1]	47	1			T41	1		T47	1		T54	2
auto[939524096:1073741823]	auto[0]	39	1			T54	1		T5	1		T61	1
auto[939524096:1073741823]	auto[1]	52	1			T41	1		T43	1		T101	1
auto[1073741824:1207959551]	auto[0]	38	1			T45	1		T67	1		T57	1
auto[1073741824:1207959551]	auto[1]	52	1			T101	1		T134	1		T170	1
auto[1207959552:1342177279]	auto[0]	31	1			T1	1		T136	1		T61	2
auto[1207959552:1342177279]	auto[1]	46	1			T2	1		T33	1		T53	1
auto[1342177280:1476395007]	auto[0]	50	1			T15	1		T237	1		T136	1
auto[1342177280:1476395007]	auto[1]	44	1			T41	1		T54	1		T27	1
auto[1476395008:1610612735]	auto[0]	49	1			T54	1		T44	1		T159	1
auto[1476395008:1610612735]	auto[1]	51	1			T134	1		T54	1		T136	1
auto[1610612736:1744830463]	auto[0]	45	1			T5	1		T160	1		T53	1
auto[1610612736:1744830463]	auto[1]	51	1			T54	1		T5	1		T145	1
auto[1744830464:1879048191]	auto[0]	53	1			T52	1		T45	1		T391	2
auto[1744830464:1879048191]	auto[1]	38	1			T101	1		T102	1		T5	1
auto[1879048192:2013265919]	auto[0]	44	1			T237	1		T44	1		T211	1
auto[1879048192:2013265919]	auto[1]	53	1			T1	1		T101	1		T54	2
auto[2013265920:2147483647]	auto[0]	36	1			T15	1		T41	1		T43	1
auto[2013265920:2147483647]	auto[1]	43	1			T54	1		T102	1		T6	3
auto[2147483648:2281701375]	auto[0]	34	1			T54	1		T6	1		T61	1
auto[2147483648:2281701375]	auto[1]	45	1			T140	1		T48	1		T159	1
auto[2281701376:2415919103]	auto[0]	37	1			T102	1		T240	1		T30	1
auto[2281701376:2415919103]	auto[1]	52	1			T61	2		T241	1		T82	2
auto[2415919104:2550136831]	auto[0]	48	1			T1	1		T120	1		T54	1
auto[2415919104:2550136831]	auto[1]	43	1			T47	1		T170	1		T48	1
auto[2550136832:2684354559]	auto[0]	53	1			T41	1		T5	1		T33	1
auto[2550136832:2684354559]	auto[1]	45	1			T6	3		T87	1		T70	1
auto[2684354560:2818572287]	auto[0]	51	1			T145	1		T6	1		T61	1
auto[2684354560:2818572287]	auto[1]	45	1			T237	1		T26	1		T33	1
auto[2818572288:2952790015]	auto[0]	42	1			T2	1		T54	1		T45	1
auto[2818572288:2952790015]	auto[1]	54	1			T42	1		T196	1		T54	1
auto[2952790016:3087007743]	auto[0]	56	1			T52	1		T160	1		T57	1
auto[2952790016:3087007743]	auto[1]	60	1			T2	1		T15	1		T26	1
auto[3087007744:3221225471]	auto[0]	42	1			T1	1		T140	1		T8	1
auto[3087007744:3221225471]	auto[1]	49	1			T46	1		T120	1		T54	1
auto[3221225472:3355443199]	auto[0]	39	1			T54	3		T33	1		T199	1
auto[3221225472:3355443199]	auto[1]	38	1			T54	2		T6	1		T284	1
auto[3355443200:3489660927]	auto[0]	49	1			T1	1		T15	1		T44	1
auto[3355443200:3489660927]	auto[1]	57	1			T2	2		T18	1		T43	1
auto[3489660928:3623878655]	auto[0]	47	1			T7	1		T52	1		T44	1
auto[3489660928:3623878655]	auto[1]	53	1			T54	3		T237	1		T55	1
auto[3623878656:3758096383]	auto[0]	63	1			T1	1		T54	1		T19	1
auto[3623878656:3758096383]	auto[1]	47	1			T2	1		T43	1		T54	2
auto[3758096384:3892314111]	auto[0]	39	1			T7	1		T54	1		T137	2
auto[3758096384:3892314111]	auto[1]	46	1			T18	1		T120	1		T5	2
auto[3892314112:4026531839]	auto[0]	43	1			T26	1		T27	1		T5	2
auto[3892314112:4026531839]	auto[1]	60	1			T18	1		T43	1		T25	1
auto[4026531840:4160749567]	auto[0]	38	1			T44	1		T5	1		T93	1
auto[4026531840:4160749567]	auto[1]	46	1			T147	1		T61	2		T213	2
auto[4160749568:4294967295]	auto[0]	41	1			T41	1		T54	1		T102	1
auto[4160749568:4294967295]	auto[1]	48	1			T42	2		T54	3		T6	1