Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.07 97.75 98.57 100.00 99.11 98.41 91.71


Total test records in report: 1094
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T1011 /workspace/coverage/default/46.keymgr_lc_disable.1084203403 Feb 04 03:25:35 PM PST 24 Feb 04 03:25:42 PM PST 24 483912644 ps
T1012 /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3608338257 Feb 04 03:25:06 PM PST 24 Feb 04 03:25:15 PM PST 24 137379707 ps
T1013 /workspace/coverage/default/10.keymgr_sideload_aes.436164491 Feb 04 03:21:42 PM PST 24 Feb 04 03:21:49 PM PST 24 2039034551 ps
T1014 /workspace/coverage/default/16.keymgr_custom_cm.186406472 Feb 04 03:22:41 PM PST 24 Feb 04 03:22:51 PM PST 24 140899974 ps
T1015 /workspace/coverage/default/42.keymgr_sync_async_fault_cross.132205311 Feb 04 03:25:12 PM PST 24 Feb 04 03:25:21 PM PST 24 81018894 ps
T1016 /workspace/coverage/default/19.keymgr_sideload_kmac.820015841 Feb 04 03:22:55 PM PST 24 Feb 04 03:22:59 PM PST 24 388646855 ps
T1017 /workspace/coverage/default/5.keymgr_lc_disable.1135626732 Feb 04 03:21:09 PM PST 24 Feb 04 03:21:18 PM PST 24 296011319 ps
T1018 /workspace/coverage/default/28.keymgr_random.1123882868 Feb 04 03:24:10 PM PST 24 Feb 04 03:24:14 PM PST 24 74542575 ps
T1019 /workspace/coverage/default/47.keymgr_smoke.208184596 Feb 04 03:25:43 PM PST 24 Feb 04 03:25:47 PM PST 24 240637409 ps
T1020 /workspace/coverage/default/42.keymgr_sw_invalid_input.2773966085 Feb 04 03:25:09 PM PST 24 Feb 04 03:25:33 PM PST 24 693608193 ps
T1021 /workspace/coverage/default/35.keymgr_stress_all.2969421293 Feb 04 03:24:49 PM PST 24 Feb 04 03:25:27 PM PST 24 1756208787 ps
T1022 /workspace/coverage/default/1.keymgr_alert_test.2770610315 Feb 04 03:20:16 PM PST 24 Feb 04 03:20:18 PM PST 24 32994834 ps
T220 /workspace/coverage/default/43.keymgr_custom_cm.1495823951 Feb 04 03:25:10 PM PST 24 Feb 04 03:25:21 PM PST 24 109139491 ps
T1023 /workspace/coverage/default/36.keymgr_sw_invalid_input.3172348221 Feb 04 03:25:02 PM PST 24 Feb 04 03:25:09 PM PST 24 124200970 ps
T1024 /workspace/coverage/default/11.keymgr_sideload_protect.3700882323 Feb 04 03:22:08 PM PST 24 Feb 04 03:22:16 PM PST 24 327303547 ps
T1025 /workspace/coverage/default/39.keymgr_direct_to_disabled.248522137 Feb 04 03:25:08 PM PST 24 Feb 04 03:25:19 PM PST 24 102962229 ps
T1026 /workspace/coverage/default/33.keymgr_sw_invalid_input.2800766667 Feb 04 03:24:26 PM PST 24 Feb 04 03:25:03 PM PST 24 1224389219 ps
T331 /workspace/coverage/default/46.keymgr_stress_all.3207389446 Feb 04 03:25:37 PM PST 24 Feb 04 03:25:54 PM PST 24 276234764 ps
T389 /workspace/coverage/default/23.keymgr_cfg_regwen.4007511896 Feb 04 03:23:22 PM PST 24 Feb 04 03:23:34 PM PST 24 730491448 ps
T1027 /workspace/coverage/default/43.keymgr_sideload_aes.2726519393 Feb 04 03:25:12 PM PST 24 Feb 04 03:26:01 PM PST 24 1629609349 ps
T1028 /workspace/coverage/default/18.keymgr_alert_test.808345523 Feb 04 03:22:51 PM PST 24 Feb 04 03:22:55 PM PST 24 10159869 ps
T1029 /workspace/coverage/default/32.keymgr_stress_all.2938431713 Feb 04 03:24:17 PM PST 24 Feb 04 03:24:26 PM PST 24 1340248262 ps
T1030 /workspace/coverage/default/42.keymgr_sideload_otbn.4146903089 Feb 04 03:25:01 PM PST 24 Feb 04 03:25:05 PM PST 24 59443487 ps
T1031 /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1289397004 Feb 04 03:22:19 PM PST 24 Feb 04 03:22:26 PM PST 24 241122300 ps
T1032 /workspace/coverage/default/10.keymgr_lc_disable.979113922 Feb 04 03:21:50 PM PST 24 Feb 04 03:21:56 PM PST 24 379646763 ps
T1033 /workspace/coverage/default/34.keymgr_sideload.567150869 Feb 04 03:24:32 PM PST 24 Feb 04 03:24:37 PM PST 24 155444409 ps
T1034 /workspace/coverage/default/5.keymgr_sideload.1357616257 Feb 04 03:20:54 PM PST 24 Feb 04 03:21:01 PM PST 24 429030178 ps
T1035 /workspace/coverage/default/36.keymgr_direct_to_disabled.3455287091 Feb 04 03:25:01 PM PST 24 Feb 04 03:25:06 PM PST 24 77435586 ps
T358 /workspace/coverage/default/24.keymgr_cfg_regwen.1476887806 Feb 04 03:23:35 PM PST 24 Feb 04 03:23:46 PM PST 24 532123839 ps
T1036 /workspace/coverage/default/4.keymgr_stress_all.681262767 Feb 04 03:20:53 PM PST 24 Feb 04 03:21:29 PM PST 24 4244325093 ps
T1037 /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4249750379 Feb 04 03:23:26 PM PST 24 Feb 04 03:23:42 PM PST 24 2035340774 ps
T388 /workspace/coverage/default/31.keymgr_cfg_regwen.2325987005 Feb 04 03:24:14 PM PST 24 Feb 04 03:24:25 PM PST 24 182213350 ps
T229 /workspace/coverage/default/14.keymgr_stress_all.1469719024 Feb 04 03:22:25 PM PST 24 Feb 04 03:23:05 PM PST 24 1992689403 ps
T1038 /workspace/coverage/default/37.keymgr_direct_to_disabled.1375705034 Feb 04 03:25:04 PM PST 24 Feb 04 03:25:14 PM PST 24 287700505 ps
T1039 /workspace/coverage/default/7.keymgr_direct_to_disabled.1274103021 Feb 04 03:21:23 PM PST 24 Feb 04 03:21:28 PM PST 24 1755776891 ps
T1040 /workspace/coverage/default/24.keymgr_sideload_protect.3676153593 Feb 04 03:23:37 PM PST 24 Feb 04 03:23:44 PM PST 24 109670558 ps
T1041 /workspace/coverage/default/20.keymgr_sideload_aes.2487574224 Feb 04 03:22:59 PM PST 24 Feb 04 03:23:37 PM PST 24 3645596610 ps
T1042 /workspace/coverage/default/37.keymgr_kmac_rsp_err.1444609710 Feb 04 03:24:54 PM PST 24 Feb 04 03:25:58 PM PST 24 27101278931 ps
T1043 /workspace/coverage/default/10.keymgr_smoke.3044152878 Feb 04 03:21:45 PM PST 24 Feb 04 03:22:12 PM PST 24 4014228723 ps
T1044 /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3874797588 Feb 04 03:24:19 PM PST 24 Feb 04 03:24:23 PM PST 24 50957668 ps
T1045 /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3945815198 Feb 04 03:22:33 PM PST 24 Feb 04 03:22:51 PM PST 24 2587883240 ps
T401 /workspace/coverage/default/46.keymgr_cfg_regwen.2374588609 Feb 04 03:25:35 PM PST 24 Feb 04 03:25:43 PM PST 24 116089093 ps
T1046 /workspace/coverage/default/15.keymgr_random.4264888689 Feb 04 03:22:39 PM PST 24 Feb 04 03:22:51 PM PST 24 587000508 ps
T1047 /workspace/coverage/default/23.keymgr_smoke.1099048052 Feb 04 03:23:24 PM PST 24 Feb 04 03:23:28 PM PST 24 103215611 ps
T1048 /workspace/coverage/default/3.keymgr_cfg_regwen.1083012700 Feb 04 03:20:33 PM PST 24 Feb 04 03:20:43 PM PST 24 432177232 ps
T1049 /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2183010255 Feb 04 03:23:34 PM PST 24 Feb 04 03:23:39 PM PST 24 53147193 ps
T1050 /workspace/coverage/default/11.keymgr_alert_test.3047901977 Feb 04 03:22:11 PM PST 24 Feb 04 03:22:13 PM PST 24 14297574 ps
T1051 /workspace/coverage/default/40.keymgr_alert_test.3436696914 Feb 04 03:25:08 PM PST 24 Feb 04 03:25:16 PM PST 24 23831038 ps
T1052 /workspace/coverage/default/41.keymgr_direct_to_disabled.63577789 Feb 04 03:25:07 PM PST 24 Feb 04 03:25:18 PM PST 24 234694829 ps
T1053 /workspace/coverage/default/26.keymgr_sideload.3088776147 Feb 04 03:23:46 PM PST 24 Feb 04 03:23:54 PM PST 24 224789278 ps
T1054 /workspace/coverage/default/18.keymgr_direct_to_disabled.59120456 Feb 04 03:22:55 PM PST 24 Feb 04 03:23:01 PM PST 24 92114182 ps
T1055 /workspace/coverage/default/9.keymgr_stress_all.2159232692 Feb 04 03:21:43 PM PST 24 Feb 04 03:21:53 PM PST 24 189805569 ps
T1056 /workspace/coverage/default/25.keymgr_cfg_regwen.3002158395 Feb 04 03:23:33 PM PST 24 Feb 04 03:23:46 PM PST 24 186860447 ps
T1057 /workspace/coverage/default/30.keymgr_sideload_protect.3784973050 Feb 04 03:24:25 PM PST 24 Feb 04 03:24:32 PM PST 24 91430319 ps
T1058 /workspace/coverage/default/8.keymgr_lc_disable.2748849151 Feb 04 03:21:29 PM PST 24 Feb 04 03:21:37 PM PST 24 314174026 ps
T367 /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3734463927 Feb 04 03:22:17 PM PST 24 Feb 04 03:22:22 PM PST 24 74423020 ps
T1059 /workspace/coverage/default/5.keymgr_random.3824084216 Feb 04 03:20:58 PM PST 24 Feb 04 03:21:02 PM PST 24 680497323 ps
T1060 /workspace/coverage/default/0.keymgr_sideload_aes.414617158 Feb 04 03:19:42 PM PST 24 Feb 04 03:19:49 PM PST 24 293639570 ps
T1061 /workspace/coverage/default/21.keymgr_sideload_otbn.4118167243 Feb 04 03:23:14 PM PST 24 Feb 04 03:23:21 PM PST 24 70672843 ps
T1062 /workspace/coverage/default/30.keymgr_kmac_rsp_err.1932401933 Feb 04 03:24:14 PM PST 24 Feb 04 03:24:48 PM PST 24 1185556357 ps
T1063 /workspace/coverage/default/17.keymgr_kmac_rsp_err.1842255344 Feb 04 03:22:45 PM PST 24 Feb 04 03:22:59 PM PST 24 913507882 ps
T1064 /workspace/coverage/default/8.keymgr_sw_invalid_input.1591630058 Feb 04 03:21:29 PM PST 24 Feb 04 03:21:39 PM PST 24 238826294 ps
T1065 /workspace/coverage/default/22.keymgr_cfg_regwen.2036470705 Feb 04 03:23:20 PM PST 24 Feb 04 03:23:26 PM PST 24 251314634 ps
T1066 /workspace/coverage/default/15.keymgr_stress_all.2656050284 Feb 04 03:22:52 PM PST 24 Feb 04 03:23:11 PM PST 24 588263418 ps
T1067 /workspace/coverage/default/45.keymgr_cfg_regwen.3828407901 Feb 04 03:25:18 PM PST 24 Feb 04 03:25:31 PM PST 24 186718589 ps
T1068 /workspace/coverage/default/35.keymgr_cfg_regwen.1690331494 Feb 04 03:24:46 PM PST 24 Feb 04 03:25:06 PM PST 24 2639221255 ps
T1069 /workspace/coverage/default/20.keymgr_smoke.1479593758 Feb 04 03:23:02 PM PST 24 Feb 04 03:23:07 PM PST 24 184687083 ps
T1070 /workspace/coverage/default/38.keymgr_sideload_protect.1269285842 Feb 04 03:25:03 PM PST 24 Feb 04 03:25:06 PM PST 24 52267976 ps
T217 /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.500191125 Feb 04 03:25:31 PM PST 24 Feb 04 03:25:38 PM PST 24 1137927412 ps
T1071 /workspace/coverage/default/38.keymgr_sideload_otbn.781496463 Feb 04 03:24:46 PM PST 24 Feb 04 03:24:57 PM PST 24 520684396 ps
T1072 /workspace/coverage/default/16.keymgr_kmac_rsp_err.2755869201 Feb 04 03:22:39 PM PST 24 Feb 04 03:22:54 PM PST 24 242866480 ps
T1073 /workspace/coverage/default/37.keymgr_alert_test.501124291 Feb 04 03:24:48 PM PST 24 Feb 04 03:24:53 PM PST 24 19159045 ps
T1074 /workspace/coverage/default/42.keymgr_alert_test.642189193 Feb 04 03:25:12 PM PST 24 Feb 04 03:25:19 PM PST 24 9365678 ps
T1075 /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3763133443 Feb 04 03:22:16 PM PST 24 Feb 04 03:22:49 PM PST 24 1817503825 ps
T1076 /workspace/coverage/default/19.keymgr_smoke.150665827 Feb 04 03:22:55 PM PST 24 Feb 04 03:23:00 PM PST 24 139240989 ps
T1077 /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1306814459 Feb 04 03:25:10 PM PST 24 Feb 04 03:25:21 PM PST 24 143010476 ps
T1078 /workspace/coverage/default/15.keymgr_sideload_aes.3832699494 Feb 04 03:22:43 PM PST 24 Feb 04 03:22:50 PM PST 24 43979283 ps
T1079 /workspace/coverage/default/13.keymgr_sideload.1380771351 Feb 04 03:22:17 PM PST 24 Feb 04 03:22:27 PM PST 24 933749078 ps
T1080 /workspace/coverage/default/16.keymgr_lc_disable.4071640814 Feb 04 03:22:38 PM PST 24 Feb 04 03:22:43 PM PST 24 81311080 ps
T1081 /workspace/coverage/default/28.keymgr_cfg_regwen.1354300242 Feb 04 03:23:58 PM PST 24 Feb 04 03:24:16 PM PST 24 591749560 ps
T1082 /workspace/coverage/default/9.keymgr_direct_to_disabled.2988808916 Feb 04 03:21:42 PM PST 24 Feb 04 03:21:49 PM PST 24 176544831 ps
T1083 /workspace/coverage/default/41.keymgr_sideload.1382292587 Feb 04 03:25:09 PM PST 24 Feb 04 03:25:55 PM PST 24 4122795904 ps
T400 /workspace/coverage/default/42.keymgr_cfg_regwen.3810470853 Feb 04 03:25:08 PM PST 24 Feb 04 03:25:32 PM PST 24 1589008955 ps
T1084 /workspace/coverage/default/3.keymgr_custom_cm.1520156044 Feb 04 03:20:51 PM PST 24 Feb 04 03:20:56 PM PST 24 145120561 ps
T1085 /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4264322034 Feb 04 03:23:03 PM PST 24 Feb 04 03:23:07 PM PST 24 71225437 ps
T1086 /workspace/coverage/default/17.keymgr_alert_test.2380791079 Feb 04 03:22:53 PM PST 24 Feb 04 03:22:56 PM PST 24 155167798 ps
T1087 /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2868585170 Feb 04 03:23:29 PM PST 24 Feb 04 03:23:42 PM PST 24 763462435 ps
T1088 /workspace/coverage/default/9.keymgr_sw_invalid_input.2048380552 Feb 04 03:21:44 PM PST 24 Feb 04 03:21:49 PM PST 24 130087557 ps
T1089 /workspace/coverage/default/31.keymgr_sw_invalid_input.428845768 Feb 04 03:24:25 PM PST 24 Feb 04 03:24:33 PM PST 24 237757013 ps
T1090 /workspace/coverage/default/5.keymgr_kmac_rsp_err.1148530636 Feb 04 03:21:12 PM PST 24 Feb 04 03:21:21 PM PST 24 267194689 ps
T1091 /workspace/coverage/default/48.keymgr_alert_test.2545241602 Feb 04 03:25:56 PM PST 24 Feb 04 03:26:08 PM PST 24 10447413 ps
T1092 /workspace/coverage/default/6.keymgr_sideload_aes.6510891 Feb 04 03:21:19 PM PST 24 Feb 04 03:21:25 PM PST 24 172680244 ps
T1093 /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1537076297 Feb 04 03:22:45 PM PST 24 Feb 04 03:22:54 PM PST 24 135538648 ps
T1094 /workspace/coverage/default/18.keymgr_sideload_protect.3483560513 Feb 04 03:22:48 PM PST 24 Feb 04 03:22:57 PM PST 24 567754265 ps

Test location /workspace/coverage/default/47.keymgr_stress_all.4231814325
Short name T2
Test name
Test status
Simulation time 4090865607 ps
CPU time 23.09 seconds
Started Feb 04 03:25:44 PM PST 24
Finished Feb 04 03:26:08 PM PST 24
Peak memory 219692 kb
Host smart-e9172e57-9fc3-49e7-ab3d-559037f839af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231814325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4231814325
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3310215997
Short name T54
Test name
Test status
Simulation time 3736363735 ps
CPU time 37.51 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:41 PM PST 24
Peak memory 223124 kb
Host smart-0dbc22ea-6965-418d-8957-d8d752f18a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310215997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3310215997
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1169039860
Short name T70
Test name
Test status
Simulation time 1810797223 ps
CPU time 26.8 seconds
Started Feb 04 03:22:47 PM PST 24
Finished Feb 04 03:23:18 PM PST 24
Peak memory 223056 kb
Host smart-a37fa8fe-c769-4ced-8db7-abee0e7fe360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169039860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1169039860
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3257759764
Short name T128
Test name
Test status
Simulation time 297356960 ps
CPU time 10.7 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 209180 kb
Host smart-d364f830-74db-4014-b742-16fa6e23f30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257759764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3257759764
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3443879186
Short name T11
Test name
Test status
Simulation time 707316513 ps
CPU time 11.21 seconds
Started Feb 04 03:20:01 PM PST 24
Finished Feb 04 03:20:15 PM PST 24
Peak memory 232296 kb
Host smart-6ca1465f-4124-40ff-901e-c8dc9ee653e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443879186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3443879186
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2699364524
Short name T7
Test name
Test status
Simulation time 394696073 ps
CPU time 3.4 seconds
Started Feb 04 03:25:27 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 223332 kb
Host smart-440153f2-ef8e-454e-b780-61e241282779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699364524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2699364524
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3680461670
Short name T61
Test name
Test status
Simulation time 5498934619 ps
CPU time 45.96 seconds
Started Feb 04 03:20:26 PM PST 24
Finished Feb 04 03:21:13 PM PST 24
Peak memory 223148 kb
Host smart-d3e10dd6-4e2c-45a5-9d1b-62ccbe66d42e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680461670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3680461670
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.813218546
Short name T52
Test name
Test status
Simulation time 136116843 ps
CPU time 5.56 seconds
Started Feb 04 03:24:42 PM PST 24
Finished Feb 04 03:24:50 PM PST 24
Peak memory 211392 kb
Host smart-9f2ba5a7-1dfd-4ac2-854a-9eefdccacdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813218546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.813218546
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1969655227
Short name T101
Test name
Test status
Simulation time 1039648002 ps
CPU time 11.87 seconds
Started Feb 04 03:22:18 PM PST 24
Finished Feb 04 03:22:31 PM PST 24
Peak memory 222932 kb
Host smart-efcdbbf2-bc33-4f7c-ac68-709f6b60035b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969655227 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1969655227
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3607661881
Short name T370
Test name
Test status
Simulation time 722471526 ps
CPU time 9.2 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:13 PM PST 24
Peak memory 215856 kb
Host smart-f281efc8-85c3-47d7-afd3-3cf537e5b763
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607661881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3607661881
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3991727829
Short name T49
Test name
Test status
Simulation time 2919344292 ps
CPU time 25.57 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:48 PM PST 24
Peak memory 217132 kb
Host smart-f09fb975-fe84-4531-9a2a-1946fe1ee462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991727829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3991727829
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.633086385
Short name T117
Test name
Test status
Simulation time 162986807 ps
CPU time 6.82 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 214404 kb
Host smart-1fc5a2bb-c71a-48d7-8e09-05c0c4ab50fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633086385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.633086385
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3078690982
Short name T399
Test name
Test status
Simulation time 180323781 ps
CPU time 9.86 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:33 PM PST 24
Peak memory 215704 kb
Host smart-3c2a99c2-e4a5-4edd-9a5c-551fd0b5cac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078690982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3078690982
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1310448611
Short name T27
Test name
Test status
Simulation time 1320972419 ps
CPU time 28.96 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 220400 kb
Host smart-245f9a4f-0a13-4fb6-a72e-2aa06e0cae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310448611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1310448611
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2228937737
Short name T6
Test name
Test status
Simulation time 16842478412 ps
CPU time 49.03 seconds
Started Feb 04 03:24:06 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 223096 kb
Host smart-7e8e2579-c198-45c2-b9fe-e888216458c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228937737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2228937737
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3569394716
Short name T111
Test name
Test status
Simulation time 336540514 ps
CPU time 10.1 seconds
Started Feb 04 03:24:18 PM PST 24
Finished Feb 04 03:24:29 PM PST 24
Peak memory 215684 kb
Host smart-f38ff017-d4ff-405d-8594-e4f9f7bb3809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569394716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3569394716
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2281982368
Short name T271
Test name
Test status
Simulation time 232892208 ps
CPU time 13.39 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:34 PM PST 24
Peak memory 215772 kb
Host smart-ac9b95d6-f872-42a5-a1a4-10bd961bd49f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281982368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2281982368
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.493650113
Short name T382
Test name
Test status
Simulation time 3460311127 ps
CPU time 44.41 seconds
Started Feb 04 03:25:39 PM PST 24
Finished Feb 04 03:26:26 PM PST 24
Peak memory 214976 kb
Host smart-b9335aa4-89ce-4464-bc77-3960fcd454d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493650113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.493650113
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1734284819
Short name T213
Test name
Test status
Simulation time 12787416806 ps
CPU time 69.6 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:23:29 PM PST 24
Peak memory 216544 kb
Host smart-20a0b8e6-4c79-48a4-9b32-6c580ef108eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734284819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1734284819
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2836076875
Short name T219
Test name
Test status
Simulation time 5237941783 ps
CPU time 50.2 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:26:06 PM PST 24
Peak memory 215868 kb
Host smart-baf4efb2-cf24-4dd9-ac92-52aa4e74317c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836076875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2836076875
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2314916196
Short name T120
Test name
Test status
Simulation time 130937708 ps
CPU time 4.42 seconds
Started Feb 04 03:23:26 PM PST 24
Finished Feb 04 03:23:36 PM PST 24
Peak memory 214840 kb
Host smart-ed1754ee-0308-427c-97cd-ab3da2ee4a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314916196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2314916196
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2215334957
Short name T5
Test name
Test status
Simulation time 2362269728 ps
CPU time 54.15 seconds
Started Feb 04 03:25:30 PM PST 24
Finished Feb 04 03:26:25 PM PST 24
Peak memory 221564 kb
Host smart-369a0280-0f91-4111-9963-d9ec7e33ef63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215334957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2215334957
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2787521473
Short name T38
Test name
Test status
Simulation time 84431038 ps
CPU time 2.59 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:23 PM PST 24
Peak memory 209960 kb
Host smart-c0123c61-c220-4a40-b5fb-5fa673cabc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787521473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2787521473
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.228995564
Short name T88
Test name
Test status
Simulation time 492115941 ps
CPU time 4.44 seconds
Started Feb 04 03:22:53 PM PST 24
Finished Feb 04 03:23:00 PM PST 24
Peak memory 209416 kb
Host smart-82add5ce-3c63-4865-9b46-8807da659f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228995564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.228995564
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3263062850
Short name T31
Test name
Test status
Simulation time 111481238 ps
CPU time 2.79 seconds
Started Feb 04 03:23:54 PM PST 24
Finished Feb 04 03:24:03 PM PST 24
Peak memory 208768 kb
Host smart-f157f49b-c1d6-4fe4-9762-380fdb5863cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263062850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3263062850
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_random.2511908695
Short name T41
Test name
Test status
Simulation time 232813185 ps
CPU time 5.36 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:20 PM PST 24
Peak memory 210200 kb
Host smart-2c55270c-c1cd-4290-ae9e-2330c07ae5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511908695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2511908695
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3378153537
Short name T62
Test name
Test status
Simulation time 56333500 ps
CPU time 3.37 seconds
Started Feb 04 03:21:42 PM PST 24
Finished Feb 04 03:21:46 PM PST 24
Peak memory 211568 kb
Host smart-c50475dc-218f-48d9-804c-23ffa826de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378153537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3378153537
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4007511896
Short name T389
Test name
Test status
Simulation time 730491448 ps
CPU time 10.27 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:34 PM PST 24
Peak memory 215628 kb
Host smart-131d4b9a-6cc3-418d-ade5-48c750997205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007511896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4007511896
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1120312313
Short name T351
Test name
Test status
Simulation time 140190230 ps
CPU time 7.5 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:34 PM PST 24
Peak memory 215556 kb
Host smart-faf23746-1ec4-4b85-b06b-7895e2364571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120312313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1120312313
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1539587841
Short name T126
Test name
Test status
Simulation time 168019065 ps
CPU time 4.16 seconds
Started Feb 04 12:51:02 PM PST 24
Finished Feb 04 12:51:09 PM PST 24
Peak memory 214424 kb
Host smart-2b380e1b-a4ea-40a1-a757-387d9cfa8f65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539587841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1539587841
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2884280753
Short name T132
Test name
Test status
Simulation time 47675322 ps
CPU time 3.01 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:57 PM PST 24
Peak memory 214120 kb
Host smart-92fda425-7a78-4d5e-aa2b-7d83ea15522d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884280753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2884280753
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1615043701
Short name T161
Test name
Test status
Simulation time 146314590 ps
CPU time 2.91 seconds
Started Feb 04 03:22:57 PM PST 24
Finished Feb 04 03:23:01 PM PST 24
Peak memory 218308 kb
Host smart-0fcefd06-70c0-4abd-92de-67aa7912289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615043701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1615043701
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3318524990
Short name T71
Test name
Test status
Simulation time 2323495281 ps
CPU time 36.66 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:24:00 PM PST 24
Peak memory 223100 kb
Host smart-7bd83b9e-d4d9-42c1-bdc1-8ea0a0fde3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318524990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3318524990
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2688892620
Short name T22
Test name
Test status
Simulation time 9117115613 ps
CPU time 20.23 seconds
Started Feb 04 03:24:51 PM PST 24
Finished Feb 04 03:25:14 PM PST 24
Peak memory 215272 kb
Host smart-d6aadcf1-93c2-4543-9edf-20129f868759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688892620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2688892620
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.467150690
Short name T264
Test name
Test status
Simulation time 183324783 ps
CPU time 6.17 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:24 PM PST 24
Peak memory 222960 kb
Host smart-6da73199-b946-465b-954c-1de9811622ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467150690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.467150690
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4195430877
Short name T177
Test name
Test status
Simulation time 111960832 ps
CPU time 3.64 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 208796 kb
Host smart-88800216-5c2e-4624-8d26-44b6fabb33dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195430877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.4195430877
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2102732080
Short name T325
Test name
Test status
Simulation time 164883005 ps
CPU time 8.67 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:17 PM PST 24
Peak memory 214748 kb
Host smart-8e2ab933-81b8-4e0a-9c7c-1a897653680e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102732080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2102732080
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2762112797
Short name T408
Test name
Test status
Simulation time 40980355 ps
CPU time 0.77 seconds
Started Feb 04 03:23:11 PM PST 24
Finished Feb 04 03:23:18 PM PST 24
Peak memory 206488 kb
Host smart-458cf488-9925-48b2-9917-379b7f551daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762112797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2762112797
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3924918477
Short name T17
Test name
Test status
Simulation time 139063556 ps
CPU time 2.77 seconds
Started Feb 04 03:24:41 PM PST 24
Finished Feb 04 03:24:46 PM PST 24
Peak memory 208980 kb
Host smart-b3af0218-bb43-4550-9b56-58162392a5cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924918477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3924918477
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.975311309
Short name T205
Test name
Test status
Simulation time 82052547 ps
CPU time 1.95 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:21 PM PST 24
Peak memory 210484 kb
Host smart-003ce76c-c540-4e4f-824f-2e7fc5acd1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975311309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.975311309
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1484708593
Short name T385
Test name
Test status
Simulation time 448437445 ps
CPU time 4.99 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 215704 kb
Host smart-6a96881f-c1c9-43fb-b663-734c7ef052b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484708593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1484708593
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.758375484
Short name T274
Test name
Test status
Simulation time 176818273814 ps
CPU time 306.75 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:30:24 PM PST 24
Peak memory 220668 kb
Host smart-850d55db-4812-4fc0-a6a9-c16526195738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758375484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.758375484
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1476887806
Short name T358
Test name
Test status
Simulation time 532123839 ps
CPU time 9.52 seconds
Started Feb 04 03:23:35 PM PST 24
Finished Feb 04 03:23:46 PM PST 24
Peak memory 215952 kb
Host smart-7f82d561-487a-42f8-b92c-bec9dda19fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476887806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1476887806
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2529039513
Short name T246
Test name
Test status
Simulation time 78844820 ps
CPU time 4.12 seconds
Started Feb 04 03:25:39 PM PST 24
Finished Feb 04 03:25:46 PM PST 24
Peak memory 222920 kb
Host smart-20b7b1d0-fb79-4f39-83fb-25dda9340a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529039513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2529039513
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1821480848
Short name T173
Test name
Test status
Simulation time 1416063814 ps
CPU time 15.14 seconds
Started Feb 04 12:51:14 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 208732 kb
Host smart-b0c2c614-63c4-4d46-a8bc-62f078f84416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821480848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1821480848
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4206886671
Short name T182
Test name
Test status
Simulation time 180476944 ps
CPU time 6.29 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:07 PM PST 24
Peak memory 209148 kb
Host smart-8438a9f2-54bd-4095-a960-f5fccd63f292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206886671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4206886671
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.639065453
Short name T176
Test name
Test status
Simulation time 354617633 ps
CPU time 12.14 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:39 PM PST 24
Peak memory 210800 kb
Host smart-58edfa8c-31e1-45a9-bd79-777c7e3b5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639065453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.639065453
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2297819696
Short name T162
Test name
Test status
Simulation time 196946302 ps
CPU time 2.58 seconds
Started Feb 04 03:20:19 PM PST 24
Finished Feb 04 03:20:24 PM PST 24
Peak memory 217852 kb
Host smart-850e6466-fbad-4423-be3b-3c42401d9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297819696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2297819696
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4065227486
Short name T168
Test name
Test status
Simulation time 176168656 ps
CPU time 4.36 seconds
Started Feb 04 03:20:28 PM PST 24
Finished Feb 04 03:20:33 PM PST 24
Peak memory 218516 kb
Host smart-74218e0e-226d-4554-8cf9-3fff7683c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065227486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4065227486
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3267199933
Short name T169
Test name
Test status
Simulation time 75798740 ps
CPU time 3.62 seconds
Started Feb 04 03:23:21 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 217792 kb
Host smart-001343f1-3d74-4589-81a1-42399c599766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267199933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3267199933
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.590937692
Short name T167
Test name
Test status
Simulation time 316856962 ps
CPU time 5.24 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:17 PM PST 24
Peak memory 223124 kb
Host smart-422330cc-d6c0-49ce-91e3-fa04dcaa4223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590937692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.590937692
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.178979763
Short name T74
Test name
Test status
Simulation time 1565248848 ps
CPU time 43.26 seconds
Started Feb 04 03:20:01 PM PST 24
Finished Feb 04 03:20:47 PM PST 24
Peak memory 216080 kb
Host smart-47a2dc66-01a7-4fbc-ac33-06bc6c3dc63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178979763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.178979763
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1239875062
Short name T283
Test name
Test status
Simulation time 56043059752 ps
CPU time 724.6 seconds
Started Feb 04 03:21:48 PM PST 24
Finished Feb 04 03:33:57 PM PST 24
Peak memory 227324 kb
Host smart-29137f6d-65cd-4efe-8bc5-7f7977b9ecf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239875062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1239875062
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1469719024
Short name T229
Test name
Test status
Simulation time 1992689403 ps
CPU time 36.36 seconds
Started Feb 04 03:22:25 PM PST 24
Finished Feb 04 03:23:05 PM PST 24
Peak memory 221560 kb
Host smart-fedade06-4b88-4505-890e-7a8bad1e11b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469719024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1469719024
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1267176374
Short name T91
Test name
Test status
Simulation time 3396868700 ps
CPU time 44.46 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:24:02 PM PST 24
Peak memory 221772 kb
Host smart-b14bedba-6cc1-4550-a318-6d80f562f3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267176374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1267176374
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.988459179
Short name T276
Test name
Test status
Simulation time 130596894 ps
CPU time 4.6 seconds
Started Feb 04 03:23:55 PM PST 24
Finished Feb 04 03:24:05 PM PST 24
Peak memory 208752 kb
Host smart-928316bd-3456-47f4-820c-cb2d872cabe0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988459179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.988459179
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1489595374
Short name T320
Test name
Test status
Simulation time 1493162819 ps
CPU time 5.36 seconds
Started Feb 04 03:20:39 PM PST 24
Finished Feb 04 03:20:46 PM PST 24
Peak memory 223008 kb
Host smart-cc2e836e-64d6-4fdf-98b1-518d7963fb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489595374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1489595374
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2115971519
Short name T216
Test name
Test status
Simulation time 297903374 ps
CPU time 5.71 seconds
Started Feb 04 03:24:20 PM PST 24
Finished Feb 04 03:24:29 PM PST 24
Peak memory 223044 kb
Host smart-5631c7e7-0940-4412-aaec-cacf64b98724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115971519 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2115971519
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2337292085
Short name T390
Test name
Test status
Simulation time 10844440799 ps
CPU time 52.16 seconds
Started Feb 04 03:24:42 PM PST 24
Finished Feb 04 03:25:36 PM PST 24
Peak memory 216032 kb
Host smart-ccce575e-53d1-4fa1-8881-b24f2d5e967f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337292085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2337292085
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2797205241
Short name T257
Test name
Test status
Simulation time 103279930 ps
CPU time 4.3 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 207072 kb
Host smart-8199de33-d5ca-4dd3-88f2-968e8960df17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797205241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2797205241
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1372845012
Short name T77
Test name
Test status
Simulation time 19618482064 ps
CPU time 47.93 seconds
Started Feb 04 03:21:28 PM PST 24
Finished Feb 04 03:22:21 PM PST 24
Peak memory 217992 kb
Host smart-372dd724-d7d5-45bf-83a1-a6c3f910e230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372845012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1372845012
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1294205335
Short name T165
Test name
Test status
Simulation time 56382984 ps
CPU time 2.95 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 217936 kb
Host smart-2660e727-201f-483e-a46e-50be19f80b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294205335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1294205335
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1008600132
Short name T166
Test name
Test status
Simulation time 190230919 ps
CPU time 4.7 seconds
Started Feb 04 03:23:21 PM PST 24
Finished Feb 04 03:23:27 PM PST 24
Peak memory 218392 kb
Host smart-1a698b2d-4f56-4e3c-93ad-b936dbb9f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008600132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1008600132
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.77833361
Short name T343
Test name
Test status
Simulation time 176136620 ps
CPU time 9.31 seconds
Started Feb 04 03:20:29 PM PST 24
Finished Feb 04 03:20:40 PM PST 24
Peak memory 214832 kb
Host smart-b99ad377-aede-4c02-869a-a1a8316cabb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77833361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.77833361
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.53516712
Short name T239
Test name
Test status
Simulation time 468331681 ps
CPU time 12.58 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:22:05 PM PST 24
Peak memory 214820 kb
Host smart-63b8c1f6-874c-4bc4-b91a-dad5eb1be601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53516712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.53516712
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2763501395
Short name T250
Test name
Test status
Simulation time 140647803 ps
CPU time 5.38 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:21:58 PM PST 24
Peak memory 218764 kb
Host smart-b53d9a18-b7f0-46f3-8e93-a46333f4b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763501395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2763501395
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4252879210
Short name T302
Test name
Test status
Simulation time 96834322 ps
CPU time 3.57 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:40 PM PST 24
Peak memory 223004 kb
Host smart-ab9b7db9-9748-4af5-923f-2174c40fc00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252879210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4252879210
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1983460350
Short name T203
Test name
Test status
Simulation time 783122288 ps
CPU time 9.81 seconds
Started Feb 04 03:23:47 PM PST 24
Finished Feb 04 03:24:00 PM PST 24
Peak memory 212028 kb
Host smart-e4e1a191-1080-4237-9705-c675def4784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983460350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1983460350
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.4237983847
Short name T225
Test name
Test status
Simulation time 522779821 ps
CPU time 11.53 seconds
Started Feb 04 03:20:42 PM PST 24
Finished Feb 04 03:20:55 PM PST 24
Peak memory 222888 kb
Host smart-a4df1ed6-48f3-4970-9836-abad682a9386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237983847 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.4237983847
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.147016426
Short name T567
Test name
Test status
Simulation time 207473060 ps
CPU time 2.29 seconds
Started Feb 04 03:24:46 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 206408 kb
Host smart-34d09f3e-c155-46ea-a970-4ebe58fb4249
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147016426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.147016426
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1881767382
Short name T234
Test name
Test status
Simulation time 345898315 ps
CPU time 18.72 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 216704 kb
Host smart-7776997c-27b9-4d9e-9a87-eb78313f8103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881767382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1881767382
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3252950946
Short name T268
Test name
Test status
Simulation time 336806560 ps
CPU time 6.5 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:27 PM PST 24
Peak memory 222980 kb
Host smart-32922646-d08b-42f4-99b1-15285c72db2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252950946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3252950946
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.36440404
Short name T187
Test name
Test status
Simulation time 909475321 ps
CPU time 10.41 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 209028 kb
Host smart-c5e800d2-4cba-4034-8a66-5c9af2c04c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.36440404
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3401167781
Short name T462
Test name
Test status
Simulation time 54210791 ps
CPU time 2.28 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 214064 kb
Host smart-d5d32c9d-2551-49e3-8d01-39f5f2b090b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401167781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3401167781
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2860555641
Short name T181
Test name
Test status
Simulation time 729860874 ps
CPU time 16.1 seconds
Started Feb 04 12:51:10 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 209208 kb
Host smart-599b7003-7b56-48e6-b1e5-76ab6afd3ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860555641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2860555641
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1400719672
Short name T179
Test name
Test status
Simulation time 80510986 ps
CPU time 3.56 seconds
Started Feb 04 12:51:27 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 209388 kb
Host smart-600b4be9-7bf8-41a0-9e4f-04ee0fc4d769
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400719672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1400719672
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1163198911
Short name T164
Test name
Test status
Simulation time 117896662 ps
CPU time 4.55 seconds
Started Feb 04 03:21:09 PM PST 24
Finished Feb 04 03:21:19 PM PST 24
Peak memory 223188 kb
Host smart-43e71dfa-5dab-4991-8a91-1681fcdf3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163198911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1163198911
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2154461159
Short name T57
Test name
Test status
Simulation time 147567075 ps
CPU time 7.81 seconds
Started Feb 04 03:20:29 PM PST 24
Finished Feb 04 03:20:38 PM PST 24
Peak memory 214476 kb
Host smart-5c3e3044-2b34-4b17-a8b7-416a906850fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154461159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2154461159
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4076470512
Short name T34
Test name
Test status
Simulation time 1876330018 ps
CPU time 19.49 seconds
Started Feb 04 03:22:08 PM PST 24
Finished Feb 04 03:22:29 PM PST 24
Peak memory 210784 kb
Host smart-3915d031-6098-4a28-8a2e-d0a247407987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076470512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4076470512
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2860588683
Short name T305
Test name
Test status
Simulation time 659609232 ps
CPU time 9.51 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 220540 kb
Host smart-07d06b78-aadb-4fea-bd82-d181b7403ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860588683 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2860588683
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3997658013
Short name T235
Test name
Test status
Simulation time 58951546 ps
CPU time 3.73 seconds
Started Feb 04 03:22:40 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 210084 kb
Host smart-19dec5d6-d452-4a28-9713-07615b5e7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997658013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3997658013
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1038051158
Short name T236
Test name
Test status
Simulation time 27383015 ps
CPU time 2.23 seconds
Started Feb 04 03:20:26 PM PST 24
Finished Feb 04 03:20:29 PM PST 24
Peak memory 214960 kb
Host smart-837ce022-a635-47fd-a114-d130e9291164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038051158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1038051158
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4289078693
Short name T348
Test name
Test status
Simulation time 3650749124 ps
CPU time 34.82 seconds
Started Feb 04 03:23:27 PM PST 24
Finished Feb 04 03:24:08 PM PST 24
Peak memory 223128 kb
Host smart-8897e300-631c-4e3b-b8b7-8606e5045c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289078693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4289078693
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.599360095
Short name T199
Test name
Test status
Simulation time 439395932 ps
CPU time 5.15 seconds
Started Feb 04 03:23:49 PM PST 24
Finished Feb 04 03:23:57 PM PST 24
Peak memory 214780 kb
Host smart-2546bb2f-51fe-494b-b08c-c3b2ae452a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599360095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.599360095
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.403936881
Short name T361
Test name
Test status
Simulation time 291481673 ps
CPU time 4.21 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:07 PM PST 24
Peak memory 209548 kb
Host smart-07fb11b5-64a2-4d0a-9600-747c682b94e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403936881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.403936881
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2030437059
Short name T233
Test name
Test status
Simulation time 1304362130 ps
CPU time 32.17 seconds
Started Feb 04 03:24:43 PM PST 24
Finished Feb 04 03:25:17 PM PST 24
Peak memory 217116 kb
Host smart-149249ec-c764-431e-b87b-c2b32a057150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030437059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2030437059
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3151439107
Short name T366
Test name
Test status
Simulation time 130941704 ps
CPU time 4.69 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 214720 kb
Host smart-2e092202-0e05-40c1-b25e-624276d223ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151439107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3151439107
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2093165400
Short name T365
Test name
Test status
Simulation time 632223447 ps
CPU time 3.52 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:17 PM PST 24
Peak memory 209744 kb
Host smart-350e0d73-cc7e-4e48-9eea-80e6da029df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093165400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2093165400
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_random.2179470967
Short name T137
Test name
Test status
Simulation time 1181308593 ps
CPU time 8.43 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:24 PM PST 24
Peak memory 208188 kb
Host smart-7512b3b0-4d8b-446c-9fef-21bd127504ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179470967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2179470967
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1495823951
Short name T220
Test name
Test status
Simulation time 109139491 ps
CPU time 3.56 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 220744 kb
Host smart-3f2f5c67-a597-4c6e-8361-62388392f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495823951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1495823951
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2165126175
Short name T341
Test name
Test status
Simulation time 58236195 ps
CPU time 1.96 seconds
Started Feb 04 03:25:49 PM PST 24
Finished Feb 04 03:25:54 PM PST 24
Peak memory 209276 kb
Host smart-2f6183dc-0298-4178-aa6a-5860ffbcabdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165126175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2165126175
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.619949661
Short name T319
Test name
Test status
Simulation time 527612264 ps
CPU time 5.35 seconds
Started Feb 04 03:21:29 PM PST 24
Finished Feb 04 03:21:39 PM PST 24
Peak memory 214772 kb
Host smart-db592bff-1ac4-4599-ab38-176eb3653cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619949661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.619949661
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4134893615
Short name T163
Test name
Test status
Simulation time 1588922021 ps
CPU time 13.81 seconds
Started Feb 04 03:22:23 PM PST 24
Finished Feb 04 03:22:43 PM PST 24
Peak memory 217676 kb
Host smart-494d4b2a-4051-4344-87c0-1304cfd7b562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134893615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4134893615
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.718697835
Short name T460
Test name
Test status
Simulation time 974384748 ps
CPU time 14.99 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 205884 kb
Host smart-608e56a0-5b35-44b5-86e7-2486016a72f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718697835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.718697835
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3535028729
Short name T432
Test name
Test status
Simulation time 9302514278 ps
CPU time 19.71 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:51:16 PM PST 24
Peak memory 205968 kb
Host smart-54b553e8-faf3-47ec-b008-5bde9a2deebe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535028729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
535028729
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.464316028
Short name T420
Test name
Test status
Simulation time 39172829 ps
CPU time 1.22 seconds
Started Feb 04 12:50:51 PM PST 24
Finished Feb 04 12:50:54 PM PST 24
Peak memory 205812 kb
Host smart-f7c365b7-952c-4108-9407-ffc275fffd17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464316028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.464316028
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2351410156
Short name T470
Test name
Test status
Simulation time 66763613 ps
CPU time 1.86 seconds
Started Feb 04 12:51:05 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 214168 kb
Host smart-1b5ccd7d-105e-4a7d-aef9-b8c143f2bbf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351410156 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2351410156
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2703689462
Short name T520
Test name
Test status
Simulation time 364476354 ps
CPU time 1.48 seconds
Started Feb 04 12:50:49 PM PST 24
Finished Feb 04 12:50:53 PM PST 24
Peak memory 205896 kb
Host smart-0d21e4cd-63c1-47bc-8977-c0f2d6a5021c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703689462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2703689462
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3257630008
Short name T464
Test name
Test status
Simulation time 14392800 ps
CPU time 0.78 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:50:57 PM PST 24
Peak memory 205476 kb
Host smart-2a472782-8cc2-46d8-af92-1dd4f23d722f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257630008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3257630008
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2738264981
Short name T536
Test name
Test status
Simulation time 206092315 ps
CPU time 1.54 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 205864 kb
Host smart-a1d5c5fb-ff4d-4e4d-bc68-a00abfe87d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738264981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2738264981
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.220216449
Short name T538
Test name
Test status
Simulation time 315679414 ps
CPU time 3.39 seconds
Started Feb 04 12:50:51 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 214440 kb
Host smart-8eae6045-5a58-4147-b73b-a64a5af49593
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220216449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.220216449
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3470389085
Short name T540
Test name
Test status
Simulation time 5898612008 ps
CPU time 9.47 seconds
Started Feb 04 12:50:56 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 222656 kb
Host smart-5d18f612-ab8a-4b55-9ad9-789733455541
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470389085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3470389085
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1459822194
Short name T517
Test name
Test status
Simulation time 514213090 ps
CPU time 2.86 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 213920 kb
Host smart-212630c0-930f-451a-ac65-63e01b68beb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459822194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1459822194
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2516201155
Short name T528
Test name
Test status
Simulation time 2580557945 ps
CPU time 12.07 seconds
Started Feb 04 12:50:50 PM PST 24
Finished Feb 04 12:51:04 PM PST 24
Peak memory 205956 kb
Host smart-13947313-90f0-417f-9497-c1d3e11bce20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516201155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
516201155
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2066879622
Short name T429
Test name
Test status
Simulation time 255110754 ps
CPU time 15.38 seconds
Started Feb 04 12:50:49 PM PST 24
Finished Feb 04 12:51:07 PM PST 24
Peak memory 205788 kb
Host smart-0c49a072-dfe7-42c5-b165-8198b7a54ae9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066879622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
066879622
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.166307980
Short name T411
Test name
Test status
Simulation time 37468633 ps
CPU time 1.14 seconds
Started Feb 04 12:50:50 PM PST 24
Finished Feb 04 12:50:53 PM PST 24
Peak memory 205908 kb
Host smart-c5b47fcc-3e52-4a16-81ca-554f35344a5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166307980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.166307980
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.138078157
Short name T431
Test name
Test status
Simulation time 49929766 ps
CPU time 1.24 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 205660 kb
Host smart-8b94e856-4fa5-4f43-94ea-6cc66cf6b470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138078157 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.138078157
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.571099242
Short name T505
Test name
Test status
Simulation time 15477636 ps
CPU time 1.2 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 205808 kb
Host smart-41495f03-d8f1-447f-869c-f4e5e0527d9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571099242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.571099242
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1049924852
Short name T559
Test name
Test status
Simulation time 16285389 ps
CPU time 0.84 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:02 PM PST 24
Peak memory 205376 kb
Host smart-997838df-8ea4-4fd7-af95-3d683e4713a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049924852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1049924852
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1239945401
Short name T477
Test name
Test status
Simulation time 32271867 ps
CPU time 2.06 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:03 PM PST 24
Peak memory 205736 kb
Host smart-7dd11444-4ef6-4b81-b595-67ec658ca6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239945401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1239945401
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.652394585
Short name T561
Test name
Test status
Simulation time 327409780 ps
CPU time 4.23 seconds
Started Feb 04 12:50:51 PM PST 24
Finished Feb 04 12:50:57 PM PST 24
Peak memory 214472 kb
Host smart-b49f46d7-d82f-4e9e-a24e-196ecadd38a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652394585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.652394585
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1556100085
Short name T116
Test name
Test status
Simulation time 1322959820 ps
CPU time 7.69 seconds
Started Feb 04 12:50:49 PM PST 24
Finished Feb 04 12:51:00 PM PST 24
Peak memory 214424 kb
Host smart-a28e7a07-b7b4-4ccd-b5fb-9d24cd8e4247
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556100085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1556100085
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.780002114
Short name T172
Test name
Test status
Simulation time 1672680916 ps
CPU time 11.54 seconds
Started Feb 04 12:50:59 PM PST 24
Finished Feb 04 12:51:15 PM PST 24
Peak memory 209308 kb
Host smart-1a3a6816-53e6-45cb-b91b-1ea4a5bfa5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780002114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
780002114
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.564390172
Short name T511
Test name
Test status
Simulation time 53685686 ps
CPU time 1.28 seconds
Started Feb 04 12:51:16 PM PST 24
Finished Feb 04 12:51:19 PM PST 24
Peak memory 205760 kb
Host smart-b0a633fc-a59b-4669-86d5-4520d7c45e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564390172 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.564390172
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.806426891
Short name T153
Test name
Test status
Simulation time 59228461 ps
CPU time 1.1 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 205740 kb
Host smart-da44509c-09ce-43b7-a54f-dd4f399ebf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806426891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.806426891
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2659609148
Short name T509
Test name
Test status
Simulation time 13932328 ps
CPU time 0.73 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 205420 kb
Host smart-85e62e63-dbfd-4bd0-ab1f-1fbe7db2e25b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659609148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2659609148
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3527909181
Short name T504
Test name
Test status
Simulation time 80002366 ps
CPU time 1.62 seconds
Started Feb 04 12:51:19 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 205844 kb
Host smart-cf762aa6-1e1a-4061-a143-52fbbad3663c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527909181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3527909181
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4048413072
Short name T125
Test name
Test status
Simulation time 62191923 ps
CPU time 2.24 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 214324 kb
Host smart-fe035ba3-ad7d-44e2-be7c-9e2cde2b415b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048413072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4048413072
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3708943131
Short name T472
Test name
Test status
Simulation time 738316199 ps
CPU time 7.06 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:24 PM PST 24
Peak memory 214324 kb
Host smart-8f86241b-d64c-4b40-8558-d11c14438e66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708943131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3708943131
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4028907279
Short name T551
Test name
Test status
Simulation time 34171059 ps
CPU time 1.14 seconds
Started Feb 04 12:51:13 PM PST 24
Finished Feb 04 12:51:16 PM PST 24
Peak memory 205860 kb
Host smart-f2855fb7-69fd-4ce8-9391-6ef49bca112e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028907279 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4028907279
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2952358493
Short name T546
Test name
Test status
Simulation time 90060647 ps
CPU time 1.04 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 205468 kb
Host smart-ec2e966d-b178-4527-a60d-c8e2db10e261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952358493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2952358493
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3006086281
Short name T468
Test name
Test status
Simulation time 51411219 ps
CPU time 0.85 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:24 PM PST 24
Peak memory 205536 kb
Host smart-cf47e65a-c0ca-4e27-bee9-96efeee56184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006086281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3006086281
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1291935089
Short name T543
Test name
Test status
Simulation time 46774592 ps
CPU time 1.67 seconds
Started Feb 04 12:51:22 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 205860 kb
Host smart-7ac9910b-2109-4500-9a56-05b6a4c7cc17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291935089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1291935089
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1020429558
Short name T503
Test name
Test status
Simulation time 328031911 ps
CPU time 2.48 seconds
Started Feb 04 12:51:16 PM PST 24
Finished Feb 04 12:51:20 PM PST 24
Peak memory 214420 kb
Host smart-12337a44-1f13-4e01-be48-63d5d6c6c13b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020429558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1020429558
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2551940523
Short name T527
Test name
Test status
Simulation time 334326961 ps
CPU time 4.02 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 214492 kb
Host smart-9cbaae9a-722b-4dff-805f-bac08f7e2679
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551940523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2551940523
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.245236658
Short name T506
Test name
Test status
Simulation time 113614098 ps
CPU time 4.1 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 216060 kb
Host smart-6f7769e7-6b81-4d1b-ad5d-52804e1a4530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245236658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.245236658
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.6899517
Short name T171
Test name
Test status
Simulation time 123500984 ps
CPU time 6.41 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 209628 kb
Host smart-e6e6ce16-030e-452b-a2e2-f0f4d2874dda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6899517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.6899517
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3819132687
Short name T427
Test name
Test status
Simulation time 33286918 ps
CPU time 1.36 seconds
Started Feb 04 12:51:11 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 214100 kb
Host smart-a23a4199-9292-4245-bacd-878eb13813c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819132687 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3819132687
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3254888230
Short name T537
Test name
Test status
Simulation time 10055969 ps
CPU time 0.89 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205732 kb
Host smart-c4d1cb21-2895-48a1-ad05-c5c49f98f320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254888230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3254888230
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3147730133
Short name T510
Test name
Test status
Simulation time 15613068 ps
CPU time 0.81 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:24 PM PST 24
Peak memory 205592 kb
Host smart-7a0ebd24-e069-47e0-ada1-6f9313b87309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147730133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3147730133
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3382864833
Short name T563
Test name
Test status
Simulation time 123663850 ps
CPU time 2.32 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:12 PM PST 24
Peak memory 205928 kb
Host smart-173ed3b7-c622-4cba-8d4e-5def35c90277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382864833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3382864833
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2422420550
Short name T463
Test name
Test status
Simulation time 5483130883 ps
CPU time 19.62 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 214484 kb
Host smart-3ac068cc-cd6d-4628-9ff5-b5947e257fe8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422420550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2422420550
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.70926459
Short name T459
Test name
Test status
Simulation time 94251147 ps
CPU time 3.49 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:20 PM PST 24
Peak memory 220008 kb
Host smart-67977283-2c8b-4dac-a233-76bc1ddab883
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70926459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_shadow_reg_errors_with_csr_rw.70926459
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2249316572
Short name T555
Test name
Test status
Simulation time 38618043 ps
CPU time 2.07 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 214112 kb
Host smart-5815869f-1cd3-4a8f-9b7e-70cec693d88c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249316572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2249316572
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4104940356
Short name T453
Test name
Test status
Simulation time 58322939 ps
CPU time 1.68 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 213972 kb
Host smart-2ee5807e-45c7-4df1-9263-001620bc52e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104940356 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4104940356
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3597908680
Short name T447
Test name
Test status
Simulation time 37603025 ps
CPU time 0.93 seconds
Started Feb 04 12:51:25 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205668 kb
Host smart-5b5d2362-8ca7-430a-bb78-8741ed0ba1b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597908680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3597908680
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3604203702
Short name T442
Test name
Test status
Simulation time 12794755 ps
CPU time 0.78 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 205532 kb
Host smart-4867be3e-dc5b-4f7a-92be-a00078fac4e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604203702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3604203702
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3696422842
Short name T553
Test name
Test status
Simulation time 270687597 ps
CPU time 2.1 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205924 kb
Host smart-ca32d255-eba5-4650-ad52-dfcd6161e81b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696422842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3696422842
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1737219003
Short name T444
Test name
Test status
Simulation time 223868588 ps
CPU time 2.46 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 214376 kb
Host smart-51fc796f-02e0-45c6-8ed1-db07a28d1e2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737219003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1737219003
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1527323055
Short name T515
Test name
Test status
Simulation time 1158462849 ps
CPU time 8.83 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 214488 kb
Host smart-97593717-5aef-4078-a54d-a760852e32b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527323055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1527323055
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2179794327
Short name T512
Test name
Test status
Simulation time 320391187 ps
CPU time 1.97 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 214044 kb
Host smart-2a7d9ea0-e059-45a7-b151-5f9802dce950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179794327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2179794327
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4116338709
Short name T500
Test name
Test status
Simulation time 56127098 ps
CPU time 3.15 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 209272 kb
Host smart-f006ceef-7c84-4c28-948f-d28116796c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116338709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4116338709
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2181849141
Short name T191
Test name
Test status
Simulation time 29394676 ps
CPU time 1.62 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 213972 kb
Host smart-fd20929f-e6e2-4d29-bcbe-0ee930efd7aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181849141 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2181849141
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1901267937
Short name T487
Test name
Test status
Simulation time 57034619 ps
CPU time 1.19 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205804 kb
Host smart-e9ea8c0d-13fa-4bd7-b169-c45bf4da7ec6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901267937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1901267937
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2382862347
Short name T523
Test name
Test status
Simulation time 12108960 ps
CPU time 0.81 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 205484 kb
Host smart-cb473d25-d6df-41f5-806d-c334d6b7488a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382862347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2382862347
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4234473306
Short name T552
Test name
Test status
Simulation time 93208746 ps
CPU time 3.76 seconds
Started Feb 04 12:51:27 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 205736 kb
Host smart-63182bdf-e5a9-4817-96fd-14d2c0be06d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234473306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4234473306
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.986861519
Short name T449
Test name
Test status
Simulation time 189312850 ps
CPU time 3.82 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:34 PM PST 24
Peak memory 218496 kb
Host smart-6af2f003-46e1-4362-92b0-3c098fb67adf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986861519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.986861519
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1835814428
Short name T529
Test name
Test status
Simulation time 3508828456 ps
CPU time 5.32 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 214444 kb
Host smart-aa0fd915-dd2c-488f-a85d-617b060309e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835814428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1835814428
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2459599227
Short name T532
Test name
Test status
Simulation time 237999113 ps
CPU time 3.22 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 214048 kb
Host smart-969b4ae9-7257-4f9f-9cae-2551c8fc8e58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459599227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2459599227
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.665171636
Short name T539
Test name
Test status
Simulation time 57945554 ps
CPU time 2.13 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 214004 kb
Host smart-21a01fa3-e489-4655-87fb-f9bb81e571ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665171636 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.665171636
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2908794666
Short name T490
Test name
Test status
Simulation time 24672074 ps
CPU time 1.09 seconds
Started Feb 04 12:51:35 PM PST 24
Finished Feb 04 12:51:39 PM PST 24
Peak memory 205708 kb
Host smart-057eaea3-75ab-47e6-9ad6-c35fee48ff0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908794666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2908794666
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2333556536
Short name T457
Test name
Test status
Simulation time 12478079 ps
CPU time 0.72 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 205480 kb
Host smart-7a9884f0-7e01-4303-9a71-ce68a0e693a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333556536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2333556536
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.521496522
Short name T195
Test name
Test status
Simulation time 115612833 ps
CPU time 4.28 seconds
Started Feb 04 12:51:35 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 205788 kb
Host smart-ff9b0437-65d9-49fd-8451-79f62992f85e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521496522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.521496522
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4038902342
Short name T516
Test name
Test status
Simulation time 215361244 ps
CPU time 5.86 seconds
Started Feb 04 12:51:39 PM PST 24
Finished Feb 04 12:51:46 PM PST 24
Peak memory 222372 kb
Host smart-e9a26434-6f96-4e11-8ed4-645d30197a9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038902342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4038902342
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2009086707
Short name T508
Test name
Test status
Simulation time 2568486784 ps
CPU time 13.06 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 221204 kb
Host smart-cc17b81d-068f-4675-8264-7f234f00d069
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009086707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2009086707
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2964330895
Short name T451
Test name
Test status
Simulation time 656378204 ps
CPU time 5.67 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:37 PM PST 24
Peak memory 216244 kb
Host smart-daf1a9d7-e9ad-4825-b036-4c02c3dc7f85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964330895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2964330895
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2191608703
Short name T186
Test name
Test status
Simulation time 659034524 ps
CPU time 20.35 seconds
Started Feb 04 12:51:47 PM PST 24
Finished Feb 04 12:52:10 PM PST 24
Peak memory 209044 kb
Host smart-0198afbf-6aeb-4f96-b37a-2191d02d92a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191608703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2191608703
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1261530546
Short name T194
Test name
Test status
Simulation time 138258819 ps
CPU time 1.68 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:52 PM PST 24
Peak memory 213956 kb
Host smart-716c3c6b-47ae-4d5d-b850-99df4a222bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261530546 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1261530546
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2319182878
Short name T155
Test name
Test status
Simulation time 61858579 ps
CPU time 0.98 seconds
Started Feb 04 12:51:40 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 205664 kb
Host smart-4658ab2e-e23e-4711-b077-256e4b28bc42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319182878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2319182878
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2999525197
Short name T409
Test name
Test status
Simulation time 18191030 ps
CPU time 0.95 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 205756 kb
Host smart-ece55037-98dc-405b-9689-78bc4003bc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999525197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2999525197
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1898370268
Short name T158
Test name
Test status
Simulation time 398170473 ps
CPU time 3.54 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 205860 kb
Host smart-e7de8cfb-45a3-4744-9f01-96bd5fde5220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898370268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1898370268
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2032531413
Short name T121
Test name
Test status
Simulation time 80712800 ps
CPU time 2.7 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:41 PM PST 24
Peak memory 214404 kb
Host smart-34a52124-0e09-45ca-8362-6b99ecdbbcea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032531413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2032531413
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2880588774
Short name T480
Test name
Test status
Simulation time 635280067 ps
CPU time 3.12 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:42 PM PST 24
Peak memory 215212 kb
Host smart-4336d95d-6ba2-4942-bcd9-148f661297f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880588774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2880588774
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2570666689
Short name T143
Test name
Test status
Simulation time 42537779 ps
CPU time 1.86 seconds
Started Feb 04 12:51:59 PM PST 24
Finished Feb 04 12:52:05 PM PST 24
Peak memory 214056 kb
Host smart-0cea4d24-caab-4c4b-b24c-c8966da19145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570666689 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2570666689
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2228571669
Short name T499
Test name
Test status
Simulation time 12404695 ps
CPU time 1.05 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 205880 kb
Host smart-852477fe-07e6-4e87-a681-5a4e3752b1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228571669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2228571669
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2162527086
Short name T450
Test name
Test status
Simulation time 15836816 ps
CPU time 0.87 seconds
Started Feb 04 12:51:54 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 205760 kb
Host smart-587fdd52-e6b4-4fa7-b068-fe2643b24d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162527086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2162527086
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3579143434
Short name T156
Test name
Test status
Simulation time 20840101 ps
CPU time 1.34 seconds
Started Feb 04 12:51:46 PM PST 24
Finished Feb 04 12:51:50 PM PST 24
Peak memory 205956 kb
Host smart-dea5c55d-6159-44b4-a147-1b74d4b6e4ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579143434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3579143434
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.707204886
Short name T558
Test name
Test status
Simulation time 146505966 ps
CPU time 3.25 seconds
Started Feb 04 12:52:03 PM PST 24
Finished Feb 04 12:52:09 PM PST 24
Peak memory 214384 kb
Host smart-8f238000-0772-4d0a-97d6-513898b72f06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707204886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.707204886
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1148257971
Short name T501
Test name
Test status
Simulation time 352629441 ps
CPU time 4.28 seconds
Started Feb 04 12:52:02 PM PST 24
Finished Feb 04 12:52:10 PM PST 24
Peak memory 220080 kb
Host smart-91e30acc-8fbc-449e-b255-9cb24151d865
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148257971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1148257971
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3117382673
Short name T129
Test name
Test status
Simulation time 78008619 ps
CPU time 2.46 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:51:57 PM PST 24
Peak memory 213964 kb
Host smart-a0bf0473-6392-43d7-8f60-3006097ed2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117382673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3117382673
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2975173918
Short name T184
Test name
Test status
Simulation time 166868146 ps
CPU time 6.38 seconds
Started Feb 04 12:51:53 PM PST 24
Finished Feb 04 12:52:01 PM PST 24
Peak memory 209380 kb
Host smart-6395c267-e87e-4c0e-8083-36342fb14729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975173918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2975173918
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.898521188
Short name T131
Test name
Test status
Simulation time 44099169 ps
CPU time 1.79 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 218112 kb
Host smart-62717152-92b0-4b53-a9d6-e5cb0461b4bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898521188 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.898521188
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2490664898
Short name T149
Test name
Test status
Simulation time 33440718 ps
CPU time 0.88 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205700 kb
Host smart-ec04ed7c-2d60-4633-8e28-c0be7d777f6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490664898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2490664898
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.578742292
Short name T433
Test name
Test status
Simulation time 33091917 ps
CPU time 0.7 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:17 PM PST 24
Peak memory 205464 kb
Host smart-d85aa1d9-14c8-4697-afa4-e809f92b6a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578742292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.578742292
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1999396909
Short name T415
Test name
Test status
Simulation time 331355041 ps
CPU time 1.9 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:19 PM PST 24
Peak memory 205844 kb
Host smart-ab8f6cb0-f8a8-42ee-a15e-9a44b9e6b574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999396909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1999396909
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.420495545
Short name T547
Test name
Test status
Simulation time 374038822 ps
CPU time 4.93 seconds
Started Feb 04 12:51:14 PM PST 24
Finished Feb 04 12:51:22 PM PST 24
Peak memory 214400 kb
Host smart-3f5e12a4-83ae-4eef-ad4f-b0c35e0f15ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420495545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.420495545
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1646232726
Short name T531
Test name
Test status
Simulation time 336092767 ps
CPU time 11.77 seconds
Started Feb 04 12:51:18 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 214304 kb
Host smart-5ad08bc0-e4a1-4b94-923a-8b6657acf68f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646232726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1646232726
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1696827192
Short name T550
Test name
Test status
Simulation time 232086780 ps
CPU time 4.29 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 216076 kb
Host smart-14d185c6-9bc6-4a6b-8390-2651178a6d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696827192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1696827192
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3183522646
Short name T560
Test name
Test status
Simulation time 866569692 ps
CPU time 6.27 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:30 PM PST 24
Peak memory 213868 kb
Host smart-0e4fbc98-e026-4e39-8de3-96f8ee8281ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183522646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3183522646
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2096337327
Short name T556
Test name
Test status
Simulation time 83941307 ps
CPU time 1.3 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 213836 kb
Host smart-783fa7a7-fc9b-4e2a-9c37-a3690e8b2c79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096337327 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2096337327
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2963782229
Short name T369
Test name
Test status
Simulation time 29066640 ps
CPU time 0.93 seconds
Started Feb 04 12:51:25 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205632 kb
Host smart-43ecd7bc-61b0-4dc1-9e76-ab0b6abfe72b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963782229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2963782229
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2978403078
Short name T542
Test name
Test status
Simulation time 23359001 ps
CPU time 0.83 seconds
Started Feb 04 12:51:16 PM PST 24
Finished Feb 04 12:51:19 PM PST 24
Peak memory 205544 kb
Host smart-75f3a447-3121-4954-b195-b908d9e76c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978403078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2978403078
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.994689707
Short name T439
Test name
Test status
Simulation time 251516055 ps
CPU time 2.79 seconds
Started Feb 04 12:51:16 PM PST 24
Finished Feb 04 12:51:20 PM PST 24
Peak memory 205840 kb
Host smart-fbcd3c71-faa5-4e40-b24d-bfbccca776e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994689707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.994689707
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2544223408
Short name T190
Test name
Test status
Simulation time 420163627 ps
CPU time 2.62 seconds
Started Feb 04 12:51:18 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 214304 kb
Host smart-d24e2565-ff63-4c5b-b2e2-f193ec62be2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544223408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2544223408
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2672235734
Short name T458
Test name
Test status
Simulation time 3181265267 ps
CPU time 7.96 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 220228 kb
Host smart-7aaa372d-bfb1-4de6-81aa-679918dd89b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672235734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2672235734
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1934019179
Short name T178
Test name
Test status
Simulation time 449378007 ps
CPU time 2.27 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 214108 kb
Host smart-a2996869-7cca-4bff-95fc-bd624f48d7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934019179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1934019179
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1154020782
Short name T557
Test name
Test status
Simulation time 359978037 ps
CPU time 9.55 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:11 PM PST 24
Peak memory 205976 kb
Host smart-4836f9c5-7f9a-4ea0-b77c-98e3b9247fe4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154020782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
154020782
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1683541798
Short name T414
Test name
Test status
Simulation time 255701685 ps
CPU time 13.89 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 205696 kb
Host smart-b534e8c4-a21d-4748-ab6f-d60b30dd4ffa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683541798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
683541798
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.611122633
Short name T410
Test name
Test status
Simulation time 19643966 ps
CPU time 1 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:02 PM PST 24
Peak memory 205632 kb
Host smart-375f48b3-0c0a-4a67-b90c-6250673ffeb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611122633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.611122633
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3149792058
Short name T448
Test name
Test status
Simulation time 18333133 ps
CPU time 1.19 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:02 PM PST 24
Peak memory 205864 kb
Host smart-3db84843-c157-4784-b7f6-76a57dd8df7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149792058 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3149792058
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.749819008
Short name T423
Test name
Test status
Simulation time 24977868 ps
CPU time 1.37 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 205628 kb
Host smart-882aae8e-9269-48c4-af12-3fea7464f1f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749819008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.749819008
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1288329016
Short name T426
Test name
Test status
Simulation time 71889262 ps
CPU time 0.83 seconds
Started Feb 04 12:50:56 PM PST 24
Finished Feb 04 12:50:58 PM PST 24
Peak memory 205604 kb
Host smart-61fad698-b8b2-422c-8731-9dff60a29b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288329016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1288329016
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1608329936
Short name T473
Test name
Test status
Simulation time 346395287 ps
CPU time 3.63 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:14 PM PST 24
Peak memory 205632 kb
Host smart-902667a2-ecc7-4c4d-a085-a0790f2cc7fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608329936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1608329936
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1738848975
Short name T548
Test name
Test status
Simulation time 211307240 ps
CPU time 2.05 seconds
Started Feb 04 12:50:51 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 218680 kb
Host smart-f427b6aa-4f85-4347-9ead-f79b5e5d1230
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738848975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1738848975
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1553328358
Short name T122
Test name
Test status
Simulation time 377427580 ps
CPU time 13.43 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:14 PM PST 24
Peak memory 214456 kb
Host smart-c6f2d0cd-f62d-4d61-85fa-0bc446bfa68e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553328358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1553328358
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.869865024
Short name T425
Test name
Test status
Simulation time 26648725 ps
CPU time 1.65 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 214044 kb
Host smart-3218882f-d795-485d-b3bc-a5949f229c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869865024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.869865024
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2507027573
Short name T185
Test name
Test status
Simulation time 985226857 ps
CPU time 7.14 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:51:04 PM PST 24
Peak memory 208920 kb
Host smart-c3cee6b5-0ab7-4c4e-b515-970f4993e14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507027573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2507027573
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2890295684
Short name T502
Test name
Test status
Simulation time 18509690 ps
CPU time 0.69 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205452 kb
Host smart-effa4a18-b9b0-4731-8633-78410251fc3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890295684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2890295684
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1527283996
Short name T541
Test name
Test status
Simulation time 16465215 ps
CPU time 0.78 seconds
Started Feb 04 12:51:27 PM PST 24
Finished Feb 04 12:51:30 PM PST 24
Peak memory 205496 kb
Host smart-61a9486d-2017-445e-a6ba-f067e9639fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527283996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1527283996
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1120211729
Short name T534
Test name
Test status
Simulation time 27599571 ps
CPU time 0.73 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 205496 kb
Host smart-e1ca698c-0428-4cd1-a68a-9ea0d4904c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120211729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1120211729
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.526919860
Short name T489
Test name
Test status
Simulation time 33506870 ps
CPU time 0.8 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205420 kb
Host smart-16949af9-d991-48c1-9ee4-6e161d1197fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526919860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.526919860
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4031341862
Short name T454
Test name
Test status
Simulation time 8472767 ps
CPU time 0.71 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205376 kb
Host smart-697a64ac-5cc7-4483-bcc5-b369735ee191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031341862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4031341862
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3871346246
Short name T416
Test name
Test status
Simulation time 34601839 ps
CPU time 0.77 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 205548 kb
Host smart-a623beb5-2693-4fb9-bc20-c285bb88f23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871346246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3871346246
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1202100940
Short name T518
Test name
Test status
Simulation time 70482644 ps
CPU time 0.72 seconds
Started Feb 04 12:51:32 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 205472 kb
Host smart-1d9af87d-6438-4bb6-bc4f-cabb193156ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202100940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1202100940
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3026986031
Short name T544
Test name
Test status
Simulation time 25809903 ps
CPU time 1.09 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 205720 kb
Host smart-c2009526-fb13-4293-9f5e-050532e338b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026986031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3026986031
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.601755128
Short name T507
Test name
Test status
Simulation time 11169858 ps
CPU time 0.91 seconds
Started Feb 04 12:51:30 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 205544 kb
Host smart-1ce6713a-2ef3-4a7e-a993-dc708b404b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601755128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.601755128
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.567621986
Short name T412
Test name
Test status
Simulation time 77331491 ps
CPU time 0.83 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 205420 kb
Host smart-9f26f680-cdb0-4703-bbc8-601c6b45ca73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567621986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.567621986
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1220798600
Short name T535
Test name
Test status
Simulation time 296988666 ps
CPU time 4.47 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:51:03 PM PST 24
Peak memory 205908 kb
Host smart-da0ac94f-bb71-4200-ac57-8218e4bad88d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220798600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
220798600
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1391870141
Short name T456
Test name
Test status
Simulation time 661579646 ps
CPU time 8.98 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:51:07 PM PST 24
Peak memory 205760 kb
Host smart-5d385f83-1fca-42cc-8030-dfa5dbcebf3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391870141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
391870141
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3717333696
Short name T151
Test name
Test status
Simulation time 32499620 ps
CPU time 0.94 seconds
Started Feb 04 12:50:59 PM PST 24
Finished Feb 04 12:51:04 PM PST 24
Peak memory 205656 kb
Host smart-f58754a1-dd46-47ed-8bfe-995510f37ac7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717333696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
717333696
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2857716150
Short name T455
Test name
Test status
Simulation time 55481473 ps
CPU time 1.27 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 214100 kb
Host smart-bfed21ee-85af-48f2-ba32-108032b48015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857716150 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2857716150
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3618025101
Short name T452
Test name
Test status
Simulation time 50124788 ps
CPU time 1.4 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:54 PM PST 24
Peak memory 205844 kb
Host smart-25237fe8-b78c-483b-b4a3-08573724d5d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618025101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3618025101
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.137380314
Short name T435
Test name
Test status
Simulation time 8626363 ps
CPU time 0.69 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:54 PM PST 24
Peak memory 205564 kb
Host smart-a42d8d87-38d3-450e-b2f4-08a5e955bbd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137380314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.137380314
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3344604502
Short name T481
Test name
Test status
Simulation time 88055504 ps
CPU time 2.52 seconds
Started Feb 04 12:51:01 PM PST 24
Finished Feb 04 12:51:07 PM PST 24
Peak memory 205928 kb
Host smart-680561d6-af80-4845-8d3b-2fac480fefdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344604502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3344604502
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.320445079
Short name T119
Test name
Test status
Simulation time 326447403 ps
CPU time 5.13 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:51:03 PM PST 24
Peak memory 214376 kb
Host smart-6f6c60b5-d8be-4100-9eb2-ddbbd603273f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320445079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.320445079
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.883939400
Short name T492
Test name
Test status
Simulation time 380067109 ps
CPU time 8.58 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:10 PM PST 24
Peak memory 214440 kb
Host smart-622f88e6-a524-4a42-91c4-c6024c768415
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883939400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.883939400
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.865149578
Short name T130
Test name
Test status
Simulation time 38494789 ps
CPU time 2.68 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:04 PM PST 24
Peak memory 214124 kb
Host smart-57e2ee6a-d52a-4f60-adb8-fa45b3a035d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865149578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.865149578
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3185143911
Short name T142
Test name
Test status
Simulation time 133686628 ps
CPU time 5.85 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:51:02 PM PST 24
Peak memory 209096 kb
Host smart-313ef1dd-1ff5-4d6e-9eaf-c69639140609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185143911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3185143911
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.387023338
Short name T525
Test name
Test status
Simulation time 34693968 ps
CPU time 0.72 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205608 kb
Host smart-5630b82d-1d5e-4ea5-aa2b-6333a27b15e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387023338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.387023338
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.756942187
Short name T554
Test name
Test status
Simulation time 42265148 ps
CPU time 0.82 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205492 kb
Host smart-04715098-6b72-4932-8a16-fc2db1bdb27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756942187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.756942187
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4111392322
Short name T430
Test name
Test status
Simulation time 11790502 ps
CPU time 0.76 seconds
Started Feb 04 12:51:31 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 205400 kb
Host smart-10656ad1-5019-441f-9f92-a7b6d3de08fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111392322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4111392322
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3382845458
Short name T522
Test name
Test status
Simulation time 11382801 ps
CPU time 0.74 seconds
Started Feb 04 12:51:27 PM PST 24
Finished Feb 04 12:51:30 PM PST 24
Peak memory 205420 kb
Host smart-2b4a2525-98ae-48a8-ad10-3777a219214e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382845458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3382845458
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2385984363
Short name T549
Test name
Test status
Simulation time 8309846 ps
CPU time 0.72 seconds
Started Feb 04 12:51:25 PM PST 24
Finished Feb 04 12:51:28 PM PST 24
Peak memory 205604 kb
Host smart-de04fda9-3bef-455f-bcca-89d02c138cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385984363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2385984363
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1271881233
Short name T438
Test name
Test status
Simulation time 13183688 ps
CPU time 0.76 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 205484 kb
Host smart-5530b140-8f98-4eda-935a-e3cb3a02b085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271881233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1271881233
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1992374011
Short name T474
Test name
Test status
Simulation time 120032065 ps
CPU time 0.72 seconds
Started Feb 04 12:51:34 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 205560 kb
Host smart-8701043c-df6e-4c5b-ba8d-2a3d91a91377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992374011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1992374011
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1785269311
Short name T495
Test name
Test status
Simulation time 21241619 ps
CPU time 0.73 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:40 PM PST 24
Peak memory 205508 kb
Host smart-ced373b1-c7b7-4ba7-accd-50dbc0c0ad34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785269311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1785269311
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3414629325
Short name T498
Test name
Test status
Simulation time 26750634 ps
CPU time 0.75 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:49 PM PST 24
Peak memory 205552 kb
Host smart-93200ab0-f26a-4a95-878b-e5ddcfdd22fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414629325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3414629325
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1577136895
Short name T526
Test name
Test status
Simulation time 9822367 ps
CPU time 0.79 seconds
Started Feb 04 12:51:36 PM PST 24
Finished Feb 04 12:51:40 PM PST 24
Peak memory 205604 kb
Host smart-89c9e1ae-b8ac-4c6e-abb8-bd8e8bef54e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577136895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1577136895
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3288810880
Short name T533
Test name
Test status
Simulation time 141034469 ps
CPU time 4.82 seconds
Started Feb 04 12:51:00 PM PST 24
Finished Feb 04 12:51:09 PM PST 24
Peak memory 205880 kb
Host smart-058d4e6d-e088-457b-86f1-202e957c6cc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288810880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
288810880
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.722182116
Short name T491
Test name
Test status
Simulation time 1007064707 ps
CPU time 12.5 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 205892 kb
Host smart-1f8eac34-7a0f-4f10-a813-f16cd438a3a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722182116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.722182116
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2634993176
Short name T519
Test name
Test status
Simulation time 31687418 ps
CPU time 1.54 seconds
Started Feb 04 12:51:02 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 205884 kb
Host smart-4cc8080f-1134-4490-954c-e028379e4e93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634993176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
634993176
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1697243061
Short name T465
Test name
Test status
Simulation time 48601442 ps
CPU time 1.24 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 214120 kb
Host smart-29f877c7-8b09-4e5e-8dae-cd05d9b0f5b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697243061 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1697243061
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4041048698
Short name T424
Test name
Test status
Simulation time 42087964 ps
CPU time 1.14 seconds
Started Feb 04 12:51:06 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 205988 kb
Host smart-349fae57-c423-496f-b789-04ed07d5825d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041048698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4041048698
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1073018206
Short name T413
Test name
Test status
Simulation time 16441549 ps
CPU time 0.73 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 205496 kb
Host smart-0826c7e7-1fae-4b81-ae74-033868f85433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073018206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1073018206
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1209164567
Short name T461
Test name
Test status
Simulation time 77334529 ps
CPU time 2.69 seconds
Started Feb 04 12:51:06 PM PST 24
Finished Feb 04 12:51:10 PM PST 24
Peak memory 205872 kb
Host smart-8e679b43-f3c3-4a24-823b-d954ea8bac2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209164567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1209164567
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.722056486
Short name T513
Test name
Test status
Simulation time 329539641 ps
CPU time 8.69 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:14 PM PST 24
Peak memory 214232 kb
Host smart-ab86564a-3111-49b1-ab2b-58a39a0d010d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722056486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.722056486
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3574115810
Short name T436
Test name
Test status
Simulation time 31451967 ps
CPU time 1.85 seconds
Started Feb 04 12:51:01 PM PST 24
Finished Feb 04 12:51:07 PM PST 24
Peak memory 215220 kb
Host smart-e8425181-31e0-40c4-b013-db99e72b7bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574115810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3574115810
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.729122661
Short name T175
Test name
Test status
Simulation time 507427328 ps
CPU time 5.95 seconds
Started Feb 04 12:51:06 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 208816 kb
Host smart-36a82d72-ea1e-47b8-a5cc-8c5b8c209adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729122661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
729122661
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2399086795
Short name T418
Test name
Test status
Simulation time 21245182 ps
CPU time 0.76 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:48 PM PST 24
Peak memory 205580 kb
Host smart-fe7014be-0023-4d45-8f0c-61cc6d7a8cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399086795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2399086795
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3525780017
Short name T482
Test name
Test status
Simulation time 11160892 ps
CPU time 0.72 seconds
Started Feb 04 12:51:48 PM PST 24
Finished Feb 04 12:51:51 PM PST 24
Peak memory 205560 kb
Host smart-d4697ecb-bea3-42f1-a38b-43626698a181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525780017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3525780017
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3906922389
Short name T422
Test name
Test status
Simulation time 15714106 ps
CPU time 0.76 seconds
Started Feb 04 12:51:33 PM PST 24
Finished Feb 04 12:51:36 PM PST 24
Peak memory 205608 kb
Host smart-33840e96-4708-45ee-be4b-c89b40e470c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906922389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3906922389
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1359290522
Short name T479
Test name
Test status
Simulation time 13706224 ps
CPU time 0.75 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 205484 kb
Host smart-76158264-ed10-44a8-91be-56fd0e0c52fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359290522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1359290522
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2005681527
Short name T443
Test name
Test status
Simulation time 33469800 ps
CPU time 0.68 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:51:44 PM PST 24
Peak memory 205512 kb
Host smart-8d26c713-2dd5-45a5-9aba-e6f9940ebef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005681527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2005681527
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.403315376
Short name T441
Test name
Test status
Simulation time 23082444 ps
CPU time 0.74 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 205572 kb
Host smart-6d81b646-c5c2-4565-b600-a2efdedd01a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403315376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.403315376
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1959196973
Short name T445
Test name
Test status
Simulation time 27783634 ps
CPU time 0.73 seconds
Started Feb 04 12:51:38 PM PST 24
Finished Feb 04 12:51:40 PM PST 24
Peak memory 205528 kb
Host smart-025659c3-db26-4b6b-b993-96110fa6beda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959196973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1959196973
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3932270856
Short name T421
Test name
Test status
Simulation time 11614053 ps
CPU time 0.93 seconds
Started Feb 04 12:51:29 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 205500 kb
Host smart-d7785cd1-5e9d-43da-af33-d9dca415babb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932270856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3932270856
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.917943063
Short name T562
Test name
Test status
Simulation time 10958475 ps
CPU time 0.84 seconds
Started Feb 04 12:51:45 PM PST 24
Finished Feb 04 12:51:48 PM PST 24
Peak memory 205468 kb
Host smart-fa45ad89-93be-4625-baed-a6f78a29dc58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917943063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.917943063
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1587401767
Short name T440
Test name
Test status
Simulation time 138588661 ps
CPU time 0.75 seconds
Started Feb 04 12:51:41 PM PST 24
Finished Feb 04 12:51:43 PM PST 24
Peak memory 205436 kb
Host smart-ea9873d9-9893-4df7-9a5a-b7aeddedfd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587401767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1587401767
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2420777431
Short name T437
Test name
Test status
Simulation time 36336797 ps
CPU time 1.45 seconds
Started Feb 04 12:51:06 PM PST 24
Finished Feb 04 12:51:09 PM PST 24
Peak memory 214056 kb
Host smart-bed0c18c-f2c0-457b-8674-71dc721f765c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420777431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2420777431
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.19012780
Short name T152
Test name
Test status
Simulation time 12242670 ps
CPU time 1.08 seconds
Started Feb 04 12:51:02 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 205836 kb
Host smart-c11d6189-5f95-4d7d-a6ed-7861eceb2d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.19012780
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3909857609
Short name T488
Test name
Test status
Simulation time 60989361 ps
CPU time 0.85 seconds
Started Feb 04 12:51:01 PM PST 24
Finished Feb 04 12:51:06 PM PST 24
Peak memory 205472 kb
Host smart-1662228f-decf-4c6b-a31e-dd4df1bb8bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909857609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3909857609
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2992153
Short name T157
Test name
Test status
Simulation time 149875767 ps
CPU time 2.05 seconds
Started Feb 04 12:51:04 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 205820 kb
Host smart-816aa1cd-b413-4c6e-8ce5-6330ac809cab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_
csr_outstanding.2992153
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1532250986
Short name T189
Test name
Test status
Simulation time 202768864 ps
CPU time 5.69 seconds
Started Feb 04 12:51:02 PM PST 24
Finished Feb 04 12:51:11 PM PST 24
Peak memory 214352 kb
Host smart-03a3c3b9-337b-415b-b314-ab372577e1a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532250986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1532250986
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1568021840
Short name T475
Test name
Test status
Simulation time 160864625 ps
CPU time 4.63 seconds
Started Feb 04 12:51:04 PM PST 24
Finished Feb 04 12:51:10 PM PST 24
Peak memory 214452 kb
Host smart-48dcbdd9-c89c-4841-8d88-d22db470f2c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568021840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1568021840
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3254349170
Short name T469
Test name
Test status
Simulation time 74024203 ps
CPU time 2.44 seconds
Started Feb 04 12:51:03 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 213932 kb
Host smart-e754cc8d-15b8-4c95-b26b-15a59d074386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254349170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3254349170
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2339908650
Short name T368
Test name
Test status
Simulation time 126217811 ps
CPU time 3.6 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 209684 kb
Host smart-7fe08180-94bb-4d70-bed7-5a6e2a8cf9c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339908650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2339908650
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2584970206
Short name T466
Test name
Test status
Simulation time 27807036 ps
CPU time 1.7 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:12 PM PST 24
Peak memory 214104 kb
Host smart-8b0a7808-4f2a-4d3b-aab5-e997771230a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584970206 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2584970206
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2341345739
Short name T150
Test name
Test status
Simulation time 45580510 ps
CPU time 1.17 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:02 PM PST 24
Peak memory 205880 kb
Host smart-5c26d955-7585-431f-8bff-408d7362b035
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341345739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2341345739
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1950307755
Short name T545
Test name
Test status
Simulation time 106653335 ps
CPU time 0.91 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 205608 kb
Host smart-12f25c26-86b4-4397-a0da-4b7d54d8f3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950307755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1950307755
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2345378271
Short name T154
Test name
Test status
Simulation time 43743535 ps
CPU time 1.95 seconds
Started Feb 04 12:51:12 PM PST 24
Finished Feb 04 12:51:16 PM PST 24
Peak memory 205932 kb
Host smart-a89c6fdd-90df-40e9-9723-bd10c084ecf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345378271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2345378271
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.331499461
Short name T493
Test name
Test status
Simulation time 352898089 ps
CPU time 6.28 seconds
Started Feb 04 12:51:06 PM PST 24
Finished Feb 04 12:51:14 PM PST 24
Peak memory 214428 kb
Host smart-1ab34a2a-6a83-403c-a319-8361176e630f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331499461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.331499461
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1216919892
Short name T124
Test name
Test status
Simulation time 623304510 ps
CPU time 8.29 seconds
Started Feb 04 12:51:00 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 214424 kb
Host smart-c811e34a-ba0f-49c6-b90a-36f4b26e68bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216919892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1216919892
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1861131898
Short name T471
Test name
Test status
Simulation time 688237600 ps
CPU time 3.06 seconds
Started Feb 04 12:51:05 PM PST 24
Finished Feb 04 12:51:09 PM PST 24
Peak memory 216132 kb
Host smart-0312cb9d-30e6-46c9-884d-a99c1514df31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861131898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1861131898
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1241277218
Short name T446
Test name
Test status
Simulation time 13841028 ps
CPU time 0.83 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205564 kb
Host smart-46f492f6-2740-49a3-b323-1656117d432d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241277218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1241277218
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.869890185
Short name T514
Test name
Test status
Simulation time 144641926 ps
CPU time 1.27 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:50:58 PM PST 24
Peak memory 205836 kb
Host smart-88b49905-ee4a-45db-a2e0-72338eaae507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869890185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.869890185
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.382974154
Short name T530
Test name
Test status
Simulation time 22265162 ps
CPU time 0.76 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:50:58 PM PST 24
Peak memory 205604 kb
Host smart-97701935-e961-46c0-9153-fbf635b80b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382974154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.382974154
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4281146627
Short name T484
Test name
Test status
Simulation time 449089727 ps
CPU time 3.13 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:58 PM PST 24
Peak memory 205700 kb
Host smart-23cd9015-ee75-4604-a3a5-e1246c4387d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281146627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4281146627
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.317840363
Short name T434
Test name
Test status
Simulation time 116099107 ps
CPU time 3.14 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:13 PM PST 24
Peak memory 222240 kb
Host smart-775ec5a9-ba5c-4d6e-8695-a7c2ec57baa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317840363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.317840363
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1955789001
Short name T485
Test name
Test status
Simulation time 1734799309 ps
CPU time 7.09 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:51:05 PM PST 24
Peak memory 220124 kb
Host smart-f21a0986-7bba-475e-aec6-a63628aa4f15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955789001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1955789001
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2695042133
Short name T494
Test name
Test status
Simulation time 85118729 ps
CPU time 2.27 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:12 PM PST 24
Peak memory 216308 kb
Host smart-600f0f65-b905-41a0-81fc-e87d88d00d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695042133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2695042133
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.747754527
Short name T188
Test name
Test status
Simulation time 142665580 ps
CPU time 4.73 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 209300 kb
Host smart-7fa059a5-1366-41b9-9b29-9f736d464908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747754527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
747754527
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.557228415
Short name T521
Test name
Test status
Simulation time 113225805 ps
CPU time 1.61 seconds
Started Feb 04 12:51:15 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 213856 kb
Host smart-e8b5d91f-ad09-43be-9c2d-1656c94b6d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557228415 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.557228415
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.220034080
Short name T467
Test name
Test status
Simulation time 52772431 ps
CPU time 1.04 seconds
Started Feb 04 12:51:09 PM PST 24
Finished Feb 04 12:51:11 PM PST 24
Peak memory 205924 kb
Host smart-a3ab19f2-8c2a-4092-adc1-5b4bb726a038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220034080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.220034080
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.305069873
Short name T476
Test name
Test status
Simulation time 191580292 ps
CPU time 0.84 seconds
Started Feb 04 12:51:21 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 205552 kb
Host smart-07c021bb-e061-44ad-a6e8-cb0d5226a662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305069873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.305069873
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3826121386
Short name T486
Test name
Test status
Simulation time 44335564 ps
CPU time 1.55 seconds
Started Feb 04 12:51:28 PM PST 24
Finished Feb 04 12:51:32 PM PST 24
Peak memory 205876 kb
Host smart-fd7e76e3-d6cb-44de-8beb-902cfacf7ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826121386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3826121386
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1191934851
Short name T123
Test name
Test status
Simulation time 1368831718 ps
CPU time 8.8 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 214424 kb
Host smart-454339a9-fbd2-4f8b-882c-db2fdcd4cddb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191934851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1191934851
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3375233573
Short name T118
Test name
Test status
Simulation time 336813675 ps
CPU time 3.98 seconds
Started Feb 04 12:51:11 PM PST 24
Finished Feb 04 12:51:17 PM PST 24
Peak memory 214392 kb
Host smart-4b2f1941-a7ab-4298-b8b1-d3ff8dd6d0ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375233573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3375233573
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2770899924
Short name T483
Test name
Test status
Simulation time 76293772 ps
CPU time 2.78 seconds
Started Feb 04 12:51:18 PM PST 24
Finished Feb 04 12:51:27 PM PST 24
Peak memory 215044 kb
Host smart-d1832b27-87c1-4845-b3d8-e11796e01c20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770899924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2770899924
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3262852813
Short name T497
Test name
Test status
Simulation time 492131352 ps
CPU time 5.05 seconds
Started Feb 04 12:51:17 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 209144 kb
Host smart-67d92fb9-58d0-4868-a23c-e2d04bf993d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262852813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3262852813
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.186030694
Short name T133
Test name
Test status
Simulation time 17610434 ps
CPU time 1.43 seconds
Started Feb 04 12:51:20 PM PST 24
Finished Feb 04 12:51:26 PM PST 24
Peak memory 214036 kb
Host smart-e1baea74-bd4c-467e-b5a8-36a0d3bdac34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186030694 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.186030694
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2012217781
Short name T428
Test name
Test status
Simulation time 240226382 ps
CPU time 1.56 seconds
Started Feb 04 12:51:16 PM PST 24
Finished Feb 04 12:51:19 PM PST 24
Peak memory 205872 kb
Host smart-f80bbdce-f2d7-43e4-9b62-b94caca02633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012217781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2012217781
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.417886558
Short name T417
Test name
Test status
Simulation time 41377083 ps
CPU time 0.73 seconds
Started Feb 04 12:51:26 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 205420 kb
Host smart-18b423ba-0a56-49ee-859e-9508f410e47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417886558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.417886558
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3944776196
Short name T419
Test name
Test status
Simulation time 222808691 ps
CPU time 2.32 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 205904 kb
Host smart-6807a73f-611b-458f-a243-cd3c470ffbf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944776196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3944776196
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2003660154
Short name T524
Test name
Test status
Simulation time 594892946 ps
CPU time 3.47 seconds
Started Feb 04 12:51:24 PM PST 24
Finished Feb 04 12:51:29 PM PST 24
Peak memory 214424 kb
Host smart-bb53e324-2dfb-4ff0-a134-5f107121d269
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003660154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2003660154
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1321381336
Short name T478
Test name
Test status
Simulation time 639581185 ps
CPU time 8.36 seconds
Started Feb 04 12:51:23 PM PST 24
Finished Feb 04 12:51:33 PM PST 24
Peak memory 219968 kb
Host smart-5c812d8b-51f8-48db-9d86-8f2f38efaab8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321381336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1321381336
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.358995753
Short name T496
Test name
Test status
Simulation time 158862698 ps
CPU time 3.34 seconds
Started Feb 04 12:51:11 PM PST 24
Finished Feb 04 12:51:15 PM PST 24
Peak memory 213984 kb
Host smart-f2361597-68de-4dc2-b41e-e877a85a2bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358995753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.358995753
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2081280612
Short name T174
Test name
Test status
Simulation time 145632868 ps
CPU time 6.02 seconds
Started Feb 04 12:51:14 PM PST 24
Finished Feb 04 12:51:23 PM PST 24
Peak memory 208892 kb
Host smart-eaff8477-c6bb-4ed4-86e8-08331282093c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081280612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2081280612
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.445171993
Short name T847
Test name
Test status
Simulation time 10426588 ps
CPU time 0.72 seconds
Started Feb 04 03:19:55 PM PST 24
Finished Feb 04 03:19:57 PM PST 24
Peak memory 206484 kb
Host smart-f8bcd53a-21e6-4150-9655-fabcc2ba64d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445171993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.445171993
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3139577252
Short name T280
Test name
Test status
Simulation time 52835403 ps
CPU time 2.98 seconds
Started Feb 04 03:19:40 PM PST 24
Finished Feb 04 03:19:47 PM PST 24
Peak memory 215528 kb
Host smart-a60bff28-6580-4648-8b2a-5adeeca441c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139577252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3139577252
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.257393562
Short name T23
Test name
Test status
Simulation time 3597634348 ps
CPU time 18.53 seconds
Started Feb 04 03:19:40 PM PST 24
Finished Feb 04 03:20:03 PM PST 24
Peak memory 215164 kb
Host smart-0f7c9585-8be4-4406-a9c3-bd555785f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257393562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.257393562
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2355654227
Short name T854
Test name
Test status
Simulation time 52512652 ps
CPU time 2.89 seconds
Started Feb 04 03:19:42 PM PST 24
Finished Feb 04 03:19:47 PM PST 24
Peak memory 214756 kb
Host smart-bf360ad7-18ed-4483-9de2-78a6a0f51569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355654227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2355654227
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2668239451
Short name T830
Test name
Test status
Simulation time 203937629 ps
CPU time 6.98 seconds
Started Feb 04 03:19:41 PM PST 24
Finished Feb 04 03:19:51 PM PST 24
Peak memory 220668 kb
Host smart-8316e1f0-b1b3-4c65-8ba1-a22eba6cc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668239451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2668239451
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3316875774
Short name T337
Test name
Test status
Simulation time 2086004922 ps
CPU time 61.57 seconds
Started Feb 04 03:19:42 PM PST 24
Finished Feb 04 03:20:46 PM PST 24
Peak memory 222972 kb
Host smart-3928e4f0-32df-458c-a62d-b3fb7eef650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316875774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3316875774
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3636377710
Short name T752
Test name
Test status
Simulation time 76678008 ps
CPU time 2.57 seconds
Started Feb 04 03:19:43 PM PST 24
Finished Feb 04 03:19:47 PM PST 24
Peak memory 207200 kb
Host smart-57c9e7be-f6f3-4211-a542-bfba9d0bee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636377710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3636377710
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4185435493
Short name T628
Test name
Test status
Simulation time 4779022132 ps
CPU time 61.92 seconds
Started Feb 04 03:19:43 PM PST 24
Finished Feb 04 03:20:46 PM PST 24
Peak memory 208944 kb
Host smart-fac77a14-23d2-4bf6-9451-ce0dac0da1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185435493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4185435493
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2809338942
Short name T706
Test name
Test status
Simulation time 4701152661 ps
CPU time 8.58 seconds
Started Feb 04 03:19:44 PM PST 24
Finished Feb 04 03:19:54 PM PST 24
Peak memory 208756 kb
Host smart-e99ad30f-854a-4f37-961a-1f966537c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809338942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2809338942
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.414617158
Short name T1060
Test name
Test status
Simulation time 293639570 ps
CPU time 4.92 seconds
Started Feb 04 03:19:42 PM PST 24
Finished Feb 04 03:19:49 PM PST 24
Peak memory 207276 kb
Host smart-933da10c-c4c6-4b30-ac4b-faf31295033e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414617158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.414617158
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1182969395
Short name T602
Test name
Test status
Simulation time 251402801 ps
CPU time 6.98 seconds
Started Feb 04 03:19:41 PM PST 24
Finished Feb 04 03:19:51 PM PST 24
Peak memory 208168 kb
Host smart-2644ccbc-0c13-4de9-ae57-968e6777bd1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182969395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1182969395
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3550344298
Short name T783
Test name
Test status
Simulation time 226233219 ps
CPU time 6.12 seconds
Started Feb 04 03:19:44 PM PST 24
Finished Feb 04 03:19:52 PM PST 24
Peak memory 208132 kb
Host smart-4f3a2ca0-b03f-4a7c-8238-a0ae36380493
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550344298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3550344298
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4270771040
Short name T237
Test name
Test status
Simulation time 30852768 ps
CPU time 2.13 seconds
Started Feb 04 03:19:54 PM PST 24
Finished Feb 04 03:19:57 PM PST 24
Peak memory 210576 kb
Host smart-f58fd31c-1d4a-4e3c-bbe9-b9606f26f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270771040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4270771040
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1569729891
Short name T885
Test name
Test status
Simulation time 123000166 ps
CPU time 2.78 seconds
Started Feb 04 03:19:37 PM PST 24
Finished Feb 04 03:19:41 PM PST 24
Peak memory 208588 kb
Host smart-7d564b34-e387-428a-82fa-914f96de954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569729891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1569729891
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2276920151
Short name T877
Test name
Test status
Simulation time 99280361 ps
CPU time 3.41 seconds
Started Feb 04 03:19:42 PM PST 24
Finished Feb 04 03:19:48 PM PST 24
Peak memory 207796 kb
Host smart-40369164-c6d3-41d1-b31e-2f44663ff0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276920151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2276920151
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1440238632
Short name T810
Test name
Test status
Simulation time 622752898 ps
CPU time 4.22 seconds
Started Feb 04 03:19:56 PM PST 24
Finished Feb 04 03:20:01 PM PST 24
Peak memory 211056 kb
Host smart-7c6c3bc5-1f1d-4b54-a048-11134368b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440238632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1440238632
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2770610315
Short name T1022
Test name
Test status
Simulation time 32994834 ps
CPU time 0.73 seconds
Started Feb 04 03:20:16 PM PST 24
Finished Feb 04 03:20:18 PM PST 24
Peak memory 206444 kb
Host smart-1fb24596-f3fe-4a74-ade8-c652c384fb20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770610315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2770610315
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.480606102
Short name T245
Test name
Test status
Simulation time 318703266 ps
CPU time 2.82 seconds
Started Feb 04 03:20:16 PM PST 24
Finished Feb 04 03:20:20 PM PST 24
Peak memory 214804 kb
Host smart-992b4c4c-9aa6-4170-910c-f02220f01ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480606102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.480606102
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.52893440
Short name T289
Test name
Test status
Simulation time 206924190 ps
CPU time 4.32 seconds
Started Feb 04 03:20:15 PM PST 24
Finished Feb 04 03:20:21 PM PST 24
Peak memory 214764 kb
Host smart-a870e67b-606b-4901-bd32-8f719b1c0247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52893440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.52893440
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2722084737
Short name T362
Test name
Test status
Simulation time 440939892 ps
CPU time 6.96 seconds
Started Feb 04 03:20:17 PM PST 24
Finished Feb 04 03:20:25 PM PST 24
Peak memory 222980 kb
Host smart-1ff3ed38-4550-4891-af08-b10570f28f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722084737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2722084737
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2274227662
Short name T45
Test name
Test status
Simulation time 1514060450 ps
CPU time 7.96 seconds
Started Feb 04 03:20:19 PM PST 24
Finished Feb 04 03:20:30 PM PST 24
Peak memory 210876 kb
Host smart-4708b842-00f5-41d1-9c16-570d8dd41e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274227662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2274227662
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4279081711
Short name T692
Test name
Test status
Simulation time 426705723 ps
CPU time 9.15 seconds
Started Feb 04 03:20:18 PM PST 24
Finished Feb 04 03:20:28 PM PST 24
Peak memory 214840 kb
Host smart-c4628f9e-d1d0-4f23-bfe9-9489ee017f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279081711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4279081711
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3235330762
Short name T105
Test name
Test status
Simulation time 1073638861 ps
CPU time 9.93 seconds
Started Feb 04 03:20:17 PM PST 24
Finished Feb 04 03:20:28 PM PST 24
Peak memory 231124 kb
Host smart-ad4e28d6-dfc2-4eac-8c66-04ca01e384ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235330762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3235330762
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1173982606
Short name T729
Test name
Test status
Simulation time 27680894 ps
CPU time 2.08 seconds
Started Feb 04 03:19:54 PM PST 24
Finished Feb 04 03:19:57 PM PST 24
Peak memory 209092 kb
Host smart-e1d7b380-6a9d-4965-b85d-e3f041f3edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173982606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1173982606
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1167739354
Short name T673
Test name
Test status
Simulation time 122296048 ps
CPU time 2.66 seconds
Started Feb 04 03:20:17 PM PST 24
Finished Feb 04 03:20:21 PM PST 24
Peak memory 207964 kb
Host smart-37a4e904-8168-4195-99ee-69bcf38d6c4d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167739354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1167739354
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3197353188
Short name T593
Test name
Test status
Simulation time 6173901833 ps
CPU time 35.6 seconds
Started Feb 04 03:20:20 PM PST 24
Finished Feb 04 03:20:59 PM PST 24
Peak memory 209184 kb
Host smart-646f934b-c66a-47c4-8183-9fb2d9b2bcde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197353188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3197353188
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2404976832
Short name T334
Test name
Test status
Simulation time 48118590 ps
CPU time 2.57 seconds
Started Feb 04 03:20:14 PM PST 24
Finished Feb 04 03:20:18 PM PST 24
Peak memory 207196 kb
Host smart-44b8e168-915d-4648-9b82-428c0f444a6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404976832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2404976832
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.784843537
Short name T837
Test name
Test status
Simulation time 111595269 ps
CPU time 2.04 seconds
Started Feb 04 03:20:29 PM PST 24
Finished Feb 04 03:20:32 PM PST 24
Peak memory 208280 kb
Host smart-31feedcf-1c79-44ba-be00-b6438507116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784843537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.784843537
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.919517173
Short name T676
Test name
Test status
Simulation time 152622214 ps
CPU time 3.33 seconds
Started Feb 04 03:19:55 PM PST 24
Finished Feb 04 03:19:59 PM PST 24
Peak memory 209020 kb
Host smart-a91ddc2b-c953-43ff-b3e8-6a244c8c5004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919517173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.919517173
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1523946307
Short name T967
Test name
Test status
Simulation time 146226018 ps
CPU time 2.71 seconds
Started Feb 04 03:20:15 PM PST 24
Finished Feb 04 03:20:19 PM PST 24
Peak memory 207972 kb
Host smart-56192f66-27e7-480e-8837-a4842c11e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523946307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1523946307
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2475635191
Short name T976
Test name
Test status
Simulation time 278949289 ps
CPU time 3.82 seconds
Started Feb 04 03:20:19 PM PST 24
Finished Feb 04 03:20:25 PM PST 24
Peak memory 210468 kb
Host smart-f1391b24-97e7-4c7c-a271-573be31a2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475635191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2475635191
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.399739788
Short name T632
Test name
Test status
Simulation time 17674991 ps
CPU time 0.86 seconds
Started Feb 04 03:21:50 PM PST 24
Finished Feb 04 03:21:54 PM PST 24
Peak memory 206480 kb
Host smart-2a53feb8-e8f5-4614-8dff-44f7683905e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399739788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.399739788
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.992651800
Short name T29
Test name
Test status
Simulation time 94262596 ps
CPU time 3.69 seconds
Started Feb 04 03:21:50 PM PST 24
Finished Feb 04 03:21:57 PM PST 24
Peak memory 223272 kb
Host smart-6799f86d-7733-444e-a661-065479795c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992651800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.992651800
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.64923888
Short name T47
Test name
Test status
Simulation time 751145915 ps
CPU time 7.45 seconds
Started Feb 04 03:21:48 PM PST 24
Finished Feb 04 03:21:59 PM PST 24
Peak memory 208892 kb
Host smart-415942ed-184b-4db0-9d5c-02143b2e702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64923888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.64923888
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2753939598
Short name T296
Test name
Test status
Simulation time 330383545 ps
CPU time 5.04 seconds
Started Feb 04 03:21:47 PM PST 24
Finished Feb 04 03:21:57 PM PST 24
Peak memory 210124 kb
Host smart-370cadcf-a3d5-4683-be5e-72c5e7421040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753939598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2753939598
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3211350107
Short name T985
Test name
Test status
Simulation time 586069076 ps
CPU time 12.24 seconds
Started Feb 04 03:21:48 PM PST 24
Finished Feb 04 03:22:04 PM PST 24
Peak memory 214808 kb
Host smart-1f0eb006-fee0-4b8d-a507-b2df85a30b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211350107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3211350107
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.979113922
Short name T1032
Test name
Test status
Simulation time 379646763 ps
CPU time 3.41 seconds
Started Feb 04 03:21:50 PM PST 24
Finished Feb 04 03:21:56 PM PST 24
Peak memory 209088 kb
Host smart-97cc72f3-1c8b-4940-a1f2-927c3fba15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979113922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.979113922
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2264602109
Short name T371
Test name
Test status
Simulation time 239977443 ps
CPU time 6.91 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:21:59 PM PST 24
Peak memory 210116 kb
Host smart-0d608b60-d3d0-4f39-879a-8c7738b48346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264602109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2264602109
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3859756993
Short name T315
Test name
Test status
Simulation time 190029800 ps
CPU time 2.7 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:21:55 PM PST 24
Peak memory 206968 kb
Host smart-c4d7be2e-8aaf-4d3f-b9ca-f648ab221b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859756993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3859756993
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.436164491
Short name T1013
Test name
Test status
Simulation time 2039034551 ps
CPU time 5.88 seconds
Started Feb 04 03:21:42 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 208124 kb
Host smart-966e6fdf-ad3c-4a27-bae9-2b8c5a324acd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436164491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.436164491
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3869060466
Short name T671
Test name
Test status
Simulation time 221111903 ps
CPU time 3.09 seconds
Started Feb 04 03:21:42 PM PST 24
Finished Feb 04 03:21:46 PM PST 24
Peak memory 207192 kb
Host smart-042d0164-7205-46d1-aa73-53f90a27237a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869060466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3869060466
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3051447265
Short name T600
Test name
Test status
Simulation time 502965996 ps
CPU time 4.09 seconds
Started Feb 04 03:21:44 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 207144 kb
Host smart-4932e31d-2554-4bbf-b050-2435f5d56566
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051447265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3051447265
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.21478863
Short name T958
Test name
Test status
Simulation time 481878136 ps
CPU time 11.43 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:22:04 PM PST 24
Peak memory 209296 kb
Host smart-e019f12a-44ba-41f6-9df2-672121d176a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21478863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.21478863
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3044152878
Short name T1043
Test name
Test status
Simulation time 4014228723 ps
CPU time 25.02 seconds
Started Feb 04 03:21:45 PM PST 24
Finished Feb 04 03:22:12 PM PST 24
Peak memory 209000 kb
Host smart-4d09a116-d1e2-462a-b892-5eb6388f99f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044152878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3044152878
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2451023351
Short name T735
Test name
Test status
Simulation time 245472261 ps
CPU time 7.11 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:22:00 PM PST 24
Peak memory 220632 kb
Host smart-cd3c193a-eff8-4eb6-a7dc-d299801fc4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451023351 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2451023351
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2064562943
Short name T818
Test name
Test status
Simulation time 143860212 ps
CPU time 2.31 seconds
Started Feb 04 03:21:47 PM PST 24
Finished Feb 04 03:21:53 PM PST 24
Peak memory 210300 kb
Host smart-48e983a5-e55b-477f-9474-d1c0ba3bcb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064562943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2064562943
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3047901977
Short name T1050
Test name
Test status
Simulation time 14297574 ps
CPU time 0.94 seconds
Started Feb 04 03:22:11 PM PST 24
Finished Feb 04 03:22:13 PM PST 24
Peak memory 206508 kb
Host smart-83bd50ff-20ae-4da9-b4e1-e98b27f28d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047901977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3047901977
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1522726015
Short name T310
Test name
Test status
Simulation time 1282038902 ps
CPU time 16.92 seconds
Started Feb 04 03:21:58 PM PST 24
Finished Feb 04 03:22:18 PM PST 24
Peak memory 214820 kb
Host smart-f76d5bbe-ec7f-44a0-acbb-c3b2f0818dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522726015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1522726015
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1068766989
Short name T816
Test name
Test status
Simulation time 83339715 ps
CPU time 3.63 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:12 PM PST 24
Peak memory 218016 kb
Host smart-70eef732-924f-4bf9-8322-5c95d2252d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068766989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1068766989
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.47864560
Short name T394
Test name
Test status
Simulation time 1147089825 ps
CPU time 7.58 seconds
Started Feb 04 03:21:59 PM PST 24
Finished Feb 04 03:22:09 PM PST 24
Peak memory 208052 kb
Host smart-edef35e3-3f56-40e3-b12c-7dd6cf375044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47864560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.47864560
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2439512222
Short name T814
Test name
Test status
Simulation time 83127237 ps
CPU time 4.05 seconds
Started Feb 04 03:22:12 PM PST 24
Finished Feb 04 03:22:17 PM PST 24
Peak memory 208616 kb
Host smart-c90cbfb2-7470-4cbd-9366-4098f420f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439512222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2439512222
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3775428089
Short name T938
Test name
Test status
Simulation time 203596494 ps
CPU time 5.92 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:15 PM PST 24
Peak memory 214776 kb
Host smart-aae66f1d-0bca-496c-b8f7-217b93adaf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775428089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3775428089
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2435350792
Short name T921
Test name
Test status
Simulation time 292591932 ps
CPU time 3.75 seconds
Started Feb 04 03:21:57 PM PST 24
Finished Feb 04 03:22:05 PM PST 24
Peak memory 210164 kb
Host smart-1bd590c4-e1bb-4f63-a757-1173cf03296e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435350792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2435350792
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1960737526
Short name T353
Test name
Test status
Simulation time 377891876 ps
CPU time 3.26 seconds
Started Feb 04 03:21:58 PM PST 24
Finished Feb 04 03:22:04 PM PST 24
Peak memory 214892 kb
Host smart-dd5d2061-d433-4017-bf85-d90f7844f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960737526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1960737526
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1828959677
Short name T647
Test name
Test status
Simulation time 51154665 ps
CPU time 3.06 seconds
Started Feb 04 03:22:01 PM PST 24
Finished Feb 04 03:22:06 PM PST 24
Peak memory 208940 kb
Host smart-5cdb71a4-dab2-47ed-a14d-376a2625445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828959677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1828959677
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3458792673
Short name T867
Test name
Test status
Simulation time 202715189 ps
CPU time 4.31 seconds
Started Feb 04 03:21:58 PM PST 24
Finished Feb 04 03:22:05 PM PST 24
Peak memory 209424 kb
Host smart-c3cbe856-1635-48eb-b992-2dfa7ebcc128
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458792673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3458792673
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2657251057
Short name T710
Test name
Test status
Simulation time 381452080 ps
CPU time 8.25 seconds
Started Feb 04 03:21:58 PM PST 24
Finished Feb 04 03:22:10 PM PST 24
Peak memory 208320 kb
Host smart-40aaa593-e8f8-4056-af92-ffd499d610a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657251057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2657251057
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1654361158
Short name T603
Test name
Test status
Simulation time 1324895616 ps
CPU time 6.91 seconds
Started Feb 04 03:22:02 PM PST 24
Finished Feb 04 03:22:10 PM PST 24
Peak memory 208400 kb
Host smart-534ae446-b93d-4f53-ba61-583bba85a022
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654361158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1654361158
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3700882323
Short name T1024
Test name
Test status
Simulation time 327303547 ps
CPU time 7.23 seconds
Started Feb 04 03:22:08 PM PST 24
Finished Feb 04 03:22:16 PM PST 24
Peak memory 208432 kb
Host smart-6149a2a2-c834-4c08-9bc7-144c9f8e9db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700882323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3700882323
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2330371814
Short name T695
Test name
Test status
Simulation time 248446285 ps
CPU time 3.08 seconds
Started Feb 04 03:21:48 PM PST 24
Finished Feb 04 03:21:55 PM PST 24
Peak memory 208972 kb
Host smart-ef63f96a-aef0-4920-b108-c15da7257fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330371814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2330371814
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.38909478
Short name T242
Test name
Test status
Simulation time 3476495835 ps
CPU time 25.97 seconds
Started Feb 04 03:22:06 PM PST 24
Finished Feb 04 03:22:34 PM PST 24
Peak memory 215916 kb
Host smart-502c825a-5c41-4312-97e4-f54650fea18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.38909478
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3629472769
Short name T941
Test name
Test status
Simulation time 2458936777 ps
CPU time 9.52 seconds
Started Feb 04 03:22:12 PM PST 24
Finished Feb 04 03:22:23 PM PST 24
Peak memory 223236 kb
Host smart-bb001400-e747-449a-ba8a-c8f63d2dd456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629472769 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3629472769
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4082932379
Short name T691
Test name
Test status
Simulation time 1090166213 ps
CPU time 5.08 seconds
Started Feb 04 03:21:59 PM PST 24
Finished Feb 04 03:22:07 PM PST 24
Peak memory 207828 kb
Host smart-b2499a87-8557-4853-90c6-a887039f652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082932379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4082932379
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1917304966
Short name T904
Test name
Test status
Simulation time 11388367 ps
CPU time 0.9 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:20 PM PST 24
Peak memory 206500 kb
Host smart-dc8125e0-c443-4d78-af36-26f4ccbc73cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917304966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1917304966
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4176101578
Short name T896
Test name
Test status
Simulation time 191015944 ps
CPU time 1.47 seconds
Started Feb 04 03:22:26 PM PST 24
Finished Feb 04 03:22:30 PM PST 24
Peak memory 219776 kb
Host smart-143cc7db-2fae-4e03-98d3-24348461148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176101578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4176101578
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2284449277
Short name T318
Test name
Test status
Simulation time 21625695 ps
CPU time 1.8 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:10 PM PST 24
Peak memory 207464 kb
Host smart-a17cc30e-a4e5-4043-bf69-9ff7909337e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284449277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2284449277
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3734463927
Short name T367
Test name
Test status
Simulation time 74423020 ps
CPU time 3.46 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:22 PM PST 24
Peak memory 214832 kb
Host smart-441ff1b2-1ad1-4ba2-b2a2-1303a7037000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734463927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3734463927
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2817526042
Short name T678
Test name
Test status
Simulation time 431699852 ps
CPU time 4.02 seconds
Started Feb 04 03:22:06 PM PST 24
Finished Feb 04 03:22:12 PM PST 24
Peak memory 216364 kb
Host smart-f60a1eb1-3df2-4c5a-af64-d8827fdff09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817526042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2817526042
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3893300678
Short name T597
Test name
Test status
Simulation time 41680315 ps
CPU time 3.05 seconds
Started Feb 04 03:22:05 PM PST 24
Finished Feb 04 03:22:11 PM PST 24
Peak memory 208264 kb
Host smart-c4771528-b583-4a37-9591-a7c667deb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893300678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3893300678
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3907706675
Short name T995
Test name
Test status
Simulation time 939311877 ps
CPU time 11.72 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:20 PM PST 24
Peak memory 208944 kb
Host smart-83ed87bd-38c7-454b-965b-b504968b46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907706675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3907706675
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2865598021
Short name T753
Test name
Test status
Simulation time 5023748197 ps
CPU time 31.25 seconds
Started Feb 04 03:22:06 PM PST 24
Finished Feb 04 03:22:39 PM PST 24
Peak memory 209256 kb
Host smart-6564e9a9-8c2a-4787-93dc-fe0ef516e243
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865598021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2865598021
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.54094776
Short name T796
Test name
Test status
Simulation time 173159593 ps
CPU time 3.62 seconds
Started Feb 04 03:22:08 PM PST 24
Finished Feb 04 03:22:12 PM PST 24
Peak memory 209128 kb
Host smart-517eb50b-f4de-434c-9031-a1f96781608f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54094776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.54094776
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.788907596
Short name T407
Test name
Test status
Simulation time 272989193 ps
CPU time 3.29 seconds
Started Feb 04 03:22:12 PM PST 24
Finished Feb 04 03:22:16 PM PST 24
Peak memory 208280 kb
Host smart-3ee77869-e789-4ece-922e-3a787adfedb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788907596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.788907596
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.76296269
Short name T354
Test name
Test status
Simulation time 27007900 ps
CPU time 2.02 seconds
Started Feb 04 03:22:24 PM PST 24
Finished Feb 04 03:22:31 PM PST 24
Peak memory 215560 kb
Host smart-caec4f11-1f9e-4b71-8cb6-9deff4268a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76296269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.76296269
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2542927967
Short name T661
Test name
Test status
Simulation time 1584043478 ps
CPU time 20.62 seconds
Started Feb 04 03:22:07 PM PST 24
Finished Feb 04 03:22:29 PM PST 24
Peak memory 208068 kb
Host smart-22af95c4-1653-4470-a9de-bcd203f56538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542927967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2542927967
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2407128721
Short name T680
Test name
Test status
Simulation time 4416704957 ps
CPU time 15.52 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:33 PM PST 24
Peak memory 216480 kb
Host smart-bb4e24b3-b5e0-4e89-b63e-658cbccc833f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407128721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2407128721
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3284194035
Short name T843
Test name
Test status
Simulation time 1199209089 ps
CPU time 5.02 seconds
Started Feb 04 03:22:06 PM PST 24
Finished Feb 04 03:22:13 PM PST 24
Peak memory 207996 kb
Host smart-835fc875-a2ba-400d-94ce-5b451b34037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284194035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3284194035
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2087630491
Short name T928
Test name
Test status
Simulation time 52809627 ps
CPU time 1.76 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:20 PM PST 24
Peak memory 210204 kb
Host smart-6a10ae00-902e-4250-9916-460044828170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087630491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2087630491
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1412860474
Short name T874
Test name
Test status
Simulation time 21779263 ps
CPU time 0.87 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:22 PM PST 24
Peak memory 206488 kb
Host smart-c16e068e-27f6-4f9e-99ee-f7d266dcbeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412860474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1412860474
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3695699192
Short name T298
Test name
Test status
Simulation time 57634499 ps
CPU time 2.33 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:21 PM PST 24
Peak memory 214864 kb
Host smart-31313aaa-5899-4747-8fef-5f2628a4d6e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695699192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3695699192
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1867282752
Short name T996
Test name
Test status
Simulation time 524244962 ps
CPU time 15.26 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:36 PM PST 24
Peak memory 209236 kb
Host smart-6eeddb15-7277-48a2-bde3-00193befaa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867282752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1867282752
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3763133443
Short name T1075
Test name
Test status
Simulation time 1817503825 ps
CPU time 30.44 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:49 PM PST 24
Peak memory 214836 kb
Host smart-f557292f-a1c0-4fe7-8c12-3010c54bec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763133443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3763133443
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3259361011
Short name T322
Test name
Test status
Simulation time 133388737 ps
CPU time 6.84 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:28 PM PST 24
Peak memory 214712 kb
Host smart-1fb2c4e1-73d9-45bf-9e07-a96d005bdc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259361011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3259361011
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4111025925
Short name T911
Test name
Test status
Simulation time 97643407 ps
CPU time 2.99 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:21 PM PST 24
Peak memory 209056 kb
Host smart-2ee66e07-66e2-418f-833c-e1f25a6b14ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111025925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4111025925
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1747264355
Short name T853
Test name
Test status
Simulation time 362735067 ps
CPU time 3.98 seconds
Started Feb 04 03:22:27 PM PST 24
Finished Feb 04 03:22:33 PM PST 24
Peak memory 214676 kb
Host smart-afafaf0b-23b5-4541-b2a8-f0f372be2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747264355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1747264355
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1380771351
Short name T1079
Test name
Test status
Simulation time 933749078 ps
CPU time 8.71 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:27 PM PST 24
Peak memory 207140 kb
Host smart-049484fe-88cb-438e-966b-1616de908fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380771351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1380771351
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3374952490
Short name T570
Test name
Test status
Simulation time 536624122 ps
CPU time 2.81 seconds
Started Feb 04 03:22:26 PM PST 24
Finished Feb 04 03:22:32 PM PST 24
Peak memory 207200 kb
Host smart-68bfafec-a0ec-4fb7-a10b-1e5dc0621ca1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374952490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3374952490
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2392465421
Short name T764
Test name
Test status
Simulation time 115143976 ps
CPU time 4.15 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:23 PM PST 24
Peak memory 208980 kb
Host smart-7ea95285-8b18-486a-a94a-8b597865e8d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392465421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2392465421
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3894043346
Short name T951
Test name
Test status
Simulation time 458628324 ps
CPU time 4.27 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:22 PM PST 24
Peak memory 208432 kb
Host smart-0ffe37d3-836f-43dd-ba2a-237d43f2cfd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894043346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3894043346
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2606797949
Short name T791
Test name
Test status
Simulation time 151081654 ps
CPU time 2.68 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:24 PM PST 24
Peak memory 214788 kb
Host smart-07b2a4fe-da4a-4ef2-88bf-66b1bac01e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606797949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2606797949
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1911895828
Short name T776
Test name
Test status
Simulation time 213923168 ps
CPU time 3.33 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:23 PM PST 24
Peak memory 208508 kb
Host smart-ed4c463f-e429-49a9-bea9-ceb724ee2c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911895828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1911895828
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4151035839
Short name T618
Test name
Test status
Simulation time 473891294 ps
CPU time 4.04 seconds
Started Feb 04 03:22:16 PM PST 24
Finished Feb 04 03:22:22 PM PST 24
Peak memory 222988 kb
Host smart-4744fd3e-9f91-4118-a022-941cf50637d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151035839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4151035839
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3635485
Short name T694
Test name
Test status
Simulation time 1528934262 ps
CPU time 11.02 seconds
Started Feb 04 03:22:26 PM PST 24
Finished Feb 04 03:22:40 PM PST 24
Peak memory 209380 kb
Host smart-9a7fb3e1-241a-4b11-84f8-90a4dafd36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3635485
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4190198483
Short name T931
Test name
Test status
Simulation time 452156048 ps
CPU time 11.03 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:32 PM PST 24
Peak memory 210964 kb
Host smart-9a6bc18e-3469-4164-b87c-7112bc76bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190198483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4190198483
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3887683684
Short name T739
Test name
Test status
Simulation time 53706948 ps
CPU time 0.98 seconds
Started Feb 04 03:22:22 PM PST 24
Finished Feb 04 03:22:29 PM PST 24
Peak memory 206644 kb
Host smart-d337d8f4-f9f5-4dd6-9e08-4364805fe024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887683684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3887683684
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1352991686
Short name T708
Test name
Test status
Simulation time 91062348 ps
CPU time 3.3 seconds
Started Feb 04 03:22:20 PM PST 24
Finished Feb 04 03:22:25 PM PST 24
Peak memory 207588 kb
Host smart-db38c8d9-0b42-4dbb-8071-1217fdb2328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352991686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1352991686
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1289397004
Short name T1031
Test name
Test status
Simulation time 241122300 ps
CPU time 5.18 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:26 PM PST 24
Peak memory 214824 kb
Host smart-3e5c9bea-39c9-42f2-9f35-a4a5b0f4a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289397004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1289397004
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1312691074
Short name T286
Test name
Test status
Simulation time 127303582 ps
CPU time 5.66 seconds
Started Feb 04 03:22:25 PM PST 24
Finished Feb 04 03:22:34 PM PST 24
Peak memory 214720 kb
Host smart-c158dd29-5a8d-4623-b735-e2de9a1feff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312691074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1312691074
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4255396385
Short name T50
Test name
Test status
Simulation time 854406894 ps
CPU time 3.5 seconds
Started Feb 04 03:22:28 PM PST 24
Finished Feb 04 03:22:33 PM PST 24
Peak memory 214952 kb
Host smart-f486a035-c6c6-40f9-bb52-e98ea388426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255396385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4255396385
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3649093870
Short name T261
Test name
Test status
Simulation time 388741813 ps
CPU time 9.53 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:30 PM PST 24
Peak memory 208128 kb
Host smart-c790cce7-140c-4147-85c8-3c0435c05ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649093870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3649093870
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2392407638
Short name T840
Test name
Test status
Simulation time 322986585 ps
CPU time 6.58 seconds
Started Feb 04 03:22:21 PM PST 24
Finished Feb 04 03:22:29 PM PST 24
Peak memory 207136 kb
Host smart-68429d65-727f-4595-9759-38183f6dbac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392407638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2392407638
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3692270910
Short name T248
Test name
Test status
Simulation time 9585599615 ps
CPU time 28.95 seconds
Started Feb 04 03:22:29 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 209104 kb
Host smart-dcfcbf65-da73-45b9-acb3-6ef6601f1825
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692270910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3692270910
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.19955159
Short name T579
Test name
Test status
Simulation time 34834384 ps
CPU time 2.29 seconds
Started Feb 04 03:22:25 PM PST 24
Finished Feb 04 03:22:31 PM PST 24
Peak memory 207172 kb
Host smart-c8a166ea-c866-4107-9d6a-2a0fba4a0ae2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.19955159
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1979836954
Short name T740
Test name
Test status
Simulation time 82154914 ps
CPU time 4 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:25 PM PST 24
Peak memory 209144 kb
Host smart-65e27080-780c-4f64-8208-d8084772c341
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979836954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1979836954
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4087896750
Short name T863
Test name
Test status
Simulation time 482756886 ps
CPU time 11.49 seconds
Started Feb 04 03:22:28 PM PST 24
Finished Feb 04 03:22:41 PM PST 24
Peak memory 209772 kb
Host smart-0bbea174-3f10-42ba-907a-881033c445b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087896750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4087896750
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3530008459
Short name T3
Test name
Test status
Simulation time 103186552 ps
CPU time 2.69 seconds
Started Feb 04 03:22:20 PM PST 24
Finished Feb 04 03:22:25 PM PST 24
Peak memory 207152 kb
Host smart-a2e37f92-064b-4502-b2b1-3c9d5ccd2cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530008459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3530008459
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.760676452
Short name T925
Test name
Test status
Simulation time 422362011 ps
CPU time 5.84 seconds
Started Feb 04 03:22:26 PM PST 24
Finished Feb 04 03:22:35 PM PST 24
Peak memory 223032 kb
Host smart-6f1189d4-1d78-4cf9-a507-0c73b9ec4556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760676452 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.760676452
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.90698087
Short name T145
Test name
Test status
Simulation time 332925871 ps
CPU time 8.91 seconds
Started Feb 04 03:22:27 PM PST 24
Finished Feb 04 03:22:38 PM PST 24
Peak memory 208376 kb
Host smart-9062ce0f-e044-4e02-92cc-0a691bf2e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90698087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.90698087
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2561393055
Short name T1006
Test name
Test status
Simulation time 97597187 ps
CPU time 2.6 seconds
Started Feb 04 03:22:19 PM PST 24
Finished Feb 04 03:22:23 PM PST 24
Peak memory 210600 kb
Host smart-8c7ce14e-c73d-49b6-93ca-8c425aec636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561393055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2561393055
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.6766933
Short name T822
Test name
Test status
Simulation time 51117891 ps
CPU time 0.8 seconds
Started Feb 04 03:22:51 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 206472 kb
Host smart-4637c11e-1395-4618-9b19-35f29c3de26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6766933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.6766933
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4268646712
Short name T282
Test name
Test status
Simulation time 538618226 ps
CPU time 7.4 seconds
Started Feb 04 03:22:34 PM PST 24
Finished Feb 04 03:22:45 PM PST 24
Peak memory 215808 kb
Host smart-a8573239-96e3-4f98-bcae-91d0d24728eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268646712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4268646712
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1569761516
Short name T866
Test name
Test status
Simulation time 274395504 ps
CPU time 5.98 seconds
Started Feb 04 03:22:44 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 209756 kb
Host smart-8504c21f-f3cd-4d0d-8ac9-6462d29b2854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569761516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1569761516
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2633979904
Short name T80
Test name
Test status
Simulation time 264355932 ps
CPU time 4.64 seconds
Started Feb 04 03:22:32 PM PST 24
Finished Feb 04 03:22:39 PM PST 24
Peak memory 210380 kb
Host smart-2bfaf9a6-2e7e-4214-a55b-3b963d4064c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633979904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2633979904
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.758438748
Short name T97
Test name
Test status
Simulation time 307668119 ps
CPU time 9.89 seconds
Started Feb 04 03:22:34 PM PST 24
Finished Feb 04 03:22:47 PM PST 24
Peak memory 211748 kb
Host smart-80959643-4e01-4675-9489-0e717cb3f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758438748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.758438748
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1168946158
Short name T744
Test name
Test status
Simulation time 303837047 ps
CPU time 3.72 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 206644 kb
Host smart-e9632e33-ecbd-4448-a357-55701266a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168946158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1168946158
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4264888689
Short name T1046
Test name
Test status
Simulation time 587000508 ps
CPU time 5.29 seconds
Started Feb 04 03:22:39 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 218736 kb
Host smart-abe47031-dd74-42ea-a310-18c3fe5fb628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264888689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4264888689
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3832699494
Short name T1078
Test name
Test status
Simulation time 43979283 ps
CPU time 2.53 seconds
Started Feb 04 03:22:43 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 207624 kb
Host smart-a5d0fc32-754d-41bd-a9b1-f6682107b27c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832699494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3832699494
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1690526455
Short name T914
Test name
Test status
Simulation time 308563347 ps
CPU time 8.85 seconds
Started Feb 04 03:22:25 PM PST 24
Finished Feb 04 03:22:38 PM PST 24
Peak memory 209064 kb
Host smart-9e6d7e0e-cc0f-4852-bf5e-297ed4294215
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690526455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1690526455
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.434375823
Short name T902
Test name
Test status
Simulation time 957922743 ps
CPU time 24.08 seconds
Started Feb 04 03:22:34 PM PST 24
Finished Feb 04 03:23:01 PM PST 24
Peak memory 208340 kb
Host smart-2bb6ed87-fbf1-4929-999b-d6e1123f4d17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434375823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.434375823
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2143009103
Short name T259
Test name
Test status
Simulation time 43698042 ps
CPU time 1.95 seconds
Started Feb 04 03:22:37 PM PST 24
Finished Feb 04 03:22:41 PM PST 24
Peak memory 208276 kb
Host smart-b3b674c0-661a-4448-b632-7fa4d888e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143009103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2143009103
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3533293919
Short name T743
Test name
Test status
Simulation time 33235608 ps
CPU time 2.29 seconds
Started Feb 04 03:22:17 PM PST 24
Finished Feb 04 03:22:21 PM PST 24
Peak memory 207076 kb
Host smart-aa1d28bc-5e16-4e1d-82b3-28b737db2d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533293919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3533293919
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2656050284
Short name T1066
Test name
Test status
Simulation time 588263418 ps
CPU time 16.49 seconds
Started Feb 04 03:22:52 PM PST 24
Finished Feb 04 03:23:11 PM PST 24
Peak memory 215652 kb
Host smart-042b088c-ac43-4971-947c-24e35634d01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656050284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2656050284
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2990408708
Short name T922
Test name
Test status
Simulation time 990216989 ps
CPU time 7.98 seconds
Started Feb 04 03:22:39 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 223112 kb
Host smart-6a39c872-2ab2-41ec-933a-5fbe3c2eddd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990408708 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2990408708
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2151422679
Short name T831
Test name
Test status
Simulation time 282842479 ps
CPU time 9.01 seconds
Started Feb 04 03:22:32 PM PST 24
Finished Feb 04 03:22:44 PM PST 24
Peak memory 208368 kb
Host smart-6e6e43d8-9605-48e8-b8a3-ea4ff18a3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151422679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2151422679
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3945815198
Short name T1045
Test name
Test status
Simulation time 2587883240 ps
CPU time 14.42 seconds
Started Feb 04 03:22:33 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 211536 kb
Host smart-75354692-ad42-492c-808c-331ccde7e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945815198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3945815198
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.379484060
Short name T81
Test name
Test status
Simulation time 20127626 ps
CPU time 0.72 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:22:48 PM PST 24
Peak memory 206364 kb
Host smart-2fd1ae04-fa68-4fbf-b4ee-ca617255bd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379484060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.379484060
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2404462783
Short name T285
Test name
Test status
Simulation time 39712186 ps
CPU time 2.65 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 215400 kb
Host smart-0ffe5817-2588-4ef8-847a-6294accbacf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404462783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2404462783
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.186406472
Short name T1014
Test name
Test status
Simulation time 140899974 ps
CPU time 3.01 seconds
Started Feb 04 03:22:41 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 221808 kb
Host smart-4a849dca-fd7b-455e-b58a-2657502c2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186406472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.186406472
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3013210080
Short name T301
Test name
Test status
Simulation time 134564987 ps
CPU time 3.11 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 218668 kb
Host smart-acf97f22-1788-4307-8877-8e60119f0411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013210080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3013210080
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2549336843
Short name T669
Test name
Test status
Simulation time 588311306 ps
CPU time 15.06 seconds
Started Feb 04 03:22:34 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 209256 kb
Host smart-3a128f69-25fe-4818-b24e-09b38348a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549336843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2549336843
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2755869201
Short name T1072
Test name
Test status
Simulation time 242866480 ps
CPU time 7.28 seconds
Started Feb 04 03:22:39 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 211076 kb
Host smart-c9bc30cb-26dc-43c5-94db-927cf142263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755869201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2755869201
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4071640814
Short name T1080
Test name
Test status
Simulation time 81311080 ps
CPU time 3.7 seconds
Started Feb 04 03:22:38 PM PST 24
Finished Feb 04 03:22:43 PM PST 24
Peak memory 209740 kb
Host smart-da6d9e2b-733f-4074-9aea-04747c453681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071640814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4071640814
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1574477048
Short name T953
Test name
Test status
Simulation time 134246519 ps
CPU time 4.74 seconds
Started Feb 04 03:22:34 PM PST 24
Finished Feb 04 03:22:42 PM PST 24
Peak memory 208104 kb
Host smart-9f400854-658f-48e7-88fd-e544f05b20e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574477048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1574477048
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3557351511
Short name T955
Test name
Test status
Simulation time 19269849591 ps
CPU time 92.5 seconds
Started Feb 04 03:22:33 PM PST 24
Finished Feb 04 03:24:08 PM PST 24
Peak memory 209508 kb
Host smart-6adaeffd-a033-47e5-8ff8-a9f3098fc28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557351511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3557351511
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1716260850
Short name T878
Test name
Test status
Simulation time 77735955 ps
CPU time 1.98 seconds
Started Feb 04 03:22:41 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 207008 kb
Host smart-ff83d142-9053-475c-950c-58fa22253081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716260850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1716260850
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3380145110
Short name T798
Test name
Test status
Simulation time 75143551 ps
CPU time 3.74 seconds
Started Feb 04 03:22:40 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 208788 kb
Host smart-8b23ebd8-3ec1-44b7-8ea7-9d4dd01c22af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380145110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3380145110
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1859291100
Short name T968
Test name
Test status
Simulation time 549269621 ps
CPU time 4.46 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 209104 kb
Host smart-89cd6680-0081-4305-895d-9ab94226cfb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859291100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1859291100
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4045807819
Short name T346
Test name
Test status
Simulation time 310429844 ps
CPU time 3.9 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 216592 kb
Host smart-205b4d41-79da-45b4-8195-45b5a787b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045807819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4045807819
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.908126117
Short name T649
Test name
Test status
Simulation time 798599620 ps
CPU time 8.17 seconds
Started Feb 04 03:22:39 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 209024 kb
Host smart-10cd1641-bd21-4466-8d37-c538b460cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908126117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.908126117
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3579332188
Short name T295
Test name
Test status
Simulation time 170367957 ps
CPU time 4.04 seconds
Started Feb 04 03:22:44 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 209752 kb
Host smart-a0bb99de-d1bc-42e3-aa51-997df12b4633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579332188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3579332188
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.702153322
Short name T1007
Test name
Test status
Simulation time 100015245 ps
CPU time 1.28 seconds
Started Feb 04 03:22:44 PM PST 24
Finished Feb 04 03:22:49 PM PST 24
Peak memory 210020 kb
Host smart-8e298825-d439-4d0b-b748-b5b306a2b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702153322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.702153322
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2380791079
Short name T1086
Test name
Test status
Simulation time 155167798 ps
CPU time 0.92 seconds
Started Feb 04 03:22:53 PM PST 24
Finished Feb 04 03:22:56 PM PST 24
Peak memory 206408 kb
Host smart-6034b6b7-e64c-40e7-874f-de5640c08327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380791079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2380791079
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3488644438
Short name T260
Test name
Test status
Simulation time 108109657 ps
CPU time 3.33 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 207828 kb
Host smart-9d0d9d2b-5dd4-4908-a4b1-dd045f6196e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488644438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3488644438
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.530490137
Short name T800
Test name
Test status
Simulation time 370917214 ps
CPU time 4.19 seconds
Started Feb 04 03:22:52 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 209868 kb
Host smart-f3d88ddd-da46-4965-8f8a-17d393c10f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530490137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.530490137
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1842255344
Short name T1063
Test name
Test status
Simulation time 913507882 ps
CPU time 9.64 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 222932 kb
Host smart-9b4f8c5a-9a49-49e2-bf7e-891c97d9f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842255344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1842255344
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.3564947660
Short name T598
Test name
Test status
Simulation time 192327477 ps
CPU time 5.12 seconds
Started Feb 04 03:22:43 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 210400 kb
Host smart-bda28281-44ed-48d7-8f6a-f510953ae615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564947660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3564947660
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2042079589
Short name T963
Test name
Test status
Simulation time 516710246 ps
CPU time 3.48 seconds
Started Feb 04 03:22:50 PM PST 24
Finished Feb 04 03:22:57 PM PST 24
Peak memory 208720 kb
Host smart-235086d7-5faf-4527-bde3-dfd233a46af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042079589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2042079589
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1531884907
Short name T712
Test name
Test status
Simulation time 68032089 ps
CPU time 3.36 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 208156 kb
Host smart-75a66376-80b8-432d-8e90-9f7b7eb2e1eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531884907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1531884907
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3624721768
Short name T686
Test name
Test status
Simulation time 182927337 ps
CPU time 3.41 seconds
Started Feb 04 03:22:54 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 209184 kb
Host smart-451ca8e0-5c77-41ce-b2e2-6364c9aaff6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624721768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3624721768
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.983514801
Short name T768
Test name
Test status
Simulation time 453678250 ps
CPU time 3.94 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 208968 kb
Host smart-bb055882-bba2-4a35-88fa-040a50e83f41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983514801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.983514801
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3968203962
Short name T134
Test name
Test status
Simulation time 260018402 ps
CPU time 2.53 seconds
Started Feb 04 03:22:44 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 209440 kb
Host smart-c17f7d2f-9a6a-4f2e-a1fe-8dde9e8bb33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968203962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3968203962
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3928742452
Short name T881
Test name
Test status
Simulation time 384193964 ps
CPU time 4.08 seconds
Started Feb 04 03:22:41 PM PST 24
Finished Feb 04 03:22:52 PM PST 24
Peak memory 207792 kb
Host smart-0419c502-7023-47b0-bbbb-b61594138680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928742452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3928742452
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1537076297
Short name T1093
Test name
Test status
Simulation time 135538648 ps
CPU time 5.59 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 220440 kb
Host smart-66959102-200a-45b7-9f1e-064136318447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537076297 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1537076297
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1755867006
Short name T106
Test name
Test status
Simulation time 911298636 ps
CPU time 23.03 seconds
Started Feb 04 03:22:40 PM PST 24
Finished Feb 04 03:23:11 PM PST 24
Peak memory 210296 kb
Host smart-167d9928-d909-447b-84a5-d2770573f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755867006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1755867006
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2285354287
Short name T697
Test name
Test status
Simulation time 146565728 ps
CPU time 2.16 seconds
Started Feb 04 03:22:43 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 210428 kb
Host smart-1bdf8d89-6bc9-43f4-92f7-4c0c23668e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285354287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2285354287
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.808345523
Short name T1028
Test name
Test status
Simulation time 10159869 ps
CPU time 0.75 seconds
Started Feb 04 03:22:51 PM PST 24
Finished Feb 04 03:22:55 PM PST 24
Peak memory 206440 kb
Host smart-100c306e-663d-404a-808a-6ef518068771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808345523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.808345523
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1504884974
Short name T386
Test name
Test status
Simulation time 39556648 ps
CPU time 2.79 seconds
Started Feb 04 03:22:43 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 215528 kb
Host smart-07377c27-6051-44c3-a672-bd8214667cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504884974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1504884974
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3191575502
Short name T228
Test name
Test status
Simulation time 344111595 ps
CPU time 5.33 seconds
Started Feb 04 03:22:51 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 218744 kb
Host smart-ebc06792-2876-43e0-90bb-732838a9dd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191575502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3191575502
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.59120456
Short name T1054
Test name
Test status
Simulation time 92114182 ps
CPU time 3.64 seconds
Started Feb 04 03:22:55 PM PST 24
Finished Feb 04 03:23:01 PM PST 24
Peak memory 214756 kb
Host smart-167747a5-6d95-41c1-a6e0-11da01a9adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59120456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.59120456
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3073694963
Short name T306
Test name
Test status
Simulation time 2163794073 ps
CPU time 49.69 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 214868 kb
Host smart-b3e0ab05-6c7f-4c46-a870-2807ff952095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073694963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3073694963
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3159790984
Short name T338
Test name
Test status
Simulation time 576318890 ps
CPU time 5.56 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 212144 kb
Host smart-b1375edc-569f-4232-b8ed-872a2bf61c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159790984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3159790984
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4191901027
Short name T660
Test name
Test status
Simulation time 353447042 ps
CPU time 4.26 seconds
Started Feb 04 03:22:47 PM PST 24
Finished Feb 04 03:22:55 PM PST 24
Peak memory 214872 kb
Host smart-c3d89dcb-d563-4307-bbd5-73a762e1d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191901027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4191901027
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1920921670
Short name T147
Test name
Test status
Simulation time 402803129 ps
CPU time 2.69 seconds
Started Feb 04 03:22:45 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 218924 kb
Host smart-0a57bc14-1385-4554-b51f-fea914ebde32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920921670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1920921670
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3135761586
Short name T907
Test name
Test status
Simulation time 274876092 ps
CPU time 2.85 seconds
Started Feb 04 03:22:42 PM PST 24
Finished Feb 04 03:22:50 PM PST 24
Peak memory 207048 kb
Host smart-3b75b0f1-d8ad-4503-a395-37730070eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135761586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3135761586
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1691436426
Short name T920
Test name
Test status
Simulation time 114598554 ps
CPU time 3.05 seconds
Started Feb 04 03:22:43 PM PST 24
Finished Feb 04 03:22:51 PM PST 24
Peak memory 209152 kb
Host smart-1f2bc878-af9d-460c-a008-68bb73aa6b1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691436426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1691436426
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1771348086
Short name T883
Test name
Test status
Simulation time 442923202 ps
CPU time 8.51 seconds
Started Feb 04 03:22:54 PM PST 24
Finished Feb 04 03:23:04 PM PST 24
Peak memory 208768 kb
Host smart-6a1aeeba-c756-4b6b-9576-fd2bc35a1509
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771348086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1771348086
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1077210369
Short name T846
Test name
Test status
Simulation time 134728777 ps
CPU time 2.33 seconds
Started Feb 04 03:22:56 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 207804 kb
Host smart-f58c0555-d4fc-4d69-9b95-5f266a39b547
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077210369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1077210369
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3483560513
Short name T1094
Test name
Test status
Simulation time 567754265 ps
CPU time 5.6 seconds
Started Feb 04 03:22:48 PM PST 24
Finished Feb 04 03:22:57 PM PST 24
Peak memory 216328 kb
Host smart-d28eb27b-8b04-4ca1-b265-e60a02c6c7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483560513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3483560513
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3457581429
Short name T665
Test name
Test status
Simulation time 91704660 ps
CPU time 4.07 seconds
Started Feb 04 03:22:46 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 208812 kb
Host smart-9a98a841-1874-42ab-bdfa-c5bf631dc4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457581429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3457581429
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3513372852
Short name T638
Test name
Test status
Simulation time 150545863 ps
CPU time 4.81 seconds
Started Feb 04 03:22:50 PM PST 24
Finished Feb 04 03:22:58 PM PST 24
Peak memory 223088 kb
Host smart-df2ac2b1-d12d-4336-9ac5-89ccdf4c7eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513372852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3513372852
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3550587347
Short name T811
Test name
Test status
Simulation time 94061115 ps
CPU time 4.45 seconds
Started Feb 04 03:22:48 PM PST 24
Finished Feb 04 03:22:56 PM PST 24
Peak memory 209576 kb
Host smart-cc9e6d54-ab0d-4cdf-9464-ac8dc8d295fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550587347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3550587347
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3018738003
Short name T646
Test name
Test status
Simulation time 160651903 ps
CPU time 3.65 seconds
Started Feb 04 03:22:51 PM PST 24
Finished Feb 04 03:22:57 PM PST 24
Peak memory 210812 kb
Host smart-735929a3-ec12-422c-8dd0-04db0d383e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018738003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3018738003
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1765165540
Short name T807
Test name
Test status
Simulation time 41916968 ps
CPU time 0.9 seconds
Started Feb 04 03:23:11 PM PST 24
Finished Feb 04 03:23:18 PM PST 24
Peak memory 206484 kb
Host smart-6388f29c-bf70-46f4-8473-76d563a6bee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765165540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1765165540
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.253783591
Short name T360
Test name
Test status
Simulation time 239200529 ps
CPU time 9.77 seconds
Started Feb 04 03:22:54 PM PST 24
Finished Feb 04 03:23:05 PM PST 24
Peak memory 215608 kb
Host smart-638cf34e-c9ad-4ad6-a046-03ab53b570e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253783591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.253783591
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1060746073
Short name T32
Test name
Test status
Simulation time 186640251 ps
CPU time 2.99 seconds
Started Feb 04 03:23:02 PM PST 24
Finished Feb 04 03:23:06 PM PST 24
Peak memory 208564 kb
Host smart-61085571-f304-4e71-810b-21defd16d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060746073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1060746073
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1687779114
Short name T48
Test name
Test status
Simulation time 25082866 ps
CPU time 1.84 seconds
Started Feb 04 03:22:53 PM PST 24
Finished Feb 04 03:22:57 PM PST 24
Peak memory 207708 kb
Host smart-e76314f3-be64-4f31-8cf4-c28c1ee1998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687779114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1687779114
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.308857250
Short name T912
Test name
Test status
Simulation time 177494883 ps
CPU time 5.93 seconds
Started Feb 04 03:23:03 PM PST 24
Finished Feb 04 03:23:09 PM PST 24
Peak memory 218860 kb
Host smart-179469d8-268d-4980-82be-2da712d50efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308857250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.308857250
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2341637012
Short name T53
Test name
Test status
Simulation time 281313235 ps
CPU time 3.72 seconds
Started Feb 04 03:23:12 PM PST 24
Finished Feb 04 03:23:21 PM PST 24
Peak memory 209632 kb
Host smart-16860bc1-6b3b-407f-a4aa-ec225797863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341637012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2341637012
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.577626265
Short name T273
Test name
Test status
Simulation time 111879747 ps
CPU time 5.56 seconds
Started Feb 04 03:23:10 PM PST 24
Finished Feb 04 03:23:22 PM PST 24
Peak memory 220892 kb
Host smart-b1cc85aa-cbf3-400f-bdad-5b32ed606886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577626265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.577626265
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1500064671
Short name T899
Test name
Test status
Simulation time 293634613 ps
CPU time 3.65 seconds
Started Feb 04 03:22:46 PM PST 24
Finished Feb 04 03:22:53 PM PST 24
Peak memory 207812 kb
Host smart-512eee60-7a71-44e1-97c2-3dd7a2878811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500064671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1500064671
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1938233271
Short name T890
Test name
Test status
Simulation time 953020973 ps
CPU time 17.77 seconds
Started Feb 04 03:22:57 PM PST 24
Finished Feb 04 03:23:16 PM PST 24
Peak memory 209064 kb
Host smart-31258f20-c7f9-474a-948e-440054cf8342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938233271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1938233271
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1958059590
Short name T826
Test name
Test status
Simulation time 40918711 ps
CPU time 1.99 seconds
Started Feb 04 03:22:50 PM PST 24
Finished Feb 04 03:22:55 PM PST 24
Peak memory 207000 kb
Host smart-60515f9f-00d7-49f1-9bb7-c99d2df07e5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958059590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1958059590
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.820015841
Short name T1016
Test name
Test status
Simulation time 388646855 ps
CPU time 3.11 seconds
Started Feb 04 03:22:55 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 208888 kb
Host smart-cebf8eed-76c1-4060-a812-b894fd6a3d86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820015841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.820015841
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2348926441
Short name T934
Test name
Test status
Simulation time 48079488 ps
CPU time 2.58 seconds
Started Feb 04 03:22:48 PM PST 24
Finished Feb 04 03:22:54 PM PST 24
Peak memory 207184 kb
Host smart-4dbfb1d0-9bed-4676-b99d-e6dd452c29e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348926441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2348926441
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1828399678
Short name T869
Test name
Test status
Simulation time 366086330 ps
CPU time 3.31 seconds
Started Feb 04 03:22:54 PM PST 24
Finished Feb 04 03:22:59 PM PST 24
Peak memory 209412 kb
Host smart-7bb1f309-873a-4459-a3e9-f3f012ebb3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828399678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1828399678
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.150665827
Short name T1076
Test name
Test status
Simulation time 139240989 ps
CPU time 3.98 seconds
Started Feb 04 03:22:55 PM PST 24
Finished Feb 04 03:23:00 PM PST 24
Peak memory 208740 kb
Host smart-5c9df5db-1127-4499-94c5-8be96d13ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150665827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.150665827
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.657098035
Short name T762
Test name
Test status
Simulation time 26902788079 ps
CPU time 182.37 seconds
Started Feb 04 03:23:09 PM PST 24
Finished Feb 04 03:26:12 PM PST 24
Peak memory 223096 kb
Host smart-79f6d1d8-832a-47d6-bb09-975b16cf99d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657098035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.657098035
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2017011304
Short name T582
Test name
Test status
Simulation time 180113989 ps
CPU time 3.8 seconds
Started Feb 04 03:23:12 PM PST 24
Finished Feb 04 03:23:21 PM PST 24
Peak memory 218096 kb
Host smart-1f88c74e-d9f9-42cb-9440-840be2e99b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017011304 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2017011304
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1668814532
Short name T328
Test name
Test status
Simulation time 96375779 ps
CPU time 3.27 seconds
Started Feb 04 03:23:10 PM PST 24
Finished Feb 04 03:23:20 PM PST 24
Peak memory 208532 kb
Host smart-64c14f1a-5d93-4a87-8680-16e89f18d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668814532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1668814532
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4264322034
Short name T1085
Test name
Test status
Simulation time 71225437 ps
CPU time 3.25 seconds
Started Feb 04 03:23:03 PM PST 24
Finished Feb 04 03:23:07 PM PST 24
Peak memory 210248 kb
Host smart-528d92dc-bc4d-4ee9-af12-eb00e85134f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264322034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4264322034
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1121893041
Short name T889
Test name
Test status
Simulation time 14440297 ps
CPU time 0.77 seconds
Started Feb 04 03:20:35 PM PST 24
Finished Feb 04 03:20:36 PM PST 24
Peak memory 206484 kb
Host smart-48bfe845-dbac-421b-914f-f4bb7d58837a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121893041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1121893041
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4046907432
Short name T662
Test name
Test status
Simulation time 171527357 ps
CPU time 2.53 seconds
Started Feb 04 03:20:30 PM PST 24
Finished Feb 04 03:20:34 PM PST 24
Peak memory 209068 kb
Host smart-28aa6d5a-abb6-4445-9a0b-9ca3c72e7002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046907432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4046907432
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3708632477
Short name T917
Test name
Test status
Simulation time 276004870 ps
CPU time 2.81 seconds
Started Feb 04 03:20:24 PM PST 24
Finished Feb 04 03:20:28 PM PST 24
Peak memory 208732 kb
Host smart-4c09a1d0-4732-43bd-a159-1d1891236a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708632477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3708632477
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2008675477
Short name T321
Test name
Test status
Simulation time 434672978 ps
CPU time 5.38 seconds
Started Feb 04 03:20:27 PM PST 24
Finished Feb 04 03:20:33 PM PST 24
Peak memory 222864 kb
Host smart-04bba8da-5543-4783-9101-23192bd180ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008675477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2008675477
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1014543388
Short name T933
Test name
Test status
Simulation time 490653989 ps
CPU time 3.66 seconds
Started Feb 04 03:20:15 PM PST 24
Finished Feb 04 03:20:19 PM PST 24
Peak memory 214836 kb
Host smart-80a19173-2615-41a5-aa41-c6b17de09394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014543388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1014543388
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2389751982
Short name T788
Test name
Test status
Simulation time 1367264139 ps
CPU time 7.72 seconds
Started Feb 04 03:20:21 PM PST 24
Finished Feb 04 03:20:31 PM PST 24
Peak memory 208456 kb
Host smart-3318cac5-c327-4d3a-bb48-e518e2f0351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389751982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2389751982
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4010558313
Short name T104
Test name
Test status
Simulation time 2721497809 ps
CPU time 25.1 seconds
Started Feb 04 03:20:32 PM PST 24
Finished Feb 04 03:20:58 PM PST 24
Peak memory 233668 kb
Host smart-a6ae519a-57e4-4d87-a3a3-8a803846d7f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010558313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4010558313
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3540301988
Short name T747
Test name
Test status
Simulation time 74974140 ps
CPU time 3.49 seconds
Started Feb 04 03:20:15 PM PST 24
Finished Feb 04 03:20:20 PM PST 24
Peak memory 207424 kb
Host smart-5a169afe-c8d4-4d5d-9e53-ed7ac6e35f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540301988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3540301988
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3648891757
Short name T730
Test name
Test status
Simulation time 221284291 ps
CPU time 3.32 seconds
Started Feb 04 03:20:18 PM PST 24
Finished Feb 04 03:20:24 PM PST 24
Peak memory 207212 kb
Host smart-e76b0b0c-ab0c-41ce-9981-4434f1656fef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648891757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3648891757
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.379965498
Short name T959
Test name
Test status
Simulation time 826153895 ps
CPU time 22.49 seconds
Started Feb 04 03:20:17 PM PST 24
Finished Feb 04 03:20:41 PM PST 24
Peak memory 208864 kb
Host smart-538a871d-8b72-492c-a929-c0064194982a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379965498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.379965498
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1754053449
Short name T949
Test name
Test status
Simulation time 153962381 ps
CPU time 3 seconds
Started Feb 04 03:20:28 PM PST 24
Finished Feb 04 03:20:32 PM PST 24
Peak memory 209424 kb
Host smart-bbf493e3-cba7-4f4c-8078-fcfd002cc629
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754053449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1754053449
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.163244201
Short name T709
Test name
Test status
Simulation time 2948477300 ps
CPU time 4.67 seconds
Started Feb 04 03:20:26 PM PST 24
Finished Feb 04 03:20:32 PM PST 24
Peak memory 209508 kb
Host smart-c783c6ad-4353-4ed6-ae73-1bae45d8bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163244201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.163244201
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3760555221
Short name T633
Test name
Test status
Simulation time 265272580 ps
CPU time 5.08 seconds
Started Feb 04 03:20:16 PM PST 24
Finished Feb 04 03:20:22 PM PST 24
Peak memory 208796 kb
Host smart-5cb83c4c-d4c9-41f8-bb4b-428b73538cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760555221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3760555221
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1454517887
Short name T586
Test name
Test status
Simulation time 265996919 ps
CPU time 3.3 seconds
Started Feb 04 03:20:32 PM PST 24
Finished Feb 04 03:20:36 PM PST 24
Peak memory 214872 kb
Host smart-dd6d16a5-0ad2-4c33-b086-2ed05de2d2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454517887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1454517887
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2411196861
Short name T936
Test name
Test status
Simulation time 142344808 ps
CPU time 3.83 seconds
Started Feb 04 03:20:30 PM PST 24
Finished Feb 04 03:20:35 PM PST 24
Peak memory 218796 kb
Host smart-a8f47a57-f2a3-44bb-b260-37eb712012ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411196861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2411196861
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1852687663
Short name T85
Test name
Test status
Simulation time 454899953 ps
CPU time 2.22 seconds
Started Feb 04 03:20:30 PM PST 24
Finished Feb 04 03:20:33 PM PST 24
Peak memory 210304 kb
Host smart-0683c9ac-adb8-4d15-a9e3-14acc41b49f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852687663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1852687663
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.339177050
Short name T402
Test name
Test status
Simulation time 330157991 ps
CPU time 3.99 seconds
Started Feb 04 03:23:03 PM PST 24
Finished Feb 04 03:23:08 PM PST 24
Peak memory 214848 kb
Host smart-af234b7a-d451-4efc-869f-871273f759fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339177050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.339177050
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.379920252
Short name T299
Test name
Test status
Simulation time 1054567522 ps
CPU time 24.79 seconds
Started Feb 04 03:23:00 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 209588 kb
Host smart-881fc124-e506-43cd-8e11-e900f5fd84dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379920252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.379920252
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2688959712
Short name T266
Test name
Test status
Simulation time 8854765509 ps
CPU time 91.47 seconds
Started Feb 04 03:23:23 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 214928 kb
Host smart-4ad393a2-f504-4793-aae7-4c2a0c92f68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688959712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2688959712
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.409200497
Short name T391
Test name
Test status
Simulation time 298861678 ps
CPU time 3.24 seconds
Started Feb 04 03:23:13 PM PST 24
Finished Feb 04 03:23:20 PM PST 24
Peak memory 218632 kb
Host smart-c2934605-6bf7-4b32-a237-05f7f5957d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409200497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.409200497
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3116707505
Short name T722
Test name
Test status
Simulation time 140055463 ps
CPU time 3 seconds
Started Feb 04 03:23:02 PM PST 24
Finished Feb 04 03:23:06 PM PST 24
Peak memory 209084 kb
Host smart-165d9870-084e-4177-a0f2-52ab4e21aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116707505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3116707505
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1565634619
Short name T292
Test name
Test status
Simulation time 123574866 ps
CPU time 3.23 seconds
Started Feb 04 03:23:01 PM PST 24
Finished Feb 04 03:23:05 PM PST 24
Peak memory 208752 kb
Host smart-cea8c218-44ce-4c9b-9c34-4f9afafdbde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565634619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1565634619
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2487574224
Short name T1041
Test name
Test status
Simulation time 3645596610 ps
CPU time 36.31 seconds
Started Feb 04 03:22:59 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 209260 kb
Host smart-b01fc4ef-8340-4789-806f-4715a9f4ad06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487574224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2487574224
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.944937747
Short name T977
Test name
Test status
Simulation time 366433375 ps
CPU time 3.3 seconds
Started Feb 04 03:23:10 PM PST 24
Finished Feb 04 03:23:20 PM PST 24
Peak memory 208292 kb
Host smart-f33b7022-b131-4712-89ce-cd53df48007b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944937747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.944937747
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1370963055
Short name T856
Test name
Test status
Simulation time 201081383 ps
CPU time 2.87 seconds
Started Feb 04 03:23:08 PM PST 24
Finished Feb 04 03:23:12 PM PST 24
Peak memory 207208 kb
Host smart-b0848be3-be0b-46e4-b311-0b7788c9dfe9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370963055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1370963055
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3593989593
Short name T723
Test name
Test status
Simulation time 504356302 ps
CPU time 12.11 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:36 PM PST 24
Peak memory 210080 kb
Host smart-82306fef-f1e4-4116-a782-5a2b449ec934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593989593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3593989593
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1479593758
Short name T1069
Test name
Test status
Simulation time 184687083 ps
CPU time 3.37 seconds
Started Feb 04 03:23:02 PM PST 24
Finished Feb 04 03:23:07 PM PST 24
Peak memory 207060 kb
Host smart-01001eca-803a-41eb-912e-01c336d1af2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479593758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1479593758
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.303888650
Short name T107
Test name
Test status
Simulation time 52038718 ps
CPU time 2.79 seconds
Started Feb 04 03:23:11 PM PST 24
Finished Feb 04 03:23:20 PM PST 24
Peak memory 218472 kb
Host smart-6a25e507-7b44-445c-8bc9-93cde37c1672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303888650 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.303888650
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3612737763
Short name T802
Test name
Test status
Simulation time 792346185 ps
CPU time 24.12 seconds
Started Feb 04 03:23:21 PM PST 24
Finished Feb 04 03:23:46 PM PST 24
Peak memory 212168 kb
Host smart-51bf7c7d-3e65-414c-95d9-96be18b4b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612737763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3612737763
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.267032673
Short name T1002
Test name
Test status
Simulation time 11674373 ps
CPU time 0.95 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:30 PM PST 24
Peak memory 206452 kb
Host smart-d80ead10-180a-4b31-afe0-fd247a5a4a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267032673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.267032673
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.257486836
Short name T652
Test name
Test status
Simulation time 379566337 ps
CPU time 4.19 seconds
Started Feb 04 03:23:27 PM PST 24
Finished Feb 04 03:23:38 PM PST 24
Peak memory 210884 kb
Host smart-51d5e373-aeae-4027-b3d8-483f6dbfec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257486836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.257486836
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.239385809
Short name T272
Test name
Test status
Simulation time 1609489315 ps
CPU time 7.26 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:31 PM PST 24
Peak memory 210556 kb
Host smart-201faed5-6aa0-4ea3-9a1c-26d3f43e40df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239385809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.239385809
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1164943490
Short name T26
Test name
Test status
Simulation time 51200167 ps
CPU time 3.35 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:23:21 PM PST 24
Peak memory 209712 kb
Host smart-e14ae583-2f0f-4768-9a21-7942795b268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164943490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1164943490
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.299823570
Short name T989
Test name
Test status
Simulation time 3116388726 ps
CPU time 12.81 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:23:31 PM PST 24
Peak memory 223168 kb
Host smart-e9a49dd1-5c05-4d59-b9a5-c734f06e39fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299823570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.299823570
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3901497873
Short name T291
Test name
Test status
Simulation time 650290876 ps
CPU time 8 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 210808 kb
Host smart-a1a8137c-f30c-40fd-a731-962da50fdaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901497873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3901497873
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1617266899
Short name T339
Test name
Test status
Simulation time 57469017 ps
CPU time 2.17 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 209056 kb
Host smart-1bdae7c2-8277-4a6d-9e2f-e7460bec38a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617266899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1617266899
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3509073792
Short name T192
Test name
Test status
Simulation time 1570558165 ps
CPU time 10.93 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:23:29 PM PST 24
Peak memory 208124 kb
Host smart-9e5db138-8461-4260-bc96-5fc4ce5f9442
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509073792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3509073792
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.571035387
Short name T873
Test name
Test status
Simulation time 249921695 ps
CPU time 4.64 seconds
Started Feb 04 03:23:15 PM PST 24
Finished Feb 04 03:23:22 PM PST 24
Peak memory 207136 kb
Host smart-6715773f-e524-4854-a18b-59eb9b106c43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571035387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.571035387
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4118167243
Short name T1061
Test name
Test status
Simulation time 70672843 ps
CPU time 3.48 seconds
Started Feb 04 03:23:14 PM PST 24
Finished Feb 04 03:23:21 PM PST 24
Peak memory 208956 kb
Host smart-ccfcaf78-683e-4ce6-81a5-ad6d8aeb8a3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118167243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4118167243
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1117707578
Short name T269
Test name
Test status
Simulation time 123792886 ps
CPU time 2.57 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:23:21 PM PST 24
Peak memory 218760 kb
Host smart-68f48b81-6d8d-445e-93c3-d6b79e3cc5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117707578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1117707578
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3135229793
Short name T765
Test name
Test status
Simulation time 169734712 ps
CPU time 2.29 seconds
Started Feb 04 03:23:20 PM PST 24
Finished Feb 04 03:23:24 PM PST 24
Peak memory 206952 kb
Host smart-e262f017-f860-4982-9885-6b43d9cfeb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135229793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3135229793
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.105884660
Short name T75
Test name
Test status
Simulation time 16167184076 ps
CPU time 93.61 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:24:59 PM PST 24
Peak memory 223036 kb
Host smart-388f0d4b-8e85-4603-89cb-bd7a1bfb82d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105884660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.105884660
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.513847013
Short name T674
Test name
Test status
Simulation time 168431034 ps
CPU time 5.9 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:29 PM PST 24
Peak memory 222976 kb
Host smart-c69aba72-d5ea-4066-923d-21a0b840dff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513847013 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.513847013
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.104882798
Short name T648
Test name
Test status
Simulation time 1255580008 ps
CPU time 12.61 seconds
Started Feb 04 03:23:14 PM PST 24
Finished Feb 04 03:23:30 PM PST 24
Peak memory 210228 kb
Host smart-36fdcc48-0df8-4c90-8675-a89d756857c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104882798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.104882798
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2994304856
Short name T994
Test name
Test status
Simulation time 610256235 ps
CPU time 2.65 seconds
Started Feb 04 03:23:15 PM PST 24
Finished Feb 04 03:23:20 PM PST 24
Peak memory 209872 kb
Host smart-63921b67-8a30-4401-aa55-c222703c3e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994304856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2994304856
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.232230735
Short name T585
Test name
Test status
Simulation time 13321537 ps
CPU time 0.75 seconds
Started Feb 04 03:23:21 PM PST 24
Finished Feb 04 03:23:23 PM PST 24
Peak memory 206500 kb
Host smart-dd5de9af-844e-49cf-9e05-2de2b19fc21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232230735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.232230735
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2036470705
Short name T1065
Test name
Test status
Simulation time 251314634 ps
CPU time 4.97 seconds
Started Feb 04 03:23:20 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 215944 kb
Host smart-d9c3f8e7-ecd3-453f-8be6-fb5d8f5faf55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036470705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2036470705
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4258341395
Short name T999
Test name
Test status
Simulation time 140848567 ps
CPU time 2.02 seconds
Started Feb 04 03:23:19 PM PST 24
Finished Feb 04 03:23:22 PM PST 24
Peak memory 210684 kb
Host smart-dface797-0811-40bc-ab02-81827e07ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258341395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4258341395
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1332496262
Short name T986
Test name
Test status
Simulation time 156211249 ps
CPU time 4.09 seconds
Started Feb 04 03:23:23 PM PST 24
Finished Feb 04 03:23:29 PM PST 24
Peak memory 222108 kb
Host smart-12c27371-b143-4a85-921c-7fc99eaf10a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332496262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1332496262
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1273990905
Short name T253
Test name
Test status
Simulation time 203455038 ps
CPU time 4.14 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:30 PM PST 24
Peak memory 220516 kb
Host smart-07de0ad4-0b63-4b44-aa31-b0228d92dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273990905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1273990905
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.829232797
Short name T861
Test name
Test status
Simulation time 141820471 ps
CPU time 5.9 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:23:40 PM PST 24
Peak memory 207776 kb
Host smart-073dc7c4-a33d-4ca0-8a28-a4a2c9133575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829232797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.829232797
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.450980823
Short name T906
Test name
Test status
Simulation time 200383253 ps
CPU time 5.66 seconds
Started Feb 04 03:23:14 PM PST 24
Finished Feb 04 03:23:23 PM PST 24
Peak memory 208184 kb
Host smart-78221966-0173-4731-9921-ae07256f108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450980823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.450980823
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2668111303
Short name T820
Test name
Test status
Simulation time 270472335 ps
CPU time 7.4 seconds
Started Feb 04 03:23:15 PM PST 24
Finished Feb 04 03:23:25 PM PST 24
Peak memory 209044 kb
Host smart-8276d5cb-da4f-4893-950f-fa64220169c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668111303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2668111303
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.40227303
Short name T625
Test name
Test status
Simulation time 47722321 ps
CPU time 2.67 seconds
Started Feb 04 03:23:23 PM PST 24
Finished Feb 04 03:23:28 PM PST 24
Peak memory 208292 kb
Host smart-8afa61a4-c53f-4007-a969-d0102c19b07d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40227303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.40227303
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1235285242
Short name T13
Test name
Test status
Simulation time 641219536 ps
CPU time 7.52 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:32 PM PST 24
Peak memory 208392 kb
Host smart-ae25a251-5e54-467c-9ef7-2e550c26a632
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235285242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1235285242
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2695890289
Short name T249
Test name
Test status
Simulation time 496899959 ps
CPU time 2.68 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:23:28 PM PST 24
Peak memory 209784 kb
Host smart-f67c2dd9-cbad-421e-bbf1-c723cffea75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695890289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2695890289
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1652357443
Short name T808
Test name
Test status
Simulation time 1368771678 ps
CPU time 6.4 seconds
Started Feb 04 03:23:16 PM PST 24
Finished Feb 04 03:23:24 PM PST 24
Peak memory 207092 kb
Host smart-1fe79002-6ca4-416a-b64f-d2178b027d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652357443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1652357443
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.698328411
Short name T658
Test name
Test status
Simulation time 173006699 ps
CPU time 4.4 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 219748 kb
Host smart-46b1fdb6-f3cd-4cda-bd94-1ccf0e2a2506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698328411 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.698328411
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3481792835
Short name T279
Test name
Test status
Simulation time 4438563660 ps
CPU time 22.54 seconds
Started Feb 04 03:23:28 PM PST 24
Finished Feb 04 03:23:57 PM PST 24
Peak memory 209624 kb
Host smart-d80787df-3ebf-4e24-99e8-9826dd022685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481792835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3481792835
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4249750379
Short name T1037
Test name
Test status
Simulation time 2035340774 ps
CPU time 9.57 seconds
Started Feb 04 03:23:26 PM PST 24
Finished Feb 04 03:23:42 PM PST 24
Peak memory 210696 kb
Host smart-a1304688-08cc-4220-86f2-018316f4c396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249750379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4249750379
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2719553902
Short name T83
Test name
Test status
Simulation time 17029651 ps
CPU time 0.83 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:29 PM PST 24
Peak memory 206444 kb
Host smart-57b39397-3ab5-4d0a-992b-98500bed19b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719553902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2719553902
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3473944195
Short name T33
Test name
Test status
Simulation time 214520213 ps
CPU time 5.89 seconds
Started Feb 04 03:23:23 PM PST 24
Finished Feb 04 03:23:30 PM PST 24
Peak memory 223220 kb
Host smart-c6abd41b-e5df-4e0f-8b18-9d57bb47e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473944195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3473944195
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3069650989
Short name T55
Test name
Test status
Simulation time 193204279 ps
CPU time 1.93 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 208328 kb
Host smart-38a49da0-bf86-4410-95e5-fb0a4bc8c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069650989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3069650989
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3793260275
Short name T667
Test name
Test status
Simulation time 599310098 ps
CPU time 5.32 seconds
Started Feb 04 03:23:26 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 214832 kb
Host smart-9edacab9-ccdb-442f-8c83-0e20835a14fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793260275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3793260275
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.824820898
Short name T990
Test name
Test status
Simulation time 196890334 ps
CPU time 3.56 seconds
Started Feb 04 03:23:27 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 211500 kb
Host smart-cf457757-664d-4c02-bf01-870a576a46f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824820898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.824820898
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.702481410
Short name T214
Test name
Test status
Simulation time 64297177 ps
CPU time 3.16 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:32 PM PST 24
Peak memory 210756 kb
Host smart-b0befd35-ae25-4a0f-bc3c-035574162d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702481410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.702481410
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.902045725
Short name T243
Test name
Test status
Simulation time 82364056 ps
CPU time 3.93 seconds
Started Feb 04 03:23:27 PM PST 24
Finished Feb 04 03:23:38 PM PST 24
Peak memory 207320 kb
Host smart-0facbeec-e176-42ff-bf01-adfd6e64edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902045725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.902045725
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3805485390
Short name T193
Test name
Test status
Simulation time 401436132 ps
CPU time 6.86 seconds
Started Feb 04 03:23:23 PM PST 24
Finished Feb 04 03:23:32 PM PST 24
Peak memory 208168 kb
Host smart-88e2053b-18b2-49a0-8b2b-7a08fba8810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805485390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3805485390
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4059727757
Short name T626
Test name
Test status
Simulation time 137918127 ps
CPU time 2.81 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:27 PM PST 24
Peak memory 209084 kb
Host smart-9a23b2cf-6985-4a6f-a3e3-80fa1b6f0031
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059727757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4059727757
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1508040808
Short name T787
Test name
Test status
Simulation time 191745095 ps
CPU time 5 seconds
Started Feb 04 03:23:27 PM PST 24
Finished Feb 04 03:23:38 PM PST 24
Peak memory 208232 kb
Host smart-673f0490-7bfd-410b-93c0-9d4ef1c4c9f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508040808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1508040808
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3156760795
Short name T616
Test name
Test status
Simulation time 55058627 ps
CPU time 2.33 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:23:26 PM PST 24
Peak memory 209400 kb
Host smart-a6b09757-efe7-444c-baf7-167790494dc1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156760795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3156760795
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3994490160
Short name T611
Test name
Test status
Simulation time 2310678310 ps
CPU time 5 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:23:31 PM PST 24
Peak memory 210196 kb
Host smart-f3cce3e8-07f2-49cf-87c0-a03870a21e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994490160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3994490160
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1099048052
Short name T1047
Test name
Test status
Simulation time 103215611 ps
CPU time 2.2 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:23:28 PM PST 24
Peak memory 208812 kb
Host smart-4b1fc63b-f4dd-4297-a55b-e10ec1fc13cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099048052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1099048052
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1873327751
Short name T832
Test name
Test status
Simulation time 18951754658 ps
CPU time 113.97 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:25:28 PM PST 24
Peak memory 223064 kb
Host smart-ddf48237-79e1-49e9-8a22-0a316bf39617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873327751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1873327751
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2868585170
Short name T1087
Test name
Test status
Simulation time 763462435 ps
CPU time 7.84 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:23:42 PM PST 24
Peak memory 220828 kb
Host smart-6bef6414-799f-41a9-9103-3c6360c61905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868585170 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2868585170
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3757789039
Short name T888
Test name
Test status
Simulation time 214039551 ps
CPU time 7.7 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:23:33 PM PST 24
Peak memory 218932 kb
Host smart-d23c0304-152e-42a0-868e-b884e9de8012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757789039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3757789039
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2074585887
Short name T880
Test name
Test status
Simulation time 260682543 ps
CPU time 2.13 seconds
Started Feb 04 03:23:24 PM PST 24
Finished Feb 04 03:23:28 PM PST 24
Peak memory 210364 kb
Host smart-b005c78a-eea7-488d-90a5-749c9a46e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074585887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2074585887
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1996067336
Short name T742
Test name
Test status
Simulation time 56792070 ps
CPU time 0.87 seconds
Started Feb 04 03:23:35 PM PST 24
Finished Feb 04 03:23:38 PM PST 24
Peak memory 206368 kb
Host smart-33503a8f-b7ac-41e2-a2bb-3aa7eeb9bd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996067336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1996067336
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1184997788
Short name T375
Test name
Test status
Simulation time 40673353 ps
CPU time 1.59 seconds
Started Feb 04 03:23:35 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 208708 kb
Host smart-3e89f2bf-cee8-4d9f-a7d3-617f5dad3010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184997788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1184997788
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2390124499
Short name T774
Test name
Test status
Simulation time 209011842 ps
CPU time 2.5 seconds
Started Feb 04 03:23:35 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 210196 kb
Host smart-22c5a292-f972-435b-bd01-abac1e00caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390124499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2390124499
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1793350371
Short name T997
Test name
Test status
Simulation time 85596451 ps
CPU time 3.13 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 214892 kb
Host smart-1aaacd5a-1e47-4341-9450-0c2d212f91b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793350371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1793350371
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_random.3194265940
Short name T43
Test name
Test status
Simulation time 83519307 ps
CPU time 3.18 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 218964 kb
Host smart-c1caf0b6-5097-4a47-9da7-720cfb31a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194265940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3194265940
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.124757120
Short name T845
Test name
Test status
Simulation time 3622370760 ps
CPU time 34.44 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:24:09 PM PST 24
Peak memory 207864 kb
Host smart-2ed0ee6b-08db-4e58-b3fe-b7c1650f1280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124757120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.124757120
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2552449781
Short name T115
Test name
Test status
Simulation time 6385154782 ps
CPU time 62.68 seconds
Started Feb 04 03:23:22 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 208620 kb
Host smart-3416ba23-5dda-4fb2-944d-d6594af79e13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552449781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2552449781
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.552701334
Short name T146
Test name
Test status
Simulation time 142666250 ps
CPU time 4.87 seconds
Started Feb 04 03:23:25 PM PST 24
Finished Feb 04 03:23:34 PM PST 24
Peak memory 209016 kb
Host smart-ad270f42-484a-4aa1-b9eb-2dc9fd5f036f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552701334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.552701334
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4163988384
Short name T797
Test name
Test status
Simulation time 31037209 ps
CPU time 2.5 seconds
Started Feb 04 03:23:29 PM PST 24
Finished Feb 04 03:23:37 PM PST 24
Peak memory 206520 kb
Host smart-f03993af-3a19-4f33-bd1c-259358327b6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163988384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4163988384
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3676153593
Short name T1040
Test name
Test status
Simulation time 109670558 ps
CPU time 3.33 seconds
Started Feb 04 03:23:37 PM PST 24
Finished Feb 04 03:23:44 PM PST 24
Peak memory 210068 kb
Host smart-54c53b2c-8587-4a98-81cb-5af77899938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676153593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3676153593
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.347215521
Short name T954
Test name
Test status
Simulation time 194631140 ps
CPU time 4.88 seconds
Started Feb 04 03:23:30 PM PST 24
Finished Feb 04 03:23:40 PM PST 24
Peak memory 207044 kb
Host smart-bad7104c-618b-4c05-b727-1e62bbf0860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347215521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.347215521
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.743870701
Short name T44
Test name
Test status
Simulation time 362763122 ps
CPU time 7.17 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:44 PM PST 24
Peak memory 217560 kb
Host smart-14fef436-73f4-4fa6-bbc3-3b4bd98ed0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743870701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.743870701
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3178962308
Short name T703
Test name
Test status
Simulation time 180694146 ps
CPU time 3.45 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:40 PM PST 24
Peak memory 223180 kb
Host smart-9354754c-be70-4bcd-b9d7-337549fa8d08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178962308 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3178962308
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3384548590
Short name T1005
Test name
Test status
Simulation time 196004354 ps
CPU time 7.43 seconds
Started Feb 04 03:23:38 PM PST 24
Finished Feb 04 03:23:49 PM PST 24
Peak memory 208436 kb
Host smart-aa4cb920-cdab-494b-a6bf-d671ea926ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384548590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3384548590
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2183010255
Short name T1049
Test name
Test status
Simulation time 53147193 ps
CPU time 2.68 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 210156 kb
Host smart-4e7b6baf-dae5-47b8-97eb-c69ddfa8e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183010255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2183010255
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.152313601
Short name T84
Test name
Test status
Simulation time 35833465 ps
CPU time 0.8 seconds
Started Feb 04 03:23:59 PM PST 24
Finished Feb 04 03:24:03 PM PST 24
Peak memory 206376 kb
Host smart-915fef10-bc65-42aa-ad00-c27148ab617d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152313601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.152313601
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3002158395
Short name T1056
Test name
Test status
Simulation time 186860447 ps
CPU time 10.15 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:46 PM PST 24
Peak memory 215496 kb
Host smart-c5e1a703-901e-42ef-9dc9-ed2a68632320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002158395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3002158395
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1400604784
Short name T297
Test name
Test status
Simulation time 830297034 ps
CPU time 22.67 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:59 PM PST 24
Peak memory 209776 kb
Host smart-8f19be6a-7380-45f6-8424-77e4d7324364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400604784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1400604784
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3966324342
Short name T653
Test name
Test status
Simulation time 131530968 ps
CPU time 5.26 seconds
Started Feb 04 03:23:45 PM PST 24
Finished Feb 04 03:23:51 PM PST 24
Peak memory 214808 kb
Host smart-7246d03f-5e6d-4d38-a0cf-af5e915116a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966324342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3966324342
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1361623446
Short name T636
Test name
Test status
Simulation time 667863627 ps
CPU time 7.37 seconds
Started Feb 04 03:23:48 PM PST 24
Finished Feb 04 03:23:58 PM PST 24
Peak memory 215472 kb
Host smart-5ceb6354-663e-4314-bf02-79f3fb123c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361623446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1361623446
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2695376855
Short name T355
Test name
Test status
Simulation time 8556135689 ps
CPU time 55.94 seconds
Started Feb 04 03:23:35 PM PST 24
Finished Feb 04 03:24:34 PM PST 24
Peak memory 217172 kb
Host smart-317ca94c-692d-4a43-8ab5-aba140c8f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695376855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2695376855
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.746004743
Short name T639
Test name
Test status
Simulation time 332889549 ps
CPU time 6.87 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:43 PM PST 24
Peak memory 207100 kb
Host smart-fed44dc5-81c0-466b-ad2f-db2a5fe72195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746004743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.746004743
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3569273326
Short name T666
Test name
Test status
Simulation time 61008113 ps
CPU time 3.06 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:39 PM PST 24
Peak memory 207304 kb
Host smart-586a9f41-75c8-4935-981c-61a0cffff69a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569273326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3569273326
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2534542340
Short name T316
Test name
Test status
Simulation time 522689830 ps
CPU time 5.44 seconds
Started Feb 04 03:23:34 PM PST 24
Finished Feb 04 03:23:42 PM PST 24
Peak memory 207200 kb
Host smart-926f0adb-a8bd-4270-89d3-c3605ebef786
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534542340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2534542340
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3392058687
Short name T599
Test name
Test status
Simulation time 228379221 ps
CPU time 6.64 seconds
Started Feb 04 03:23:32 PM PST 24
Finished Feb 04 03:23:42 PM PST 24
Peak memory 208172 kb
Host smart-0d608b83-9776-4e23-a8a0-d510ac5719e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392058687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3392058687
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1867034193
Short name T140
Test name
Test status
Simulation time 156446365 ps
CPU time 3.65 seconds
Started Feb 04 03:23:56 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 210304 kb
Host smart-0d67863d-793c-43c5-b4b3-905be00de45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867034193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1867034193
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1040908049
Short name T679
Test name
Test status
Simulation time 203259357 ps
CPU time 2.19 seconds
Started Feb 04 03:23:33 PM PST 24
Finished Feb 04 03:23:38 PM PST 24
Peak memory 206928 kb
Host smart-160e58b7-ed69-44f7-ae4a-b7fb7e24eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040908049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1040908049
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3029570261
Short name T734
Test name
Test status
Simulation time 7593914157 ps
CPU time 29.54 seconds
Started Feb 04 03:23:46 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 216616 kb
Host smart-c278e93c-a2ce-40f4-a672-ef35b3642028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029570261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3029570261
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3943328251
Short name T372
Test name
Test status
Simulation time 536837863 ps
CPU time 7.66 seconds
Started Feb 04 03:23:57 PM PST 24
Finished Feb 04 03:24:09 PM PST 24
Peak memory 223100 kb
Host smart-4f7f8fa4-d872-4f7f-a9fb-7533585c574e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943328251 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3943328251
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.908188220
Short name T930
Test name
Test status
Simulation time 589315767 ps
CPU time 6.95 seconds
Started Feb 04 03:23:53 PM PST 24
Finished Feb 04 03:24:07 PM PST 24
Peak memory 210352 kb
Host smart-1331363a-6496-4854-b095-ebb7b76a3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908188220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.908188220
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2719684671
Short name T886
Test name
Test status
Simulation time 609786812 ps
CPU time 6.61 seconds
Started Feb 04 03:23:48 PM PST 24
Finished Feb 04 03:23:58 PM PST 24
Peak memory 210948 kb
Host smart-932d2098-c53e-46f0-8efa-e8bdf42fa47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719684671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2719684671
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3037233891
Short name T565
Test name
Test status
Simulation time 17115899 ps
CPU time 0.71 seconds
Started Feb 04 03:23:51 PM PST 24
Finished Feb 04 03:23:53 PM PST 24
Peak memory 206368 kb
Host smart-2f09efcf-9fad-4973-a1b9-c77bcaa24d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037233891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3037233891
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1179558532
Short name T1008
Test name
Test status
Simulation time 213308308 ps
CPU time 3.02 seconds
Started Feb 04 03:23:46 PM PST 24
Finished Feb 04 03:23:51 PM PST 24
Peak memory 215172 kb
Host smart-8e36bd6f-ee8d-495c-ba46-e9bcd3206a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179558532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1179558532
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4232867870
Short name T803
Test name
Test status
Simulation time 44447734 ps
CPU time 1.71 seconds
Started Feb 04 03:23:50 PM PST 24
Finished Feb 04 03:23:54 PM PST 24
Peak memory 209748 kb
Host smart-56ca627f-740e-42ae-a9ba-62a1601b363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232867870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4232867870
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.982643264
Short name T352
Test name
Test status
Simulation time 4249020138 ps
CPU time 32.2 seconds
Started Feb 04 03:23:49 PM PST 24
Finished Feb 04 03:24:24 PM PST 24
Peak memory 220872 kb
Host smart-b9a4035c-b454-4b0e-8024-1645dc204246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982643264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.982643264
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3231863522
Short name T663
Test name
Test status
Simulation time 78882921 ps
CPU time 4.08 seconds
Started Feb 04 03:23:49 PM PST 24
Finished Feb 04 03:23:56 PM PST 24
Peak memory 222888 kb
Host smart-67b480a3-7c4a-46e1-ab83-314b297006fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231863522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3231863522
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2643949261
Short name T307
Test name
Test status
Simulation time 347570054 ps
CPU time 9.12 seconds
Started Feb 04 03:23:55 PM PST 24
Finished Feb 04 03:24:10 PM PST 24
Peak memory 214680 kb
Host smart-5f1c64bd-6424-4fdc-8bc5-61bed3dd8494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643949261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2643949261
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3088776147
Short name T1053
Test name
Test status
Simulation time 224789278 ps
CPU time 4.67 seconds
Started Feb 04 03:23:46 PM PST 24
Finished Feb 04 03:23:54 PM PST 24
Peak memory 207264 kb
Host smart-aedc47d7-c0c0-4cb5-8aaf-49ee6b7dd7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088776147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3088776147
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2536250499
Short name T139
Test name
Test status
Simulation time 535009751 ps
CPU time 5.73 seconds
Started Feb 04 03:23:51 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 208240 kb
Host smart-2ef3acd7-a655-4b63-b809-e5b7733ba732
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536250499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2536250499
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3080045496
Short name T756
Test name
Test status
Simulation time 445538761 ps
CPU time 5.6 seconds
Started Feb 04 03:23:57 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 208936 kb
Host smart-9e9eb6c0-6ca6-411d-b6eb-7ae288c3db5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080045496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3080045496
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2978219293
Short name T589
Test name
Test status
Simulation time 116166692 ps
CPU time 3.21 seconds
Started Feb 04 03:23:51 PM PST 24
Finished Feb 04 03:23:55 PM PST 24
Peak memory 206956 kb
Host smart-077b4316-788a-49b0-9f25-f913d4565f21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978219293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2978219293
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3876242531
Short name T396
Test name
Test status
Simulation time 240075612 ps
CPU time 1.54 seconds
Started Feb 04 03:23:45 PM PST 24
Finished Feb 04 03:23:49 PM PST 24
Peak memory 208008 kb
Host smart-c31cc00a-edb9-4776-ae37-4682cf343d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876242531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3876242531
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3275710787
Short name T404
Test name
Test status
Simulation time 116638290 ps
CPU time 2.64 seconds
Started Feb 04 03:23:49 PM PST 24
Finished Feb 04 03:23:54 PM PST 24
Peak memory 206876 kb
Host smart-62f10660-a30b-40e2-8785-c0037854c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275710787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3275710787
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2913580157
Short name T78
Test name
Test status
Simulation time 2137365214 ps
CPU time 19.89 seconds
Started Feb 04 03:23:59 PM PST 24
Finished Feb 04 03:24:22 PM PST 24
Peak memory 215360 kb
Host smart-6f030262-42a0-475d-bfa5-8e51e8766988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913580157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2913580157
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3943958806
Short name T763
Test name
Test status
Simulation time 90088134 ps
CPU time 3.27 seconds
Started Feb 04 03:23:53 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 223032 kb
Host smart-fd4657ae-35ec-49a7-8ded-d0e52d5ddbba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943958806 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3943958806
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1543335728
Short name T838
Test name
Test status
Simulation time 231403894 ps
CPU time 3.22 seconds
Started Feb 04 03:23:55 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 208496 kb
Host smart-cde93573-4107-4466-b280-c4391011e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543335728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1543335728
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2491814308
Short name T613
Test name
Test status
Simulation time 223143326 ps
CPU time 5.31 seconds
Started Feb 04 03:23:51 PM PST 24
Finished Feb 04 03:24:03 PM PST 24
Peak memory 210656 kb
Host smart-6f56daad-e256-4f0f-bfe2-645ceb08710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491814308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2491814308
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2257852553
Short name T731
Test name
Test status
Simulation time 17492317 ps
CPU time 1 seconds
Started Feb 04 03:23:52 PM PST 24
Finished Feb 04 03:24:01 PM PST 24
Peak memory 206644 kb
Host smart-8916effd-1dc4-4500-bd3f-dfdaadf1559b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257852553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2257852553
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3271147478
Short name T363
Test name
Test status
Simulation time 185745974 ps
CPU time 3.79 seconds
Started Feb 04 03:23:47 PM PST 24
Finished Feb 04 03:23:53 PM PST 24
Peak memory 215228 kb
Host smart-aa9f4a24-5634-4847-ac63-bfe2d4641cff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271147478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3271147478
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3110197644
Short name T979
Test name
Test status
Simulation time 537140685 ps
CPU time 3.54 seconds
Started Feb 04 03:23:51 PM PST 24
Finished Feb 04 03:23:56 PM PST 24
Peak memory 209240 kb
Host smart-34e1dcf6-34b6-4609-971e-07cd0308cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110197644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3110197644
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4006670437
Short name T68
Test name
Test status
Simulation time 82963358 ps
CPU time 2.36 seconds
Started Feb 04 03:23:58 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 208388 kb
Host smart-9e8b1c37-5515-416c-b025-9ad6beb797f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006670437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4006670437
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.376408230
Short name T90
Test name
Test status
Simulation time 465214943 ps
CPU time 5.07 seconds
Started Feb 04 03:23:56 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 214752 kb
Host smart-3b0db213-7a43-4419-b261-b93bb53c34da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376408230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.376408230
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1186147243
Short name T304
Test name
Test status
Simulation time 454551650 ps
CPU time 5.46 seconds
Started Feb 04 03:23:50 PM PST 24
Finished Feb 04 03:23:57 PM PST 24
Peak memory 222936 kb
Host smart-1da32320-63e1-443e-ab0a-d4b795c3b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186147243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1186147243
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4057371719
Short name T226
Test name
Test status
Simulation time 345110273 ps
CPU time 4.54 seconds
Started Feb 04 03:23:53 PM PST 24
Finished Feb 04 03:24:05 PM PST 24
Peak memory 216368 kb
Host smart-0d15645c-7cf6-4b72-87c4-ee1e63cd2991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057371719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4057371719
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.159513931
Short name T645
Test name
Test status
Simulation time 106987627 ps
CPU time 2.35 seconds
Started Feb 04 03:23:54 PM PST 24
Finished Feb 04 03:24:03 PM PST 24
Peak memory 214852 kb
Host smart-a0c1e9e6-219f-4124-8eda-a5084e10c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159513931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.159513931
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.689419093
Short name T828
Test name
Test status
Simulation time 55231353 ps
CPU time 2.56 seconds
Started Feb 04 03:23:58 PM PST 24
Finished Feb 04 03:24:03 PM PST 24
Peak memory 207180 kb
Host smart-30765ce6-22f4-490f-ae85-24e05606cd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689419093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.689419093
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1653400844
Short name T347
Test name
Test status
Simulation time 146427885 ps
CPU time 2.82 seconds
Started Feb 04 03:23:49 PM PST 24
Finished Feb 04 03:23:54 PM PST 24
Peak memory 209096 kb
Host smart-69837ac5-1d51-4a74-80e4-1c9af05163ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653400844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1653400844
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2508329833
Short name T946
Test name
Test status
Simulation time 1585881112 ps
CPU time 35.04 seconds
Started Feb 04 03:23:57 PM PST 24
Finished Feb 04 03:24:36 PM PST 24
Peak memory 208488 kb
Host smart-39d8289d-9306-4f1b-9d9d-7138f883936a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508329833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2508329833
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4065295528
Short name T406
Test name
Test status
Simulation time 67501459 ps
CPU time 2.53 seconds
Started Feb 04 03:23:47 PM PST 24
Finished Feb 04 03:23:52 PM PST 24
Peak memory 207176 kb
Host smart-2c185134-e4ae-4e0c-aca6-7f7522849dcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065295528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4065295528
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1510058025
Short name T677
Test name
Test status
Simulation time 128134766 ps
CPU time 2.06 seconds
Started Feb 04 03:23:59 PM PST 24
Finished Feb 04 03:24:05 PM PST 24
Peak memory 207176 kb
Host smart-342a7928-0088-4eab-b77f-c2b8408974e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510058025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1510058025
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.83187497
Short name T974
Test name
Test status
Simulation time 400118408 ps
CPU time 8.24 seconds
Started Feb 04 03:23:56 PM PST 24
Finished Feb 04 03:24:09 PM PST 24
Peak memory 208128 kb
Host smart-e94a38ea-af06-481e-9f02-3d65aef67090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83187497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.83187497
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.223137675
Short name T699
Test name
Test status
Simulation time 167960892 ps
CPU time 4.53 seconds
Started Feb 04 03:23:54 PM PST 24
Finished Feb 04 03:24:05 PM PST 24
Peak memory 223132 kb
Host smart-f289c4f7-898e-42dd-afac-50e26813ab83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223137675 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.223137675
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3201742270
Short name T284
Test name
Test status
Simulation time 246362185 ps
CPU time 3.66 seconds
Started Feb 04 03:23:53 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 207860 kb
Host smart-958ccb63-e2eb-4543-ad97-2fda4383780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201742270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3201742270
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.424909954
Short name T825
Test name
Test status
Simulation time 301528398 ps
CPU time 1.33 seconds
Started Feb 04 03:23:48 PM PST 24
Finished Feb 04 03:23:52 PM PST 24
Peak memory 209824 kb
Host smart-0b195744-980c-4bb0-89de-aa91ea696e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424909954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.424909954
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.170217153
Short name T687
Test name
Test status
Simulation time 55653807 ps
CPU time 0.78 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 206468 kb
Host smart-d008cf1c-04ab-411a-ab6c-fa4b6a628dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170217153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.170217153
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1354300242
Short name T1081
Test name
Test status
Simulation time 591749560 ps
CPU time 15.03 seconds
Started Feb 04 03:23:58 PM PST 24
Finished Feb 04 03:24:16 PM PST 24
Peak memory 214848 kb
Host smart-85ca7d33-affc-4fc5-a516-54739ed4c6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354300242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1354300242
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2915394859
Short name T719
Test name
Test status
Simulation time 958177316 ps
CPU time 23.25 seconds
Started Feb 04 03:24:10 PM PST 24
Finished Feb 04 03:24:34 PM PST 24
Peak memory 210368 kb
Host smart-b05d521d-32da-4a2a-8159-7f8c153c3d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915394859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2915394859
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2697208102
Short name T290
Test name
Test status
Simulation time 51448660 ps
CPU time 3.3 seconds
Started Feb 04 03:23:58 PM PST 24
Finished Feb 04 03:24:04 PM PST 24
Peak memory 214828 kb
Host smart-c97c86c3-7da4-494e-bedd-30aae14580d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697208102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2697208102
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3431026377
Short name T209
Test name
Test status
Simulation time 430458234 ps
CPU time 4.22 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:16 PM PST 24
Peak memory 212252 kb
Host smart-7ec083d1-e91b-41fd-a559-7da501584ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431026377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3431026377
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2210291442
Short name T227
Test name
Test status
Simulation time 66576812 ps
CPU time 3.77 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:08 PM PST 24
Peak memory 220884 kb
Host smart-ec0bf16d-6e96-43cf-aaff-1b8f5aecf278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210291442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2210291442
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1123882868
Short name T1018
Test name
Test status
Simulation time 74542575 ps
CPU time 3.36 seconds
Started Feb 04 03:24:10 PM PST 24
Finished Feb 04 03:24:14 PM PST 24
Peak memory 207676 kb
Host smart-8bac3ea8-53d8-4c70-abe3-84e2cf5a1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123882868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1123882868
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1736019007
Short name T725
Test name
Test status
Simulation time 298270074 ps
CPU time 3.55 seconds
Started Feb 04 03:23:59 PM PST 24
Finished Feb 04 03:24:05 PM PST 24
Peak memory 208864 kb
Host smart-a5899b7f-6f8c-4385-9b56-f48f93864b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736019007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1736019007
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4099220707
Short name T568
Test name
Test status
Simulation time 283344117 ps
CPU time 7.71 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:12 PM PST 24
Peak memory 208640 kb
Host smart-a81d361d-c69e-4980-8b1e-735ec85c57a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099220707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4099220707
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1593295844
Short name T773
Test name
Test status
Simulation time 51792192 ps
CPU time 2.76 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 208576 kb
Host smart-3e6d15ca-9a8c-4c74-8697-0f47954346a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593295844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1593295844
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3116198494
Short name T821
Test name
Test status
Simulation time 384846454 ps
CPU time 2.87 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 209868 kb
Host smart-858a4f06-f013-432e-b712-9487d5840c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116198494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3116198494
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3415628518
Short name T608
Test name
Test status
Simulation time 43950109 ps
CPU time 1.93 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 208844 kb
Host smart-a0b4559b-80d5-47f4-a3be-af3e7feeff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415628518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3415628518
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2928509756
Short name T377
Test name
Test status
Simulation time 726679512 ps
CPU time 8.04 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:11 PM PST 24
Peak memory 220720 kb
Host smart-27852dcc-e6e0-45e8-a430-49feb165f82e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928509756 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2928509756
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3544042074
Short name T18
Test name
Test status
Simulation time 358797755 ps
CPU time 6.43 seconds
Started Feb 04 03:24:07 PM PST 24
Finished Feb 04 03:24:14 PM PST 24
Peak memory 207928 kb
Host smart-0c41d92c-354d-4263-a993-cfc8ca1521de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544042074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3544042074
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3152408999
Short name T681
Test name
Test status
Simulation time 4993847531 ps
CPU time 15.47 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 223136 kb
Host smart-a30501d2-2663-4c80-be02-ea65850203f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152408999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3152408999
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1402175843
Short name T569
Test name
Test status
Simulation time 65052633 ps
CPU time 0.84 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:17 PM PST 24
Peak memory 206400 kb
Host smart-76e80a8b-1fda-400a-95f2-ad65486d6523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402175843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1402175843
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4276355849
Short name T39
Test name
Test status
Simulation time 43951435 ps
CPU time 2.75 seconds
Started Feb 04 03:24:06 PM PST 24
Finished Feb 04 03:24:11 PM PST 24
Peak memory 217028 kb
Host smart-5b4b703f-5e75-4fb7-aa78-f49d7eb1538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276355849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4276355849
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.497740300
Short name T336
Test name
Test status
Simulation time 376514909 ps
CPU time 2.04 seconds
Started Feb 04 03:24:02 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 207488 kb
Host smart-1b089a99-4d10-41ee-a2d2-defc71e4b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497740300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.497740300
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.868202280
Short name T82
Test name
Test status
Simulation time 1374233165 ps
CPU time 4.88 seconds
Started Feb 04 03:24:02 PM PST 24
Finished Feb 04 03:24:09 PM PST 24
Peak memory 209528 kb
Host smart-21e9efd0-8a60-465e-a909-63ffd9a6e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868202280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.868202280
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2117961220
Short name T864
Test name
Test status
Simulation time 108115703 ps
CPU time 5.32 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:08 PM PST 24
Peak memory 222872 kb
Host smart-e96e3271-cbc6-4556-9df2-941eb6f29038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117961220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2117961220
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2990989511
Short name T1001
Test name
Test status
Simulation time 227548915 ps
CPU time 5.32 seconds
Started Feb 04 03:24:04 PM PST 24
Finished Feb 04 03:24:11 PM PST 24
Peak memory 220532 kb
Host smart-07125502-7825-4d7d-aa8f-1500ed18c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990989511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2990989511
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1707398269
Short name T998
Test name
Test status
Simulation time 2527358957 ps
CPU time 4.31 seconds
Started Feb 04 03:24:03 PM PST 24
Finished Feb 04 03:24:10 PM PST 24
Peak memory 208292 kb
Host smart-74e40e7f-5c6f-4f1f-a69a-b1f266ed5fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707398269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1707398269
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2764616743
Short name T991
Test name
Test status
Simulation time 548585086 ps
CPU time 14.21 seconds
Started Feb 04 03:24:02 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 209244 kb
Host smart-6b14334c-8066-46d7-86c1-d4537e921999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764616743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2764616743
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3790612504
Short name T833
Test name
Test status
Simulation time 142765608 ps
CPU time 4.06 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:07 PM PST 24
Peak memory 207264 kb
Host smart-0c4c9d7e-06ac-4b99-a7bd-3227d8040113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790612504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3790612504
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2083408959
Short name T940
Test name
Test status
Simulation time 42445971 ps
CPU time 2.67 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 207184 kb
Host smart-0b056a62-a296-4a21-a71a-9df05f68f03b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083408959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2083408959
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1533970343
Short name T741
Test name
Test status
Simulation time 1129120728 ps
CPU time 9.16 seconds
Started Feb 04 03:24:01 PM PST 24
Finished Feb 04 03:24:12 PM PST 24
Peak memory 208252 kb
Host smart-7b4d897c-afbb-44f4-9fc1-e2454013e207
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533970343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1533970343
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2889766470
Short name T79
Test name
Test status
Simulation time 149727517 ps
CPU time 2.33 seconds
Started Feb 04 03:24:05 PM PST 24
Finished Feb 04 03:24:09 PM PST 24
Peak memory 207368 kb
Host smart-0c423497-34a8-4e32-9c8b-cd7f7cc7d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889766470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2889766470
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.33441930
Short name T376
Test name
Test status
Simulation time 181540854 ps
CPU time 4.74 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:08 PM PST 24
Peak memory 208296 kb
Host smart-1bc2e81c-6f0e-40ff-bd5e-fb7666a39e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33441930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.33441930
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3487996877
Short name T223
Test name
Test status
Simulation time 127019231 ps
CPU time 8.28 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:24 PM PST 24
Peak memory 223072 kb
Host smart-74f09323-bf2f-48a6-bb7b-1d70accdf674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487996877 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3487996877
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3907103232
Short name T910
Test name
Test status
Simulation time 207105448 ps
CPU time 3.56 seconds
Started Feb 04 03:24:00 PM PST 24
Finished Feb 04 03:24:06 PM PST 24
Peak memory 210096 kb
Host smart-9f101fa5-510b-4f23-9599-de32c25b9b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907103232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3907103232
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.162733592
Short name T842
Test name
Test status
Simulation time 81638635 ps
CPU time 1.99 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 209988 kb
Host smart-409bd45f-47e5-4ac9-a0c9-1a87ab5b41de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162733592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.162733592
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.165983361
Short name T892
Test name
Test status
Simulation time 10251832 ps
CPU time 0.86 seconds
Started Feb 04 03:20:39 PM PST 24
Finished Feb 04 03:20:43 PM PST 24
Peak memory 206420 kb
Host smart-efc7f527-b336-4c87-a837-055f65971ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165983361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.165983361
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1083012700
Short name T1048
Test name
Test status
Simulation time 432177232 ps
CPU time 8.31 seconds
Started Feb 04 03:20:33 PM PST 24
Finished Feb 04 03:20:43 PM PST 24
Peak memory 215080 kb
Host smart-ffbd6a42-0783-4a9e-9757-af4abb2ca42b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083012700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1083012700
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1520156044
Short name T1084
Test name
Test status
Simulation time 145120561 ps
CPU time 4.48 seconds
Started Feb 04 03:20:51 PM PST 24
Finished Feb 04 03:20:56 PM PST 24
Peak memory 221408 kb
Host smart-f4affa46-2042-4c0c-b221-d3dc1d7331f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520156044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1520156044
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1705320752
Short name T60
Test name
Test status
Simulation time 92022344 ps
CPU time 2.2 seconds
Started Feb 04 03:20:36 PM PST 24
Finished Feb 04 03:20:39 PM PST 24
Peak memory 208064 kb
Host smart-98f05919-6d30-4d4b-8fce-fbc2eec913d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705320752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1705320752
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3800036311
Short name T95
Test name
Test status
Simulation time 62032421 ps
CPU time 3.79 seconds
Started Feb 04 03:20:39 PM PST 24
Finished Feb 04 03:20:44 PM PST 24
Peak memory 221996 kb
Host smart-57972889-9326-4035-b269-d0a2a6aed2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800036311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3800036311
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3496208667
Short name T380
Test name
Test status
Simulation time 77087611 ps
CPU time 3.63 seconds
Started Feb 04 03:20:31 PM PST 24
Finished Feb 04 03:20:36 PM PST 24
Peak memory 216356 kb
Host smart-3f415cf5-1d1e-4409-b519-4f425996ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496208667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3496208667
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3291081386
Short name T640
Test name
Test status
Simulation time 249172145 ps
CPU time 8.55 seconds
Started Feb 04 03:20:33 PM PST 24
Finished Feb 04 03:20:44 PM PST 24
Peak memory 218860 kb
Host smart-8aedceaf-b30f-4108-863a-afbd11d39073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291081386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3291081386
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.296050325
Short name T10
Test name
Test status
Simulation time 586028198 ps
CPU time 12.72 seconds
Started Feb 04 03:20:40 PM PST 24
Finished Feb 04 03:20:55 PM PST 24
Peak memory 231924 kb
Host smart-e65a07ef-fd51-4241-8957-bf69a67e1e76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296050325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.296050325
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.549931592
Short name T971
Test name
Test status
Simulation time 57082641 ps
CPU time 3.23 seconds
Started Feb 04 03:20:32 PM PST 24
Finished Feb 04 03:20:36 PM PST 24
Peak memory 209188 kb
Host smart-60a2a3c3-52fb-474c-b6cd-d64ae1400608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549931592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.549931592
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2420925804
Short name T572
Test name
Test status
Simulation time 313200829 ps
CPU time 3.49 seconds
Started Feb 04 03:20:34 PM PST 24
Finished Feb 04 03:20:39 PM PST 24
Peak memory 207164 kb
Host smart-e3ccbb55-2361-4443-bd38-cbe0a6ee5f7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420925804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2420925804
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1653019268
Short name T823
Test name
Test status
Simulation time 203826267 ps
CPU time 3.35 seconds
Started Feb 04 03:20:33 PM PST 24
Finished Feb 04 03:20:38 PM PST 24
Peak memory 209244 kb
Host smart-f17defc0-5f31-4193-bcbd-eae2d3120a36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653019268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1653019268
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.583082544
Short name T329
Test name
Test status
Simulation time 524388641 ps
CPU time 2.51 seconds
Started Feb 04 03:20:32 PM PST 24
Finished Feb 04 03:20:35 PM PST 24
Peak memory 209260 kb
Host smart-53d38ad0-8cf6-4197-bceb-9ecc3203ff6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583082544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.583082544
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3730143099
Short name T871
Test name
Test status
Simulation time 236675686 ps
CPU time 3.17 seconds
Started Feb 04 03:20:41 PM PST 24
Finished Feb 04 03:20:47 PM PST 24
Peak memory 209572 kb
Host smart-16cc345e-75be-4404-8403-2e516d002406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730143099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3730143099
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.548413472
Short name T650
Test name
Test status
Simulation time 372464604 ps
CPU time 2.67 seconds
Started Feb 04 03:20:33 PM PST 24
Finished Feb 04 03:20:37 PM PST 24
Peak memory 208924 kb
Host smart-64977729-93f5-42d6-bbef-75907e107444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548413472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.548413472
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3034559868
Short name T72
Test name
Test status
Simulation time 5365740625 ps
CPU time 57.07 seconds
Started Feb 04 03:20:39 PM PST 24
Finished Feb 04 03:21:38 PM PST 24
Peak memory 215600 kb
Host smart-b4f82d9b-c1d5-47a1-9991-2bd07d04adf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034559868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3034559868
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2051729417
Short name T42
Test name
Test status
Simulation time 701083931 ps
CPU time 5.61 seconds
Started Feb 04 03:20:32 PM PST 24
Finished Feb 04 03:20:38 PM PST 24
Peak memory 208696 kb
Host smart-d2808008-d228-4316-bba4-a54718dc59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051729417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2051729417
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2098635220
Short name T988
Test name
Test status
Simulation time 107125438 ps
CPU time 2.68 seconds
Started Feb 04 03:20:52 PM PST 24
Finished Feb 04 03:20:55 PM PST 24
Peak memory 210556 kb
Host smart-6a89d128-63a5-4091-84cf-01e84927c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098635220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2098635220
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1277946909
Short name T794
Test name
Test status
Simulation time 58262794 ps
CPU time 0.81 seconds
Started Feb 04 03:24:25 PM PST 24
Finished Feb 04 03:24:28 PM PST 24
Peak memory 206472 kb
Host smart-df0d1376-6629-4c30-a109-2a3f3c337529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277946909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1277946909
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4039138685
Short name T281
Test name
Test status
Simulation time 62497985 ps
CPU time 3.95 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:20 PM PST 24
Peak memory 214872 kb
Host smart-3732a2e1-a9ce-466a-9443-d8ef6742362f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039138685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4039138685
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4200921681
Short name T46
Test name
Test status
Simulation time 341291884 ps
CPU time 4.97 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 207832 kb
Host smart-f04c2ec7-be4e-4eb5-b513-63795c58ffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200921681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4200921681
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2239301382
Short name T850
Test name
Test status
Simulation time 3144393338 ps
CPU time 91.12 seconds
Started Feb 04 03:24:12 PM PST 24
Finished Feb 04 03:25:45 PM PST 24
Peak memory 221432 kb
Host smart-3b61e498-f184-4425-be4f-b2fc2a3a25ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239301382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2239301382
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1932401933
Short name T1062
Test name
Test status
Simulation time 1185556357 ps
CPU time 31.75 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:48 PM PST 24
Peak memory 214772 kb
Host smart-5279093c-be8f-4253-978b-24b1beb5b8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932401933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1932401933
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1528200508
Short name T980
Test name
Test status
Simulation time 1055474501 ps
CPU time 4.57 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:20 PM PST 24
Peak memory 220748 kb
Host smart-b24a3102-c8e5-49cf-aa7d-b493078c7be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528200508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1528200508
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2790792036
Short name T258
Test name
Test status
Simulation time 127546893 ps
CPU time 2.37 seconds
Started Feb 04 03:24:12 PM PST 24
Finished Feb 04 03:24:16 PM PST 24
Peak memory 207400 kb
Host smart-fa1e0e39-e336-4721-83fc-54b192ccd3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790792036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2790792036
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3738161210
Short name T332
Test name
Test status
Simulation time 3514383171 ps
CPU time 23.18 seconds
Started Feb 04 03:24:06 PM PST 24
Finished Feb 04 03:24:31 PM PST 24
Peak memory 209364 kb
Host smart-2756d31c-883b-4e7a-b318-7876e5a10ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738161210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3738161210
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.145345989
Short name T309
Test name
Test status
Simulation time 3748030191 ps
CPU time 10.02 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 209284 kb
Host smart-0bfcd101-e271-4128-bee9-de1d1c59c055
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145345989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.145345989
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3687898872
Short name T702
Test name
Test status
Simulation time 255559869 ps
CPU time 6.68 seconds
Started Feb 04 03:24:05 PM PST 24
Finished Feb 04 03:24:13 PM PST 24
Peak memory 208912 kb
Host smart-f9e8a297-841c-441f-bcdb-6e33b3ef9900
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687898872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3687898872
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1401465032
Short name T944
Test name
Test status
Simulation time 51775619 ps
CPU time 3.04 seconds
Started Feb 04 03:24:15 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 208976 kb
Host smart-ca845536-2f9e-4290-843f-d5203e39ddb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401465032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1401465032
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3784973050
Short name T1057
Test name
Test status
Simulation time 91430319 ps
CPU time 4.17 seconds
Started Feb 04 03:24:25 PM PST 24
Finished Feb 04 03:24:32 PM PST 24
Peak memory 210220 kb
Host smart-774375ca-6e43-43c7-a900-aeac8bc08daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784973050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3784973050
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4162481550
Short name T841
Test name
Test status
Simulation time 208298428 ps
CPU time 2.94 seconds
Started Feb 04 03:24:06 PM PST 24
Finished Feb 04 03:24:10 PM PST 24
Peak memory 207152 kb
Host smart-a0a59664-05ae-44b3-9103-4318fca622d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162481550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4162481550
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.369465436
Short name T221
Test name
Test status
Simulation time 151584873 ps
CPU time 10.11 seconds
Started Feb 04 03:24:10 PM PST 24
Finished Feb 04 03:24:21 PM PST 24
Peak memory 223188 kb
Host smart-642ed2e8-253c-4a1f-b353-db7f8de025fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369465436 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.369465436
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.576264361
Short name T601
Test name
Test status
Simulation time 70815964 ps
CPU time 4.21 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:16 PM PST 24
Peak memory 207864 kb
Host smart-16b9a2d7-350e-4780-a22d-5690f0ca7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576264361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.576264361
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2354381599
Short name T736
Test name
Test status
Simulation time 1505874193 ps
CPU time 3.56 seconds
Started Feb 04 03:24:25 PM PST 24
Finished Feb 04 03:24:31 PM PST 24
Peak memory 210276 kb
Host smart-47f85ca6-c09a-4e1a-8be6-28906c3e60f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354381599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2354381599
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1214005201
Short name T727
Test name
Test status
Simulation time 17850142 ps
CPU time 0.79 seconds
Started Feb 04 03:24:10 PM PST 24
Finished Feb 04 03:24:12 PM PST 24
Peak memory 206452 kb
Host smart-f0c71575-6e71-4a63-9da3-d029608c58ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214005201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1214005201
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2325987005
Short name T388
Test name
Test status
Simulation time 182213350 ps
CPU time 9.74 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:25 PM PST 24
Peak memory 214768 kb
Host smart-f47d725a-680c-4845-bba7-3cff4e504953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325987005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2325987005
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1454471310
Short name T969
Test name
Test status
Simulation time 828750675 ps
CPU time 7.09 seconds
Started Feb 04 03:24:12 PM PST 24
Finished Feb 04 03:24:21 PM PST 24
Peak memory 219048 kb
Host smart-c1f5dd71-985c-4f49-a93a-2168fdc50b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454471310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1454471310
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1151119930
Short name T67
Test name
Test status
Simulation time 22986739 ps
CPU time 1.76 seconds
Started Feb 04 03:24:16 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 207952 kb
Host smart-47a8900c-888f-4bca-9065-8a05c647e44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151119930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1151119930
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3659537518
Short name T937
Test name
Test status
Simulation time 776473465 ps
CPU time 8.8 seconds
Started Feb 04 03:24:26 PM PST 24
Finished Feb 04 03:24:36 PM PST 24
Peak memory 209748 kb
Host smart-21b17d8d-215b-494b-8296-bf903f266905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659537518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3659537518
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1010582050
Short name T202
Test name
Test status
Simulation time 1688295785 ps
CPU time 13.49 seconds
Started Feb 04 03:24:26 PM PST 24
Finished Feb 04 03:24:41 PM PST 24
Peak memory 210492 kb
Host smart-ab73fabe-2bfc-4d6f-bfcd-eb35e3b89471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010582050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1010582050
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2020469120
Short name T870
Test name
Test status
Simulation time 109615471 ps
CPU time 5.48 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:21 PM PST 24
Peak memory 214868 kb
Host smart-6e208b6d-a598-4de5-bd8f-c54b6352f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020469120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2020469120
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2114005662
Short name T109
Test name
Test status
Simulation time 254597931 ps
CPU time 5.3 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 218664 kb
Host smart-d6863970-3522-44ef-a87e-d21a11b6a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114005662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2114005662
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2715354530
Short name T141
Test name
Test status
Simulation time 80598300 ps
CPU time 2.95 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:15 PM PST 24
Peak memory 207048 kb
Host smart-cfcb9316-154c-40b9-9717-1c3674098de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715354530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2715354530
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2952577523
Short name T340
Test name
Test status
Simulation time 24281230 ps
CPU time 2.05 seconds
Started Feb 04 03:24:26 PM PST 24
Finished Feb 04 03:24:30 PM PST 24
Peak memory 209040 kb
Host smart-8ad1a17e-02ab-498d-a384-a5faa0efb882
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952577523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2952577523
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.387330772
Short name T574
Test name
Test status
Simulation time 146254730 ps
CPU time 5.48 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:18 PM PST 24
Peak memory 208224 kb
Host smart-aceba922-fe33-4732-bf0d-87f7291f2263
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387330772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.387330772
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2335127128
Short name T622
Test name
Test status
Simulation time 1413309306 ps
CPU time 11.03 seconds
Started Feb 04 03:24:15 PM PST 24
Finished Feb 04 03:24:28 PM PST 24
Peak memory 208180 kb
Host smart-d585307e-619e-44db-bad9-25fb8dd40b9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335127128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2335127128
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1984895039
Short name T839
Test name
Test status
Simulation time 94463839 ps
CPU time 3.04 seconds
Started Feb 04 03:24:25 PM PST 24
Finished Feb 04 03:24:31 PM PST 24
Peak memory 210044 kb
Host smart-c7fb401d-c37d-4d9e-9ad4-89189df41a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984895039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1984895039
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3018545374
Short name T605
Test name
Test status
Simulation time 101032875 ps
CPU time 3.63 seconds
Started Feb 04 03:24:12 PM PST 24
Finished Feb 04 03:24:17 PM PST 24
Peak memory 207028 kb
Host smart-6c1b9fe0-32a2-4c45-a32e-bbe1af5a5b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018545374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3018545374
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1779759935
Short name T714
Test name
Test status
Simulation time 342445262 ps
CPU time 6.2 seconds
Started Feb 04 03:24:12 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 207160 kb
Host smart-ea66a294-8e91-4a0d-923a-064bab214a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779759935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1779759935
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.914351822
Short name T992
Test name
Test status
Simulation time 407081072 ps
CPU time 8.81 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:24 PM PST 24
Peak memory 222920 kb
Host smart-d620772b-7b40-4dc8-bd81-b05ef162b805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914351822 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.914351822
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.428845768
Short name T1089
Test name
Test status
Simulation time 237757013 ps
CPU time 5.89 seconds
Started Feb 04 03:24:25 PM PST 24
Finished Feb 04 03:24:33 PM PST 24
Peak memory 209996 kb
Host smart-c3861546-6bfd-46e5-8a9d-ea0bfbcbbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428845768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.428845768
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1551651266
Short name T834
Test name
Test status
Simulation time 39521004 ps
CPU time 2.04 seconds
Started Feb 04 03:24:16 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 209948 kb
Host smart-c9b8931b-0f97-41ea-bd45-80a2b66ecf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551651266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1551651266
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.290537764
Short name T98
Test name
Test status
Simulation time 9972002 ps
CPU time 0.74 seconds
Started Feb 04 03:24:17 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 206360 kb
Host smart-679e42c3-8065-4699-adc5-c93f288a5bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290537764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.290537764
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1959503011
Short name T978
Test name
Test status
Simulation time 57855169 ps
CPU time 2.93 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:23 PM PST 24
Peak memory 223304 kb
Host smart-6451b035-c914-422d-9c78-8b923eb55cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959503011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1959503011
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3436553151
Short name T606
Test name
Test status
Simulation time 22689546 ps
CPU time 1.62 seconds
Started Feb 04 03:24:20 PM PST 24
Finished Feb 04 03:24:25 PM PST 24
Peak memory 208396 kb
Host smart-a8d463e3-5695-45be-8f9f-3ffab49cc896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436553151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3436553151
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3874797588
Short name T1044
Test name
Test status
Simulation time 50957668 ps
CPU time 3.42 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:23 PM PST 24
Peak memory 209344 kb
Host smart-b3a077a5-0646-48c3-b481-b88b054be7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874797588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3874797588
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1997186696
Short name T1004
Test name
Test status
Simulation time 299735290 ps
CPU time 6.81 seconds
Started Feb 04 03:24:20 PM PST 24
Finished Feb 04 03:24:31 PM PST 24
Peak memory 222916 kb
Host smart-e4240d3d-8a12-43cd-985c-c40c45f497bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997186696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1997186696
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1919823075
Short name T659
Test name
Test status
Simulation time 162426360 ps
CPU time 4.18 seconds
Started Feb 04 03:24:18 PM PST 24
Finished Feb 04 03:24:23 PM PST 24
Peak memory 220476 kb
Host smart-2f60528b-8c21-40cf-8bc9-874f91fa2a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919823075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1919823075
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3915714971
Short name T929
Test name
Test status
Simulation time 997160687 ps
CPU time 6.24 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 208572 kb
Host smart-ac542db6-a008-4b7f-bebd-9267450f48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915714971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3915714971
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1227441845
Short name T689
Test name
Test status
Simulation time 963896670 ps
CPU time 8.12 seconds
Started Feb 04 03:24:13 PM PST 24
Finished Feb 04 03:24:22 PM PST 24
Peak memory 209004 kb
Host smart-29c0fa97-c845-42d7-a644-782eb05b592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227441845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1227441845
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1096373876
Short name T919
Test name
Test status
Simulation time 49339697 ps
CPU time 2.82 seconds
Started Feb 04 03:24:14 PM PST 24
Finished Feb 04 03:24:19 PM PST 24
Peak memory 207168 kb
Host smart-f3eff6f5-5d20-46cf-89fb-8abca855221a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096373876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1096373876
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1562628113
Short name T308
Test name
Test status
Simulation time 49150807 ps
CPU time 2.73 seconds
Started Feb 04 03:24:11 PM PST 24
Finished Feb 04 03:24:15 PM PST 24
Peak memory 209060 kb
Host smart-27a814cd-ee45-4c42-b316-fde0233f1249
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562628113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1562628113
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1774479115
Short name T595
Test name
Test status
Simulation time 228755087 ps
CPU time 6.31 seconds
Started Feb 04 03:24:13 PM PST 24
Finished Feb 04 03:24:21 PM PST 24
Peak memory 209032 kb
Host smart-4062b8ab-1463-438e-863b-4f0010dfbf92
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774479115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1774479115
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2799730483
Short name T403
Test name
Test status
Simulation time 106419414 ps
CPU time 3.59 seconds
Started Feb 04 03:24:23 PM PST 24
Finished Feb 04 03:24:30 PM PST 24
Peak memory 214836 kb
Host smart-586ca3d1-5bef-485e-ac30-2150a1b4bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799730483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2799730483
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1591702874
Short name T775
Test name
Test status
Simulation time 1689743272 ps
CPU time 5.45 seconds
Started Feb 04 03:24:10 PM PST 24
Finished Feb 04 03:24:16 PM PST 24
Peak memory 209084 kb
Host smart-13bb51b9-e887-472a-9841-f47fa9ef5b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591702874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1591702874
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2938431713
Short name T1029
Test name
Test status
Simulation time 1340248262 ps
CPU time 7.17 seconds
Started Feb 04 03:24:17 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 220312 kb
Host smart-9b43b8f1-ff37-4eac-9058-03143172dcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938431713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2938431713
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1697708211
Short name T393
Test name
Test status
Simulation time 4317738362 ps
CPU time 45.81 seconds
Started Feb 04 03:24:18 PM PST 24
Finished Feb 04 03:25:04 PM PST 24
Peak memory 210128 kb
Host smart-3599f392-5bda-46f4-8dce-258c079488f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697708211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1697708211
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2154384099
Short name T14
Test name
Test status
Simulation time 87895495 ps
CPU time 2.38 seconds
Started Feb 04 03:24:22 PM PST 24
Finished Feb 04 03:24:28 PM PST 24
Peak memory 210592 kb
Host smart-17d9b017-2af4-40ab-9f84-d2fcbb299aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154384099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2154384099
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3094789319
Short name T693
Test name
Test status
Simulation time 48428657 ps
CPU time 0.85 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:36 PM PST 24
Peak memory 206352 kb
Host smart-2359fd34-003d-4707-b030-810e77e24faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094789319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3094789319
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1221209188
Short name T395
Test name
Test status
Simulation time 1370911897 ps
CPU time 5.79 seconds
Started Feb 04 03:24:22 PM PST 24
Finished Feb 04 03:24:32 PM PST 24
Peak memory 214684 kb
Host smart-1e7da13e-c17e-4425-9442-7d244fe6d821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221209188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1221209188
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4144758303
Short name T20
Test name
Test status
Simulation time 102002591 ps
CPU time 2.4 seconds
Started Feb 04 03:24:28 PM PST 24
Finished Feb 04 03:24:37 PM PST 24
Peak memory 209200 kb
Host smart-3ea7c275-572f-4e3f-871c-5fcd1cc29cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144758303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4144758303
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1771114330
Short name T300
Test name
Test status
Simulation time 212826346 ps
CPU time 1.54 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:22 PM PST 24
Peak memory 209060 kb
Host smart-28e70207-8a93-4511-a72f-cf123527db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771114330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1771114330
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2266492218
Short name T786
Test name
Test status
Simulation time 150593063 ps
CPU time 4.63 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 209712 kb
Host smart-31a06a3f-165d-48ca-8489-27b209ee8448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266492218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2266492218
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2526766398
Short name T247
Test name
Test status
Simulation time 158924105 ps
CPU time 4.77 seconds
Started Feb 04 03:24:22 PM PST 24
Finished Feb 04 03:24:31 PM PST 24
Peak memory 214652 kb
Host smart-560f3b77-b99d-45ff-9d6f-7366f35c9a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526766398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2526766398
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1991634709
Short name T926
Test name
Test status
Simulation time 1031518718 ps
CPU time 6.33 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 210344 kb
Host smart-9c90aca1-a749-4a1a-a0a0-336fdbc8700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991634709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1991634709
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2296858943
Short name T755
Test name
Test status
Simulation time 401117485 ps
CPU time 4.06 seconds
Started Feb 04 03:24:23 PM PST 24
Finished Feb 04 03:24:30 PM PST 24
Peak memory 210272 kb
Host smart-0bf6c3c1-5dcc-4a64-b490-dfd63f9bfe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296858943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2296858943
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1330961276
Short name T901
Test name
Test status
Simulation time 4225931469 ps
CPU time 8.42 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:28 PM PST 24
Peak memory 208400 kb
Host smart-89da6930-95ea-4858-83d2-dd14151b833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330961276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1330961276
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.258222795
Short name T607
Test name
Test status
Simulation time 111437683 ps
CPU time 3.02 seconds
Started Feb 04 03:24:20 PM PST 24
Finished Feb 04 03:24:26 PM PST 24
Peak memory 207644 kb
Host smart-6e0c7bd8-c610-4c71-be39-61e962c72ff3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258222795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.258222795
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3535938472
Short name T757
Test name
Test status
Simulation time 268149817 ps
CPU time 7.72 seconds
Started Feb 04 03:24:21 PM PST 24
Finished Feb 04 03:24:33 PM PST 24
Peak memory 209140 kb
Host smart-18c54097-6d36-4111-9e05-2c1f581f32ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535938472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3535938472
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4145016838
Short name T935
Test name
Test status
Simulation time 7448190635 ps
CPU time 60.79 seconds
Started Feb 04 03:24:20 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 209000 kb
Host smart-bf055d42-c4af-4034-9381-6622033754fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145016838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4145016838
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2247228033
Short name T965
Test name
Test status
Simulation time 256072115 ps
CPU time 3.53 seconds
Started Feb 04 03:24:19 PM PST 24
Finished Feb 04 03:24:23 PM PST 24
Peak memory 208964 kb
Host smart-8e0ac434-0338-494f-a003-0f90ef4a70cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247228033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2247228033
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.441334332
Short name T945
Test name
Test status
Simulation time 1581576968 ps
CPU time 17.83 seconds
Started Feb 04 03:24:17 PM PST 24
Finished Feb 04 03:24:35 PM PST 24
Peak memory 208092 kb
Host smart-51dcb066-1533-4cad-8520-4ffcaadc3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441334332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.441334332
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3068547987
Short name T64
Test name
Test status
Simulation time 774094697 ps
CPU time 26.98 seconds
Started Feb 04 03:24:33 PM PST 24
Finished Feb 04 03:25:02 PM PST 24
Peak memory 222928 kb
Host smart-b632daf7-1e65-4dfb-9c7d-d4c769319868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068547987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3068547987
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.661011292
Short name T617
Test name
Test status
Simulation time 84201476 ps
CPU time 3.64 seconds
Started Feb 04 03:24:36 PM PST 24
Finished Feb 04 03:24:41 PM PST 24
Peak memory 218916 kb
Host smart-e2c109a9-1f74-4573-92f6-ee468dafdbda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661011292 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.661011292
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2800766667
Short name T1026
Test name
Test status
Simulation time 1224389219 ps
CPU time 31.21 seconds
Started Feb 04 03:24:26 PM PST 24
Finished Feb 04 03:25:03 PM PST 24
Peak memory 218732 kb
Host smart-0c19ae35-093d-4260-a413-6d7ce0cb42d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800766667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2800766667
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2168885677
Short name T654
Test name
Test status
Simulation time 60833287 ps
CPU time 2.92 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 210300 kb
Host smart-06a950ed-7f03-4778-9f9c-6cb4631d219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168885677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2168885677
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3347124445
Short name T751
Test name
Test status
Simulation time 110353074 ps
CPU time 1.19 seconds
Started Feb 04 03:24:42 PM PST 24
Finished Feb 04 03:24:46 PM PST 24
Peak memory 206636 kb
Host smart-fcaac21c-a6ea-4ae8-96d5-9df94a1f9fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347124445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3347124445
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.143274867
Short name T879
Test name
Test status
Simulation time 108751294 ps
CPU time 2.97 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 214876 kb
Host smart-d51b2553-628b-4c91-894a-49056cf43491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143274867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.143274867
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4035162838
Short name T65
Test name
Test status
Simulation time 2259272641 ps
CPU time 34.92 seconds
Started Feb 04 03:24:29 PM PST 24
Finished Feb 04 03:25:10 PM PST 24
Peak memory 219976 kb
Host smart-9fa195cb-ed61-4e4b-a1ea-cd8fb478f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035162838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4035162838
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.70192943
Short name T960
Test name
Test status
Simulation time 32022673 ps
CPU time 2.37 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:37 PM PST 24
Peak memory 220100 kb
Host smart-c664e327-7933-4703-a90f-0727d8ff32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70192943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.70192943
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.326672696
Short name T875
Test name
Test status
Simulation time 392728669 ps
CPU time 2.76 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 214716 kb
Host smart-db65b1f7-e81b-418b-9a57-432340a45218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326672696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.326672696
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3297856490
Short name T957
Test name
Test status
Simulation time 546882180 ps
CPU time 3.76 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:39 PM PST 24
Peak memory 208588 kb
Host smart-7de5cff3-b047-4143-8869-a9c6ea5529ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297856490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3297856490
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.567150869
Short name T1033
Test name
Test status
Simulation time 155444409 ps
CPU time 1.8 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:37 PM PST 24
Peak memory 207068 kb
Host smart-515a8461-49fe-42ec-ad40-d7bc3f345823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567150869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.567150869
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.134275956
Short name T359
Test name
Test status
Simulation time 66103661 ps
CPU time 3.35 seconds
Started Feb 04 03:24:34 PM PST 24
Finished Feb 04 03:24:39 PM PST 24
Peak memory 207252 kb
Host smart-6c35b219-1a20-4c17-883b-7ff610fd3917
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134275956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.134275956
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1362927376
Short name T908
Test name
Test status
Simulation time 233706266 ps
CPU time 4.07 seconds
Started Feb 04 03:24:40 PM PST 24
Finished Feb 04 03:24:46 PM PST 24
Peak memory 207020 kb
Host smart-93ba2149-7feb-464d-bbba-93c319bbdf62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362927376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1362927376
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3006210411
Short name T256
Test name
Test status
Simulation time 153849511 ps
CPU time 3.57 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:39 PM PST 24
Peak memory 218736 kb
Host smart-988906c1-6086-4f93-be8f-1b2ca5c065c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006210411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3006210411
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.700006283
Short name T619
Test name
Test status
Simulation time 59885960 ps
CPU time 2.91 seconds
Started Feb 04 03:24:33 PM PST 24
Finished Feb 04 03:24:38 PM PST 24
Peak memory 208760 kb
Host smart-6d5e6d0c-61ec-482b-92e5-d7fbc77265de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700006283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.700006283
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2479813047
Short name T342
Test name
Test status
Simulation time 5048507384 ps
CPU time 8.26 seconds
Started Feb 04 03:24:38 PM PST 24
Finished Feb 04 03:24:47 PM PST 24
Peak memory 208992 kb
Host smart-c5b11e23-1bf2-43cc-a209-eb098b3b1ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479813047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2479813047
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2898376230
Short name T183
Test name
Test status
Simulation time 194306266 ps
CPU time 2.66 seconds
Started Feb 04 03:24:34 PM PST 24
Finished Feb 04 03:24:38 PM PST 24
Peak memory 210500 kb
Host smart-d2159f61-7d4e-4323-81b3-7a00d9fab09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898376230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2898376230
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.338122847
Short name T717
Test name
Test status
Simulation time 51527679 ps
CPU time 0.85 seconds
Started Feb 04 03:24:55 PM PST 24
Finished Feb 04 03:24:59 PM PST 24
Peak memory 206508 kb
Host smart-9b9b4df0-cad4-4b52-8643-cee32c60005e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338122847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.338122847
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1690331494
Short name T1068
Test name
Test status
Simulation time 2639221255 ps
CPU time 13.55 seconds
Started Feb 04 03:24:46 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 214404 kb
Host smart-7a169f6a-9071-45b3-8903-4bbcc762b60d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690331494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1690331494
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1440621434
Short name T230
Test name
Test status
Simulation time 105855282 ps
CPU time 4.33 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 210080 kb
Host smart-8cd130bb-bef0-4fbb-999e-9a9b88efb8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440621434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1440621434
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.83117084
Short name T790
Test name
Test status
Simulation time 108390364 ps
CPU time 1.79 seconds
Started Feb 04 03:24:46 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 206980 kb
Host smart-c55b7397-3132-4812-b0c2-765c9093b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83117084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.83117084
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.645035089
Short name T92
Test name
Test status
Simulation time 289567774 ps
CPU time 8.84 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 214860 kb
Host smart-0d7cdebf-9af2-4e3d-8f51-ba9f2b62021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645035089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.645035089
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2547297739
Short name T224
Test name
Test status
Simulation time 234564406 ps
CPU time 3.27 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 214828 kb
Host smart-1fcab07f-2386-48f4-958d-3fa3a35071b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547297739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2547297739
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.727564953
Short name T621
Test name
Test status
Simulation time 2898668554 ps
CPU time 22.13 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 210856 kb
Host smart-809804dd-d58f-4c5d-8275-fa86b797d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727564953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.727564953
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.809421362
Short name T909
Test name
Test status
Simulation time 5139923826 ps
CPU time 57.65 seconds
Started Feb 04 03:24:32 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 209116 kb
Host smart-9e0a331a-787b-4a96-a6e9-9776469ef6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809421362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.809421362
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2182489503
Short name T615
Test name
Test status
Simulation time 100934719 ps
CPU time 2.95 seconds
Started Feb 04 03:24:35 PM PST 24
Finished Feb 04 03:24:39 PM PST 24
Peak memory 207192 kb
Host smart-f6ae5b1c-1e38-4dfa-a0d8-aaa2133f8db5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182489503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2182489503
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2597323454
Short name T745
Test name
Test status
Simulation time 33911282 ps
CPU time 2.42 seconds
Started Feb 04 03:24:40 PM PST 24
Finished Feb 04 03:24:45 PM PST 24
Peak memory 207140 kb
Host smart-985bb5b6-f4fb-449d-96dd-04da5581b2bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597323454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2597323454
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1634633649
Short name T1000
Test name
Test status
Simulation time 88060522 ps
CPU time 1.85 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 209320 kb
Host smart-9f2bcbb9-1d4c-4e08-81f2-1c7499f39b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634633649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1634633649
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2416827155
Short name T829
Test name
Test status
Simulation time 79221284 ps
CPU time 1.9 seconds
Started Feb 04 03:24:43 PM PST 24
Finished Feb 04 03:24:46 PM PST 24
Peak memory 207368 kb
Host smart-ee9e4adf-fcd0-4847-99a4-0cef80e46ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416827155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2416827155
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2969421293
Short name T1021
Test name
Test status
Simulation time 1756208787 ps
CPU time 34.11 seconds
Started Feb 04 03:24:49 PM PST 24
Finished Feb 04 03:25:27 PM PST 24
Peak memory 215556 kb
Host smart-82079a47-8c9a-4189-8a8f-c17ca5016e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969421293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2969421293
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.834141848
Short name T634
Test name
Test status
Simulation time 294593317 ps
CPU time 8.04 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:25:01 PM PST 24
Peak memory 223148 kb
Host smart-5ea9ab24-8fea-47f6-bd80-0945c5ff6c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834141848 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.834141848
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.814086726
Short name T312
Test name
Test status
Simulation time 529827467 ps
CPU time 4.94 seconds
Started Feb 04 03:24:46 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 209420 kb
Host smart-421531fd-77c3-4253-a67d-3c089f32589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814086726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.814086726
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2467412059
Short name T733
Test name
Test status
Simulation time 197462459 ps
CPU time 2.93 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 210652 kb
Host smart-ec934917-da8e-4ee7-a86c-b53d6f21c7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467412059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2467412059
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2967542673
Short name T887
Test name
Test status
Simulation time 13701627 ps
CPU time 0.91 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 206560 kb
Host smart-311c7b55-870a-490e-8962-cb9322122ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967542673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2967542673
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2480401491
Short name T314
Test name
Test status
Simulation time 54461779 ps
CPU time 4.02 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 215604 kb
Host smart-b99b1a4b-2b01-4758-94c2-61398947f14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480401491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2480401491
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1541292843
Short name T40
Test name
Test status
Simulation time 1367686547 ps
CPU time 6.5 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:10 PM PST 24
Peak memory 214756 kb
Host smart-68e90265-5159-4ea0-bd4a-8ef30abe7d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541292843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1541292843
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3455287091
Short name T1035
Test name
Test status
Simulation time 77435586 ps
CPU time 2.72 seconds
Started Feb 04 03:25:01 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 207604 kb
Host smart-49c65d12-266b-4bde-a2a2-5246f1088c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455287091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3455287091
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2346947080
Short name T748
Test name
Test status
Simulation time 370296992 ps
CPU time 3.14 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 209696 kb
Host smart-2bc64e35-a048-4ffe-8074-8565cf87f0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346947080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2346947080
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4040558111
Short name T222
Test name
Test status
Simulation time 85089985 ps
CPU time 2.9 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 216092 kb
Host smart-04ef4785-45d7-43bc-b1ae-6a3fec185f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040558111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4040558111
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2916747141
Short name T657
Test name
Test status
Simulation time 549546855 ps
CPU time 19.56 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:25:12 PM PST 24
Peak memory 209460 kb
Host smart-7065d738-548e-49e8-a967-f860e4e21caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916747141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2916747141
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1424774059
Short name T780
Test name
Test status
Simulation time 77177625 ps
CPU time 3.63 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 208440 kb
Host smart-74a4aad8-4297-48c9-ab99-58b277a81c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424774059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1424774059
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2042983580
Short name T637
Test name
Test status
Simulation time 778348601 ps
CPU time 6.48 seconds
Started Feb 04 03:24:54 PM PST 24
Finished Feb 04 03:25:04 PM PST 24
Peak memory 208280 kb
Host smart-ae60cddf-0623-4d38-b39e-c4278e1ca758
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042983580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2042983580
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.758885315
Short name T975
Test name
Test status
Simulation time 73408713 ps
CPU time 2.51 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 208044 kb
Host smart-1f92ec61-1444-4370-a5d5-5f07ac8cf9aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758885315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.758885315
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1436397675
Short name T614
Test name
Test status
Simulation time 532224628 ps
CPU time 15.53 seconds
Started Feb 04 03:24:45 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 214772 kb
Host smart-80d8de57-c002-4f74-80be-1222f43ef454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436397675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1436397675
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.52098445
Short name T591
Test name
Test status
Simulation time 214124469 ps
CPU time 1.89 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 207580 kb
Host smart-cf14e5e6-7e69-4519-abe5-1bc7cd3c1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52098445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.52098445
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1847369567
Short name T58
Test name
Test status
Simulation time 799594989 ps
CPU time 16.86 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 222868 kb
Host smart-d9205942-0a78-4676-bff6-0236ecb661be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847369567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1847369567
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.615502633
Short name T858
Test name
Test status
Simulation time 1066341205 ps
CPU time 12.78 seconds
Started Feb 04 03:24:49 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 223032 kb
Host smart-8d82020e-18f0-41b4-92d3-9ab7b6d901c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615502633 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.615502633
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3172348221
Short name T1023
Test name
Test status
Simulation time 124200970 ps
CPU time 5.27 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 209940 kb
Host smart-693f189f-c4cf-4037-bab8-b46ad1a043d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172348221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3172348221
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.788893689
Short name T37
Test name
Test status
Simulation time 620877184 ps
CPU time 7.17 seconds
Started Feb 04 03:24:43 PM PST 24
Finished Feb 04 03:24:52 PM PST 24
Peak memory 210600 kb
Host smart-45af8109-ccea-4763-8ff2-23b5932926e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788893689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.788893689
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.501124291
Short name T1073
Test name
Test status
Simulation time 19159045 ps
CPU time 0.71 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:53 PM PST 24
Peak memory 206468 kb
Host smart-a283e4cc-a28f-41c0-8517-133cf8c1421e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501124291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.501124291
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.671915642
Short name T110
Test name
Test status
Simulation time 153532286 ps
CPU time 3.16 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 215556 kb
Host smart-1a21b982-cc1d-49e2-84df-95612d199e49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671915642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.671915642
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3051743285
Short name T24
Test name
Test status
Simulation time 114444374 ps
CPU time 2.88 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 209772 kb
Host smart-18e40d8c-73f3-4934-8401-97fcd3fe24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051743285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3051743285
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1375705034
Short name T1038
Test name
Test status
Simulation time 287700505 ps
CPU time 9.27 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:14 PM PST 24
Peak memory 209272 kb
Host smart-8a6fb6bf-e4c7-4081-ac55-8f14736996be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375705034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1375705034
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1444609710
Short name T1042
Test name
Test status
Simulation time 27101278931 ps
CPU time 60.42 seconds
Started Feb 04 03:24:54 PM PST 24
Finished Feb 04 03:25:58 PM PST 24
Peak memory 214896 kb
Host smart-1bd2f268-c103-4a55-a69b-3c214e34f626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444609710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1444609710
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3015880609
Short name T779
Test name
Test status
Simulation time 40802620 ps
CPU time 2.96 seconds
Started Feb 04 03:24:55 PM PST 24
Finished Feb 04 03:25:01 PM PST 24
Peak memory 218204 kb
Host smart-0a4bb8fe-7055-4064-a82a-0b3f27ad073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015880609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3015880609
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.629455866
Short name T784
Test name
Test status
Simulation time 193338358 ps
CPU time 3.7 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 208788 kb
Host smart-1a6e6e09-935c-485f-b9da-6c05598ede78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629455866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.629455866
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.214258247
Short name T746
Test name
Test status
Simulation time 406716168 ps
CPU time 10.37 seconds
Started Feb 04 03:24:49 PM PST 24
Finished Feb 04 03:25:03 PM PST 24
Peak memory 208156 kb
Host smart-6fc0d0f0-c96a-4c09-ac3f-e16945a4277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214258247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.214258247
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1876538441
Short name T112
Test name
Test status
Simulation time 326558775 ps
CPU time 4.18 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 208892 kb
Host smart-7cf8c586-cf8c-417b-9270-e8100f509a58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876538441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1876538441
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4227284805
Short name T631
Test name
Test status
Simulation time 135582809 ps
CPU time 2.56 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 207004 kb
Host smart-a367c570-fec4-469b-b7bb-d6da7f3437e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227284805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4227284805
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2816799615
Short name T882
Test name
Test status
Simulation time 40319169 ps
CPU time 2.15 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:55 PM PST 24
Peak memory 207112 kb
Host smart-3e62c20d-d287-4626-8a0a-a7209f137817
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816799615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2816799615
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2585713671
Short name T905
Test name
Test status
Simulation time 278980746 ps
CPU time 2.16 seconds
Started Feb 04 03:25:01 PM PST 24
Finished Feb 04 03:25:04 PM PST 24
Peak memory 209756 kb
Host smart-8ebbb82c-7036-4aa6-95ba-804a4f53d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585713671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2585713671
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.808702576
Short name T670
Test name
Test status
Simulation time 53414438 ps
CPU time 2.75 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 208796 kb
Host smart-12f65cd2-7ce7-4bb4-ba26-5af150924aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808702576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.808702576
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4251931666
Short name T792
Test name
Test status
Simulation time 4828894126 ps
CPU time 45.1 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:25:38 PM PST 24
Peak memory 215500 kb
Host smart-c930b541-809a-433e-a221-0df5d4c537de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251931666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4251931666
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3625016173
Short name T392
Test name
Test status
Simulation time 103276435 ps
CPU time 3.47 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 223004 kb
Host smart-b4b1a3d4-7f70-40b7-a15b-e10d7772e403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625016173 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3625016173
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2558223719
Short name T993
Test name
Test status
Simulation time 1138542040 ps
CPU time 8.82 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:25:01 PM PST 24
Peak memory 207996 kb
Host smart-11e57a75-39a2-4c74-9f0d-dccc39fd59c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558223719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2558223719
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1873037872
Short name T624
Test name
Test status
Simulation time 27893567 ps
CPU time 1.89 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:10 PM PST 24
Peak memory 210028 kb
Host smart-17f50d84-f2a6-473d-9130-c661d229f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873037872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1873037872
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.535123553
Short name T924
Test name
Test status
Simulation time 15159735 ps
CPU time 0.83 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 206396 kb
Host smart-1149227c-5b13-4bf5-b738-5c393453dc52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535123553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.535123553
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3274194411
Short name T254
Test name
Test status
Simulation time 2966439290 ps
CPU time 79.69 seconds
Started Feb 04 03:25:00 PM PST 24
Finished Feb 04 03:26:21 PM PST 24
Peak memory 223140 kb
Host smart-edeeabc8-6254-4a9e-a6e2-c6a752443a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274194411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3274194411
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2010044922
Short name T737
Test name
Test status
Simulation time 246329890 ps
CPU time 8.46 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:25:02 PM PST 24
Peak memory 209712 kb
Host smart-1576bee5-0cb0-41c3-b71b-796d01733fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010044922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2010044922
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2047693165
Short name T265
Test name
Test status
Simulation time 433276923 ps
CPU time 5.19 seconds
Started Feb 04 03:24:50 PM PST 24
Finished Feb 04 03:24:59 PM PST 24
Peak memory 223028 kb
Host smart-89b40dae-073f-4811-a7f3-6d9f11781db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047693165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2047693165
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1923985524
Short name T827
Test name
Test status
Simulation time 585521615 ps
CPU time 2.96 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 219884 kb
Host smart-c08df217-e8c0-48dc-a1d1-e86e857fd389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923985524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1923985524
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3313310740
Short name T947
Test name
Test status
Simulation time 190536622 ps
CPU time 4.18 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:08 PM PST 24
Peak memory 207396 kb
Host smart-147f537c-aa03-4cb0-bbbf-88d230bedb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313310740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3313310740
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2070896396
Short name T630
Test name
Test status
Simulation time 347492087 ps
CPU time 2.99 seconds
Started Feb 04 03:24:48 PM PST 24
Finished Feb 04 03:24:56 PM PST 24
Peak memory 207084 kb
Host smart-12f8785d-7f64-424c-8c6b-67ac56368f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070896396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2070896396
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1583039842
Short name T759
Test name
Test status
Simulation time 38391694 ps
CPU time 2.85 seconds
Started Feb 04 03:24:56 PM PST 24
Finished Feb 04 03:25:01 PM PST 24
Peak memory 209144 kb
Host smart-ca0e4c12-70bf-4f64-854f-0957265a9b0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583039842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1583039842
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2741481839
Short name T900
Test name
Test status
Simulation time 365928464 ps
CPU time 3.79 seconds
Started Feb 04 03:24:51 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 209104 kb
Host smart-27827ef9-555e-4c73-b085-b060209fd043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741481839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2741481839
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.781496463
Short name T1071
Test name
Test status
Simulation time 520684396 ps
CPU time 4.39 seconds
Started Feb 04 03:24:46 PM PST 24
Finished Feb 04 03:24:57 PM PST 24
Peak memory 207168 kb
Host smart-bef00a8e-cef2-41ad-9d81-1bb5a15484e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781496463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.781496463
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1269285842
Short name T1070
Test name
Test status
Simulation time 52267976 ps
CPU time 2.08 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 215712 kb
Host smart-7c921d05-89cf-451f-9e06-e59f58531743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269285842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1269285842
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4016780779
Short name T577
Test name
Test status
Simulation time 22752689 ps
CPU time 1.74 seconds
Started Feb 04 03:24:47 PM PST 24
Finished Feb 04 03:24:54 PM PST 24
Peak memory 207408 kb
Host smart-05c85a12-13bf-4c90-9ad4-16162bd2ecea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016780779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4016780779
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2182972725
Short name T127
Test name
Test status
Simulation time 160368503 ps
CPU time 3.47 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 223036 kb
Host smart-86415094-5dd6-406a-b827-307238dcb9b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182972725 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2182972725
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2506529358
Short name T330
Test name
Test status
Simulation time 96145290 ps
CPU time 4.79 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 208544 kb
Host smart-6a0dd791-7d74-4411-b68c-8d5392bb497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506529358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2506529358
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2116364545
Short name T180
Test name
Test status
Simulation time 45262951 ps
CPU time 2.2 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:13 PM PST 24
Peak memory 210260 kb
Host smart-8a10caab-4909-444e-8f30-3c86f96c16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116364545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2116364545
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.389077517
Short name T891
Test name
Test status
Simulation time 29274366 ps
CPU time 0.97 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:12 PM PST 24
Peak memory 206548 kb
Host smart-9e3f0d99-61c7-4882-a67a-d3c5d979b2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389077517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.389077517
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4163712172
Short name T159
Test name
Test status
Simulation time 32389978 ps
CPU time 2.7 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:17 PM PST 24
Peak memory 214784 kb
Host smart-906c08db-28e0-4966-af8a-7e5c490b5436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163712172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4163712172
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4035434249
Short name T859
Test name
Test status
Simulation time 169783488 ps
CPU time 3.15 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:08 PM PST 24
Peak memory 218472 kb
Host smart-51bf2c3a-3380-4f2a-b342-5e47223c7bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035434249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4035434249
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.248522137
Short name T1025
Test name
Test status
Simulation time 102962229 ps
CPU time 3.59 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 217928 kb
Host smart-a07681fe-7550-4db0-8c82-1f11afe51005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248522137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.248522137
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3608338257
Short name T1012
Test name
Test status
Simulation time 137379707 ps
CPU time 4.31 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 222112 kb
Host smart-7e3bfd28-ca22-41c3-85a9-a2eaf6938b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608338257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3608338257
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.964332806
Short name T198
Test name
Test status
Simulation time 247362565 ps
CPU time 5.66 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:11 PM PST 24
Peak memory 222976 kb
Host smart-790afb84-f1e4-4f7d-9f9f-72b0e0a4b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964332806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.964332806
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2587202300
Short name T59
Test name
Test status
Simulation time 145238020 ps
CPU time 3.7 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 220552 kb
Host smart-fd1e4b8e-a289-4d5f-8210-7e385225e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587202300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2587202300
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2417755457
Short name T876
Test name
Test status
Simulation time 1334711842 ps
CPU time 4.36 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 210428 kb
Host smart-9bb01a31-3747-4a8b-9ebf-4b2427801731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417755457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2417755457
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1092445298
Short name T698
Test name
Test status
Simulation time 784166849 ps
CPU time 7.47 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:22 PM PST 24
Peak memory 207784 kb
Host smart-dedcf35e-17d3-40b1-89ad-5ad274863105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092445298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1092445298
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4275004240
Short name T277
Test name
Test status
Simulation time 156935202 ps
CPU time 3.55 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:17 PM PST 24
Peak memory 208768 kb
Host smart-c958af83-029e-4c91-b9bb-5636a4a41e3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275004240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4275004240
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.570128308
Short name T819
Test name
Test status
Simulation time 225484109 ps
CPU time 4.89 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 207220 kb
Host smart-d9cb44d6-bfe2-4535-8adb-9c209b492f14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570128308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.570128308
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2257510873
Short name T766
Test name
Test status
Simulation time 2861401753 ps
CPU time 51.83 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:26:03 PM PST 24
Peak memory 209372 kb
Host smart-363e635e-5984-4a9f-a01b-89539d5daebf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257510873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2257510873
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3217876530
Short name T211
Test name
Test status
Simulation time 57424390 ps
CPU time 1.97 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 207904 kb
Host smart-cea1b1ac-8997-42ea-a0c3-2ace590fde81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217876530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3217876530
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.288119207
Short name T778
Test name
Test status
Simulation time 54700612 ps
CPU time 2.07 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 207040 kb
Host smart-2d13a56c-d6bc-4497-958e-308469e7fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288119207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.288119207
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3607526844
Short name T781
Test name
Test status
Simulation time 27957654021 ps
CPU time 614.59 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:35:19 PM PST 24
Peak memory 232204 kb
Host smart-22d686ab-fb25-44e1-8412-0afd7c41b027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607526844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3607526844
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2288890582
Short name T212
Test name
Test status
Simulation time 94468922 ps
CPU time 6.48 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:11 PM PST 24
Peak memory 220340 kb
Host smart-226de4b6-8397-4269-bf20-fa97e6f59e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288890582 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2288890582
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1968393159
Short name T728
Test name
Test status
Simulation time 1891388620 ps
CPU time 6.51 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:10 PM PST 24
Peak memory 207772 kb
Host smart-d034d5eb-e610-4f88-8279-0844b8e70003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968393159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1968393159
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4278871873
Short name T942
Test name
Test status
Simulation time 7219485822 ps
CPU time 17.09 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 222908 kb
Host smart-14e521cd-2531-4410-b522-93a6a23eec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278871873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4278871873
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3662130478
Short name T612
Test name
Test status
Simulation time 26944383 ps
CPU time 0.8 seconds
Started Feb 04 03:20:57 PM PST 24
Finished Feb 04 03:20:59 PM PST 24
Peak memory 206412 kb
Host smart-64522987-6403-4187-868d-818c4f39a2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662130478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3662130478
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.709474539
Short name T381
Test name
Test status
Simulation time 126292822 ps
CPU time 4.04 seconds
Started Feb 04 03:20:51 PM PST 24
Finished Feb 04 03:20:56 PM PST 24
Peak memory 222960 kb
Host smart-d0b02661-2f95-4048-a4b1-4e82ae20810d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709474539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.709474539
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.50188228
Short name T785
Test name
Test status
Simulation time 485442616 ps
CPU time 5.37 seconds
Started Feb 04 03:20:53 PM PST 24
Finished Feb 04 03:20:59 PM PST 24
Peak memory 218924 kb
Host smart-a0ba2c70-9873-4cc3-a485-3d995621f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50188228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.50188228
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4147313437
Short name T76
Test name
Test status
Simulation time 855219027 ps
CPU time 9.22 seconds
Started Feb 04 03:21:00 PM PST 24
Finished Feb 04 03:21:11 PM PST 24
Peak memory 214800 kb
Host smart-6543c97b-8b85-4dbe-84f5-03c4ef91e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147313437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4147313437
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3811727581
Short name T801
Test name
Test status
Simulation time 80016434 ps
CPU time 3.94 seconds
Started Feb 04 03:20:58 PM PST 24
Finished Feb 04 03:21:03 PM PST 24
Peak memory 222884 kb
Host smart-af2b9682-6d52-4e37-9b5a-046f1ceef50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811727581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3811727581
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2068227791
Short name T350
Test name
Test status
Simulation time 833489015 ps
CPU time 16.53 seconds
Started Feb 04 03:20:52 PM PST 24
Finished Feb 04 03:21:09 PM PST 24
Peak memory 222928 kb
Host smart-0c0abeb4-d555-4991-b082-1eef04987d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068227791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2068227791
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.629385728
Short name T313
Test name
Test status
Simulation time 118146059 ps
CPU time 3.53 seconds
Started Feb 04 03:20:59 PM PST 24
Finished Feb 04 03:21:04 PM PST 24
Peak memory 210472 kb
Host smart-01d3b7a9-df11-4fb0-860b-2230d93aa855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629385728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.629385728
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2113113336
Short name T270
Test name
Test status
Simulation time 1351509463 ps
CPU time 13 seconds
Started Feb 04 03:20:38 PM PST 24
Finished Feb 04 03:20:52 PM PST 24
Peak memory 218912 kb
Host smart-fa12ba94-45d3-4b5f-bf7b-f4f538057181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113113336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2113113336
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2076853542
Short name T12
Test name
Test status
Simulation time 841233442 ps
CPU time 8.02 seconds
Started Feb 04 03:20:59 PM PST 24
Finished Feb 04 03:21:08 PM PST 24
Peak memory 229608 kb
Host smart-8a81f38b-a83b-4ec7-aea6-97d3906ddcd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076853542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2076853542
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.712456015
Short name T682
Test name
Test status
Simulation time 715920442 ps
CPU time 6.18 seconds
Started Feb 04 03:20:40 PM PST 24
Finished Feb 04 03:20:48 PM PST 24
Peak memory 208984 kb
Host smart-5ef61fdb-1b40-4e77-a082-1bc480c8ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712456015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.712456015
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4254965183
Short name T609
Test name
Test status
Simulation time 124925192 ps
CPU time 2.47 seconds
Started Feb 04 03:20:39 PM PST 24
Finished Feb 04 03:20:43 PM PST 24
Peak memory 207200 kb
Host smart-1b9cdecd-4f28-45c9-9d7e-38287fd4a781
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254965183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4254965183
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4004974771
Short name T208
Test name
Test status
Simulation time 118152332 ps
CPU time 3.11 seconds
Started Feb 04 03:20:41 PM PST 24
Finished Feb 04 03:20:46 PM PST 24
Peak memory 207076 kb
Host smart-f09157c9-8ac0-4623-bc52-dd2ac8ad6a0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004974771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4004974771
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.952961167
Short name T932
Test name
Test status
Simulation time 555787360 ps
CPU time 2.38 seconds
Started Feb 04 03:20:43 PM PST 24
Finished Feb 04 03:20:47 PM PST 24
Peak memory 207184 kb
Host smart-9c59cd80-e0fb-4063-94d0-87202bff639a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952961167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.952961167
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.761083204
Short name T809
Test name
Test status
Simulation time 36415858 ps
CPU time 2.03 seconds
Started Feb 04 03:20:52 PM PST 24
Finished Feb 04 03:20:55 PM PST 24
Peak memory 209360 kb
Host smart-0ac4a901-2fdb-4bef-adcb-92cdce4745f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761083204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.761083204
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3150306307
Short name T584
Test name
Test status
Simulation time 1283164861 ps
CPU time 15.41 seconds
Started Feb 04 03:20:42 PM PST 24
Finished Feb 04 03:20:59 PM PST 24
Peak memory 208964 kb
Host smart-a74ac548-b6a8-4d41-94d1-8a744364b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150306307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3150306307
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.681262767
Short name T1036
Test name
Test status
Simulation time 4244325093 ps
CPU time 35.28 seconds
Started Feb 04 03:20:53 PM PST 24
Finished Feb 04 03:21:29 PM PST 24
Peak memory 217008 kb
Host smart-308804dc-e22f-4c2b-9ddd-3a90e7813b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681262767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.681262767
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3137907194
Short name T716
Test name
Test status
Simulation time 651240277 ps
CPU time 14.18 seconds
Started Feb 04 03:20:53 PM PST 24
Finished Feb 04 03:21:08 PM PST 24
Peak memory 223068 kb
Host smart-46b9a85f-f3d1-48c8-89b1-94826ebcc7fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137907194 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3137907194
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.699782966
Short name T720
Test name
Test status
Simulation time 163186339 ps
CPU time 4.88 seconds
Started Feb 04 03:20:58 PM PST 24
Finished Feb 04 03:21:04 PM PST 24
Peak memory 207896 kb
Host smart-6b76b1a5-b29e-4b77-afdc-6beb66b98183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699782966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.699782966
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2432265845
Short name T701
Test name
Test status
Simulation time 379525696 ps
CPU time 2.74 seconds
Started Feb 04 03:21:00 PM PST 24
Finished Feb 04 03:21:03 PM PST 24
Peak memory 210516 kb
Host smart-d0e8d8b1-9bac-4c98-b72c-db0f37125d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432265845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2432265845
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3436696914
Short name T1051
Test name
Test status
Simulation time 23831038 ps
CPU time 0.75 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 206420 kb
Host smart-b7ffcff4-6d49-40a2-b262-5023511cfa0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436696914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3436696914
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2178001263
Short name T384
Test name
Test status
Simulation time 13989054772 ps
CPU time 62.41 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:26:17 PM PST 24
Peak memory 222908 kb
Host smart-06f5aaa6-316d-4639-92c4-7d13f321dd03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178001263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2178001263
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1377077711
Short name T948
Test name
Test status
Simulation time 176593052 ps
CPU time 1.89 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 209732 kb
Host smart-87919392-1b80-40d1-b30f-d95a66cf8f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377077711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1377077711
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3027651887
Short name T726
Test name
Test status
Simulation time 454517172 ps
CPU time 3.31 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:20 PM PST 24
Peak memory 214868 kb
Host smart-5db23bc2-558d-4db0-b00d-0757dfdf6291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027651887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3027651887
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3122038659
Short name T824
Test name
Test status
Simulation time 297378827 ps
CPU time 7.97 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:24 PM PST 24
Peak memory 209304 kb
Host smart-df9565e2-3aee-4574-9185-62676346ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122038659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3122038659
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.146442098
Short name T201
Test name
Test status
Simulation time 10165930207 ps
CPU time 73.86 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:26:29 PM PST 24
Peak memory 227552 kb
Host smart-0076b456-0db8-4dfe-9a4b-082ad60bd4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146442098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.146442098
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.784067893
Short name T232
Test name
Test status
Simulation time 317579643 ps
CPU time 3.4 seconds
Started Feb 04 03:25:01 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 209760 kb
Host smart-e9c9b860-3eda-4251-b97b-b449fb5501d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784067893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.784067893
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_sideload.659084474
Short name T713
Test name
Test status
Simulation time 71487905 ps
CPU time 2.36 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:13 PM PST 24
Peak memory 207036 kb
Host smart-e92888bb-347c-49ee-ac08-8d31a03827c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659084474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.659084474
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1247909241
Short name T970
Test name
Test status
Simulation time 177882814 ps
CPU time 2.8 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 207200 kb
Host smart-66323108-4981-4b9d-8bab-209f8e1df43b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247909241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1247909241
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3845423301
Short name T643
Test name
Test status
Simulation time 2281632812 ps
CPU time 20.71 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:24 PM PST 24
Peak memory 208620 kb
Host smart-669b2a71-65b3-42ea-9022-145d125e6679
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845423301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3845423301
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.925294935
Short name T865
Test name
Test status
Simulation time 481909045 ps
CPU time 2.99 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 207040 kb
Host smart-daea4235-347e-4b76-bede-80833b4b7527
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925294935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.925294935
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1330100246
Short name T278
Test name
Test status
Simulation time 116015964 ps
CPU time 2.05 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 209588 kb
Host smart-82dbf7e1-a216-4479-91fb-3f8612b34546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330100246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1330100246
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1121653585
Short name T777
Test name
Test status
Simulation time 631391395 ps
CPU time 4.54 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 206888 kb
Host smart-2f217bba-6bdb-474d-bb3c-0e2ce5e31467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121653585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1121653585
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3998924482
Short name T852
Test name
Test status
Simulation time 2099383273 ps
CPU time 18.63 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 217004 kb
Host smart-969ea906-bc90-42fa-b245-a4e63333bba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998924482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3998924482
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3171014649
Short name T592
Test name
Test status
Simulation time 91614938 ps
CPU time 3.01 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:20 PM PST 24
Peak memory 217868 kb
Host smart-67fc00b6-db3f-45d0-8b20-05124387fcfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171014649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3171014649
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2664281048
Short name T1
Test name
Test status
Simulation time 53268695 ps
CPU time 3.44 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:11 PM PST 24
Peak memory 210360 kb
Host smart-e3ab19d6-b768-44cc-a950-1024e9e1abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664281048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2664281048
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3138193152
Short name T754
Test name
Test status
Simulation time 41796613 ps
CPU time 1.75 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:10 PM PST 24
Peak memory 210164 kb
Host smart-104b8ca3-30e1-4211-adb8-1707c7deb47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138193152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3138193152
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4275149123
Short name T927
Test name
Test status
Simulation time 15316722 ps
CPU time 0.77 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:15 PM PST 24
Peak memory 206388 kb
Host smart-55d58c6c-abc1-4f04-81d2-1bc6d9c2a685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275149123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4275149123
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1961575987
Short name T364
Test name
Test status
Simulation time 227213246 ps
CPU time 4.17 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 215312 kb
Host smart-489f339e-01bb-40f3-9b2f-bf96d1e20296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961575987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1961575987
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.63577789
Short name T1052
Test name
Test status
Simulation time 234694829 ps
CPU time 3.13 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 208916 kb
Host smart-a8022367-6174-44db-b981-d3e79a12b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63577789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.63577789
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2850071980
Short name T89
Test name
Test status
Simulation time 1357939875 ps
CPU time 31.43 seconds
Started Feb 04 03:25:02 PM PST 24
Finished Feb 04 03:25:35 PM PST 24
Peak memory 215532 kb
Host smart-fa4e81f9-05e2-4154-8261-774ad5a4b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850071980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2850071980
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.185483624
Short name T349
Test name
Test status
Simulation time 486963073 ps
CPU time 6.7 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:20 PM PST 24
Peak memory 211348 kb
Host smart-7f77b8dd-8527-49d1-b082-5f75a689b687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185483624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.185483624
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2442822135
Short name T987
Test name
Test status
Simulation time 168521290 ps
CPU time 2.42 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 210120 kb
Host smart-f62e6ada-3d0d-4828-b56f-37eca1ff1142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442822135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2442822135
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1382292587
Short name T1083
Test name
Test status
Simulation time 4122795904 ps
CPU time 38.18 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:55 PM PST 24
Peak memory 208760 kb
Host smart-699fb837-5a73-4f4a-8ff4-ea70cf61d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382292587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1382292587
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1566063756
Short name T378
Test name
Test status
Simulation time 161327244 ps
CPU time 2.53 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:14 PM PST 24
Peak memory 207192 kb
Host smart-1b1d6d38-ea30-4167-ab3a-a13afde2808d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566063756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1566063756
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1544962909
Short name T844
Test name
Test status
Simulation time 256076024 ps
CPU time 3.72 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 208840 kb
Host smart-ed5bd303-1d1a-429e-87d3-2ea23327e590
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544962909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1544962909
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.912892370
Short name T610
Test name
Test status
Simulation time 134294070 ps
CPU time 4.05 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 209016 kb
Host smart-71a20fe8-0ad4-4040-93f7-4e762883f42d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912892370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.912892370
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1812849300
Short name T326
Test name
Test status
Simulation time 528377183 ps
CPU time 4.12 seconds
Started Feb 04 03:25:00 PM PST 24
Finished Feb 04 03:25:06 PM PST 24
Peak memory 209552 kb
Host smart-8de5ff02-4fde-459b-80da-c5244432675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812849300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1812849300
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1010798734
Short name T897
Test name
Test status
Simulation time 5275586435 ps
CPU time 12.43 seconds
Started Feb 04 03:25:03 PM PST 24
Finished Feb 04 03:25:17 PM PST 24
Peak memory 208560 kb
Host smart-4f33fb13-0f8d-4eaa-b177-837d70c327ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010798734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1010798734
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3349278528
Short name T51
Test name
Test status
Simulation time 602952169 ps
CPU time 21.96 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:29 PM PST 24
Peak memory 222960 kb
Host smart-fb45265c-f956-4d04-9432-fab0e5d84d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349278528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3349278528
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3531467655
Short name T644
Test name
Test status
Simulation time 166196401 ps
CPU time 8.74 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 222952 kb
Host smart-322c6ed2-fe83-4f6b-9aed-733ef4bdb6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531467655 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3531467655
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.865036500
Short name T571
Test name
Test status
Simulation time 3694854332 ps
CPU time 59.11 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:26:15 PM PST 24
Peak memory 208984 kb
Host smart-010185a5-4a65-46a0-b4a8-23ccb2d0a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865036500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.865036500
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.713107564
Short name T113
Test name
Test status
Simulation time 54666447 ps
CPU time 2.86 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:18 PM PST 24
Peak memory 210008 kb
Host smart-fabfb781-6717-4c5d-a883-c280c36507dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713107564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.713107564
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.642189193
Short name T1074
Test name
Test status
Simulation time 9365678 ps
CPU time 0.74 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 206472 kb
Host smart-7beaa1da-1beb-4479-9e60-83d4aa16712a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642189193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.642189193
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3810470853
Short name T400
Test name
Test status
Simulation time 1589008955 ps
CPU time 17.17 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:32 PM PST 24
Peak memory 215044 kb
Host smart-ed8d2752-6682-440e-9638-4b61c6fbed9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810470853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3810470853
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2633246590
Short name T19
Test name
Test status
Simulation time 51290865 ps
CPU time 3.32 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 209152 kb
Host smart-db14b5d3-2b75-40f5-8dc4-086fb00647dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633246590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2633246590
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3071955940
Short name T629
Test name
Test status
Simulation time 591648196 ps
CPU time 18.53 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 214804 kb
Host smart-45f9c35f-29e3-449c-b3e1-19f89c2f5efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071955940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3071955940
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2933720199
Short name T913
Test name
Test status
Simulation time 564763552 ps
CPU time 6.8 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:25 PM PST 24
Peak memory 223020 kb
Host smart-a9bc83ad-8e18-4f3a-9852-83ee2afddfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933720199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2933720199
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2716145656
Short name T749
Test name
Test status
Simulation time 80034532 ps
CPU time 3.52 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 223036 kb
Host smart-076d084a-8827-4bb4-8605-b7d20333e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716145656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2716145656
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.45231630
Short name T895
Test name
Test status
Simulation time 335275106 ps
CPU time 6.11 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 208952 kb
Host smart-86cbfb74-1e2d-4ac1-82d3-d7cbba0face5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45231630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.45231630
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3095421246
Short name T750
Test name
Test status
Simulation time 119392521 ps
CPU time 4.65 seconds
Started Feb 04 03:25:07 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 206920 kb
Host smart-cca544b0-8c16-4310-ba83-93cc8113f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095421246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3095421246
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.455041611
Short name T696
Test name
Test status
Simulation time 524423402 ps
CPU time 2.53 seconds
Started Feb 04 03:25:05 PM PST 24
Finished Feb 04 03:25:13 PM PST 24
Peak memory 207072 kb
Host smart-248ed56b-361e-4a25-8647-cc5989f3a3e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455041611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.455041611
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.900497870
Short name T675
Test name
Test status
Simulation time 98759465 ps
CPU time 1.89 seconds
Started Feb 04 03:25:04 PM PST 24
Finished Feb 04 03:25:09 PM PST 24
Peak memory 207120 kb
Host smart-bb230ce7-95d5-40d1-9237-7b1f0be7b89b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900497870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.900497870
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4146903089
Short name T1030
Test name
Test status
Simulation time 59443487 ps
CPU time 2.95 seconds
Started Feb 04 03:25:01 PM PST 24
Finished Feb 04 03:25:05 PM PST 24
Peak memory 207744 kb
Host smart-72f73cc7-ccbb-4df2-8ed9-4d41ad16c682
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146903089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4146903089
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1826459918
Short name T705
Test name
Test status
Simulation time 90278864 ps
CPU time 2.91 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 208756 kb
Host smart-e919bb6d-4871-4b6f-9ef5-da4f756d546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826459918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1826459918
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3598167507
Short name T576
Test name
Test status
Simulation time 79956885 ps
CPU time 3.05 seconds
Started Feb 04 03:25:06 PM PST 24
Finished Feb 04 03:25:16 PM PST 24
Peak memory 208656 kb
Host smart-4321aa6d-a59b-4797-8292-b854dfd5fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598167507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3598167507
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1306814459
Short name T1077
Test name
Test status
Simulation time 143010476 ps
CPU time 4.14 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 222276 kb
Host smart-e2c0fbe3-dea2-4221-91b5-9657379ea80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306814459 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1306814459
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2773966085
Short name T1020
Test name
Test status
Simulation time 693608193 ps
CPU time 16.45 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 208500 kb
Host smart-a2df4df4-a340-4d97-bf96-bc32d2d35251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773966085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2773966085
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.132205311
Short name T1015
Test name
Test status
Simulation time 81018894 ps
CPU time 3.05 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 210292 kb
Host smart-852b3553-e8b1-40d2-8d77-d09ed0fa34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132205311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.132205311
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.689305897
Short name T590
Test name
Test status
Simulation time 19323751 ps
CPU time 0.81 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 206468 kb
Host smart-e06a8445-34d7-4f88-a440-36145e64f18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689305897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.689305897
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.673893216
Short name T387
Test name
Test status
Simulation time 217630869 ps
CPU time 4.16 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 223012 kb
Host smart-b33a78f7-efbd-4798-8ad9-4ba186bbcf16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673893216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.673893216
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2798989295
Short name T655
Test name
Test status
Simulation time 489091069 ps
CPU time 3.83 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 209352 kb
Host smart-d9712dc8-da7a-4439-8394-939e529ec2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798989295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2798989295
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1643242032
Short name T25
Test name
Test status
Simulation time 576173794 ps
CPU time 16.52 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:34 PM PST 24
Peak memory 214864 kb
Host smart-30e89c1b-5630-498a-ba2d-9563b2526762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643242032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1643242032
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4137488583
Short name T732
Test name
Test status
Simulation time 2678196754 ps
CPU time 55.02 seconds
Started Feb 04 03:25:13 PM PST 24
Finished Feb 04 03:26:14 PM PST 24
Peak memory 220980 kb
Host smart-934e31a3-6a20-4acb-8717-3811a4a8f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137488583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4137488583
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3972629373
Short name T715
Test name
Test status
Simulation time 30869791 ps
CPU time 2.4 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:20 PM PST 24
Peak memory 207064 kb
Host smart-2b5164ae-e19d-4d2d-9923-a55d3138dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972629373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3972629373
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3111073372
Short name T981
Test name
Test status
Simulation time 974737368 ps
CPU time 3.98 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:22 PM PST 24
Peak memory 207152 kb
Host smart-937b9501-4c5f-49f3-90fc-23134f453acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111073372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3111073372
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2726519393
Short name T1027
Test name
Test status
Simulation time 1629609349 ps
CPU time 42.18 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:26:01 PM PST 24
Peak memory 208944 kb
Host smart-d8a909e4-4a3f-404f-bfc6-8c0fb7576185
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726519393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2726519393
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3903650009
Short name T566
Test name
Test status
Simulation time 207847943 ps
CPU time 4.75 seconds
Started Feb 04 03:25:08 PM PST 24
Finished Feb 04 03:25:21 PM PST 24
Peak memory 207012 kb
Host smart-5923e4ab-4934-40cb-82c2-1aa448a48610
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903650009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3903650009
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.148184143
Short name T4
Test name
Test status
Simulation time 92975510 ps
CPU time 2.77 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:19 PM PST 24
Peak memory 209284 kb
Host smart-04d145e8-77a4-4605-ab66-cf3fadf558db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148184143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.148184143
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1217278884
Short name T718
Test name
Test status
Simulation time 279306679 ps
CPU time 3.23 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:22 PM PST 24
Peak memory 209580 kb
Host smart-fd8132b5-92c3-4574-ad13-bf7f03ae3c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217278884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1217278884
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3084565676
Short name T848
Test name
Test status
Simulation time 565883603 ps
CPU time 6.84 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 207236 kb
Host smart-c625ccba-0ecd-43a3-a4a7-521a7d4bfb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084565676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3084565676
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1762496656
Short name T374
Test name
Test status
Simulation time 372621555 ps
CPU time 5.28 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 222992 kb
Host smart-9b71389e-d3b3-4e69-8eed-e40f46ab3f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762496656 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1762496656
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2243462794
Short name T815
Test name
Test status
Simulation time 100516761 ps
CPU time 5.4 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 210400 kb
Host smart-3575ea06-52e0-4ff5-91f0-d0217cba7237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243462794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2243462794
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2711147714
Short name T799
Test name
Test status
Simulation time 3008152751 ps
CPU time 18.49 seconds
Started Feb 04 03:25:13 PM PST 24
Finished Feb 04 03:25:37 PM PST 24
Peak memory 223044 kb
Host smart-3479bcb8-e8fd-4ee1-a507-66a4f3659def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711147714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2711147714
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3793499386
Short name T918
Test name
Test status
Simulation time 84574145 ps
CPU time 0.92 seconds
Started Feb 04 03:25:19 PM PST 24
Finished Feb 04 03:25:28 PM PST 24
Peak memory 206472 kb
Host smart-f56a66db-60be-4224-9486-b2f4e4aac804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793499386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3793499386
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.181349672
Short name T373
Test name
Test status
Simulation time 683016427 ps
CPU time 2.93 seconds
Started Feb 04 03:25:20 PM PST 24
Finished Feb 04 03:25:30 PM PST 24
Peak memory 214692 kb
Host smart-bf992b0e-75ec-46da-a860-a4f88ba3e542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181349672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.181349672
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2792608331
Short name T983
Test name
Test status
Simulation time 61596830 ps
CPU time 3.15 seconds
Started Feb 04 03:25:26 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 208728 kb
Host smart-9cabd9ff-5bad-4b74-9a75-d6b4e17b31dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792608331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2792608331
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4281704000
Short name T943
Test name
Test status
Simulation time 170536246 ps
CPU time 4.59 seconds
Started Feb 04 03:25:18 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 208844 kb
Host smart-23d72aa8-1ae9-42ec-aa57-9a00e1c5e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281704000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4281704000
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1645720762
Short name T288
Test name
Test status
Simulation time 743687836 ps
CPU time 12.06 seconds
Started Feb 04 03:25:20 PM PST 24
Finished Feb 04 03:25:39 PM PST 24
Peak memory 214756 kb
Host smart-a9ea4726-e7c5-42ed-9eca-f1446918f136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645720762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1645720762
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1363035531
Short name T303
Test name
Test status
Simulation time 219647626 ps
CPU time 5.54 seconds
Started Feb 04 03:25:27 PM PST 24
Finished Feb 04 03:25:34 PM PST 24
Peak memory 210444 kb
Host smart-136470b8-5a05-4a18-8bf6-6857ad51cf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363035531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1363035531
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4139375534
Short name T672
Test name
Test status
Simulation time 107347380 ps
CPU time 2.63 seconds
Started Feb 04 03:25:22 PM PST 24
Finished Feb 04 03:25:30 PM PST 24
Peak memory 215404 kb
Host smart-ff819461-02a3-4ee2-9698-bd9ebdec7392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139375534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4139375534
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2615812455
Short name T144
Test name
Test status
Simulation time 50829013 ps
CPU time 3.3 seconds
Started Feb 04 03:25:17 PM PST 24
Finished Feb 04 03:25:30 PM PST 24
Peak memory 207640 kb
Host smart-f71419b7-6a6b-456f-afb7-5492092f76d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615812455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2615812455
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.82244038
Short name T317
Test name
Test status
Simulation time 1269031822 ps
CPU time 3.78 seconds
Started Feb 04 03:25:13 PM PST 24
Finished Feb 04 03:25:22 PM PST 24
Peak memory 209328 kb
Host smart-bb8e5d11-6c1b-4e52-aace-bb1ca465023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82244038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.82244038
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.8353373
Short name T581
Test name
Test status
Simulation time 474435029 ps
CPU time 6.15 seconds
Started Feb 04 03:25:10 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 208896 kb
Host smart-e5e5a33e-7891-431b-ac87-996dafada3b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8353373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.8353373
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2571778755
Short name T356
Test name
Test status
Simulation time 1899311978 ps
CPU time 11.34 seconds
Started Feb 04 03:25:11 PM PST 24
Finished Feb 04 03:25:29 PM PST 24
Peak memory 209096 kb
Host smart-540f7c00-e24b-4146-a761-ac44bd19ebb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571778755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2571778755
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1907268224
Short name T939
Test name
Test status
Simulation time 371223705 ps
CPU time 4.4 seconds
Started Feb 04 03:25:12 PM PST 24
Finished Feb 04 03:25:23 PM PST 24
Peak memory 209228 kb
Host smart-c3228d27-8619-448f-b0ea-ad07bef7f00d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907268224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1907268224
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2962765067
Short name T872
Test name
Test status
Simulation time 303773930 ps
CPU time 3.41 seconds
Started Feb 04 03:25:34 PM PST 24
Finished Feb 04 03:25:39 PM PST 24
Peak memory 210116 kb
Host smart-286185f6-3086-445a-8dc4-bf3618b7962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962765067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2962765067
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1949292657
Short name T760
Test name
Test status
Simulation time 862444373 ps
CPU time 6 seconds
Started Feb 04 03:25:09 PM PST 24
Finished Feb 04 03:25:22 PM PST 24
Peak memory 206908 kb
Host smart-3a7e30f4-e93d-4191-8d2d-e01ee9d50c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949292657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1949292657
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1145999900
Short name T231
Test name
Test status
Simulation time 2628279451 ps
CPU time 26.51 seconds
Started Feb 04 03:25:28 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 216944 kb
Host smart-9e51e857-b23a-4cb1-b14a-4106c8ef1fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145999900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1145999900
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.500191125
Short name T217
Test name
Test status
Simulation time 1137927412 ps
CPU time 6.27 seconds
Started Feb 04 03:25:31 PM PST 24
Finished Feb 04 03:25:38 PM PST 24
Peak memory 223020 kb
Host smart-cc2d15a4-9c43-4382-9ea9-4bce57b2a698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500191125 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.500191125
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.445770510
Short name T738
Test name
Test status
Simulation time 312139355 ps
CPU time 11.16 seconds
Started Feb 04 03:25:20 PM PST 24
Finished Feb 04 03:25:38 PM PST 24
Peak memory 208420 kb
Host smart-2561ceea-93ec-43bd-81f2-5df22634d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445770510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.445770510
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.772721086
Short name T36
Test name
Test status
Simulation time 206219280 ps
CPU time 2.67 seconds
Started Feb 04 03:25:29 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 210640 kb
Host smart-058a3cd6-d857-40a3-af44-dc098dc77295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772721086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.772721086
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.536152845
Short name T99
Test name
Test status
Simulation time 43892617 ps
CPU time 0.86 seconds
Started Feb 04 03:25:28 PM PST 24
Finished Feb 04 03:25:30 PM PST 24
Peak memory 206496 kb
Host smart-cbd797b9-085e-4cff-96b4-946b7402fda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536152845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.536152845
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3828407901
Short name T1067
Test name
Test status
Simulation time 186718589 ps
CPU time 3.76 seconds
Started Feb 04 03:25:18 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 214840 kb
Host smart-30065bf0-fa76-47f5-adfa-4ea37b93d3d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828407901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3828407901
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1351571258
Short name T30
Test name
Test status
Simulation time 495415975 ps
CPU time 4.54 seconds
Started Feb 04 03:25:27 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 209560 kb
Host smart-03ba9afc-cd88-4905-bf37-b54c65ba2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351571258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1351571258
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1034363563
Short name T964
Test name
Test status
Simulation time 193187118 ps
CPU time 5.28 seconds
Started Feb 04 03:25:31 PM PST 24
Finished Feb 04 03:25:37 PM PST 24
Peak memory 208960 kb
Host smart-70c3ba93-2363-4dfb-9634-739efa2efe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034363563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1034363563
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4155762130
Short name T956
Test name
Test status
Simulation time 467385886 ps
CPU time 11.84 seconds
Started Feb 04 03:25:27 PM PST 24
Finished Feb 04 03:25:40 PM PST 24
Peak memory 210104 kb
Host smart-9d6d6ca8-ef3a-4857-89f9-7929bb3be82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155762130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4155762130
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.787864224
Short name T323
Test name
Test status
Simulation time 411240960 ps
CPU time 5.3 seconds
Started Feb 04 03:25:34 PM PST 24
Finished Feb 04 03:25:41 PM PST 24
Peak memory 214848 kb
Host smart-9620ae43-3d6c-4bcf-8a6a-5fcf304bb624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787864224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.787864224
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1747497924
Short name T894
Test name
Test status
Simulation time 287584945 ps
CPU time 3.89 seconds
Started Feb 04 03:25:25 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 216932 kb
Host smart-4bda0c62-dcae-48b7-9423-a1f11c2e0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747497924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1747497924
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.688671636
Short name T688
Test name
Test status
Simulation time 221296035 ps
CPU time 5.56 seconds
Started Feb 04 03:25:19 PM PST 24
Finished Feb 04 03:25:33 PM PST 24
Peak memory 207392 kb
Host smart-4e2f9a98-78fe-46d4-a85f-708d51b0664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688671636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.688671636
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1540826584
Short name T952
Test name
Test status
Simulation time 346122755 ps
CPU time 10.12 seconds
Started Feb 04 03:25:25 PM PST 24
Finished Feb 04 03:25:37 PM PST 24
Peak memory 208756 kb
Host smart-4b15c020-4db3-4a4e-ace6-728f1252fd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540826584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1540826584
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3956083711
Short name T135
Test name
Test status
Simulation time 2979019892 ps
CPU time 7.36 seconds
Started Feb 04 03:25:22 PM PST 24
Finished Feb 04 03:25:35 PM PST 24
Peak memory 209040 kb
Host smart-d7d4cc9d-0039-4bf6-817b-9b02646b0cf0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956083711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3956083711
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2380647181
Short name T207
Test name
Test status
Simulation time 31722019096 ps
CPU time 56.41 seconds
Started Feb 04 03:25:30 PM PST 24
Finished Feb 04 03:26:27 PM PST 24
Peak memory 208888 kb
Host smart-ff2ef330-3506-49cc-8a4b-216f26bc3b37
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380647181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2380647181
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3051155888
Short name T855
Test name
Test status
Simulation time 291867624 ps
CPU time 3.49 seconds
Started Feb 04 03:25:17 PM PST 24
Finished Feb 04 03:25:30 PM PST 24
Peak memory 209196 kb
Host smart-0e84337b-47e6-4d64-bd4f-0b55a38c2ceb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051155888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3051155888
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.580008197
Short name T915
Test name
Test status
Simulation time 1514601947 ps
CPU time 19.72 seconds
Started Feb 04 03:25:33 PM PST 24
Finished Feb 04 03:25:54 PM PST 24
Peak memory 214880 kb
Host smart-82608280-64b3-42ea-99eb-81ddb7ef50ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580008197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.580008197
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.803016849
Short name T972
Test name
Test status
Simulation time 4080264809 ps
CPU time 27.15 seconds
Started Feb 04 03:25:23 PM PST 24
Finished Feb 04 03:25:54 PM PST 24
Peak memory 208912 kb
Host smart-0e1c85b1-f8a5-48c2-9bd6-8e8f84d793f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803016849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.803016849
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3905906777
Short name T86
Test name
Test status
Simulation time 268081052 ps
CPU time 8.91 seconds
Started Feb 04 03:25:35 PM PST 24
Finished Feb 04 03:25:45 PM PST 24
Peak memory 223756 kb
Host smart-9b089078-8a22-40de-a7ee-e14e19c151a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905906777 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3905906777
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4194630977
Short name T196
Test name
Test status
Simulation time 7122899859 ps
CPU time 39.29 seconds
Started Feb 04 03:25:32 PM PST 24
Finished Feb 04 03:26:12 PM PST 24
Peak memory 214844 kb
Host smart-9525880a-9cbc-45a9-93e6-a94c85ea3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194630977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4194630977
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4010412097
Short name T684
Test name
Test status
Simulation time 52769311 ps
CPU time 1.93 seconds
Started Feb 04 03:25:28 PM PST 24
Finished Feb 04 03:25:31 PM PST 24
Peak memory 210208 kb
Host smart-bccfed2d-e4e9-4935-b571-7a47be9bc8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010412097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4010412097
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3505440873
Short name T770
Test name
Test status
Simulation time 34502544 ps
CPU time 0.82 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:44 PM PST 24
Peak memory 206404 kb
Host smart-ca05d28c-aa65-4210-8fdb-1c508795fa0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505440873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3505440873
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2374588609
Short name T401
Test name
Test status
Simulation time 116089093 ps
CPU time 6.48 seconds
Started Feb 04 03:25:35 PM PST 24
Finished Feb 04 03:25:43 PM PST 24
Peak memory 215844 kb
Host smart-66791d2f-4f6b-4b62-9326-915ddd0be989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374588609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2374588609
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.844580717
Short name T108
Test name
Test status
Simulation time 222196404 ps
CPU time 5.07 seconds
Started Feb 04 03:25:34 PM PST 24
Finished Feb 04 03:25:40 PM PST 24
Peak memory 214856 kb
Host smart-2ee0d1d5-7315-463c-97a6-fadf52d0c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844580717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.844580717
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3083115810
Short name T87
Test name
Test status
Simulation time 120244220 ps
CPU time 5.48 seconds
Started Feb 04 03:25:28 PM PST 24
Finished Feb 04 03:25:34 PM PST 24
Peak memory 214944 kb
Host smart-dab457ca-c8b2-4054-b972-203a24d85e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083115810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3083115810
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2625889113
Short name T114
Test name
Test status
Simulation time 634972567 ps
CPU time 7.48 seconds
Started Feb 04 03:25:32 PM PST 24
Finished Feb 04 03:25:41 PM PST 24
Peak memory 222844 kb
Host smart-02173538-53d6-427c-820b-44bcf2279144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625889113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2625889113
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1084203403
Short name T1011
Test name
Test status
Simulation time 483912644 ps
CPU time 6.11 seconds
Started Feb 04 03:25:35 PM PST 24
Finished Feb 04 03:25:42 PM PST 24
Peak memory 209000 kb
Host smart-c4605e4a-94ee-46c9-81ea-08af544f90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084203403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1084203403
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3071146290
Short name T357
Test name
Test status
Simulation time 2218881626 ps
CPU time 16.42 seconds
Started Feb 04 03:25:33 PM PST 24
Finished Feb 04 03:25:51 PM PST 24
Peak memory 207720 kb
Host smart-fc4b0222-443c-4aea-b8cf-9fc7dddd0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071146290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3071146290
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2415844590
Short name T923
Test name
Test status
Simulation time 7578820299 ps
CPU time 56.2 seconds
Started Feb 04 03:25:31 PM PST 24
Finished Feb 04 03:26:28 PM PST 24
Peak memory 208980 kb
Host smart-1c086f71-ff70-4438-b495-0a8ba8474437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415844590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2415844590
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3070391211
Short name T138
Test name
Test status
Simulation time 902722516 ps
CPU time 6.79 seconds
Started Feb 04 03:25:34 PM PST 24
Finished Feb 04 03:25:42 PM PST 24
Peak memory 209020 kb
Host smart-d5bf9252-ddff-487a-a6ea-4410757dbeec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070391211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3070391211
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.726774866
Short name T898
Test name
Test status
Simulation time 340219626 ps
CPU time 3.84 seconds
Started Feb 04 03:25:30 PM PST 24
Finished Feb 04 03:25:35 PM PST 24
Peak memory 209244 kb
Host smart-85338eeb-087a-403d-a069-6403027c1761
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726774866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.726774866
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1862121690
Short name T1009
Test name
Test status
Simulation time 150117553 ps
CPU time 5.64 seconds
Started Feb 04 03:25:31 PM PST 24
Finished Feb 04 03:25:37 PM PST 24
Peak memory 208912 kb
Host smart-833834e1-e9ba-4e49-bc15-5d9d4e5a7504
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862121690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1862121690
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2944247271
Short name T241
Test name
Test status
Simulation time 411355521 ps
CPU time 4.44 seconds
Started Feb 04 03:25:43 PM PST 24
Finished Feb 04 03:25:48 PM PST 24
Peak memory 209884 kb
Host smart-06e9ff81-5288-4616-bb70-a9aa74bfd4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944247271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2944247271
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2538544266
Short name T405
Test name
Test status
Simulation time 367523777 ps
CPU time 5.47 seconds
Started Feb 04 03:25:29 PM PST 24
Finished Feb 04 03:25:35 PM PST 24
Peak memory 206952 kb
Host smart-5c97994b-ce27-4022-9a5e-bb8a8f3af004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538544266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2538544266
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3207389446
Short name T331
Test name
Test status
Simulation time 276234764 ps
CPU time 14.73 seconds
Started Feb 04 03:25:37 PM PST 24
Finished Feb 04 03:25:54 PM PST 24
Peak memory 223016 kb
Host smart-f8e7d61f-e900-4921-b7f4-2e9ab1d7897a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207389446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3207389446
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2118668786
Short name T103
Test name
Test status
Simulation time 273069912 ps
CPU time 9.59 seconds
Started Feb 04 03:25:49 PM PST 24
Finished Feb 04 03:26:02 PM PST 24
Peak memory 223156 kb
Host smart-3586b5c3-efe4-4e8f-887a-40a63c33d762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118668786 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2118668786
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2370763825
Short name T812
Test name
Test status
Simulation time 874308903 ps
CPU time 7.13 seconds
Started Feb 04 03:25:30 PM PST 24
Finished Feb 04 03:25:38 PM PST 24
Peak memory 207560 kb
Host smart-f53ac9be-e6d3-4687-a169-66ee7a8073dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370763825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2370763825
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1872750635
Short name T580
Test name
Test status
Simulation time 1670004133 ps
CPU time 9.89 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:53 PM PST 24
Peak memory 211168 kb
Host smart-d351bfc3-4f35-44a4-9cfb-8e846f8094f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872750635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1872750635
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1879705232
Short name T982
Test name
Test status
Simulation time 9546166 ps
CPU time 0.83 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:53 PM PST 24
Peak memory 206388 kb
Host smart-ddfc1b2e-fb1d-4b81-87ec-3a08dbe4bbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879705232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1879705232
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1349784796
Short name T263
Test name
Test status
Simulation time 232881291 ps
CPU time 4.32 seconds
Started Feb 04 03:25:49 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 215856 kb
Host smart-e1a5b098-a28e-4d6a-a50d-94ac84654a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349784796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1349784796
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.821275692
Short name T704
Test name
Test status
Simulation time 1261541450 ps
CPU time 33.28 seconds
Started Feb 04 03:25:47 PM PST 24
Finished Feb 04 03:26:25 PM PST 24
Peak memory 223080 kb
Host smart-e369e75a-89e2-44e9-b907-b3bf4ced9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821275692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.821275692
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2303934715
Short name T73
Test name
Test status
Simulation time 138599946 ps
CPU time 3.25 seconds
Started Feb 04 03:25:48 PM PST 24
Finished Feb 04 03:25:55 PM PST 24
Peak memory 214780 kb
Host smart-988c5b03-5f2f-480c-bdfd-891bea76b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303934715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2303934715
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3654760368
Short name T94
Test name
Test status
Simulation time 701414828 ps
CPU time 6.78 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:11 PM PST 24
Peak memory 209596 kb
Host smart-d63e5502-eec1-45be-a753-da3e7ba0e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654760368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3654760368
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3927767809
Short name T251
Test name
Test status
Simulation time 166284102 ps
CPU time 4.11 seconds
Started Feb 04 03:25:48 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 214852 kb
Host smart-dc7771ba-608c-4061-84ab-4a253a6e1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927767809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3927767809
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4802745
Short name T804
Test name
Test status
Simulation time 95211466 ps
CPU time 4.94 seconds
Started Feb 04 03:25:45 PM PST 24
Finished Feb 04 03:25:51 PM PST 24
Peak memory 210388 kb
Host smart-07e8a362-9acb-49c2-a196-7d3bdf94949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4802745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4802745
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3434798184
Short name T771
Test name
Test status
Simulation time 40243507 ps
CPU time 2.87 seconds
Started Feb 04 03:25:36 PM PST 24
Finished Feb 04 03:25:40 PM PST 24
Peak memory 208884 kb
Host smart-380857c8-a866-42f0-a02a-c5236e88bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434798184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3434798184
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4160167158
Short name T252
Test name
Test status
Simulation time 115521786 ps
CPU time 4.38 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:47 PM PST 24
Peak memory 208696 kb
Host smart-8c5847be-ba28-496e-89eb-f0356c266534
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160167158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4160167158
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.430909831
Short name T721
Test name
Test status
Simulation time 1891766312 ps
CPU time 27.3 seconds
Started Feb 04 03:25:39 PM PST 24
Finished Feb 04 03:26:10 PM PST 24
Peak memory 208520 kb
Host smart-2789ffb9-0b3f-475d-8848-e5ca8a9a970c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430909831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.430909831
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3259056591
Short name T690
Test name
Test status
Simulation time 323655346 ps
CPU time 3.71 seconds
Started Feb 04 03:25:46 PM PST 24
Finished Feb 04 03:25:53 PM PST 24
Peak memory 207000 kb
Host smart-c8b65faf-f682-4e7f-9255-3b76c80c978f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259056591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3259056591
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.979176072
Short name T311
Test name
Test status
Simulation time 151227421 ps
CPU time 4.76 seconds
Started Feb 04 03:25:51 PM PST 24
Finished Feb 04 03:25:58 PM PST 24
Peak memory 210220 kb
Host smart-d20a5f9b-9135-423d-874f-dfd31b193782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979176072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.979176072
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.208184596
Short name T1019
Test name
Test status
Simulation time 240637409 ps
CPU time 3.09 seconds
Started Feb 04 03:25:43 PM PST 24
Finished Feb 04 03:25:47 PM PST 24
Peak memory 207040 kb
Host smart-4a84029f-2ad0-46f5-8111-3ccbc5914cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208184596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.208184596
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2557145392
Short name T1003
Test name
Test status
Simulation time 193591354 ps
CPU time 6.49 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:49 PM PST 24
Peak memory 223056 kb
Host smart-be6d8981-16d1-4fd3-b8db-08a5f7e2e928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557145392 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2557145392
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4234461640
Short name T651
Test name
Test status
Simulation time 286626159 ps
CPU time 3.39 seconds
Started Feb 04 03:25:44 PM PST 24
Finished Feb 04 03:25:48 PM PST 24
Peak memory 209496 kb
Host smart-f4d158f6-08b0-4340-bfd4-dd21e55b2ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234461640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4234461640
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2995016413
Short name T63
Test name
Test status
Simulation time 293048144 ps
CPU time 2.7 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:46 PM PST 24
Peak memory 210432 kb
Host smart-2250d1aa-4148-40b9-97f1-5aa496eecee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995016413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2995016413
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2545241602
Short name T1091
Test name
Test status
Simulation time 10447413 ps
CPU time 0.83 seconds
Started Feb 04 03:25:56 PM PST 24
Finished Feb 04 03:26:08 PM PST 24
Peak memory 206468 kb
Host smart-4ea5c22d-4bb5-491c-9619-d640213c1083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545241602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2545241602
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3953725657
Short name T66
Test name
Test status
Simulation time 224334933 ps
CPU time 3.19 seconds
Started Feb 04 03:25:51 PM PST 24
Finished Feb 04 03:25:57 PM PST 24
Peak memory 215124 kb
Host smart-715df2ed-73f2-4d91-8129-78a994f2ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953725657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3953725657
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2707008015
Short name T893
Test name
Test status
Simulation time 44402353 ps
CPU time 1.76 seconds
Started Feb 04 03:25:40 PM PST 24
Finished Feb 04 03:25:45 PM PST 24
Peak memory 208364 kb
Host smart-9adf4503-6d00-47d3-b2e3-9d35067e3fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707008015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2707008015
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3680212107
Short name T287
Test name
Test status
Simulation time 1231963640 ps
CPU time 31.51 seconds
Started Feb 04 03:25:51 PM PST 24
Finished Feb 04 03:26:25 PM PST 24
Peak memory 219712 kb
Host smart-5b66be6b-b148-4eb7-9821-65341245de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680212107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3680212107
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.891795549
Short name T860
Test name
Test status
Simulation time 1450643451 ps
CPU time 29.9 seconds
Started Feb 04 03:25:44 PM PST 24
Finished Feb 04 03:26:15 PM PST 24
Peak memory 214708 kb
Host smart-e16c6a60-ddeb-4acf-9472-7bfed707b95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891795549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.891795549
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2364324933
Short name T884
Test name
Test status
Simulation time 72575925 ps
CPU time 2.51 seconds
Started Feb 04 03:25:44 PM PST 24
Finished Feb 04 03:25:48 PM PST 24
Peak memory 208420 kb
Host smart-f2d0d808-0331-40ec-8630-4dac6691a285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364324933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2364324933
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2652677096
Short name T240
Test name
Test status
Simulation time 644848667 ps
CPU time 4.02 seconds
Started Feb 04 03:25:45 PM PST 24
Finished Feb 04 03:25:50 PM PST 24
Peak memory 207744 kb
Host smart-7251f12f-fdb3-4eab-a3a9-fdddc54f28ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652677096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2652677096
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4187791823
Short name T244
Test name
Test status
Simulation time 190459266 ps
CPU time 4.63 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:09 PM PST 24
Peak memory 208908 kb
Host smart-66e77934-6e84-4dec-ae92-19a7ddc39aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187791823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4187791823
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2670219416
Short name T857
Test name
Test status
Simulation time 646568143 ps
CPU time 5.52 seconds
Started Feb 04 03:25:39 PM PST 24
Finished Feb 04 03:25:45 PM PST 24
Peak memory 208576 kb
Host smart-2ae43e39-28f3-4f1e-b913-2f7fb6c7240f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670219416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2670219416
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4291243325
Short name T596
Test name
Test status
Simulation time 270841250 ps
CPU time 3.71 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 208928 kb
Host smart-20e00651-3da7-4881-a664-7dbdd114473b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291243325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4291243325
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.655129946
Short name T379
Test name
Test status
Simulation time 754564720 ps
CPU time 6.21 seconds
Started Feb 04 03:25:45 PM PST 24
Finished Feb 04 03:25:52 PM PST 24
Peak memory 208084 kb
Host smart-f64c1a62-c5dc-4501-b79a-86a1c3e32a5e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655129946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.655129946
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3492591025
Short name T973
Test name
Test status
Simulation time 168298775 ps
CPU time 5.51 seconds
Started Feb 04 03:25:51 PM PST 24
Finished Feb 04 03:25:59 PM PST 24
Peak memory 209244 kb
Host smart-d37f4e4a-d3c0-4108-859c-e7d2b2c44737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492591025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3492591025
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2461069508
Short name T813
Test name
Test status
Simulation time 64426832 ps
CPU time 3.09 seconds
Started Feb 04 03:25:45 PM PST 24
Finished Feb 04 03:25:50 PM PST 24
Peak memory 208208 kb
Host smart-b8017033-5921-4f37-be52-b6d59c6986ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461069508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2461069508
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3944487061
Short name T215
Test name
Test status
Simulation time 203716213 ps
CPU time 5.35 seconds
Started Feb 04 03:25:48 PM PST 24
Finished Feb 04 03:25:57 PM PST 24
Peak memory 223008 kb
Host smart-62ccee52-7a92-4ec1-8f3e-c70aaf5d79cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944487061 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3944487061
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3186505375
Short name T1010
Test name
Test status
Simulation time 95971293 ps
CPU time 3.37 seconds
Started Feb 04 03:25:43 PM PST 24
Finished Feb 04 03:25:48 PM PST 24
Peak memory 218684 kb
Host smart-8365b47f-13be-4edd-9828-55b247540982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186505375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3186505375
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4110988918
Short name T588
Test name
Test status
Simulation time 110836662 ps
CPU time 1.96 seconds
Started Feb 04 03:25:56 PM PST 24
Finished Feb 04 03:26:09 PM PST 24
Peak memory 210084 kb
Host smart-6250d390-5141-4496-8ec3-41ef17d38f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110988918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4110988918
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2577152218
Short name T627
Test name
Test status
Simulation time 117020437 ps
CPU time 0.75 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:06 PM PST 24
Peak memory 206380 kb
Host smart-24eb16a0-2a23-43cb-905f-7fe563989592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577152218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2577152218
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1776392100
Short name T160
Test name
Test status
Simulation time 40942233 ps
CPU time 3.19 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:55 PM PST 24
Peak memory 214832 kb
Host smart-1405ec2d-e3c3-4254-a106-a68fc67a84c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776392100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1776392100
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.967983426
Short name T668
Test name
Test status
Simulation time 2802506985 ps
CPU time 37.6 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:26:30 PM PST 24
Peak memory 223348 kb
Host smart-03a20a6d-1701-456b-83c9-4e26e03e212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967983426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.967983426
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.302330907
Short name T817
Test name
Test status
Simulation time 4930721020 ps
CPU time 45.35 seconds
Started Feb 04 03:25:47 PM PST 24
Finished Feb 04 03:26:37 PM PST 24
Peak memory 210028 kb
Host smart-f5aaedf6-f1c2-4e24-b900-1dcd99553380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302330907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.302330907
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4207614055
Short name T28
Test name
Test status
Simulation time 80146590 ps
CPU time 2.89 seconds
Started Feb 04 03:25:56 PM PST 24
Finished Feb 04 03:26:10 PM PST 24
Peak memory 208528 kb
Host smart-83932b60-5216-472a-9155-52a0e788d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207614055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4207614055
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2901106106
Short name T324
Test name
Test status
Simulation time 169054473 ps
CPU time 3.07 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 214736 kb
Host smart-46753087-5d14-42b5-ad5d-546672f368e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901106106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2901106106
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.541638729
Short name T700
Test name
Test status
Simulation time 137738640 ps
CPU time 3.7 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:08 PM PST 24
Peak memory 215176 kb
Host smart-dacabc36-0a53-47d3-b29d-ed9cdae396ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541638729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.541638729
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.491107351
Short name T255
Test name
Test status
Simulation time 639541827 ps
CPU time 4.92 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:58 PM PST 24
Peak memory 210156 kb
Host smart-ba632363-0334-4e32-87bc-0ca6e95acd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491107351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.491107351
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1016727314
Short name T206
Test name
Test status
Simulation time 184352104 ps
CPU time 6.92 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:11 PM PST 24
Peak memory 208232 kb
Host smart-96e07464-f0a9-4fda-bedd-37ce5bdfaaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016727314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1016727314
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.846397345
Short name T849
Test name
Test status
Simulation time 53832726 ps
CPU time 2.3 seconds
Started Feb 04 03:25:50 PM PST 24
Finished Feb 04 03:25:55 PM PST 24
Peak memory 207048 kb
Host smart-e53faa93-c019-4c74-a0f7-cb5b804fbfd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846397345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.846397345
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.587510414
Short name T656
Test name
Test status
Simulation time 2420711742 ps
CPU time 15.46 seconds
Started Feb 04 03:25:46 PM PST 24
Finished Feb 04 03:26:05 PM PST 24
Peak memory 208356 kb
Host smart-23ca3962-d86d-4073-8037-9638bdf52266
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587510414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.587510414
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2314936102
Short name T782
Test name
Test status
Simulation time 1284985346 ps
CPU time 3.42 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:07 PM PST 24
Peak memory 207152 kb
Host smart-70b5752d-8abd-48ca-a84d-53849d3656e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314936102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2314936102
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3317931822
Short name T724
Test name
Test status
Simulation time 937877040 ps
CPU time 4.38 seconds
Started Feb 04 03:25:48 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 208732 kb
Host smart-b7aabe76-cf6d-44af-8363-947ffc70ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317931822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3317931822
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3095545629
Short name T335
Test name
Test status
Simulation time 522259051 ps
CPU time 10.45 seconds
Started Feb 04 03:25:56 PM PST 24
Finished Feb 04 03:26:17 PM PST 24
Peak memory 216968 kb
Host smart-2446c205-3030-44c7-afec-8e1a7cf9db44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095545629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3095545629
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.4209034641
Short name T604
Test name
Test status
Simulation time 361583567 ps
CPU time 3.65 seconds
Started Feb 04 03:25:49 PM PST 24
Finished Feb 04 03:25:56 PM PST 24
Peak memory 221780 kb
Host smart-6802d771-add0-4a4c-a065-db57e1d044c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209034641 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.4209034641
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4146432953
Short name T868
Test name
Test status
Simulation time 10338539086 ps
CPU time 107.3 seconds
Started Feb 04 03:25:56 PM PST 24
Finished Feb 04 03:27:54 PM PST 24
Peak memory 218764 kb
Host smart-9d6fd7db-9444-4a8c-afcc-aa4c42ad6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146432953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4146432953
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1434346032
Short name T805
Test name
Test status
Simulation time 111544527 ps
CPU time 2.92 seconds
Started Feb 04 03:25:53 PM PST 24
Finished Feb 04 03:26:08 PM PST 24
Peak memory 210408 kb
Host smart-084acc1e-a940-40eb-91e5-7ccd4b5730cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434346032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1434346032
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.910260681
Short name T903
Test name
Test status
Simulation time 138499131 ps
CPU time 0.96 seconds
Started Feb 04 03:21:10 PM PST 24
Finished Feb 04 03:21:15 PM PST 24
Peak memory 206552 kb
Host smart-c4055876-2f9f-41b8-870a-c95b5076d4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910260681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.910260681
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1729070422
Short name T238
Test name
Test status
Simulation time 39504365 ps
CPU time 2.88 seconds
Started Feb 04 03:21:01 PM PST 24
Finished Feb 04 03:21:05 PM PST 24
Peak memory 215096 kb
Host smart-d56f676b-b351-4786-bda1-52cfe07fd8b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729070422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1729070422
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.633936498
Short name T623
Test name
Test status
Simulation time 3295301833 ps
CPU time 20.84 seconds
Started Feb 04 03:20:59 PM PST 24
Finished Feb 04 03:21:21 PM PST 24
Peak memory 209596 kb
Host smart-cf60b6e9-3125-43f9-8ec9-eb41c5887a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633936498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.633936498
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4219284912
Short name T984
Test name
Test status
Simulation time 91063260 ps
CPU time 4.47 seconds
Started Feb 04 03:21:10 PM PST 24
Finished Feb 04 03:21:19 PM PST 24
Peak memory 209724 kb
Host smart-a7b57b6b-bb4a-48be-a7eb-2aa641a942e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219284912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4219284912
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1148530636
Short name T1090
Test name
Test status
Simulation time 267194689 ps
CPU time 6.22 seconds
Started Feb 04 03:21:12 PM PST 24
Finished Feb 04 03:21:21 PM PST 24
Peak memory 222872 kb
Host smart-1edc1290-d80d-4317-9aed-6529a906aab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148530636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1148530636
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1135626732
Short name T1017
Test name
Test status
Simulation time 296011319 ps
CPU time 3.85 seconds
Started Feb 04 03:21:09 PM PST 24
Finished Feb 04 03:21:18 PM PST 24
Peak memory 209980 kb
Host smart-862045b5-cb6a-4b30-8042-44008537f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135626732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1135626732
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3824084216
Short name T1059
Test name
Test status
Simulation time 680497323 ps
CPU time 3.53 seconds
Started Feb 04 03:20:58 PM PST 24
Finished Feb 04 03:21:02 PM PST 24
Peak memory 208448 kb
Host smart-ef0d39fd-5e5f-4151-8e1b-bc0455dab14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824084216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3824084216
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1357616257
Short name T1034
Test name
Test status
Simulation time 429030178 ps
CPU time 6.13 seconds
Started Feb 04 03:20:54 PM PST 24
Finished Feb 04 03:21:01 PM PST 24
Peak memory 208196 kb
Host smart-e9f50d9f-538b-4e08-bc89-357565b1fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357616257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1357616257
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1337086517
Short name T685
Test name
Test status
Simulation time 288603081 ps
CPU time 6.19 seconds
Started Feb 04 03:20:58 PM PST 24
Finished Feb 04 03:21:05 PM PST 24
Peak memory 208088 kb
Host smart-61236af1-90a8-4f16-bb52-ecf0c27cba32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337086517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1337086517
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3178272104
Short name T641
Test name
Test status
Simulation time 689278625 ps
CPU time 5.72 seconds
Started Feb 04 03:21:02 PM PST 24
Finished Feb 04 03:21:10 PM PST 24
Peak memory 208232 kb
Host smart-e6cd9da4-50c5-4696-9f2f-6efa883cf949
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178272104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3178272104
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.659577387
Short name T711
Test name
Test status
Simulation time 280855714 ps
CPU time 6.72 seconds
Started Feb 04 03:21:01 PM PST 24
Finished Feb 04 03:21:10 PM PST 24
Peak memory 208360 kb
Host smart-33291e88-162e-498c-82d8-4f495b7eb72f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659577387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.659577387
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2179582091
Short name T916
Test name
Test status
Simulation time 37343847 ps
CPU time 2.56 seconds
Started Feb 04 03:21:10 PM PST 24
Finished Feb 04 03:21:17 PM PST 24
Peak memory 214840 kb
Host smart-0920f762-48c1-4442-bcdd-e3318e29dd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179582091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2179582091
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1108126951
Short name T16
Test name
Test status
Simulation time 90717628 ps
CPU time 2.65 seconds
Started Feb 04 03:20:55 PM PST 24
Finished Feb 04 03:20:58 PM PST 24
Peak memory 206904 kb
Host smart-db29c9e2-7127-46ee-99d6-efa35458b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108126951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1108126951
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1088437948
Short name T170
Test name
Test status
Simulation time 236860915 ps
CPU time 4.85 seconds
Started Feb 04 03:21:10 PM PST 24
Finished Feb 04 03:21:19 PM PST 24
Peak memory 221040 kb
Host smart-09102208-6445-41cf-a91b-a449206a65e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088437948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1088437948
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1024291854
Short name T218
Test name
Test status
Simulation time 191102974 ps
CPU time 8.27 seconds
Started Feb 04 03:21:21 PM PST 24
Finished Feb 04 03:21:30 PM PST 24
Peak memory 220660 kb
Host smart-bf37f5f0-3d04-4fd8-8246-6166040175d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024291854 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1024291854
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.648102986
Short name T345
Test name
Test status
Simulation time 1191990874 ps
CPU time 34.57 seconds
Started Feb 04 03:21:21 PM PST 24
Finished Feb 04 03:21:57 PM PST 24
Peak memory 208532 kb
Host smart-e7833cea-df95-4fd7-96bc-3c501ad5c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648102986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.648102986
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1887867585
Short name T836
Test name
Test status
Simulation time 103851034 ps
CPU time 2.72 seconds
Started Feb 04 03:21:11 PM PST 24
Finished Feb 04 03:21:17 PM PST 24
Peak memory 209952 kb
Host smart-841efb30-1a14-4c61-815e-c2cc4bf1dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887867585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1887867585
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1140656036
Short name T806
Test name
Test status
Simulation time 37812110 ps
CPU time 0.89 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:24 PM PST 24
Peak memory 206484 kb
Host smart-27bc6705-e20b-4d17-a841-5c6db5f1f48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140656036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1140656036
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2680310122
Short name T8
Test name
Test status
Simulation time 46135672 ps
CPU time 1.9 seconds
Started Feb 04 03:21:17 PM PST 24
Finished Feb 04 03:21:20 PM PST 24
Peak memory 209136 kb
Host smart-01f6a42e-7acc-42ab-b453-81d0821bb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680310122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2680310122
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4170941747
Short name T767
Test name
Test status
Simulation time 62837994 ps
CPU time 2.9 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:26 PM PST 24
Peak memory 210036 kb
Host smart-8676b77f-d2dd-4fe5-b98d-f2f6e9c95da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170941747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4170941747
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2449579772
Short name T93
Test name
Test status
Simulation time 252536644 ps
CPU time 6.38 seconds
Started Feb 04 03:21:18 PM PST 24
Finished Feb 04 03:21:26 PM PST 24
Peak memory 221632 kb
Host smart-49e58008-5ff4-4b29-8714-fcea27b9aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449579772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2449579772
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.442788786
Short name T772
Test name
Test status
Simulation time 277993320 ps
CPU time 3.61 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:23 PM PST 24
Peak memory 214912 kb
Host smart-8bf10789-15c4-4e01-8153-b2c200d765b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442788786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.442788786
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1853733462
Short name T950
Test name
Test status
Simulation time 653775410 ps
CPU time 5.47 seconds
Started Feb 04 03:21:11 PM PST 24
Finished Feb 04 03:21:20 PM PST 24
Peak memory 208780 kb
Host smart-2b8b6bfa-70db-46ba-9b07-99e3f785c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853733462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1853733462
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4111792710
Short name T683
Test name
Test status
Simulation time 231597494 ps
CPU time 6.45 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:26 PM PST 24
Peak memory 209020 kb
Host smart-5f8fb111-232b-4035-ac78-2d278878dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111792710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4111792710
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.6510891
Short name T1092
Test name
Test status
Simulation time 172680244 ps
CPU time 5.04 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:25 PM PST 24
Peak memory 208928 kb
Host smart-28baf056-9b4e-4cb5-a0cf-b2799aa5af39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6510891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.6510891
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1151686451
Short name T761
Test name
Test status
Simulation time 276378536 ps
CPU time 3.8 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:24 PM PST 24
Peak memory 207140 kb
Host smart-35663629-fd74-473a-87c1-f5c309602e16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151686451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1151686451
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2538575807
Short name T795
Test name
Test status
Simulation time 59064129 ps
CPU time 2.36 seconds
Started Feb 04 03:21:11 PM PST 24
Finished Feb 04 03:21:17 PM PST 24
Peak memory 207076 kb
Host smart-54bbb0d5-2c44-4aaa-b5de-209b0cafc530
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538575807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2538575807
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1465077631
Short name T293
Test name
Test status
Simulation time 1261073037 ps
CPU time 3.52 seconds
Started Feb 04 03:21:20 PM PST 24
Finished Feb 04 03:21:25 PM PST 24
Peak memory 210148 kb
Host smart-e739ba4d-0e09-4223-908a-8b5acc17ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465077631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1465077631
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3644025462
Short name T578
Test name
Test status
Simulation time 106656882 ps
CPU time 3.37 seconds
Started Feb 04 03:21:10 PM PST 24
Finished Feb 04 03:21:18 PM PST 24
Peak memory 207524 kb
Host smart-e28a22e1-7c5d-4bce-a83f-fcb1d6ad6ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644025462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3644025462
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2002877103
Short name T102
Test name
Test status
Simulation time 400340895 ps
CPU time 7.26 seconds
Started Feb 04 03:21:23 PM PST 24
Finished Feb 04 03:21:32 PM PST 24
Peak memory 223044 kb
Host smart-da3e7904-0ce9-4bb8-9161-9da15898be36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002877103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2002877103
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2282565476
Short name T344
Test name
Test status
Simulation time 3483480725 ps
CPU time 37.38 seconds
Started Feb 04 03:21:19 PM PST 24
Finished Feb 04 03:21:57 PM PST 24
Peak memory 223116 kb
Host smart-5a3b5b02-e2f8-43db-baa4-ba7e0008a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282565476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2282565476
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2666048017
Short name T148
Test name
Test status
Simulation time 53858726 ps
CPU time 0.73 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:28 PM PST 24
Peak memory 206464 kb
Host smart-f56bc1c7-6631-408c-bf64-aa10a347cbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666048017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2666048017
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.736862437
Short name T69
Test name
Test status
Simulation time 1439168808 ps
CPU time 3.1 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:31 PM PST 24
Peak memory 219448 kb
Host smart-a65c4a16-5f56-4c7b-90b0-37baf68d1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736862437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.736862437
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1274103021
Short name T1039
Test name
Test status
Simulation time 1755776891 ps
CPU time 3.33 seconds
Started Feb 04 03:21:23 PM PST 24
Finished Feb 04 03:21:28 PM PST 24
Peak memory 209732 kb
Host smart-2d731778-691f-4aa6-bdf0-7266d702a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274103021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1274103021
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3993603280
Short name T789
Test name
Test status
Simulation time 785012815 ps
CPU time 4.97 seconds
Started Feb 04 03:21:27 PM PST 24
Finished Feb 04 03:21:36 PM PST 24
Peak memory 220924 kb
Host smart-165cb0b0-5c36-40d0-b676-a1af47603f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993603280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3993603280
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1600549564
Short name T267
Test name
Test status
Simulation time 2791254912 ps
CPU time 9.07 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:36 PM PST 24
Peak memory 211804 kb
Host smart-ef003d0d-a805-4dca-a3fc-a4d1fea7405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600549564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1600549564
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3856513284
Short name T835
Test name
Test status
Simulation time 106615975 ps
CPU time 4.08 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:27 PM PST 24
Peak memory 220656 kb
Host smart-a3422356-936d-474c-adaa-a14ea8550614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856513284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3856513284
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2421647138
Short name T620
Test name
Test status
Simulation time 1121510127 ps
CPU time 11.84 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:40 PM PST 24
Peak memory 208068 kb
Host smart-5a1d99df-ed2b-4ccb-bb82-6c0a403ff18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421647138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2421647138
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4173690606
Short name T594
Test name
Test status
Simulation time 981890839 ps
CPU time 7.46 seconds
Started Feb 04 03:21:20 PM PST 24
Finished Feb 04 03:21:28 PM PST 24
Peak memory 208296 kb
Host smart-4421b29e-2ee1-4e72-9628-63c1fdd7619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173690606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4173690606
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2056317095
Short name T961
Test name
Test status
Simulation time 104250602 ps
CPU time 2.93 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:26 PM PST 24
Peak memory 209160 kb
Host smart-52f0a973-2104-4ecd-8df7-579b0f3f2447
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056317095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2056317095
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2414820209
Short name T564
Test name
Test status
Simulation time 2780369624 ps
CPU time 14.1 seconds
Started Feb 04 03:21:25 PM PST 24
Finished Feb 04 03:21:42 PM PST 24
Peak memory 208740 kb
Host smart-9b49ea30-35c5-483a-a5f4-be84485e5c0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414820209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2414820209
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.112643591
Short name T333
Test name
Test status
Simulation time 93627962 ps
CPU time 3.39 seconds
Started Feb 04 03:21:24 PM PST 24
Finished Feb 04 03:21:29 PM PST 24
Peak memory 207116 kb
Host smart-2b5dd046-3cdd-4de0-b9c8-aaa3b6b5858a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112643591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.112643591
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3287645631
Short name T758
Test name
Test status
Simulation time 122734347 ps
CPU time 2.75 seconds
Started Feb 04 03:21:20 PM PST 24
Finished Feb 04 03:21:24 PM PST 24
Peak memory 209260 kb
Host smart-fc8e2bf2-44bb-48d8-bed9-a49ff7bab13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287645631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3287645631
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3985995121
Short name T575
Test name
Test status
Simulation time 233100820 ps
CPU time 5.09 seconds
Started Feb 04 03:21:24 PM PST 24
Finished Feb 04 03:21:30 PM PST 24
Peak memory 207944 kb
Host smart-40c449a1-222c-43d3-91a6-6e0fcd3f8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985995121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3985995121
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.463202760
Short name T966
Test name
Test status
Simulation time 498929826 ps
CPU time 15.42 seconds
Started Feb 04 03:21:23 PM PST 24
Finished Feb 04 03:21:41 PM PST 24
Peak memory 215368 kb
Host smart-8d006f78-bece-4a12-ab45-e045e168a3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463202760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.463202760
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.259005553
Short name T664
Test name
Test status
Simulation time 148275630 ps
CPU time 5.92 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:30 PM PST 24
Peak memory 219352 kb
Host smart-ac9abaf1-9fab-4583-a0b0-053181e693ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259005553 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.259005553
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1610783777
Short name T294
Test name
Test status
Simulation time 133954739 ps
CPU time 5.36 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:30 PM PST 24
Peak memory 208660 kb
Host smart-72826166-f76f-4d7d-b64d-7f73a5ee5a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610783777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1610783777
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.64419042
Short name T35
Test name
Test status
Simulation time 353945319 ps
CPU time 2.77 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:25 PM PST 24
Peak memory 210316 kb
Host smart-df8cf87f-e552-42cc-9c8d-9a6612ddb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64419042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.64419042
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1516000214
Short name T583
Test name
Test status
Simulation time 35254299 ps
CPU time 0.77 seconds
Started Feb 04 03:21:42 PM PST 24
Finished Feb 04 03:21:44 PM PST 24
Peak memory 206472 kb
Host smart-0708c811-157d-422d-90eb-edee0940c427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516000214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1516000214
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3445935799
Short name T398
Test name
Test status
Simulation time 190017656 ps
CPU time 3.66 seconds
Started Feb 04 03:21:26 PM PST 24
Finished Feb 04 03:21:34 PM PST 24
Peak memory 214784 kb
Host smart-fe3fa7ac-f63d-44fc-ab8d-80097c9d6a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445935799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3445935799
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1942658524
Short name T9
Test name
Test status
Simulation time 81689010 ps
CPU time 2.71 seconds
Started Feb 04 03:21:28 PM PST 24
Finished Feb 04 03:21:35 PM PST 24
Peak memory 210704 kb
Host smart-532e6dc8-99bb-4d0e-a118-f376af79ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942658524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1942658524
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2061016104
Short name T642
Test name
Test status
Simulation time 779557490 ps
CPU time 16.52 seconds
Started Feb 04 03:21:28 PM PST 24
Finished Feb 04 03:21:50 PM PST 24
Peak memory 208752 kb
Host smart-094c55b4-8cf2-4d6a-b101-21ab40408af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061016104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2061016104
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2825567480
Short name T96
Test name
Test status
Simulation time 221548671 ps
CPU time 5.24 seconds
Started Feb 04 03:21:30 PM PST 24
Finished Feb 04 03:21:39 PM PST 24
Peak memory 214800 kb
Host smart-edd43b54-a9cc-4f9c-aaed-c554a512cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825567480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2825567480
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2748849151
Short name T1058
Test name
Test status
Simulation time 314174026 ps
CPU time 2.86 seconds
Started Feb 04 03:21:29 PM PST 24
Finished Feb 04 03:21:37 PM PST 24
Peak memory 206632 kb
Host smart-30093eaf-2dce-4ac2-8222-6d11fa04dd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748849151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2748849151
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1709816582
Short name T327
Test name
Test status
Simulation time 369565791 ps
CPU time 9.55 seconds
Started Feb 04 03:21:29 PM PST 24
Finished Feb 04 03:21:43 PM PST 24
Peak memory 210100 kb
Host smart-7c0167dd-ea3e-4507-b4df-9d47c971bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709816582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1709816582
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2627680647
Short name T204
Test name
Test status
Simulation time 162742955 ps
CPU time 3.77 seconds
Started Feb 04 03:21:22 PM PST 24
Finished Feb 04 03:21:27 PM PST 24
Peak memory 208908 kb
Host smart-f6f9f253-4b5b-4312-a8d2-a1cf8af4e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627680647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2627680647
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1720230771
Short name T573
Test name
Test status
Simulation time 1381541103 ps
CPU time 16.49 seconds
Started Feb 04 03:21:23 PM PST 24
Finished Feb 04 03:21:41 PM PST 24
Peak memory 208220 kb
Host smart-857a0b2d-23f4-4a69-8391-94e3c7cea8d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720230771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1720230771
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2597132535
Short name T262
Test name
Test status
Simulation time 59360085 ps
CPU time 3.01 seconds
Started Feb 04 03:21:24 PM PST 24
Finished Feb 04 03:21:28 PM PST 24
Peak memory 208812 kb
Host smart-d0eddcfa-4e19-4223-9f71-441d5e0adee2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597132535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2597132535
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4003642192
Short name T210
Test name
Test status
Simulation time 36125732 ps
CPU time 2.5 seconds
Started Feb 04 03:21:27 PM PST 24
Finished Feb 04 03:21:34 PM PST 24
Peak memory 207152 kb
Host smart-8fa2dcee-6d3c-4e18-9cf9-cfb02f0f5177
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003642192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4003642192
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.764403077
Short name T136
Test name
Test status
Simulation time 1712678890 ps
CPU time 11.06 seconds
Started Feb 04 03:21:28 PM PST 24
Finished Feb 04 03:21:44 PM PST 24
Peak memory 210240 kb
Host smart-85fefa69-3e65-411c-952c-48660d9e71f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764403077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.764403077
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2258114771
Short name T197
Test name
Test status
Simulation time 622103125 ps
CPU time 4.08 seconds
Started Feb 04 03:21:26 PM PST 24
Finished Feb 04 03:21:34 PM PST 24
Peak memory 208560 kb
Host smart-3a19cda6-fc9e-4915-b3d2-91031e03ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258114771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2258114771
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1713115234
Short name T707
Test name
Test status
Simulation time 236629816 ps
CPU time 11.08 seconds
Started Feb 04 03:21:29 PM PST 24
Finished Feb 04 03:21:45 PM PST 24
Peak memory 221556 kb
Host smart-e2dc6976-47eb-4c4c-9847-da26dd07e256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713115234 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1713115234
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1591630058
Short name T1064
Test name
Test status
Simulation time 238826294 ps
CPU time 5.32 seconds
Started Feb 04 03:21:29 PM PST 24
Finished Feb 04 03:21:39 PM PST 24
Peak memory 210228 kb
Host smart-c2ff0be2-97eb-420b-ae05-85d1f689f4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591630058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1591630058
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3149198623
Short name T56
Test name
Test status
Simulation time 425699918 ps
CPU time 1.92 seconds
Started Feb 04 03:21:27 PM PST 24
Finished Feb 04 03:21:34 PM PST 24
Peak memory 209896 kb
Host smart-0041962c-d3ae-4823-9fcb-d4ffb764b9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149198623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3149198623
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.656110120
Short name T100
Test name
Test status
Simulation time 13117553 ps
CPU time 0.91 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:45 PM PST 24
Peak memory 206408 kb
Host smart-0f8d3b35-c268-4b73-9bb8-8a9895113777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656110120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.656110120
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.328179282
Short name T383
Test name
Test status
Simulation time 72619039 ps
CPU time 3.12 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:47 PM PST 24
Peak memory 214852 kb
Host smart-f3d90f7a-2373-40cc-9f15-aea86699573c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328179282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.328179282
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1530706814
Short name T21
Test name
Test status
Simulation time 88716652 ps
CPU time 4.01 seconds
Started Feb 04 03:21:49 PM PST 24
Finished Feb 04 03:21:56 PM PST 24
Peak memory 223336 kb
Host smart-47e69c47-fdd3-4896-b06a-8f1e5c7d2952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530706814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1530706814
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2988808916
Short name T1082
Test name
Test status
Simulation time 176544831 ps
CPU time 5.56 seconds
Started Feb 04 03:21:42 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 210336 kb
Host smart-c35337b7-3d78-4d1c-9168-9f82be0ffec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988808916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2988808916
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.606539551
Short name T275
Test name
Test status
Simulation time 741030726 ps
CPU time 5.89 seconds
Started Feb 04 03:21:41 PM PST 24
Finished Feb 04 03:21:48 PM PST 24
Peak memory 209028 kb
Host smart-a918b45c-74e4-4315-ad2c-5b916ebdeb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606539551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.606539551
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3795905150
Short name T15
Test name
Test status
Simulation time 270967765 ps
CPU time 3.15 seconds
Started Feb 04 03:21:39 PM PST 24
Finished Feb 04 03:21:43 PM PST 24
Peak memory 209780 kb
Host smart-3ed91612-c18a-479e-ab32-e9a56828135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795905150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3795905150
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.4163670476
Short name T397
Test name
Test status
Simulation time 459614655 ps
CPU time 5.01 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 214784 kb
Host smart-f6588219-b049-4b19-b641-bc08737f8182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163670476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4163670476
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.975336797
Short name T962
Test name
Test status
Simulation time 395307105 ps
CPU time 3.84 seconds
Started Feb 04 03:21:41 PM PST 24
Finished Feb 04 03:21:46 PM PST 24
Peak memory 208804 kb
Host smart-eb405c77-2b19-4be9-b78c-0c73d6c533b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975336797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.975336797
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.833554524
Short name T862
Test name
Test status
Simulation time 70566395 ps
CPU time 3.38 seconds
Started Feb 04 03:21:40 PM PST 24
Finished Feb 04 03:21:45 PM PST 24
Peak memory 208236 kb
Host smart-bb81ce72-1d60-4a4e-abf2-733c2cc7f113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833554524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.833554524
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1928850133
Short name T587
Test name
Test status
Simulation time 814481366 ps
CPU time 6.93 seconds
Started Feb 04 03:21:40 PM PST 24
Finished Feb 04 03:21:48 PM PST 24
Peak memory 209108 kb
Host smart-c6d7925c-4c0f-4091-9c0c-9d1805643599
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928850133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1928850133
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.241523870
Short name T793
Test name
Test status
Simulation time 698158197 ps
CPU time 5.98 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:50 PM PST 24
Peak memory 209060 kb
Host smart-f9fae48b-a282-4c58-8418-68a0b6ce9824
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241523870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.241523870
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1811363201
Short name T851
Test name
Test status
Simulation time 543343538 ps
CPU time 9 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:54 PM PST 24
Peak memory 210204 kb
Host smart-c1bece42-3cc1-4d09-9c07-87f9d6c02d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811363201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1811363201
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3322065327
Short name T200
Test name
Test status
Simulation time 585536904 ps
CPU time 4.07 seconds
Started Feb 04 03:21:40 PM PST 24
Finished Feb 04 03:21:45 PM PST 24
Peak memory 207148 kb
Host smart-55d01745-76ec-4a50-8f1a-e96a3f5e5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322065327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3322065327
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2159232692
Short name T1055
Test name
Test status
Simulation time 189805569 ps
CPU time 9.14 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:53 PM PST 24
Peak memory 222420 kb
Host smart-d7db1637-e3df-4731-b4fe-9db98cdc2ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159232692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2159232692
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1300119726
Short name T769
Test name
Test status
Simulation time 63740870 ps
CPU time 3.83 seconds
Started Feb 04 03:21:43 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 214944 kb
Host smart-5236796b-3fa3-466f-947d-e9be32cb5607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300119726 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1300119726
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2048380552
Short name T1088
Test name
Test status
Simulation time 130087557 ps
CPU time 3.95 seconds
Started Feb 04 03:21:44 PM PST 24
Finished Feb 04 03:21:49 PM PST 24
Peak memory 207768 kb
Host smart-7f904b26-6eb7-4fbb-8462-a36e17da1512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048380552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2048380552
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1024624648
Short name T635
Test name
Test status
Simulation time 167209442 ps
CPU time 3.13 seconds
Started Feb 04 03:21:44 PM PST 24
Finished Feb 04 03:21:48 PM PST 24
Peak memory 210688 kb
Host smart-cb523e31-d116-4ed1-8d69-f17593e32eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024624648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1024624648
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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