Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	76	1			T2	1		T14	1		T90	3
auto[OpGenId]	20	1			T40	1		T42	1		T191	1
auto[OpGenSwOut]	28	1			T90	1		T106	1		T64	2
auto[OpGenHwOut]	37	1			T2	1		T4	1		T5	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1587	1			T2	2		T37	2		T6	90
auto[StInit]	157	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	60	1			T13	1		T47	1		T40	2
auto[StOwnerIntKey]	41	1			T2	1		T14	1		T32	1
auto[StOwnerKey]	33	1			T42	1		T24	1		T53	1
auto[StDisabled]	373	1			T2	1		T13	5		T37	10
auto[StInvalid]	42	1			T31	1		T36	1		T54	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3225

1

T1

1

T2

4

T3

2

auto[1]

161

1

T2

2

T14

1

T4

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1576	1			T2	2		T37	2		T6	90
auto[StReset]	auto[1]	11	1			T7	1		T192	1		T44	1
auto[StInit]	auto[0]	75	1			T3	1		T89	1		T47	2
auto[StInit]	auto[1]	82	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	auto[0]	35	1			T13	1		T47	1		T48	1
auto[StCreatorRootKey]	auto[1]	25	1			T40	2		T41	1		T193	1
auto[StOwnerIntKey]	auto[0]	22	1			T32	1		T51	1		T194	1
auto[StOwnerIntKey]	auto[1]	19	1			T2	1		T14	1		T40	1
auto[StOwnerKey]	auto[0]	28	1			T24	1		T53	1		T30	1
auto[StOwnerKey]	auto[1]	5	1			T42	1		T27	1		T56	1
auto[StDisabled]	auto[0]	354	1			T2	1		T13	5		T37	10
auto[StDisabled]	auto[1]	19	1			T195	1		T196	1		T197	1
auto[StInvalid]	auto[0]	42	1			T31	1		T36	1		T54	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpAdvance] , auto[OpGenId]]	--	--	2
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	10	1			T7	1		T192	1		T44	1
auto[StReset]	auto[OpGenSwOut]	1	1			T62	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	34	1			T90	3		T40	1		T136	1
auto[StInit]	auto[OpGenId]	11	1			T42	1		T191	1		T198	1
auto[StInit]	auto[OpGenSwOut]	18	1			T90	1		T106	1		T64	2
auto[StInit]	auto[OpGenHwOut]	19	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T40	1		T41	1		T193	1
auto[StCreatorRootKey]	auto[OpGenId]	5	1			T40	1		T67	1		T199	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T200	1		T201	1		T199	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T135	1		T202	1		T203	1
auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T2	1		T14	1		T40	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T141	1		T204	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T205	1		T206	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T207	1		T199	1		T208	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T208	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	4	1			T42	1		T27	1		T56	1
auto[StDisabled]	auto[OpAdvance]	11	1			T195	1		T197	1		T209	1
auto[StDisabled]	auto[OpGenId]	2	1			T196	1		T210	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T199	1		T45	1		T143	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T210	1		T211	1		T212	1