Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10989

1

T1

8

T2

12

T3

4

auto[Attestation]

7749

1

T1

9

T2

12

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2724	1			T1	1		T2	3		T3	1
auto[Aes]	3338	1			T1	6		T2	6		T3	1
auto[Kmac]	3364	1			T1	1		T2	5		T3	1
auto[Otbn]	3429	1			T1	3		T2	5		T13	16

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7572	1			T1	8		T2	9		T3	1
auto[OpGenId]	5883	1			T1	6		T2	5		T3	2
auto[OpGenSwOut]	5853	1			T1	7		T2	12		T3	3
auto[OpGenHwOut]	7002	1			T1	4		T2	7		T12	15
auto[OpDisable]	126	1			T13	2		T39	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10035

1

T1

11

T2

22

T3

1

auto[OpDoneFail]

16401

1

T1

14

T2

11

T3

5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6145	1			T1	1		T2	9		T3	5
auto[StInit]	4120	1			T1	3		T2	7		T3	1
auto[StCreatorRootKey]	3018	1			T1	2		T2	4		T12	2
auto[StOwnerIntKey]	2559	1			T1	6		T2	7		T12	2
auto[StOwnerKey]	2318	1			T1	1		T2	6		T12	2
auto[StDisabled]	7357	1			T1	12		T12	7		T13	44
auto[StInvalid]	919	1			T31	20		T36	20		T54	13

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	321	1			T2	1		T3	1		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	122	1			T2	1		T13	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T71	1		T37	2		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T13	1		T71	1		T37	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T16	1		T37	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	207	1			T13	3		T17	1		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	19	1			T36	1		T179	2		T180	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	303	1			T3	1		T13	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	97	1			T70	1		T43	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	70	1			T13	1		T37	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T37	2		T52	1		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T2	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	193	1			T1	2		T13	3		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	26	1			T31	1		T36	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	329	1			T2	2		T13	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	99	1			T13	1		T18	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T13	1		T47	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T2	1		T13	2		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T13	1		T16	1		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	203	1			T13	2		T16	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	26	1			T31	2		T54	2		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	299	1			T13	2		T17	1		T70	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T13	1		T70	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T43	1		T182	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T1	1		T37	4		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	45	1			T52	1		T47	2		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	228	1			T1	1		T13	2		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T31	1		T36	1		T179	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T13	2		T52	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	119	1			T13	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T16	1		T17	1		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T1	1		T37	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T16	1		T52	2		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	190	1			T16	2		T17	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	31	1			T179	1		T180	4		T77	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T13	1		T37	3		T47	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T1	1		T13	1		T37	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T79	2		T52	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	60	1			T2	1		T14	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	54	1			T2	2		T70	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	214	1			T1	1		T13	3		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T54	1		T179	1		T180	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	86	1			T13	3		T37	4		T47	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T3	1		T13	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T2	1		T183	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	56	1			T52	2		T47	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T37	1		T42	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	190	1			T13	1		T39	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T36	1		T54	1		T179	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	82	1			T13	1		T31	2		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	95	1			T22	1		T47	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T2	1		T13	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T70	1		T37	2		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T2	1		T17	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	194	1			T13	1		T37	4		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T185	1		T180	3		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	264	1			T13	1		T39	1		T37	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	116	1			T17	1		T18	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T39	1		T47	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T2	1		T13	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T16	1		T37	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	152	1			T16	1		T70	3		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T31	1		T180	1		T187	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	447	1			T2	1		T13	1		T37	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T18	1		T70	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T31	1		T43	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T39	1		T63	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T52	2		T93	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	264	1			T39	1		T43	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	20	1			T179	1		T180	2		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	417	1			T12	7		T13	1		T72	11
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	143	1			T12	1		T15	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T14	1		T15	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T15	1		T37	2		T182	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T12	1		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	250	1			T1	1		T12	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T77	1		T188	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	443	1			T2	1		T13	2		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T2	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T13	1		T181	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T1	1		T13	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T37	1		T47	1		T42	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	278	1			T16	1		T183	2		T52	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	31	1			T31	3		T36	1		T179	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T37	1		T42	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T13	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	60	1			T37	2		T182	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	51	1			T47	1		T40	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T13	2		T70	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	158	1			T13	1		T16	2		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	28	1			T36	1		T179	1		T185	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T37	3		T90	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T1	1		T2	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T37	1		T79	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T182	1		T181	2		T117	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T70	1		T37	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	282	1			T1	1		T13	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T31	2		T36	1		T180	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	52	1			T31	1		T37	2		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T18	1		T39	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	116	1			T12	1		T13	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T2	1		T12	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	75	1			T189	1		T37	2		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	278	1			T12	2		T13	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T31	1		T54	1		T179	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T37	3		T52	1		T54	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	163	1			T13	1		T37	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T13	1		T14	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T2	1		T13	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	113	1			T13	1		T47	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	269	1			T16	2		T43	1		T37	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	24	1			T31	1		T36	2		T185	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	192	1			T13	1		T16	1		T71	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	680	1			T2	2		T3	1		T13	7
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	190	1			T2	1		T13	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	629	1			T1	2		T3	1		T13	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T2	1		T13	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	675	1			T2	2		T13	5		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T1	1		T43	1		T37	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	689	1			T1	1		T13	5		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	168	1			T1	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	421	1			T13	3		T14	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	182	1			T2	3		T14	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	439	1			T1	2		T13	5		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T2	1		T183	1		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	434	1			T3	1		T13	5		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T2	2		T13	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	410	1			T13	2		T31	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T2	1		T13	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	576	1			T13	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	255	1			T39	1		T43	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	865	1			T2	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	284	1			T12	1		T14	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	846	1			T1	1		T12	10		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T1	1		T13	2		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	885	1			T2	2		T13	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	162	1			T13	2		T70	1		T37	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	352	1			T13	2		T16	2		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	256	1			T70	1		T37	1		T182	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	522	1			T1	2		T2	1		T13	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	253	1			T2	1		T12	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	499	1			T12	2		T13	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	280	1			T2	1		T13	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	529	1			T13	2		T16	2		T31	1