Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30381

1

T1

30

T2

38

T3

6

auto[1]

262

1

T17

5

T118

1

T213

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30387	1			T1	30		T2	38		T3	6
auto[134217728:268435455]	6	1			T245	1		T272	1		T414	1
auto[268435456:402653183]	13	1			T17	2		T213	1		T415	2
auto[402653184:536870911]	7	1			T245	1		T331	1		T416	1
auto[536870912:671088639]	7	1			T213	1		T217	1		T314	1
auto[671088640:805306367]	4	1			T17	1		T331	1		T364	1
auto[805306368:939524095]	5	1			T256	1		T394	1		T271	1
auto[939524096:1073741823]	11	1			T393	1		T417	1		T418	1
auto[1073741824:1207959551]	7	1			T213	1		T245	1		T271	1
auto[1207959552:1342177279]	8	1			T242	1		T249	1		T394	1
auto[1342177280:1476395007]	8	1			T213	1		T256	1		T415	1
auto[1476395008:1610612735]	12	1			T17	1		T394	2		T367	1
auto[1610612736:1744830463]	8	1			T17	1		T415	1		T419	1
auto[1744830464:1879048191]	9	1			T245	1		T314	1		T272	1
auto[1879048192:2013265919]	8	1			T214	1		T415	1		T271	1
auto[2013265920:2147483647]	7	1			T246	1		T367	1		T420	1
auto[2147483648:2281701375]	2	1			T272	1		T421	1		-	-
auto[2281701376:2415919103]	13	1			T213	1		T366	1		T214	1
auto[2415919104:2550136831]	9	1			T213	1		T394	1		T246	1
auto[2550136832:2684354559]	7	1			T245	1		T326	1		T419	1
auto[2684354560:2818572287]	6	1			T314	1		T303	1		T357	1
auto[2818572288:2952790015]	7	1			T118	1		T393	1		T415	1
auto[2952790016:3087007743]	7	1			T213	1		T367	1		T303	1
auto[3087007744:3221225471]	12	1			T213	1		T256	1		T246	1
auto[3221225472:3355443199]	8	1			T245	1		T256	1		T415	1
auto[3355443200:3489660927]	11	1			T217	1		T245	1		T214	1
auto[3489660928:3623878655]	7	1			T366	1		T415	1		T314	1
auto[3623878656:3758096383]	6	1			T393	1		T245	1		T314	1
auto[3758096384:3892314111]	10	1			T213	1		T242	1		T272	1
auto[3892314112:4026531839]	9	1			T393	1		T245	1		T314	1
auto[4026531840:4160749567]	9	1			T271	2		T314	1		T420	1
auto[4160749568:4294967295]	13	1			T213	1		T415	1		T314	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30381	1			T1	30		T2	38		T3	6
auto[0:134217727]	auto[1]	6	1			T393	1		T245	1		T359	1
auto[134217728:268435455]	auto[1]	6	1			T245	1		T272	1		T414	1
auto[268435456:402653183]	auto[1]	13	1			T17	2		T213	1		T415	2
auto[402653184:536870911]	auto[1]	7	1			T245	1		T331	1		T416	1
auto[536870912:671088639]	auto[1]	7	1			T213	1		T217	1		T314	1
auto[671088640:805306367]	auto[1]	4	1			T17	1		T331	1		T364	1
auto[805306368:939524095]	auto[1]	5	1			T256	1		T394	1		T271	1
auto[939524096:1073741823]	auto[1]	11	1			T393	1		T417	1		T418	1
auto[1073741824:1207959551]	auto[1]	7	1			T213	1		T245	1		T271	1
auto[1207959552:1342177279]	auto[1]	8	1			T242	1		T249	1		T394	1
auto[1342177280:1476395007]	auto[1]	8	1			T213	1		T256	1		T415	1
auto[1476395008:1610612735]	auto[1]	12	1			T17	1		T394	2		T367	1
auto[1610612736:1744830463]	auto[1]	8	1			T17	1		T415	1		T419	1
auto[1744830464:1879048191]	auto[1]	9	1			T245	1		T314	1		T272	1
auto[1879048192:2013265919]	auto[1]	8	1			T214	1		T415	1		T271	1
auto[2013265920:2147483647]	auto[1]	7	1			T246	1		T367	1		T420	1
auto[2147483648:2281701375]	auto[1]	2	1			T272	1		T421	1		-	-
auto[2281701376:2415919103]	auto[1]	13	1			T213	1		T366	1		T214	1
auto[2415919104:2550136831]	auto[1]	9	1			T213	1		T394	1		T246	1
auto[2550136832:2684354559]	auto[1]	7	1			T245	1		T326	1		T419	1
auto[2684354560:2818572287]	auto[1]	6	1			T314	1		T303	1		T357	1
auto[2818572288:2952790015]	auto[1]	7	1			T118	1		T393	1		T415	1
auto[2952790016:3087007743]	auto[1]	7	1			T213	1		T367	1		T303	1
auto[3087007744:3221225471]	auto[1]	12	1			T213	1		T256	1		T246	1
auto[3221225472:3355443199]	auto[1]	8	1			T245	1		T256	1		T415	1
auto[3355443200:3489660927]	auto[1]	11	1			T217	1		T245	1		T214	1
auto[3489660928:3623878655]	auto[1]	7	1			T366	1		T415	1		T314	1
auto[3623878656:3758096383]	auto[1]	6	1			T393	1		T245	1		T314	1
auto[3758096384:3892314111]	auto[1]	10	1			T213	1		T242	1		T272	1
auto[3892314112:4026531839]	auto[1]	9	1			T393	1		T245	1		T314	1
auto[4026531840:4160749567]	auto[1]	9	1			T271	2		T314	1		T420	1
auto[4160749568:4294967295]	auto[1]	13	1			T213	1		T415	1		T314	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1456

1

T2

3

T3

1

T13

5

auto[1]

1731

1

T1

3

T2

5

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T14	1		T5	1		T90	1
auto[134217728:268435455]	88	1			T3	1		T39	1		T70	1
auto[268435456:402653183]	91	1			T31	1		T37	1		T47	2
auto[402653184:536870911]	113	1			T13	1		T39	2		T22	1
auto[536870912:671088639]	102	1			T13	1		T18	1		T22	1
auto[671088640:805306367]	97	1			T2	1		T14	2		T39	1
auto[805306368:939524095]	102	1			T13	2		T37	1		T182	1
auto[939524096:1073741823]	95	1			T37	1		T52	1		T47	1
auto[1073741824:1207959551]	91	1			T5	1		T37	1		T47	1
auto[1207959552:1342177279]	106	1			T13	2		T70	1		T47	6
auto[1342177280:1476395007]	97	1			T14	1		T37	1		T52	2
auto[1476395008:1610612735]	104	1			T18	1		T4	1		T37	1
auto[1610612736:1744830463]	109	1			T52	1		T50	1		T47	2
auto[1744830464:1879048191]	100	1			T17	1		T47	2		T118	2
auto[1879048192:2013265919]	93	1			T70	1		T4	1		T47	1
auto[2013265920:2147483647]	102	1			T5	1		T47	2		T95	2
auto[2147483648:2281701375]	95	1			T1	1		T2	1		T13	1
auto[2281701376:2415919103]	105	1			T18	1		T31	1		T4	1
auto[2415919104:2550136831]	105	1			T2	1		T13	3		T16	1
auto[2550136832:2684354559]	89	1			T17	1		T18	1		T5	1
auto[2684354560:2818572287]	98	1			T2	1		T13	2		T18	1
auto[2818572288:2952790015]	95	1			T13	1		T17	1		T37	1
auto[2952790016:3087007743]	94	1			T43	1		T47	1		T42	1
auto[3087007744:3221225471]	91	1			T2	1		T13	1		T18	1
auto[3221225472:3355443199]	90	1			T14	1		T31	1		T70	1
auto[3355443200:3489660927]	104	1			T1	1		T13	1		T16	1
auto[3489660928:3623878655]	84	1			T2	1		T13	1		T17	1
auto[3623878656:3758096383]	95	1			T13	2		T52	1		T47	2
auto[3758096384:3892314111]	101	1			T13	1		T14	1		T37	2
auto[3892314112:4026531839]	104	1			T2	1		T16	1		T5	1
auto[4026531840:4160749567]	109	1			T1	1		T52	1		T47	2
auto[4160749568:4294967295]	113	1			T2	1		T3	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T41	1		T118	1		T42	2
auto[0:134217727]	auto[1]	69	1			T14	1		T5	1		T90	1
auto[134217728:268435455]	auto[0]	49	1			T3	1		T39	1		T70	1
auto[134217728:268435455]	auto[1]	39	1			T181	1		T118	1		T422	1
auto[268435456:402653183]	auto[0]	46	1			T31	1		T47	2		T23	1
auto[268435456:402653183]	auto[1]	45	1			T37	1		T42	1		T135	1
auto[402653184:536870911]	auto[0]	44	1			T13	1		T39	1		T22	1
auto[402653184:536870911]	auto[1]	69	1			T39	1		T37	2		T90	1
auto[536870912:671088639]	auto[0]	55	1			T18	1		T22	1		T37	1
auto[536870912:671088639]	auto[1]	47	1			T13	1		T37	2		T52	1
auto[671088640:805306367]	auto[0]	38	1			T14	1		T39	1		T181	1
auto[671088640:805306367]	auto[1]	59	1			T2	1		T14	1		T37	1
auto[805306368:939524095]	auto[0]	47	1			T13	2		T182	1		T47	1
auto[805306368:939524095]	auto[1]	55	1			T37	1		T181	1		T76	1
auto[939524096:1073741823]	auto[0]	42	1			T47	1		T51	1		T42	1
auto[939524096:1073741823]	auto[1]	53	1			T37	1		T52	1		T40	1
auto[1073741824:1207959551]	auto[0]	50	1			T5	1		T37	1		T47	1
auto[1073741824:1207959551]	auto[1]	41	1			T40	2		T42	1		T25	1
auto[1207959552:1342177279]	auto[0]	48	1			T47	2		T42	1		T193	1
auto[1207959552:1342177279]	auto[1]	58	1			T13	2		T70	1		T47	4
auto[1342177280:1476395007]	auto[0]	43	1			T37	1		T47	1		T95	1
auto[1342177280:1476395007]	auto[1]	54	1			T14	1		T52	2		T93	1
auto[1476395008:1610612735]	auto[0]	52	1			T18	1		T37	1		T191	1
auto[1476395008:1610612735]	auto[1]	52	1			T4	1		T106	1		T216	1
auto[1610612736:1744830463]	auto[0]	45	1			T47	2		T90	1		T51	1
auto[1610612736:1744830463]	auto[1]	64	1			T52	1		T50	1		T51	1
auto[1744830464:1879048191]	auto[0]	44	1			T47	1		T118	1		T42	1
auto[1744830464:1879048191]	auto[1]	56	1			T17	1		T47	1		T118	1
auto[1879048192:2013265919]	auto[0]	43	1			T70	1		T4	1		T47	1
auto[1879048192:2013265919]	auto[1]	50	1			T42	2		T191	1		T55	1
auto[2013265920:2147483647]	auto[0]	42	1			T5	1		T47	2		T95	1
auto[2013265920:2147483647]	auto[1]	60	1			T95	1		T119	1		T42	1
auto[2147483648:2281701375]	auto[0]	39	1			T18	1		T31	1		T79	1
auto[2147483648:2281701375]	auto[1]	56	1			T1	1		T2	1		T13	1
auto[2281701376:2415919103]	auto[0]	52	1			T18	1		T31	1		T4	1
auto[2281701376:2415919103]	auto[1]	53	1			T93	1		T47	2		T40	1
auto[2415919104:2550136831]	auto[0]	41	1			T2	1		T13	2		T37	1
auto[2415919104:2550136831]	auto[1]	64	1			T13	1		T16	1		T43	1
auto[2550136832:2684354559]	auto[0]	46	1			T18	1		T5	1		T79	1
auto[2550136832:2684354559]	auto[1]	43	1			T17	1		T37	2		T40	1
auto[2684354560:2818572287]	auto[0]	47	1			T2	1		T18	1		T70	1
auto[2684354560:2818572287]	auto[1]	51	1			T13	2		T39	1		T37	1
auto[2818572288:2952790015]	auto[0]	45	1			T47	2		T40	2		T76	1
auto[2818572288:2952790015]	auto[1]	50	1			T13	1		T17	1		T37	1
auto[2952790016:3087007743]	auto[0]	31	1			T135	1		T136	1		T191	1
auto[2952790016:3087007743]	auto[1]	63	1			T43	1		T47	1		T42	1
auto[3087007744:3221225471]	auto[0]	37	1			T18	1		T37	1		T181	1
auto[3087007744:3221225471]	auto[1]	54	1			T2	1		T13	1		T89	1
auto[3221225472:3355443199]	auto[0]	52	1			T40	1		T51	2		T42	1
auto[3221225472:3355443199]	auto[1]	38	1			T14	1		T31	1		T70	1
auto[3355443200:3489660927]	auto[0]	48	1			T16	1		T118	1		T42	1
auto[3355443200:3489660927]	auto[1]	56	1			T1	1		T13	1		T93	1
auto[3489660928:3623878655]	auto[0]	34	1			T2	1		T79	1		T52	1
auto[3489660928:3623878655]	auto[1]	50	1			T13	1		T17	1		T31	1
auto[3623878656:3758096383]	auto[0]	44	1			T47	1		T90	1		T217	1
auto[3623878656:3758096383]	auto[1]	51	1			T13	2		T52	1		T47	1
auto[3758096384:3892314111]	auto[0]	52	1			T37	1		T47	2		T42	1
auto[3758096384:3892314111]	auto[1]	49	1			T13	1		T14	1		T37	1
auto[3892314112:4026531839]	auto[0]	46	1			T5	1		T41	1		T42	2
auto[3892314112:4026531839]	auto[1]	58	1			T2	1		T16	1		T52	1
auto[4026531840:4160749567]	auto[0]	45	1			T47	1		T369	1		T213	1
auto[4026531840:4160749567]	auto[1]	64	1			T1	1		T52	1		T47	1
auto[4160749568:4294967295]	auto[0]	53	1			T70	1		T4	1		T5	1
auto[4160749568:4294967295]	auto[1]	60	1			T2	1		T3	1		T16	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1465

1

T2

3

T3

2

T13

6

auto[1]

1724

1

T1

3

T2

4

T13

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T14	1		T18	1		T39	1
auto[134217728:268435455]	96	1			T13	1		T39	1		T4	1
auto[268435456:402653183]	85	1			T13	2		T16	1		T17	1
auto[402653184:536870911]	108	1			T2	1		T13	1		T18	1
auto[536870912:671088639]	99	1			T17	2		T39	1		T37	1
auto[671088640:805306367]	101	1			T13	1		T4	1		T52	2
auto[805306368:939524095]	92	1			T2	1		T18	2		T37	3
auto[939524096:1073741823]	93	1			T1	1		T16	1		T37	2
auto[1073741824:1207959551]	118	1			T13	1		T14	1		T17	1
auto[1207959552:1342177279]	93	1			T2	1		T39	1		T70	1
auto[1342177280:1476395007]	102	1			T16	1		T70	1		T47	2
auto[1476395008:1610612735]	98	1			T1	1		T14	1		T43	1
auto[1610612736:1744830463]	99	1			T16	1		T5	1		T93	1
auto[1744830464:1879048191]	97	1			T14	1		T37	1		T52	1
auto[1879048192:2013265919]	107	1			T18	1		T79	1		T47	2
auto[2013265920:2147483647]	87	1			T31	1		T37	1		T47	1
auto[2147483648:2281701375]	101	1			T18	1		T31	1		T5	1
auto[2281701376:2415919103]	92	1			T13	1		T37	1		T52	1
auto[2415919104:2550136831]	91	1			T1	1		T2	2		T13	1
auto[2550136832:2684354559]	96	1			T13	1		T37	1		T93	1
auto[2684354560:2818572287]	116	1			T3	1		T13	2		T70	2
auto[2818572288:2952790015]	105	1			T13	1		T70	1		T79	1
auto[2952790016:3087007743]	87	1			T3	1		T31	1		T4	1
auto[3087007744:3221225471]	95	1			T2	1		T13	1		T37	1
auto[3221225472:3355443199]	110	1			T13	2		T22	1		T47	2
auto[3355443200:3489660927]	107	1			T2	1		T70	1		T47	2
auto[3489660928:3623878655]	87	1			T13	2		T181	1		T51	2
auto[3623878656:3758096383]	98	1			T52	1		T47	2		T90	1
auto[3758096384:3892314111]	102	1			T39	1		T37	1		T52	1
auto[3892314112:4026531839]	102	1			T13	1		T37	1		T52	2
auto[4026531840:4160749567]	122	1			T13	1		T14	1		T31	1
auto[4160749568:4294967295]	108	1			T14	1		T18	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T18	1		T47	1		T136	1
auto[0:134217727]	auto[1]	57	1			T14	1		T39	1		T22	1
auto[134217728:268435455]	auto[0]	48	1			T39	1		T4	1		T79	1
auto[134217728:268435455]	auto[1]	48	1			T13	1		T52	1		T181	1
auto[268435456:402653183]	auto[0]	33	1			T16	1		T4	1		T52	1
auto[268435456:402653183]	auto[1]	52	1			T13	2		T17	1		T95	1
auto[402653184:536870911]	auto[0]	46	1			T2	1		T13	1		T18	1
auto[402653184:536870911]	auto[1]	62	1			T47	1		T40	1		T41	2
auto[536870912:671088639]	auto[0]	40	1			T39	1		T191	1		T229	1
auto[536870912:671088639]	auto[1]	59	1			T17	2		T37	1		T52	1
auto[671088640:805306367]	auto[0]	44	1			T52	1		T47	1		T95	1
auto[671088640:805306367]	auto[1]	57	1			T13	1		T4	1		T52	1
auto[805306368:939524095]	auto[0]	31	1			T2	1		T18	2		T90	1
auto[805306368:939524095]	auto[1]	61	1			T37	3		T52	1		T47	1
auto[939524096:1073741823]	auto[0]	47	1			T37	1		T182	1		T47	1
auto[939524096:1073741823]	auto[1]	46	1			T1	1		T16	1		T37	1
auto[1073741824:1207959551]	auto[0]	65	1			T31	1		T5	1		T181	1
auto[1073741824:1207959551]	auto[1]	53	1			T13	1		T14	1		T17	1
auto[1207959552:1342177279]	auto[0]	43	1			T39	1		T79	1		T52	2
auto[1207959552:1342177279]	auto[1]	50	1			T2	1		T70	1		T37	1
auto[1342177280:1476395007]	auto[0]	49	1			T70	1		T42	1		T55	1
auto[1342177280:1476395007]	auto[1]	53	1			T16	1		T47	2		T23	1
auto[1476395008:1610612735]	auto[0]	47	1			T52	1		T47	2		T40	1
auto[1476395008:1610612735]	auto[1]	51	1			T1	1		T14	1		T43	1
auto[1610612736:1744830463]	auto[0]	42	1			T5	1		T42	2		T19	1
auto[1610612736:1744830463]	auto[1]	57	1			T16	1		T93	1		T42	1
auto[1744830464:1879048191]	auto[0]	41	1			T37	1		T52	1		T93	1
auto[1744830464:1879048191]	auto[1]	56	1			T14	1		T118	1		T55	1
auto[1879048192:2013265919]	auto[0]	44	1			T18	1		T47	1		T76	1
auto[1879048192:2013265919]	auto[1]	63	1			T79	1		T47	1		T63	1
auto[2013265920:2147483647]	auto[0]	38	1			T47	1		T41	1		T118	1
auto[2013265920:2147483647]	auto[1]	49	1			T31	1		T37	1		T40	1
auto[2147483648:2281701375]	auto[0]	48	1			T18	1		T5	1		T90	1
auto[2147483648:2281701375]	auto[1]	53	1			T31	1		T47	2		T63	1
auto[2281701376:2415919103]	auto[0]	43	1			T37	1		T47	2		T40	1
auto[2281701376:2415919103]	auto[1]	49	1			T13	1		T52	1		T42	2
auto[2415919104:2550136831]	auto[0]	46	1			T2	1		T13	1		T5	1
auto[2415919104:2550136831]	auto[1]	45	1			T1	1		T2	1		T37	1
auto[2550136832:2684354559]	auto[0]	47	1			T47	2		T42	1		T55	1
auto[2550136832:2684354559]	auto[1]	49	1			T13	1		T37	1		T93	1
auto[2684354560:2818572287]	auto[0]	50	1			T3	1		T70	1		T5	1
auto[2684354560:2818572287]	auto[1]	66	1			T13	2		T70	1		T37	1
auto[2818572288:2952790015]	auto[0]	51	1			T70	1		T79	1		T47	1
auto[2818572288:2952790015]	auto[1]	54	1			T13	1		T89	1		T41	1
auto[2952790016:3087007743]	auto[0]	42	1			T3	1		T40	2		T41	1
auto[2952790016:3087007743]	auto[1]	45	1			T31	1		T4	1		T37	3
auto[3087007744:3221225471]	auto[0]	45	1			T13	1		T47	2		T76	1
auto[3087007744:3221225471]	auto[1]	50	1			T2	1		T37	1		T47	2
auto[3221225472:3355443199]	auto[0]	61	1			T13	1		T22	1		T47	1
auto[3221225472:3355443199]	auto[1]	49	1			T13	1		T47	1		T42	2
auto[3355443200:3489660927]	auto[0]	46	1			T70	1		T47	1		T76	1
auto[3355443200:3489660927]	auto[1]	61	1			T2	1		T47	1		T96	1
auto[3489660928:3623878655]	auto[0]	40	1			T13	1		T193	1		T186	1
auto[3489660928:3623878655]	auto[1]	47	1			T13	1		T181	1		T51	2
auto[3623878656:3758096383]	auto[0]	46	1			T42	1		T54	1		T358	1
auto[3623878656:3758096383]	auto[1]	52	1			T52	1		T47	2		T90	1
auto[3758096384:3892314111]	auto[0]	53	1			T39	1		T37	1		T118	1
auto[3758096384:3892314111]	auto[1]	49	1			T52	1		T93	1		T40	1
auto[3892314112:4026531839]	auto[0]	49	1			T13	1		T37	1		T52	1
auto[3892314112:4026531839]	auto[1]	53	1			T52	1		T47	2		T42	1
auto[4026531840:4160749567]	auto[0]	58	1			T5	1		T181	1		T47	2
auto[4026531840:4160749567]	auto[1]	64	1			T13	1		T14	1		T31	1
auto[4160749568:4294967295]	auto[0]	44	1			T18	1		T37	1		T47	1
auto[4160749568:4294967295]	auto[1]	64	1			T14	1		T43	1		T42	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1448

1

T2

3

T3

1

T13

5

auto[1]

1739

1

T1

3

T2

4

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T13	1		T18	1		T47	1
auto[134217728:268435455]	99	1			T37	1		T79	1		T181	1
auto[268435456:402653183]	103	1			T2	1		T13	2		T31	1
auto[402653184:536870911]	107	1			T13	1		T18	1		T22	1
auto[536870912:671088639]	105	1			T1	1		T2	1		T16	1
auto[671088640:805306367]	106	1			T14	1		T39	1		T41	1
auto[805306368:939524095]	96	1			T3	1		T13	2		T31	1
auto[939524096:1073741823]	114	1			T13	1		T14	1		T70	1
auto[1073741824:1207959551]	99	1			T16	1		T37	1		T52	1
auto[1207959552:1342177279]	103	1			T2	1		T13	1		T37	1
auto[1342177280:1476395007]	108	1			T70	1		T47	1		T23	2
auto[1476395008:1610612735]	111	1			T2	1		T13	1		T37	1
auto[1610612736:1744830463]	85	1			T14	1		T70	2		T37	1
auto[1744830464:1879048191]	99	1			T13	1		T17	1		T43	2
auto[1879048192:2013265919]	81	1			T2	1		T13	1		T37	1
auto[2013265920:2147483647]	104	1			T16	1		T37	1		T181	1
auto[2147483648:2281701375]	91	1			T13	1		T14	1		T31	1
auto[2281701376:2415919103]	101	1			T13	1		T14	1		T18	1
auto[2415919104:2550136831]	101	1			T2	1		T13	2		T18	1
auto[2550136832:2684354559]	91	1			T18	1		T39	1		T5	1
auto[2684354560:2818572287]	107	1			T1	1		T18	1		T4	1
auto[2818572288:2952790015]	97	1			T18	1		T52	1		T47	2
auto[2952790016:3087007743]	94	1			T47	4		T95	1		T118	1
auto[3087007744:3221225471]	97	1			T16	1		T4	1		T37	1
auto[3221225472:3355443199]	97	1			T13	1		T31	1		T47	3
auto[3355443200:3489660927]	94	1			T17	1		T5	1		T37	1
auto[3489660928:3623878655]	102	1			T3	1		T17	1		T70	1
auto[3623878656:3758096383]	97	1			T1	1		T39	1		T5	1
auto[3758096384:3892314111]	93	1			T13	1		T14	1		T37	1
auto[3892314112:4026531839]	101	1			T2	1		T17	1		T31	1
auto[4026531840:4160749567]	99	1			T13	1		T70	2		T37	1
auto[4160749568:4294967295]	100	1			T13	1		T4	1		T37	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T13	1		T18	1		T40	2
auto[0:134217727]	auto[1]	56	1			T47	1		T95	1		T96	1
auto[134217728:268435455]	auto[0]	44	1			T79	1		T181	1		T47	1
auto[134217728:268435455]	auto[1]	55	1			T37	1		T219	1		T40	1
auto[268435456:402653183]	auto[0]	45	1			T2	1		T31	1		T22	1
auto[268435456:402653183]	auto[1]	58	1			T13	2		T37	3		T52	1
auto[402653184:536870911]	auto[0]	44	1			T13	1		T18	1		T22	1
auto[402653184:536870911]	auto[1]	63	1			T93	1		T186	1		T287	1
auto[536870912:671088639]	auto[0]	48	1			T16	1		T37	1		T47	1
auto[536870912:671088639]	auto[1]	57	1			T1	1		T2	1		T37	1
auto[671088640:805306367]	auto[0]	55	1			T39	1		T41	1		T51	1
auto[671088640:805306367]	auto[1]	51	1			T14	1		T63	1		T117	1
auto[805306368:939524095]	auto[0]	40	1			T3	1		T5	1		T51	1
auto[805306368:939524095]	auto[1]	56	1			T13	2		T31	1		T52	1
auto[939524096:1073741823]	auto[0]	56	1			T40	2		T41	1		T76	1
auto[939524096:1073741823]	auto[1]	58	1			T13	1		T14	1		T70	1
auto[1073741824:1207959551]	auto[0]	43	1			T37	1		T52	1		T47	1
auto[1073741824:1207959551]	auto[1]	56	1			T16	1		T47	1		T40	1
auto[1207959552:1342177279]	auto[0]	50	1			T2	1		T52	1		T47	2
auto[1207959552:1342177279]	auto[1]	53	1			T13	1		T37	1		T96	1
auto[1342177280:1476395007]	auto[0]	37	1			T70	1		T51	1		T19	1
auto[1342177280:1476395007]	auto[1]	71	1			T47	1		T23	2		T287	1
auto[1476395008:1610612735]	auto[0]	50	1			T52	1		T47	1		T42	2
auto[1476395008:1610612735]	auto[1]	61	1			T2	1		T13	1		T37	1
auto[1610612736:1744830463]	auto[0]	37	1			T47	1		T23	1		T179	1
auto[1610612736:1744830463]	auto[1]	48	1			T14	1		T70	2		T37	1
auto[1744830464:1879048191]	auto[0]	44	1			T93	1		T42	1		T191	1
auto[1744830464:1879048191]	auto[1]	55	1			T13	1		T17	1		T43	2
auto[1879048192:2013265919]	auto[0]	34	1			T2	1		T52	1		T47	1
auto[1879048192:2013265919]	auto[1]	47	1			T13	1		T37	1		T47	1
auto[2013265920:2147483647]	auto[0]	47	1			T37	1		T181	1		T47	2
auto[2013265920:2147483647]	auto[1]	57	1			T16	1		T90	1		T96	1
auto[2147483648:2281701375]	auto[0]	43	1			T181	1		T40	2		T76	1
auto[2147483648:2281701375]	auto[1]	48	1			T13	1		T14	1		T31	1
auto[2281701376:2415919103]	auto[0]	51	1			T13	1		T18	1		T4	1
auto[2281701376:2415919103]	auto[1]	50	1			T14	1		T39	2		T40	1
auto[2415919104:2550136831]	auto[0]	43	1			T18	1		T47	1		T95	1
auto[2415919104:2550136831]	auto[1]	58	1			T2	1		T13	2		T37	1
auto[2550136832:2684354559]	auto[0]	42	1			T39	1		T5	1		T47	2
auto[2550136832:2684354559]	auto[1]	49	1			T18	1		T216	1		T321	1
auto[2684354560:2818572287]	auto[0]	47	1			T18	1		T4	1		T47	1
auto[2684354560:2818572287]	auto[1]	60	1			T1	1		T37	2		T182	1
auto[2818572288:2952790015]	auto[0]	47	1			T18	1		T42	2		T55	1
auto[2818572288:2952790015]	auto[1]	50	1			T52	1		T47	2		T41	1
auto[2952790016:3087007743]	auto[0]	45	1			T47	1		T118	1		T55	1
auto[2952790016:3087007743]	auto[1]	49	1			T47	3		T95	1		T42	1
auto[3087007744:3221225471]	auto[0]	43	1			T93	1		T47	1		T40	1
auto[3087007744:3221225471]	auto[1]	54	1			T16	1		T4	1		T37	1
auto[3221225472:3355443199]	auto[0]	46	1			T31	1		T47	3		T118	1
auto[3221225472:3355443199]	auto[1]	51	1			T13	1		T76	1		T42	1
auto[3355443200:3489660927]	auto[0]	43	1			T5	1		T52	1		T51	1
auto[3355443200:3489660927]	auto[1]	51	1			T17	1		T37	1		T52	1
auto[3489660928:3623878655]	auto[0]	43	1			T70	1		T79	1		T47	1
auto[3489660928:3623878655]	auto[1]	59	1			T3	1		T17	1		T52	1
auto[3623878656:3758096383]	auto[0]	58	1			T39	1		T5	1		T52	3
auto[3623878656:3758096383]	auto[1]	39	1			T1	1		T89	1		T47	2
auto[3758096384:3892314111]	auto[0]	37	1			T47	1		T55	1		T321	1
auto[3758096384:3892314111]	auto[1]	56	1			T13	1		T14	1		T37	1
auto[3892314112:4026531839]	auto[0]	52	1			T31	1		T5	1		T22	1
auto[3892314112:4026531839]	auto[1]	49	1			T2	1		T17	1		T51	1
auto[4026531840:4160749567]	auto[0]	45	1			T13	1		T70	1		T37	1
auto[4026531840:4160749567]	auto[1]	54	1			T70	1		T40	1		T118	1
auto[4160749568:4294967295]	auto[0]	40	1			T13	1		T4	1		T117	1
auto[4160749568:4294967295]	auto[1]	60	1			T37	1		T47	1		T23	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1481

1

T2

4

T3

2

T13

7

auto[1]

1708

1

T1

3

T2

4

T13

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T13	2		T14	1		T18	2
auto[134217728:268435455]	104	1			T2	1		T13	1		T181	1
auto[268435456:402653183]	101	1			T13	2		T47	2		T51	1
auto[402653184:536870911]	92	1			T13	1		T47	3		T96	1
auto[536870912:671088639]	92	1			T22	1		T37	2		T47	1
auto[671088640:805306367]	83	1			T13	1		T18	1		T52	1
auto[805306368:939524095]	93	1			T13	1		T31	1		T50	1
auto[939524096:1073741823]	108	1			T13	1		T16	1		T37	1
auto[1073741824:1207959551]	101	1			T13	1		T18	1		T37	2
auto[1207959552:1342177279]	103	1			T13	2		T70	2		T5	1
auto[1342177280:1476395007]	106	1			T14	1		T39	1		T37	1
auto[1476395008:1610612735]	99	1			T31	1		T70	2		T37	2
auto[1610612736:1744830463]	100	1			T17	1		T18	1		T39	1
auto[1744830464:1879048191]	99	1			T17	1		T70	1		T22	1
auto[1879048192:2013265919]	95	1			T2	1		T3	1		T13	1
auto[2013265920:2147483647]	96	1			T1	1		T14	1		T70	1
auto[2147483648:2281701375]	115	1			T14	1		T17	1		T37	2
auto[2281701376:2415919103]	110	1			T14	1		T47	2		T23	1
auto[2415919104:2550136831]	99	1			T2	2		T3	1		T39	1
auto[2550136832:2684354559]	109	1			T13	1		T18	1		T5	1
auto[2684354560:2818572287]	87	1			T13	1		T70	1		T181	1
auto[2818572288:2952790015]	104	1			T13	1		T39	1		T22	1
auto[2952790016:3087007743]	92	1			T16	1		T39	1		T4	1
auto[3087007744:3221225471]	110	1			T31	1		T4	2		T52	1
auto[3221225472:3355443199]	104	1			T1	1		T4	1		T5	1
auto[3355443200:3489660927]	101	1			T16	1		T93	1		T47	1
auto[3489660928:3623878655]	103	1			T2	1		T13	2		T31	1
auto[3623878656:3758096383]	89	1			T1	1		T2	1		T14	1
auto[3758096384:3892314111]	105	1			T2	1		T13	1		T16	1
auto[3892314112:4026531839]	94	1			T89	1		T47	5		T119	1
auto[4026531840:4160749567]	83	1			T2	1		T17	1		T18	1
auto[4160749568:4294967295]	103	1			T43	1		T5	1		T37	1