Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6467

1

T1

6

T2

9

T3

2

auto[1]

233

1

T17

3

T118

4

T213

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2738	1			T1	3		T2	2		T3	1
auto[134217728:268435455]	158	1			T13	1		T16	2		T18	1
auto[268435456:402653183]	155	1			T1	1		T3	1		T16	1
auto[402653184:536870911]	151	1			T2	1		T13	2		T16	1
auto[536870912:671088639]	145	1			T13	1		T31	1		T39	1
auto[671088640:805306367]	138	1			T2	1		T13	1		T18	1
auto[805306368:939524095]	140	1			T2	1		T70	1		T22	1
auto[939524096:1073741823]	131	1			T13	1		T17	3		T31	1
auto[1073741824:1207959551]	130	1			T1	1		T13	1		T52	1
auto[1207959552:1342177279]	112	1			T2	1		T43	1		T79	2
auto[1342177280:1476395007]	118	1			T13	1		T16	1		T17	1
auto[1476395008:1610612735]	102	1			T39	1		T37	3		T52	1
auto[1610612736:1744830463]	128	1			T13	2		T37	3		T93	1
auto[1744830464:1879048191]	127	1			T13	2		T39	1		T37	1
auto[1879048192:2013265919]	138	1			T16	1		T17	1		T31	1
auto[2013265920:2147483647]	115	1			T16	2		T37	1		T42	1
auto[2147483648:2281701375]	109	1			T17	1		T70	1		T37	2
auto[2281701376:2415919103]	108	1			T70	1		T37	1		T47	3
auto[2415919104:2550136831]	125	1			T13	1		T16	1		T31	1
auto[2550136832:2684354559]	121	1			T13	3		T39	1		T37	1
auto[2684354560:2818572287]	128	1			T13	1		T37	2		T47	2
auto[2818572288:2952790015]	120	1			T13	1		T16	1		T43	1
auto[2952790016:3087007743]	116	1			T31	1		T22	1		T37	2
auto[3087007744:3221225471]	130	1			T1	1		T14	1		T22	1
auto[3221225472:3355443199]	121	1			T2	1		T13	1		T18	1
auto[3355443200:3489660927]	127	1			T2	1		T13	3		T14	1
auto[3489660928:3623878655]	119	1			T13	1		T70	1		T37	1
auto[3623878656:3758096383]	123	1			T2	1		T37	1		T181	1
auto[3758096384:3892314111]	137	1			T13	1		T17	1		T18	2
auto[3892314112:4026531839]	117	1			T13	2		T16	1		T37	2
auto[4026531840:4160749567]	126	1			T13	1		T18	1		T37	1
auto[4160749568:4294967295]	147	1			T13	1		T39	1		T37	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2733	1			T1	3		T2	2		T3	1
auto[0:134217727]	auto[1]	5	1			T271	1		T246	1		T310	1
auto[134217728:268435455]	auto[0]	151	1			T13	1		T16	2		T18	1
auto[134217728:268435455]	auto[1]	7	1			T245	1		T271	1		T367	1
auto[268435456:402653183]	auto[0]	149	1			T1	1		T3	1		T16	1
auto[268435456:402653183]	auto[1]	6	1			T213	1		T367	1		T272	1
auto[402653184:536870911]	auto[0]	141	1			T2	1		T13	2		T16	1
auto[402653184:536870911]	auto[1]	10	1			T249	1		T271	1		T314	1
auto[536870912:671088639]	auto[0]	137	1			T13	1		T31	1		T39	1
auto[536870912:671088639]	auto[1]	8	1			T213	1		T245	1		T326	1
auto[671088640:805306367]	auto[0]	128	1			T2	1		T13	1		T18	1
auto[671088640:805306367]	auto[1]	10	1			T394	2		T415	1		T272	1
auto[805306368:939524095]	auto[0]	129	1			T2	1		T70	1		T22	1
auto[805306368:939524095]	auto[1]	11	1			T118	1		T213	1		T393	1
auto[939524096:1073741823]	auto[0]	126	1			T13	1		T17	1		T31	1
auto[939524096:1073741823]	auto[1]	5	1			T17	2		T256	1		T414	1
auto[1073741824:1207959551]	auto[0]	124	1			T1	1		T13	1		T52	1
auto[1073741824:1207959551]	auto[1]	6	1			T249	1		T256	2		T367	1
auto[1207959552:1342177279]	auto[0]	109	1			T2	1		T43	1		T79	2
auto[1207959552:1342177279]	auto[1]	3	1			T229	1		T415	1		T364	1
auto[1342177280:1476395007]	auto[0]	112	1			T13	1		T16	1		T37	2
auto[1342177280:1476395007]	auto[1]	6	1			T17	1		T271	1		T367	1
auto[1476395008:1610612735]	auto[0]	97	1			T39	1		T37	3		T52	1
auto[1476395008:1610612735]	auto[1]	5	1			T213	1		T272	1		T303	2
auto[1610612736:1744830463]	auto[0]	121	1			T13	2		T37	3		T93	1
auto[1610612736:1744830463]	auto[1]	7	1			T366	1		T272	1		T423	2
auto[1744830464:1879048191]	auto[0]	120	1			T13	2		T39	1		T37	1
auto[1744830464:1879048191]	auto[1]	7	1			T118	1		T326	1		T419	1
auto[1879048192:2013265919]	auto[0]	127	1			T16	1		T17	1		T31	1
auto[1879048192:2013265919]	auto[1]	11	1			T393	2		T245	2		T366	1
auto[2013265920:2147483647]	auto[0]	107	1			T16	2		T37	1		T42	1
auto[2013265920:2147483647]	auto[1]	8	1			T367	1		T326	2		T419	1
auto[2147483648:2281701375]	auto[0]	101	1			T17	1		T70	1		T37	2
auto[2147483648:2281701375]	auto[1]	8	1			T213	1		T245	1		T359	1
auto[2281701376:2415919103]	auto[0]	98	1			T70	1		T37	1		T47	3
auto[2281701376:2415919103]	auto[1]	10	1			T213	1		T256	1		T415	1
auto[2415919104:2550136831]	auto[0]	122	1			T13	1		T16	1		T31	1
auto[2415919104:2550136831]	auto[1]	3	1			T367	1		T215	1		T424	1
auto[2550136832:2684354559]	auto[0]	117	1			T13	3		T39	1		T37	1
auto[2550136832:2684354559]	auto[1]	4	1			T415	1		T304	1		T425	1
auto[2684354560:2818572287]	auto[0]	119	1			T13	1		T37	2		T47	2
auto[2684354560:2818572287]	auto[1]	9	1			T245	1		T394	1		T419	1
auto[2818572288:2952790015]	auto[0]	111	1			T13	1		T16	1		T43	1
auto[2818572288:2952790015]	auto[1]	9	1			T213	1		T394	1		T272	1
auto[2952790016:3087007743]	auto[0]	111	1			T31	1		T22	1		T37	2
auto[2952790016:3087007743]	auto[1]	5	1			T314	1		T272	1		T215	1
auto[3087007744:3221225471]	auto[0]	120	1			T1	1		T14	1		T22	1
auto[3087007744:3221225471]	auto[1]	10	1			T246	1		T272	1		T326	1
auto[3221225472:3355443199]	auto[0]	110	1			T2	1		T13	1		T18	1
auto[3221225472:3355443199]	auto[1]	11	1			T242	1		T393	1		T245	2
auto[3355443200:3489660927]	auto[0]	123	1			T2	1		T13	3		T14	1
auto[3355443200:3489660927]	auto[1]	4	1			T416	1		T310	1		T357	1
auto[3489660928:3623878655]	auto[0]	110	1			T13	1		T70	1		T37	1
auto[3489660928:3623878655]	auto[1]	9	1			T256	1		T418	2		T271	1
auto[3623878656:3758096383]	auto[0]	115	1			T2	1		T37	1		T181	1
auto[3623878656:3758096383]	auto[1]	8	1			T214	1		T367	1		T272	1
auto[3758096384:3892314111]	auto[0]	127	1			T13	1		T17	1		T18	2
auto[3758096384:3892314111]	auto[1]	10	1			T118	2		T213	1		T393	1
auto[3892314112:4026531839]	auto[0]	109	1			T13	2		T16	1		T37	2
auto[3892314112:4026531839]	auto[1]	8	1			T213	1		T245	1		T426	1
auto[4026531840:4160749567]	auto[0]	122	1			T13	1		T18	1		T37	1
auto[4026531840:4160749567]	auto[1]	4	1			T415	1		T359	1		T364	1
auto[4160749568:4294967295]	auto[0]	141	1			T13	1		T39	1		T37	2
auto[4160749568:4294967295]	auto[1]	6	1			T242	1		T256	1		T366	1