Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 97.91 98.53 100.00 99.11 98.41 91.63


Total test records in report: 1093
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T1019 /workspace/coverage/default/2.keymgr_lc_disable.1714369939 Feb 07 02:10:37 PM PST 24 Feb 07 02:10:42 PM PST 24 149104381 ps
T1020 /workspace/coverage/default/36.keymgr_alert_test.96417111 Feb 07 02:14:42 PM PST 24 Feb 07 02:14:44 PM PST 24 23562969 ps
T1021 /workspace/coverage/default/17.keymgr_cfg_regwen.3804835043 Feb 07 02:12:49 PM PST 24 Feb 07 02:12:52 PM PST 24 34763457 ps
T1022 /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1888346029 Feb 07 02:10:18 PM PST 24 Feb 07 02:10:24 PM PST 24 402114307 ps
T1023 /workspace/coverage/default/0.keymgr_sideload_protect.201241405 Feb 07 02:10:12 PM PST 24 Feb 07 02:10:18 PM PST 24 170917222 ps
T1024 /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2437652506 Feb 07 02:14:38 PM PST 24 Feb 07 02:14:47 PM PST 24 527331175 ps
T1025 /workspace/coverage/default/2.keymgr_sideload_kmac.4261856634 Feb 07 02:10:28 PM PST 24 Feb 07 02:10:32 PM PST 24 247793277 ps
T1026 /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2039906406 Feb 07 02:15:19 PM PST 24 Feb 07 02:15:30 PM PST 24 356496065 ps
T1027 /workspace/coverage/default/27.keymgr_sideload_kmac.36162719 Feb 07 02:13:47 PM PST 24 Feb 07 02:13:50 PM PST 24 19637295 ps
T375 /workspace/coverage/default/1.keymgr_cfg_regwen.1580871208 Feb 07 02:10:16 PM PST 24 Feb 07 02:10:21 PM PST 24 193139175 ps
T1028 /workspace/coverage/default/32.keymgr_sideload.3771477127 Feb 07 02:14:17 PM PST 24 Feb 07 02:14:23 PM PST 24 395140942 ps
T1029 /workspace/coverage/default/11.keymgr_cfg_regwen.100710704 Feb 07 02:12:09 PM PST 24 Feb 07 02:12:14 PM PST 24 327156208 ps
T1030 /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1388707981 Feb 07 02:10:51 PM PST 24 Feb 07 02:11:35 PM PST 24 3483842662 ps
T1031 /workspace/coverage/default/38.keymgr_lc_disable.2267132680 Feb 07 02:14:59 PM PST 24 Feb 07 02:15:06 PM PST 24 140339612 ps
T1032 /workspace/coverage/default/15.keymgr_sideload_protect.49219122 Feb 07 02:12:35 PM PST 24 Feb 07 02:12:39 PM PST 24 159365212 ps
T1033 /workspace/coverage/default/25.keymgr_sideload_otbn.1217188647 Feb 07 02:13:43 PM PST 24 Feb 07 02:13:46 PM PST 24 39554053 ps
T1034 /workspace/coverage/default/36.keymgr_smoke.3879565313 Feb 07 02:14:35 PM PST 24 Feb 07 02:14:58 PM PST 24 3180299155 ps
T1035 /workspace/coverage/default/38.keymgr_sideload.3793010805 Feb 07 02:14:57 PM PST 24 Feb 07 02:15:04 PM PST 24 545127109 ps
T318 /workspace/coverage/default/2.keymgr_stress_all.1495340421 Feb 07 02:10:53 PM PST 24 Feb 07 02:12:12 PM PST 24 4564195710 ps
T1036 /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.958258380 Feb 07 02:12:25 PM PST 24 Feb 07 02:12:32 PM PST 24 212730611 ps
T1037 /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1169660256 Feb 07 02:14:03 PM PST 24 Feb 07 02:14:10 PM PST 24 292579292 ps
T320 /workspace/coverage/default/16.keymgr_kmac_rsp_err.1181527731 Feb 07 02:12:42 PM PST 24 Feb 07 02:13:12 PM PST 24 962873177 ps
T1038 /workspace/coverage/default/35.keymgr_sideload.4186120532 Feb 07 02:14:37 PM PST 24 Feb 07 02:14:41 PM PST 24 78620264 ps
T1039 /workspace/coverage/default/18.keymgr_alert_test.542302432 Feb 07 02:13:06 PM PST 24 Feb 07 02:13:08 PM PST 24 14888434 ps
T430 /workspace/coverage/default/3.keymgr_cfg_regwen.945930475 Feb 07 02:10:51 PM PST 24 Feb 07 02:11:12 PM PST 24 733370028 ps
T1040 /workspace/coverage/default/24.keymgr_hwsw_invalid_input.929033228 Feb 07 02:13:30 PM PST 24 Feb 07 02:13:35 PM PST 24 569429497 ps
T350 /workspace/coverage/default/21.keymgr_stress_all.2294807065 Feb 07 02:13:18 PM PST 24 Feb 07 02:14:05 PM PST 24 2746066006 ps
T1041 /workspace/coverage/default/11.keymgr_alert_test.3026662050 Feb 07 02:12:09 PM PST 24 Feb 07 02:12:12 PM PST 24 38097098 ps
T1042 /workspace/coverage/default/31.keymgr_smoke.2192363730 Feb 07 02:14:06 PM PST 24 Feb 07 02:15:07 PM PST 24 24023220248 ps
T1043 /workspace/coverage/default/17.keymgr_alert_test.2392205890 Feb 07 02:12:46 PM PST 24 Feb 07 02:12:48 PM PST 24 66946810 ps
T1044 /workspace/coverage/default/33.keymgr_stress_all.2431258735 Feb 07 02:14:19 PM PST 24 Feb 07 02:14:28 PM PST 24 724948026 ps
T1045 /workspace/coverage/default/36.keymgr_custom_cm.2118505562 Feb 07 02:14:43 PM PST 24 Feb 07 02:14:49 PM PST 24 480855367 ps
T1046 /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1124369763 Feb 07 02:10:55 PM PST 24 Feb 07 02:11:00 PM PST 24 351512104 ps
T319 /workspace/coverage/default/38.keymgr_stress_all.557896147 Feb 07 02:14:57 PM PST 24 Feb 07 02:15:04 PM PST 24 190485032 ps
T1047 /workspace/coverage/default/23.keymgr_alert_test.3403096391 Feb 07 02:13:32 PM PST 24 Feb 07 02:13:33 PM PST 24 15034630 ps
T1048 /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2622946390 Feb 07 02:13:07 PM PST 24 Feb 07 02:13:11 PM PST 24 188406046 ps
T431 /workspace/coverage/default/27.keymgr_cfg_regwen.683309664 Feb 07 02:13:51 PM PST 24 Feb 07 02:14:01 PM PST 24 1043504159 ps
T46 /workspace/coverage/default/40.keymgr_stress_all.2235103344 Feb 07 02:15:06 PM PST 24 Feb 07 02:15:35 PM PST 24 1346218727 ps
T1049 /workspace/coverage/default/22.keymgr_random.611982831 Feb 07 02:13:27 PM PST 24 Feb 07 02:13:32 PM PST 24 323301949 ps
T1050 /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2171934145 Feb 07 02:11:22 PM PST 24 Feb 07 02:11:30 PM PST 24 197724636 ps
T424 /workspace/coverage/default/45.keymgr_cfg_regwen.3944801276 Feb 07 02:15:30 PM PST 24 Feb 07 02:15:40 PM PST 24 169311949 ps
T1051 /workspace/coverage/default/0.keymgr_lc_disable.3668567040 Feb 07 02:10:11 PM PST 24 Feb 07 02:10:15 PM PST 24 97917081 ps
T1052 /workspace/coverage/default/7.keymgr_kmac_rsp_err.811169083 Feb 07 02:11:33 PM PST 24 Feb 07 02:11:45 PM PST 24 503573037 ps
T433 /workspace/coverage/default/6.keymgr_cfg_regwen.2253840183 Feb 07 02:11:22 PM PST 24 Feb 07 02:11:37 PM PST 24 264174521 ps
T1053 /workspace/coverage/default/28.keymgr_sideload_protect.377206091 Feb 07 02:14:01 PM PST 24 Feb 07 02:14:37 PM PST 24 3951233646 ps
T1054 /workspace/coverage/default/39.keymgr_stress_all.2767077207 Feb 07 02:14:56 PM PST 24 Feb 07 02:16:08 PM PST 24 5649418445 ps
T1055 /workspace/coverage/default/49.keymgr_stress_all.1240170988 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:27 PM PST 24 1908006946 ps
T1056 /workspace/coverage/default/40.keymgr_sideload.4098251737 Feb 07 02:15:03 PM PST 24 Feb 07 02:15:08 PM PST 24 167454016 ps
T396 /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2681027159 Feb 07 02:15:09 PM PST 24 Feb 07 02:15:13 PM PST 24 57631814 ps
T1057 /workspace/coverage/default/30.keymgr_kmac_rsp_err.3677481535 Feb 07 02:14:17 PM PST 24 Feb 07 02:14:27 PM PST 24 193910689 ps
T1058 /workspace/coverage/default/32.keymgr_sideload_aes.4055826143 Feb 07 02:14:16 PM PST 24 Feb 07 02:14:23 PM PST 24 81266330 ps
T1059 /workspace/coverage/default/22.keymgr_smoke.3268722546 Feb 07 02:13:16 PM PST 24 Feb 07 02:13:23 PM PST 24 849814159 ps
T1060 /workspace/coverage/default/37.keymgr_alert_test.3096064071 Feb 07 02:15:05 PM PST 24 Feb 07 02:15:08 PM PST 24 17786791 ps
T1061 /workspace/coverage/default/42.keymgr_stress_all.2471340343 Feb 07 02:15:18 PM PST 24 Feb 07 02:15:26 PM PST 24 522939426 ps
T212 /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3332884461 Feb 07 02:10:50 PM PST 24 Feb 07 02:11:03 PM PST 24 630632528 ps
T1062 /workspace/coverage/default/35.keymgr_sideload_otbn.2639016730 Feb 07 02:14:24 PM PST 24 Feb 07 02:14:30 PM PST 24 334290311 ps
T1063 /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3962992089 Feb 07 02:14:15 PM PST 24 Feb 07 02:14:29 PM PST 24 580885637 ps
T385 /workspace/coverage/default/2.keymgr_sw_invalid_input.3628878662 Feb 07 02:10:38 PM PST 24 Feb 07 02:10:43 PM PST 24 427845121 ps
T390 /workspace/coverage/default/17.keymgr_kmac_rsp_err.1497075810 Feb 07 02:12:46 PM PST 24 Feb 07 02:13:06 PM PST 24 614974431 ps
T1064 /workspace/coverage/default/13.keymgr_smoke.3353981547 Feb 07 02:12:22 PM PST 24 Feb 07 02:12:26 PM PST 24 78142112 ps
T1065 /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4198312001 Feb 07 02:14:04 PM PST 24 Feb 07 02:14:10 PM PST 24 219238874 ps
T1066 /workspace/coverage/default/8.keymgr_custom_cm.255238704 Feb 07 02:11:45 PM PST 24 Feb 07 02:11:48 PM PST 24 534434799 ps
T1067 /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.35946220 Feb 07 02:15:37 PM PST 24 Feb 07 02:15:41 PM PST 24 143975182 ps
T1068 /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3216223676 Feb 07 02:12:08 PM PST 24 Feb 07 02:12:12 PM PST 24 66568826 ps
T1069 /workspace/coverage/default/45.keymgr_sideload_otbn.3869327024 Feb 07 02:15:24 PM PST 24 Feb 07 02:15:47 PM PST 24 850336263 ps
T1070 /workspace/coverage/default/45.keymgr_direct_to_disabled.4160234614 Feb 07 02:15:27 PM PST 24 Feb 07 02:15:30 PM PST 24 35918404 ps
T1071 /workspace/coverage/default/26.keymgr_sideload_otbn.3778540482 Feb 07 02:13:46 PM PST 24 Feb 07 02:13:49 PM PST 24 121275207 ps
T1072 /workspace/coverage/default/29.keymgr_random.1641940584 Feb 07 02:14:04 PM PST 24 Feb 07 02:14:17 PM PST 24 1556088447 ps
T143 /workspace/coverage/default/23.keymgr_custom_cm.766542439 Feb 07 02:13:24 PM PST 24 Feb 07 02:13:29 PM PST 24 425608716 ps
T1073 /workspace/coverage/default/24.keymgr_kmac_rsp_err.3974831941 Feb 07 02:13:30 PM PST 24 Feb 07 02:13:42 PM PST 24 889786081 ps
T1074 /workspace/coverage/default/30.keymgr_sideload.2241267384 Feb 07 02:14:05 PM PST 24 Feb 07 02:14:12 PM PST 24 82383674 ps
T1075 /workspace/coverage/default/30.keymgr_random.3639092189 Feb 07 02:14:17 PM PST 24 Feb 07 02:14:24 PM PST 24 182765615 ps
T1076 /workspace/coverage/default/49.keymgr_lc_disable.1813543401 Feb 07 02:16:06 PM PST 24 Feb 07 02:16:12 PM PST 24 58351211 ps
T1077 /workspace/coverage/default/48.keymgr_smoke.184419014 Feb 07 02:15:41 PM PST 24 Feb 07 02:15:49 PM PST 24 214642838 ps
T1078 /workspace/coverage/default/1.keymgr_sync_async_fault_cross.283479971 Feb 07 02:10:31 PM PST 24 Feb 07 02:10:34 PM PST 24 180218835 ps
T1079 /workspace/coverage/default/24.keymgr_custom_cm.823231934 Feb 07 02:13:31 PM PST 24 Feb 07 02:13:35 PM PST 24 59854639 ps
T1080 /workspace/coverage/default/38.keymgr_sideload_otbn.2644472989 Feb 07 02:14:56 PM PST 24 Feb 07 02:14:59 PM PST 24 34987627 ps
T1081 /workspace/coverage/default/47.keymgr_direct_to_disabled.498278862 Feb 07 02:15:38 PM PST 24 Feb 07 02:15:41 PM PST 24 110060327 ps
T1082 /workspace/coverage/default/49.keymgr_alert_test.2542964992 Feb 07 02:16:09 PM PST 24 Feb 07 02:16:12 PM PST 24 15883456 ps
T1083 /workspace/coverage/default/5.keymgr_sideload_aes.2339343878 Feb 07 02:11:20 PM PST 24 Feb 07 02:11:24 PM PST 24 188956908 ps
T1084 /workspace/coverage/default/16.keymgr_sideload_kmac.104203197 Feb 07 02:12:42 PM PST 24 Feb 07 02:12:45 PM PST 24 36974060 ps
T1085 /workspace/coverage/default/11.keymgr_lc_disable.3147999736 Feb 07 02:12:11 PM PST 24 Feb 07 02:12:24 PM PST 24 896209001 ps
T333 /workspace/coverage/default/43.keymgr_cfg_regwen.3498404008 Feb 07 02:15:24 PM PST 24 Feb 07 02:15:29 PM PST 24 58843356 ps
T1086 /workspace/coverage/default/11.keymgr_sideload_kmac.753500044 Feb 07 02:12:10 PM PST 24 Feb 07 02:12:14 PM PST 24 375955722 ps
T329 /workspace/coverage/default/41.keymgr_random.2898705949 Feb 07 02:15:20 PM PST 24 Feb 07 02:15:25 PM PST 24 414684258 ps
T1087 /workspace/coverage/default/47.keymgr_random.1946905615 Feb 07 02:15:52 PM PST 24 Feb 07 02:15:59 PM PST 24 382779521 ps
T1088 /workspace/coverage/default/27.keymgr_custom_cm.317470579 Feb 07 02:14:03 PM PST 24 Feb 07 02:14:09 PM PST 24 1162325395 ps
T1089 /workspace/coverage/default/44.keymgr_sideload_protect.895747292 Feb 07 02:15:29 PM PST 24 Feb 07 02:15:34 PM PST 24 363630619 ps
T1090 /workspace/coverage/default/28.keymgr_sideload.2438518027 Feb 07 02:14:01 PM PST 24 Feb 07 02:14:08 PM PST 24 105321792 ps
T1091 /workspace/coverage/default/26.keymgr_sw_invalid_input.1111022368 Feb 07 02:13:49 PM PST 24 Feb 07 02:13:53 PM PST 24 101779563 ps
T308 /workspace/coverage/default/4.keymgr_hwsw_invalid_input.779342273 Feb 07 02:11:17 PM PST 24 Feb 07 02:11:20 PM PST 24 32582790 ps
T1092 /workspace/coverage/default/47.keymgr_sw_invalid_input.3431001005 Feb 07 02:15:36 PM PST 24 Feb 07 02:15:48 PM PST 24 273597359 ps
T1093 /workspace/coverage/default/33.keymgr_sideload.747558045 Feb 07 02:14:16 PM PST 24 Feb 07 02:14:23 PM PST 24 59546349 ps

Test location /workspace/coverage/default/17.keymgr_stress_all.2143182518
Short name T13
Test name
Test status
Simulation time 255723666 ps
CPU time 13.21 seconds
Started Feb 07 02:12:57 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 216664 kb
Host smart-2ccf285f-7b10-4baf-b229-642cde6011ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143182518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2143182518
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1153893521
Short name T42
Test name
Test status
Simulation time 31193930949 ps
CPU time 995.76 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:30:54 PM PST 24
Peak memory 231128 kb
Host smart-1db8c378-9356-42e2-9a84-2553d43492ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153893521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1153893521
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.870206876
Short name T2
Test name
Test status
Simulation time 236904692 ps
CPU time 9.9 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:34 PM PST 24
Peak memory 222964 kb
Host smart-fdc28731-0292-4fa1-a03c-397750ee79fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870206876 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.870206876
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2653081826
Short name T6
Test name
Test status
Simulation time 1035530869 ps
CPU time 18.62 seconds
Started Feb 07 02:10:57 PM PST 24
Finished Feb 07 02:11:16 PM PST 24
Peak memory 237756 kb
Host smart-8cea3cee-9e49-41c1-b2cf-002593f74a70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653081826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2653081826
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1739975283
Short name T100
Test name
Test status
Simulation time 144093002 ps
CPU time 3.12 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 214424 kb
Host smart-c4d5d2e9-94cc-4d0a-bb83-0e252b7a08f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739975283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1739975283
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4208886569
Short name T47
Test name
Test status
Simulation time 6487095987 ps
CPU time 38.03 seconds
Started Feb 07 02:11:15 PM PST 24
Finished Feb 07 02:11:54 PM PST 24
Peak memory 216520 kb
Host smart-5caaba6c-01ca-47ee-8b3a-a269a0c4d03c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208886569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4208886569
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1010295444
Short name T230
Test name
Test status
Simulation time 1476925191 ps
CPU time 20.53 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 215340 kb
Host smart-8c0f9633-800e-4065-af93-cc8b6a5890f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010295444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1010295444
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2267071189
Short name T245
Test name
Test status
Simulation time 5027342534 ps
CPU time 75.18 seconds
Started Feb 07 02:15:39 PM PST 24
Finished Feb 07 02:16:55 PM PST 24
Peak memory 222996 kb
Host smart-c6473628-65c3-4ae3-9bfa-8cd60182ff54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267071189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2267071189
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4041785800
Short name T7
Test name
Test status
Simulation time 217308614 ps
CPU time 2.5 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:10:59 PM PST 24
Peak memory 210048 kb
Host smart-4940a096-61af-42f2-a1f8-3e2121476071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041785800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4041785800
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2218468840
Short name T45
Test name
Test status
Simulation time 746263015 ps
CPU time 36.83 seconds
Started Feb 07 02:12:44 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 214780 kb
Host smart-e8b1d906-649e-40c6-b619-cafb6bb21468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218468840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2218468840
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4272798963
Short name T98
Test name
Test status
Simulation time 626339023 ps
CPU time 6.86 seconds
Started Feb 07 02:16:30 PM PST 24
Finished Feb 07 02:16:40 PM PST 24
Peak memory 220328 kb
Host smart-0ad73b26-e14f-498c-88af-430be874c4a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272798963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4272798963
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1545191086
Short name T55
Test name
Test status
Simulation time 16304842597 ps
CPU time 137.28 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:15:45 PM PST 24
Peak memory 223132 kb
Host smart-f0b15e29-79a3-4dd7-b27f-4999f6048426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545191086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1545191086
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1089226459
Short name T23
Test name
Test status
Simulation time 132943402 ps
CPU time 4.93 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 214820 kb
Host smart-f605db5c-65eb-4179-96d5-7529ea2bed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089226459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1089226459
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2545443923
Short name T213
Test name
Test status
Simulation time 2160215931 ps
CPU time 29.05 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 214964 kb
Host smart-b68732b9-e14a-4f00-97fa-3d271f35fee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545443923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2545443923
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3431066472
Short name T31
Test name
Test status
Simulation time 446714050 ps
CPU time 10.04 seconds
Started Feb 07 02:11:17 PM PST 24
Finished Feb 07 02:11:27 PM PST 24
Peak memory 210840 kb
Host smart-5a7a31d7-607e-471c-9456-cc566a8caa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431066472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3431066472
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.945930475
Short name T430
Test name
Test status
Simulation time 733370028 ps
CPU time 20.59 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:11:12 PM PST 24
Peak memory 214824 kb
Host smart-c94cbe1c-adc4-40cc-bbcf-7e87f0e9062f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945930475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.945930475
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4148769814
Short name T207
Test name
Test status
Simulation time 4271263065 ps
CPU time 82.17 seconds
Started Feb 07 02:14:40 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 222180 kb
Host smart-0e4d888d-4be6-4c66-8ce5-2e2ab251d9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148769814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4148769814
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1006795485
Short name T215
Test name
Test status
Simulation time 1233561765 ps
CPU time 65.18 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:16:16 PM PST 24
Peak memory 222992 kb
Host smart-ec11b825-f1d7-46b4-b14b-2dd1662c293b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006795485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1006795485
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.290442851
Short name T74
Test name
Test status
Simulation time 1119226040 ps
CPU time 7.08 seconds
Started Feb 07 02:14:35 PM PST 24
Finished Feb 07 02:14:46 PM PST 24
Peak memory 209720 kb
Host smart-20ff4e1d-9d0d-4549-a921-ddb3d2852d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290442851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.290442851
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3851220945
Short name T37
Test name
Test status
Simulation time 460740769 ps
CPU time 22.88 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:52 PM PST 24
Peak memory 216044 kb
Host smart-3ede9dab-4546-439e-b9df-2f7c0dbddcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851220945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3851220945
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1619529983
Short name T357
Test name
Test status
Simulation time 330403040 ps
CPU time 18.76 seconds
Started Feb 07 02:14:49 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 214928 kb
Host smart-cd2c5ee7-059e-4abc-ae49-45f1ffd70c51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619529983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1619529983
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2505193152
Short name T162
Test name
Test status
Simulation time 3162253021 ps
CPU time 66.75 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:18:19 PM PST 24
Peak memory 224556 kb
Host smart-ae15bd90-df1c-47de-a84c-5ecb840084ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505193152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2505193152
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4057034132
Short name T27
Test name
Test status
Simulation time 69457119 ps
CPU time 3.58 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 218356 kb
Host smart-3117a7d4-ff60-47e5-8115-9e4ac0cc569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057034132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4057034132
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3944801276
Short name T424
Test name
Test status
Simulation time 169311949 ps
CPU time 8.94 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:40 PM PST 24
Peak memory 214864 kb
Host smart-753cda94-3542-49bc-bc77-f256fc32082a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944801276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3944801276
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1086706975
Short name T3
Test name
Test status
Simulation time 373759918 ps
CPU time 2.87 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 218468 kb
Host smart-10b8b1e9-7df4-4a1a-bc40-f489be43079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086706975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1086706975
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3702434203
Short name T36
Test name
Test status
Simulation time 132251432 ps
CPU time 6.3 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:22 PM PST 24
Peak memory 214784 kb
Host smart-e5e98786-e9d9-4ba7-b73f-c62d7537693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702434203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3702434203
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2518828277
Short name T145
Test name
Test status
Simulation time 1560241579 ps
CPU time 45.8 seconds
Started Feb 07 02:14:28 PM PST 24
Finished Feb 07 02:15:15 PM PST 24
Peak memory 223136 kb
Host smart-446f1341-7136-41ee-848d-f7d550ff3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518828277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2518828277
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.438932604
Short name T364
Test name
Test status
Simulation time 59363047 ps
CPU time 4.46 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:01 PM PST 24
Peak memory 215444 kb
Host smart-b65335a4-1ad7-4704-99bb-f892bed93937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438932604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.438932604
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.70335640
Short name T228
Test name
Test status
Simulation time 2214213552 ps
CPU time 49.92 seconds
Started Feb 07 02:12:47 PM PST 24
Finished Feb 07 02:13:38 PM PST 24
Peak memory 221588 kb
Host smart-114d7408-3fe3-4d84-93f5-47865a9690c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70335640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.70335640
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.957834506
Short name T303
Test name
Test status
Simulation time 277444928 ps
CPU time 14.27 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:52 PM PST 24
Peak memory 215680 kb
Host smart-9bd57131-a091-43a7-926e-973e095c8a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957834506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.957834506
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1091897525
Short name T9
Test name
Test status
Simulation time 62658990 ps
CPU time 2.63 seconds
Started Feb 07 02:14:11 PM PST 24
Finished Feb 07 02:14:15 PM PST 24
Peak memory 210800 kb
Host smart-bae4b99f-b7d6-4b34-b99a-5523dbe1b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091897525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1091897525
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.588018079
Short name T179
Test name
Test status
Simulation time 151913411 ps
CPU time 5.56 seconds
Started Feb 07 02:13:24 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 214724 kb
Host smart-11c78c90-dd87-477b-8d67-a11b1c116b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588018079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.588018079
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3169325624
Short name T86
Test name
Test status
Simulation time 12137439 ps
CPU time 0.86 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 206396 kb
Host smart-9956b1fb-58b2-4376-8c6a-76d0649711e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169325624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3169325624
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4201856650
Short name T206
Test name
Test status
Simulation time 1737777415 ps
CPU time 43.94 seconds
Started Feb 07 02:15:40 PM PST 24
Finished Feb 07 02:16:24 PM PST 24
Peak memory 223068 kb
Host smart-19e18697-43bc-4694-95d7-331cfe8a917f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201856650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4201856650
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3050583936
Short name T77
Test name
Test status
Simulation time 290708992 ps
CPU time 4.33 seconds
Started Feb 07 02:13:15 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 210376 kb
Host smart-82d4b912-fbdf-4a89-92ec-f3f2a067c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050583936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3050583936
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1916522965
Short name T510
Test name
Test status
Simulation time 567500044 ps
CPU time 8.37 seconds
Started Feb 07 02:16:25 PM PST 24
Finished Feb 07 02:16:38 PM PST 24
Peak memory 214424 kb
Host smart-3cbbd510-ebae-4b30-af26-3329a7089995
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916522965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1916522965
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1495799653
Short name T90
Test name
Test status
Simulation time 167761223 ps
CPU time 9.07 seconds
Started Feb 07 02:10:30 PM PST 24
Finished Feb 07 02:10:40 PM PST 24
Peak memory 223084 kb
Host smart-640c6cc7-a0f3-4586-9a32-115226b02c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495799653 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1495799653
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3541914543
Short name T331
Test name
Test status
Simulation time 104884035 ps
CPU time 4.73 seconds
Started Feb 07 02:12:45 PM PST 24
Finished Feb 07 02:12:51 PM PST 24
Peak memory 214816 kb
Host smart-793256dc-21e6-4d0f-84f4-36d5db418090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541914543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3541914543
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1776086054
Short name T210
Test name
Test status
Simulation time 4138484129 ps
CPU time 28.57 seconds
Started Feb 07 02:13:39 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 216200 kb
Host smart-ec5898c8-6bcf-4faf-9f7e-2a3259faa42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776086054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1776086054
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4053320183
Short name T325
Test name
Test status
Simulation time 1496188545 ps
CPU time 15.03 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:43 PM PST 24
Peak memory 215552 kb
Host smart-ec177b83-e23c-4b65-bfd1-636e0c6a5c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053320183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4053320183
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1742562247
Short name T272
Test name
Test status
Simulation time 1452801947 ps
CPU time 20.48 seconds
Started Feb 07 02:14:02 PM PST 24
Finished Feb 07 02:14:25 PM PST 24
Peak memory 215528 kb
Host smart-9056d230-2cda-4f4a-817a-f347f6e31b04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742562247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1742562247
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3903372545
Short name T76
Test name
Test status
Simulation time 491316004 ps
CPU time 3.58 seconds
Started Feb 07 02:14:03 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 214828 kb
Host smart-f74163a1-c82b-4bcd-acb9-0f6110d23607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903372545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3903372545
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1232973921
Short name T423
Test name
Test status
Simulation time 243191122 ps
CPU time 5.43 seconds
Started Feb 07 02:11:22 PM PST 24
Finished Feb 07 02:11:28 PM PST 24
Peak memory 215532 kb
Host smart-ccbc2c3c-3338-4f78-b5a3-7c32d7a8d6cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232973921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1232973921
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2733051680
Short name T147
Test name
Test status
Simulation time 1101273818 ps
CPU time 12.3 seconds
Started Feb 07 02:17:04 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 214084 kb
Host smart-092b4177-88eb-49b9-8003-1757b4d21ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733051680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2733051680
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2827296051
Short name T153
Test name
Test status
Simulation time 123078248 ps
CPU time 6.53 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:17:01 PM PST 24
Peak memory 209264 kb
Host smart-ce94575b-3f53-4fdb-9e09-26eb72b3b2de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827296051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2827296051
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1744703201
Short name T137
Test name
Test status
Simulation time 484371903 ps
CPU time 4.1 seconds
Started Feb 07 02:11:41 PM PST 24
Finished Feb 07 02:11:46 PM PST 24
Peak memory 217696 kb
Host smart-2b1fc16e-9935-4d78-81a5-4d9c99ceb358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744703201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1744703201
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2717036015
Short name T54
Test name
Test status
Simulation time 140250004 ps
CPU time 6.26 seconds
Started Feb 07 02:10:52 PM PST 24
Finished Feb 07 02:10:58 PM PST 24
Peak memory 222948 kb
Host smart-525a8414-8ed9-400f-8ed7-13f24a74dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717036015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2717036015
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.247728895
Short name T314
Test name
Test status
Simulation time 117806937 ps
CPU time 6.78 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:14 PM PST 24
Peak memory 215276 kb
Host smart-871844d8-118e-43bd-af43-5b1cb5e9de6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247728895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.247728895
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.304527597
Short name T240
Test name
Test status
Simulation time 34834810 ps
CPU time 2.73 seconds
Started Feb 07 02:13:58 PM PST 24
Finished Feb 07 02:14:05 PM PST 24
Peak memory 214724 kb
Host smart-f40ea76a-1380-4360-bb52-214459418760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304527597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.304527597
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1245377590
Short name T142
Test name
Test status
Simulation time 78867625 ps
CPU time 4.16 seconds
Started Feb 07 02:12:32 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 218020 kb
Host smart-c4e43e0f-a161-4793-8ecd-d8ab15f30958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245377590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1245377590
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2313145346
Short name T12
Test name
Test status
Simulation time 853385340 ps
CPU time 8.79 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:17 PM PST 24
Peak memory 209056 kb
Host smart-3aa125be-7b8e-488e-8b6f-97b8f8a06d41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313145346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2313145346
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3320989768
Short name T152
Test name
Test status
Simulation time 697386903 ps
CPU time 20.41 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:30 PM PST 24
Peak memory 209340 kb
Host smart-e563178a-e139-48a8-bc6e-2f40f117aff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320989768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3320989768
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2891707460
Short name T157
Test name
Test status
Simulation time 138789803 ps
CPU time 4.18 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 214164 kb
Host smart-990b751c-3512-4e64-b26b-ec8a18327d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891707460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2891707460
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.67050947
Short name T138
Test name
Test status
Simulation time 79704471 ps
CPU time 2.53 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 216964 kb
Host smart-8c89ef45-a364-4266-ae7d-5c316ae4bfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67050947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.67050947
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.237767915
Short name T141
Test name
Test status
Simulation time 50514228 ps
CPU time 3.41 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:32 PM PST 24
Peak memory 218212 kb
Host smart-36be7797-dde2-41a1-92aa-8129c77674bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237767915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.237767915
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2912021466
Short name T326
Test name
Test status
Simulation time 180639013 ps
CPU time 9.63 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:38 PM PST 24
Peak memory 216012 kb
Host smart-c9b45b06-a80e-4d77-b1ac-229ffd5f120a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912021466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2912021466
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2066041885
Short name T653
Test name
Test status
Simulation time 85515443 ps
CPU time 2.62 seconds
Started Feb 07 02:12:19 PM PST 24
Finished Feb 07 02:12:24 PM PST 24
Peak memory 208720 kb
Host smart-c5c55f82-f360-4cce-b243-43221b5029cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066041885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2066041885
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1181527731
Short name T320
Test name
Test status
Simulation time 962873177 ps
CPU time 29.27 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 214188 kb
Host smart-d0270d45-4749-424d-80bd-4a3a5c9103d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181527731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1181527731
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3651769270
Short name T238
Test name
Test status
Simulation time 113180999 ps
CPU time 5.19 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 223000 kb
Host smart-9c8e6d64-ef6d-4d33-8792-84a061f72395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651769270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3651769270
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1475150165
Short name T354
Test name
Test status
Simulation time 4105404818 ps
CPU time 33.38 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 215948 kb
Host smart-a00bb489-6e7d-4076-b726-a1a52b5f057e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475150165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1475150165
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2916392297
Short name T151
Test name
Test status
Simulation time 348873334 ps
CPU time 7.34 seconds
Started Feb 07 02:16:58 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 208224 kb
Host smart-4206d0b1-9c07-44f8-8776-2751db7908a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916392297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2916392297
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1606300594
Short name T160
Test name
Test status
Simulation time 122361354 ps
CPU time 3.72 seconds
Started Feb 07 02:15:58 PM PST 24
Finished Feb 07 02:16:03 PM PST 24
Peak memory 210896 kb
Host smart-7dd63765-963a-407b-bc4b-7d28f09cd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606300594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1606300594
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.282714273
Short name T139
Test name
Test status
Simulation time 242430751 ps
CPU time 4.09 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:10:56 PM PST 24
Peak memory 217852 kb
Host smart-8b390944-2762-40eb-82e3-cbac1b297ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282714273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.282714273
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.766542439
Short name T143
Test name
Test status
Simulation time 425608716 ps
CPU time 4.92 seconds
Started Feb 07 02:13:24 PM PST 24
Finished Feb 07 02:13:29 PM PST 24
Peak memory 223172 kb
Host smart-990ae2f6-5a5e-4e7f-aa4b-65e73adf5a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766542439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.766542439
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.916204282
Short name T140
Test name
Test status
Simulation time 1467295188 ps
CPU time 23.97 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:33 PM PST 24
Peak memory 223096 kb
Host smart-c3588514-ede6-4b5b-9e2f-673a59095cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916204282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.916204282
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3940095995
Short name T260
Test name
Test status
Simulation time 21420252580 ps
CPU time 120.05 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:12:18 PM PST 24
Peak memory 239580 kb
Host smart-93dd6cda-0df8-4a8a-9e3f-419614ed8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940095995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3940095995
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1685937590
Short name T193
Test name
Test status
Simulation time 166022807 ps
CPU time 3.87 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:15 PM PST 24
Peak memory 214868 kb
Host smart-8bc71f68-734e-40bf-aac1-814f9b5a4694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685937590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1685937590
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1495340421
Short name T318
Test name
Test status
Simulation time 4564195710 ps
CPU time 78.31 seconds
Started Feb 07 02:10:53 PM PST 24
Finished Feb 07 02:12:12 PM PST 24
Peak memory 217216 kb
Host smart-6d38f39b-a9b1-467a-8c3e-b592799506ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495340421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1495340421
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2252072299
Short name T414
Test name
Test status
Simulation time 227970577 ps
CPU time 4.55 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 215780 kb
Host smart-ea73d92f-db46-4479-8e91-b843a5129b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252072299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2252072299
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1355475486
Short name T197
Test name
Test status
Simulation time 456583352 ps
CPU time 13.52 seconds
Started Feb 07 02:13:32 PM PST 24
Finished Feb 07 02:13:46 PM PST 24
Peak memory 216168 kb
Host smart-412a7c9c-e08c-4659-b349-41ffba230cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355475486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1355475486
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.4031327415
Short name T199
Test name
Test status
Simulation time 1354395475 ps
CPU time 11.05 seconds
Started Feb 07 02:13:30 PM PST 24
Finished Feb 07 02:13:41 PM PST 24
Peak memory 220852 kb
Host smart-3edbfb02-3900-4fe1-80ce-366277d9bcec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031327415 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.4031327415
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3974831941
Short name T1073
Test name
Test status
Simulation time 889786081 ps
CPU time 10.98 seconds
Started Feb 07 02:13:30 PM PST 24
Finished Feb 07 02:13:42 PM PST 24
Peak memory 211252 kb
Host smart-7e66ea41-2e57-4c66-9aae-408bd40c71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974831941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3974831941
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3421062555
Short name T265
Test name
Test status
Simulation time 133474871 ps
CPU time 4.66 seconds
Started Feb 07 02:13:53 PM PST 24
Finished Feb 07 02:13:58 PM PST 24
Peak memory 223004 kb
Host smart-36340f4e-7cac-467a-a867-fbb936894d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421062555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3421062555
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3769436475
Short name T221
Test name
Test status
Simulation time 589285431 ps
CPU time 10.67 seconds
Started Feb 07 02:14:08 PM PST 24
Finished Feb 07 02:14:20 PM PST 24
Peak memory 209872 kb
Host smart-65ea35f5-88db-4250-90fc-e1a23244450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769436475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3769436475
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1615926254
Short name T229
Test name
Test status
Simulation time 44493493 ps
CPU time 3.06 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:42 PM PST 24
Peak memory 214760 kb
Host smart-0dbbe677-556c-49ca-ba01-767e29935454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615926254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1615926254
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.4237135705
Short name T348
Test name
Test status
Simulation time 150693233 ps
CPU time 3.09 seconds
Started Feb 07 02:15:01 PM PST 24
Finished Feb 07 02:15:05 PM PST 24
Peak memory 211404 kb
Host smart-dc83d097-b2a2-4ebd-b4e3-8d104f8d484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237135705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4237135705
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1837726894
Short name T327
Test name
Test status
Simulation time 262606387 ps
CPU time 8.83 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:37 PM PST 24
Peak memory 208716 kb
Host smart-6aefebe1-ae24-48f5-8c37-90645bd45967
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837726894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1837726894
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2890700978
Short name T250
Test name
Test status
Simulation time 2280901644 ps
CPU time 28.9 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:59 PM PST 24
Peak memory 223112 kb
Host smart-4b7e3cc7-b6e7-402e-b83d-78df1bd8ab2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890700978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2890700978
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2354306646
Short name T311
Test name
Test status
Simulation time 5365755140 ps
CPU time 27.44 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:12:02 PM PST 24
Peak memory 216452 kb
Host smart-01cb8edc-7a1c-43bc-aaab-12da95582d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354306646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2354306646
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3540906468
Short name T148
Test name
Test status
Simulation time 385918183 ps
CPU time 5.4 seconds
Started Feb 07 02:17:03 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 208856 kb
Host smart-208b7263-0fea-45af-84ee-795f5315f9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540906468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3540906468
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2142870597
Short name T155
Test name
Test status
Simulation time 683809061 ps
CPU time 7.15 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:19 PM PST 24
Peak memory 209280 kb
Host smart-7fdd45dd-b7d5-4f08-b355-9529747b4c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142870597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2142870597
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4149400840
Short name T164
Test name
Test status
Simulation time 814670400 ps
CPU time 16.1 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 214012 kb
Host smart-3129fe5f-8173-4e3a-b16c-4bde8ae7133a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149400840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4149400840
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2201190852
Short name T30
Test name
Test status
Simulation time 3722892937 ps
CPU time 13.77 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 222564 kb
Host smart-3e635673-f373-4983-9eec-eae72cf63ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201190852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2201190852
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1218987059
Short name T73
Test name
Test status
Simulation time 81495334 ps
CPU time 3.68 seconds
Started Feb 07 02:15:03 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 223004 kb
Host smart-a9f7644d-2432-4535-8cb3-9599ccccadac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218987059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1218987059
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1992582062
Short name T154
Test name
Test status
Simulation time 50913467 ps
CPU time 2.75 seconds
Started Feb 07 02:15:21 PM PST 24
Finished Feb 07 02:15:25 PM PST 24
Peak memory 210236 kb
Host smart-b2a5df80-24c6-4263-b820-02f180030659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992582062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1992582062
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3376864861
Short name T144
Test name
Test status
Simulation time 251637646 ps
CPU time 3.54 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 218272 kb
Host smart-b7d39a69-100c-4966-b78f-a4f0ede7ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376864861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3376864861
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2002974914
Short name T415
Test name
Test status
Simulation time 310810236 ps
CPU time 15.88 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:26 PM PST 24
Peak memory 214772 kb
Host smart-48f4005e-bad7-40a9-8068-a506d2de497b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002974914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2002974914
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4264217665
Short name T638
Test name
Test status
Simulation time 243514261 ps
CPU time 3.33 seconds
Started Feb 07 02:12:26 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 210680 kb
Host smart-4f6df073-4297-4a31-ab9c-4edb24147d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264217665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4264217665
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2008086971
Short name T807
Test name
Test status
Simulation time 266534730 ps
CPU time 4.13 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 208700 kb
Host smart-5b76cac9-fa29-42fc-870e-20d3847ec484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008086971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2008086971
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1714369939
Short name T1019
Test name
Test status
Simulation time 149104381 ps
CPU time 3.96 seconds
Started Feb 07 02:10:37 PM PST 24
Finished Feb 07 02:10:42 PM PST 24
Peak memory 210476 kb
Host smart-c05e5a8f-582a-492a-8e4e-e74561f627dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714369939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1714369939
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2294807065
Short name T350
Test name
Test status
Simulation time 2746066006 ps
CPU time 46.14 seconds
Started Feb 07 02:13:18 PM PST 24
Finished Feb 07 02:14:05 PM PST 24
Peak memory 216340 kb
Host smart-b3e27018-40ba-4889-bdf9-f44222b33e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294807065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2294807065
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3043432155
Short name T391
Test name
Test status
Simulation time 366255436 ps
CPU time 5.81 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:23 PM PST 24
Peak memory 214732 kb
Host smart-d17868dc-4b87-4760-96a8-a37529224fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043432155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3043432155
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2280149513
Short name T85
Test name
Test status
Simulation time 74398011 ps
CPU time 3.89 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 214840 kb
Host smart-740641b2-8907-4a96-b7e7-a608d36b6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280149513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2280149513
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.560324355
Short name T62
Test name
Test status
Simulation time 160977627 ps
CPU time 2.21 seconds
Started Feb 07 02:14:11 PM PST 24
Finished Feb 07 02:14:15 PM PST 24
Peak memory 211864 kb
Host smart-3fa63ec4-6c28-41d6-89fb-bf59f01a3fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560324355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.560324355
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2757386819
Short name T234
Test name
Test status
Simulation time 79476566 ps
CPU time 4.27 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:25 PM PST 24
Peak memory 211024 kb
Host smart-02ac6fbf-0b61-43e6-a92b-f62164e41e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757386819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2757386819
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1380658266
Short name T208
Test name
Test status
Simulation time 5131653831 ps
CPU time 32.54 seconds
Started Feb 07 02:14:36 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 223116 kb
Host smart-0127dcab-2d3c-4602-961f-df02f9e59dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380658266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1380658266
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.556738644
Short name T302
Test name
Test status
Simulation time 259946649 ps
CPU time 10.43 seconds
Started Feb 07 02:14:36 PM PST 24
Finished Feb 07 02:14:49 PM PST 24
Peak memory 214724 kb
Host smart-71cac024-f3b7-43f1-8c29-5a0f528269b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556738644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.556738644
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.341548069
Short name T235
Test name
Test status
Simulation time 434594153 ps
CPU time 3.68 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 211788 kb
Host smart-dac15ad7-ac6b-4216-bdab-650913ad1dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341548069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.341548069
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.779342273
Short name T308
Test name
Test status
Simulation time 32582790 ps
CPU time 2.49 seconds
Started Feb 07 02:11:17 PM PST 24
Finished Feb 07 02:11:20 PM PST 24
Peak memory 214740 kb
Host smart-ec44c800-3cae-4719-a27c-0d9c5f66dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779342273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.779342273
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3860455130
Short name T545
Test name
Test status
Simulation time 266677441 ps
CPU time 9.2 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:55 PM PST 24
Peak memory 205984 kb
Host smart-12311429-e9de-44a5-be29-b3bbd7e3d82e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860455130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
860455130
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2442636898
Short name T457
Test name
Test status
Simulation time 589886512 ps
CPU time 6.79 seconds
Started Feb 07 02:16:38 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 205960 kb
Host smart-879cbf67-f617-46cb-a27b-706de055df17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442636898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
442636898
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1658435548
Short name T527
Test name
Test status
Simulation time 16231858 ps
CPU time 1.21 seconds
Started Feb 07 02:16:34 PM PST 24
Finished Feb 07 02:16:38 PM PST 24
Peak memory 206004 kb
Host smart-0ca57db6-e37e-4a5b-af78-df6f07e9c304
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658435548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
658435548
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3613839490
Short name T544
Test name
Test status
Simulation time 65184846 ps
CPU time 1.04 seconds
Started Feb 07 02:16:36 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 205564 kb
Host smart-7a545769-5fc5-47fd-8fbf-7737895185b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613839490 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3613839490
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1989459606
Short name T572
Test name
Test status
Simulation time 162525892 ps
CPU time 0.97 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205732 kb
Host smart-f29a1e1a-cb38-4cbf-98d9-43ed63ce9e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989459606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1989459606
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2065104324
Short name T509
Test name
Test status
Simulation time 17178278 ps
CPU time 0.82 seconds
Started Feb 07 02:16:31 PM PST 24
Finished Feb 07 02:16:34 PM PST 24
Peak memory 205568 kb
Host smart-1cb8b6f6-011f-4e11-bd7e-72f4ac85917f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065104324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2065104324
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1297591517
Short name T539
Test name
Test status
Simulation time 47429460 ps
CPU time 1.86 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:41 PM PST 24
Peak memory 205936 kb
Host smart-8fa3d9a7-39ff-485f-bf7c-b7eee8e7b1b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297591517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1297591517
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2000783915
Short name T564
Test name
Test status
Simulation time 1241875161 ps
CPU time 21.28 seconds
Started Feb 07 02:16:22 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 214292 kb
Host smart-f17192dc-f2a1-4c8d-b6ec-1dcc47d59256
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000783915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2000783915
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3980687481
Short name T112
Test name
Test status
Simulation time 196587558 ps
CPU time 3.14 seconds
Started Feb 07 02:16:31 PM PST 24
Finished Feb 07 02:16:36 PM PST 24
Peak memory 214500 kb
Host smart-bbf55956-76c6-4f47-be85-c953e5b86c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980687481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3980687481
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1169558493
Short name T398
Test name
Test status
Simulation time 201978140 ps
CPU time 6.78 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:53 PM PST 24
Peak memory 209244 kb
Host smart-be41056f-c967-4ea2-b8e1-72f24041ea88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169558493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1169558493
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2087759349
Short name T129
Test name
Test status
Simulation time 1048043848 ps
CPU time 8.91 seconds
Started Feb 07 02:16:35 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 205908 kb
Host smart-e21d8cf9-3784-40ac-90de-f6b3734ca9cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087759349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
087759349
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1338020025
Short name T563
Test name
Test status
Simulation time 305477535 ps
CPU time 12.18 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:51 PM PST 24
Peak memory 205960 kb
Host smart-b6247add-52d3-4e84-9d1b-b744606ac72b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338020025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
338020025
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1418966881
Short name T508
Test name
Test status
Simulation time 123511188 ps
CPU time 1.1 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:40 PM PST 24
Peak memory 205964 kb
Host smart-1e4fd5d2-bbaa-4477-b7b2-cc3603e1b4a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418966881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
418966881
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1630331837
Short name T532
Test name
Test status
Simulation time 43704614 ps
CPU time 1.26 seconds
Started Feb 07 02:16:39 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 214024 kb
Host smart-3f96d933-2689-421b-be95-d8029466ac04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630331837 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1630331837
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2421005133
Short name T467
Test name
Test status
Simulation time 27497494 ps
CPU time 1.19 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:40 PM PST 24
Peak memory 205836 kb
Host smart-9b728512-6f3b-47bd-947f-32f8a19e65e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421005133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2421005133
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1576728046
Short name T465
Test name
Test status
Simulation time 11389863 ps
CPU time 0.78 seconds
Started Feb 07 02:16:30 PM PST 24
Finished Feb 07 02:16:34 PM PST 24
Peak memory 205584 kb
Host smart-8c1d1d19-f1c7-4fc5-b3f1-73214ed283b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576728046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1576728046
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2437550511
Short name T133
Test name
Test status
Simulation time 211853812 ps
CPU time 2.6 seconds
Started Feb 07 02:16:31 PM PST 24
Finished Feb 07 02:16:38 PM PST 24
Peak memory 205916 kb
Host smart-9b181e11-e814-4614-9d8c-492a06744d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437550511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2437550511
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3248869477
Short name T519
Test name
Test status
Simulation time 854534245 ps
CPU time 3.08 seconds
Started Feb 07 02:16:32 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 214400 kb
Host smart-1edf5e30-4528-4b4a-8619-0f94e6026a00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248869477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3248869477
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3949800731
Short name T555
Test name
Test status
Simulation time 140361106 ps
CPU time 6.62 seconds
Started Feb 07 02:16:35 PM PST 24
Finished Feb 07 02:16:44 PM PST 24
Peak memory 214488 kb
Host smart-1f7c175e-c3d1-4da1-97c1-024e06e201ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949800731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3949800731
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.945828636
Short name T471
Test name
Test status
Simulation time 177652032 ps
CPU time 2.49 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:49 PM PST 24
Peak memory 216024 kb
Host smart-83a94fa4-763f-4d71-bdb6-1edfee2a40b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945828636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.945828636
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2069942108
Short name T156
Test name
Test status
Simulation time 254501233 ps
CPU time 6.39 seconds
Started Feb 07 02:16:39 PM PST 24
Finished Feb 07 02:16:50 PM PST 24
Peak memory 209484 kb
Host smart-f93eeefe-90f4-4358-ac34-af105daca134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069942108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2069942108
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2884068953
Short name T529
Test name
Test status
Simulation time 26502192 ps
CPU time 1.45 seconds
Started Feb 07 02:16:57 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 214016 kb
Host smart-03a0cb5c-02a5-4e59-a8e2-1fa70c2e361b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884068953 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2884068953
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.958950700
Short name T523
Test name
Test status
Simulation time 18081178 ps
CPU time 1.13 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 205928 kb
Host smart-ad3c6df7-e8f6-432e-a5d7-3ff7c45ac514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958950700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.958950700
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2471617502
Short name T575
Test name
Test status
Simulation time 30536518 ps
CPU time 0.75 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:04 PM PST 24
Peak memory 205660 kb
Host smart-e53d90af-0d32-4d79-8b16-5b642db70d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471617502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2471617502
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4286137663
Short name T502
Test name
Test status
Simulation time 274900243 ps
CPU time 2.3 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 206024 kb
Host smart-97d262df-0f3d-4d18-aa75-1a8539b3b93d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286137663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4286137663
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2858134410
Short name T470
Test name
Test status
Simulation time 171320179 ps
CPU time 6.22 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:17:00 PM PST 24
Peak memory 214376 kb
Host smart-0ef2f8b8-9e74-49ac-9ff8-aedf2af230c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858134410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2858134410
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1372813070
Short name T109
Test name
Test status
Simulation time 48356589 ps
CPU time 1.64 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 205860 kb
Host smart-2e2bd1fa-7f3c-4112-a673-c2a885db4492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372813070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1372813070
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1795423274
Short name T166
Test name
Test status
Simulation time 495063978 ps
CPU time 6.16 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:08 PM PST 24
Peak memory 214148 kb
Host smart-4d46963d-a5c5-425d-b375-d201fe666d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795423274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1795423274
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3752361134
Short name T568
Test name
Test status
Simulation time 18438531 ps
CPU time 1.24 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 213980 kb
Host smart-4ea47eeb-5878-474f-b73e-99c46c3bc29b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752361134 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3752361134
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2346201213
Short name T132
Test name
Test status
Simulation time 28141695 ps
CPU time 0.88 seconds
Started Feb 07 02:16:58 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 205720 kb
Host smart-ed8ab813-caca-4a75-a4c1-5622b6397e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346201213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2346201213
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1361026109
Short name T483
Test name
Test status
Simulation time 39246960 ps
CPU time 0.74 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:02 PM PST 24
Peak memory 205480 kb
Host smart-429f75f4-1b59-4133-a8ca-71ea484ae9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361026109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1361026109
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1658249022
Short name T518
Test name
Test status
Simulation time 369554463 ps
CPU time 2.53 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 205920 kb
Host smart-13ca4f25-0314-4a53-bcb5-92836c616d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658249022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1658249022
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1712123144
Short name T167
Test name
Test status
Simulation time 138790889 ps
CPU time 3.93 seconds
Started Feb 07 02:16:59 PM PST 24
Finished Feb 07 02:17:08 PM PST 24
Peak memory 222580 kb
Host smart-0a63dd37-a3d9-4911-876c-df49a85ceabd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712123144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1712123144
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3476330853
Short name T513
Test name
Test status
Simulation time 214335837 ps
CPU time 7.82 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 214404 kb
Host smart-cea04409-f95f-46d8-9e15-565a8f60b8a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476330853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3476330853
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2638739222
Short name T530
Test name
Test status
Simulation time 183708446 ps
CPU time 2.77 seconds
Started Feb 07 02:16:58 PM PST 24
Finished Feb 07 02:17:07 PM PST 24
Peak memory 213536 kb
Host smart-c963ecce-46e9-424e-bf18-9e775dce4e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638739222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2638739222
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1184945168
Short name T113
Test name
Test status
Simulation time 259266989 ps
CPU time 3.52 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 208136 kb
Host smart-cfe1388d-1c10-4d1a-b3c2-1dd78917e986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184945168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1184945168
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.381049126
Short name T507
Test name
Test status
Simulation time 53628499 ps
CPU time 1.16 seconds
Started Feb 07 02:16:58 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 214144 kb
Host smart-2f9ec03d-2dd6-4ccb-81b1-78fa558054cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381049126 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.381049126
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2114640729
Short name T535
Test name
Test status
Simulation time 101293154 ps
CPU time 1.22 seconds
Started Feb 07 02:16:57 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 205980 kb
Host smart-c5f5eaa9-67db-40f3-ac65-697a367e5674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114640729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2114640729
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1475779082
Short name T131
Test name
Test status
Simulation time 55667193 ps
CPU time 0.8 seconds
Started Feb 07 02:17:00 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 205512 kb
Host smart-55917c17-5bae-4d70-90f6-55b44d82e163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475779082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1475779082
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.295840385
Short name T511
Test name
Test status
Simulation time 125044030 ps
CPU time 2.27 seconds
Started Feb 07 02:17:02 PM PST 24
Finished Feb 07 02:17:08 PM PST 24
Peak memory 205912 kb
Host smart-f1367625-e1bd-4b4f-ac6a-44cd24f059d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295840385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.295840385
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.349516710
Short name T102
Test name
Test status
Simulation time 356525743 ps
CPU time 2.84 seconds
Started Feb 07 02:17:00 PM PST 24
Finished Feb 07 02:17:07 PM PST 24
Peak memory 214404 kb
Host smart-94da0dd5-7bbc-42f3-8485-20cd71695adf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349516710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.349516710
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1928218604
Short name T500
Test name
Test status
Simulation time 134046227 ps
CPU time 3.9 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:07 PM PST 24
Peak memory 214408 kb
Host smart-12508871-641f-4c5f-8cf2-4112c6393c20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928218604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1928218604
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3790358378
Short name T515
Test name
Test status
Simulation time 109710286 ps
CPU time 1.6 seconds
Started Feb 07 02:16:57 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 214032 kb
Host smart-bbfa58b7-6264-4247-87e1-4e9fee22f7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790358378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3790358378
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.869330864
Short name T171
Test name
Test status
Simulation time 21794650 ps
CPU time 1.03 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 205620 kb
Host smart-c04370b2-40e2-4031-99e3-78d46db38e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869330864 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.869330864
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.224165046
Short name T542
Test name
Test status
Simulation time 43051707 ps
CPU time 0.95 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 205540 kb
Host smart-19848e9b-8f50-4ab1-b6d4-c2cf94670680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224165046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.224165046
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.790934416
Short name T177
Test name
Test status
Simulation time 13912845 ps
CPU time 0.84 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:09 PM PST 24
Peak memory 205600 kb
Host smart-a357f06b-7ee1-4916-b0b8-8b51178cf275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790934416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.790934416
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3175953620
Short name T451
Test name
Test status
Simulation time 180591037 ps
CPU time 2.54 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 205928 kb
Host smart-0e75d687-e5b7-4713-9b1a-65a347c325e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175953620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3175953620
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.83789904
Short name T169
Test name
Test status
Simulation time 424365800 ps
CPU time 3.55 seconds
Started Feb 07 02:16:58 PM PST 24
Finished Feb 07 02:17:08 PM PST 24
Peak memory 214424 kb
Host smart-033ebfc1-f72f-458b-ac5a-6f53673ab7bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83789904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow
_reg_errors.83789904
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2565082889
Short name T576
Test name
Test status
Simulation time 343820692 ps
CPU time 6.91 seconds
Started Feb 07 02:17:00 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 214236 kb
Host smart-7cf856eb-eaef-443e-a808-ea585ac5ab48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565082889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2565082889
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.595197607
Short name T459
Test name
Test status
Simulation time 255249342 ps
CPU time 2.56 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 214016 kb
Host smart-02fd97b0-6851-4898-98b5-2766ddd9beb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595197607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.595197607
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.270634353
Short name T170
Test name
Test status
Simulation time 23994791 ps
CPU time 1.2 seconds
Started Feb 07 02:17:03 PM PST 24
Finished Feb 07 02:17:09 PM PST 24
Peak memory 205840 kb
Host smart-cb0895a2-aa3a-4d8f-bd59-a1837dcf4864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270634353 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.270634353
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1690726560
Short name T489
Test name
Test status
Simulation time 86813315 ps
CPU time 1 seconds
Started Feb 07 02:17:03 PM PST 24
Finished Feb 07 02:17:09 PM PST 24
Peak memory 205924 kb
Host smart-a5a25c19-e7ff-4400-b284-d870bcfde441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690726560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1690726560
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.906530433
Short name T448
Test name
Test status
Simulation time 12682298 ps
CPU time 0.73 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:09 PM PST 24
Peak memory 205516 kb
Host smart-9e93432c-1782-42e6-92fa-6475c0c4a399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906530433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.906530433
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1250263011
Short name T547
Test name
Test status
Simulation time 93875243 ps
CPU time 1.58 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205848 kb
Host smart-8f45a58a-74f1-48be-ac67-4940aadc88ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250263011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1250263011
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.129199362
Short name T581
Test name
Test status
Simulation time 167629008 ps
CPU time 3.5 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 214396 kb
Host smart-03666905-995f-4829-a42e-4d7d6f7ffede
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129199362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.129199362
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1795599453
Short name T481
Test name
Test status
Simulation time 503079337 ps
CPU time 7.9 seconds
Started Feb 07 02:17:04 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 214416 kb
Host smart-a6bc5456-b6ec-4e16-a55b-23b97dcd0c18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795599453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1795599453
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3691832121
Short name T512
Test name
Test status
Simulation time 47756237 ps
CPU time 2.45 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 216352 kb
Host smart-539b0080-38d0-49d9-9460-b6c9c6c42fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691832121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3691832121
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3226645656
Short name T165
Test name
Test status
Simulation time 204192250 ps
CPU time 3.34 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 222216 kb
Host smart-6d4e567b-7271-45a4-b929-3955e66a6811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226645656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3226645656
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1891990254
Short name T446
Test name
Test status
Simulation time 42262925 ps
CPU time 1.99 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 214124 kb
Host smart-82e3413a-dd42-4190-a725-01f056f6bf51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891990254 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1891990254
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.185682392
Short name T533
Test name
Test status
Simulation time 9911125 ps
CPU time 0.9 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205688 kb
Host smart-09a1e59a-f559-41d4-afe0-5d4bbb3e9211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185682392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.185682392
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.529197377
Short name T526
Test name
Test status
Simulation time 11774661 ps
CPU time 0.9 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 205552 kb
Host smart-8e656b82-fd15-4c34-a1ac-b0bf060fb491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529197377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.529197377
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.738637628
Short name T474
Test name
Test status
Simulation time 21513529 ps
CPU time 1.44 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205868 kb
Host smart-3c45d67f-f7c4-430c-8cd6-3873d60cd625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738637628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.738637628
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1765761044
Short name T485
Test name
Test status
Simulation time 185939909 ps
CPU time 4.56 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 214460 kb
Host smart-e0c70532-516d-4075-b04d-11e11f998bbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765761044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1765761044
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.668442571
Short name T514
Test name
Test status
Simulation time 215817653 ps
CPU time 5.41 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 214272 kb
Host smart-bc773e69-b4b9-4a3f-aba0-2144e8d42400
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668442571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.668442571
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4023456777
Short name T486
Test name
Test status
Simulation time 41619502 ps
CPU time 2.58 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 214072 kb
Host smart-0b6929a5-24af-4fbd-9407-72f9ecb4fad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023456777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4023456777
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2929827881
Short name T571
Test name
Test status
Simulation time 30373016 ps
CPU time 1.57 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 214056 kb
Host smart-e0150440-0a26-4de5-87c9-547152f154e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929827881 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2929827881
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.301354899
Short name T484
Test name
Test status
Simulation time 139258527 ps
CPU time 1.18 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 205936 kb
Host smart-1b07dbf1-49e9-4f45-a9ff-58a704ae60a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301354899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.301354899
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1333017101
Short name T466
Test name
Test status
Simulation time 26941596 ps
CPU time 0.78 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205496 kb
Host smart-5d8d2cba-86c8-4273-8764-aa7e77665b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333017101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1333017101
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.746561162
Short name T504
Test name
Test status
Simulation time 77351601 ps
CPU time 1.87 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205844 kb
Host smart-5ca6e5a9-c414-443a-91e7-8a94d5f646f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746561162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.746561162
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1320578195
Short name T104
Test name
Test status
Simulation time 456421078 ps
CPU time 3.24 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 214448 kb
Host smart-98fbc5a1-2463-45d3-a525-c536008f3259
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320578195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1320578195
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.238666995
Short name T480
Test name
Test status
Simulation time 2158365389 ps
CPU time 8.83 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 214412 kb
Host smart-0be7b056-87a5-4280-9a90-10b270b7a78e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238666995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.238666995
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1848747995
Short name T540
Test name
Test status
Simulation time 259439336 ps
CPU time 2.09 seconds
Started Feb 07 02:17:06 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 214000 kb
Host smart-2c7b1d87-4038-465c-b876-c97197df33ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848747995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1848747995
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.811543025
Short name T111
Test name
Test status
Simulation time 66812469 ps
CPU time 1.88 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 214064 kb
Host smart-086f69e7-ee45-4654-92b3-9a016289c535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811543025 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.811543025
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2869797406
Short name T492
Test name
Test status
Simulation time 76154752 ps
CPU time 0.94 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 205664 kb
Host smart-4ab011e3-4918-4894-aaa9-cc74faf02b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869797406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2869797406
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.814704825
Short name T579
Test name
Test status
Simulation time 33040129 ps
CPU time 0.83 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205632 kb
Host smart-4742f58a-a2ee-44cf-9800-f7a0eb7e82fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814704825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.814704825
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1534988248
Short name T578
Test name
Test status
Simulation time 304152217 ps
CPU time 2.54 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 205944 kb
Host smart-4738af0c-f7c2-48d4-ba57-b794b6e9b300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534988248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1534988248
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2357141258
Short name T520
Test name
Test status
Simulation time 375936770 ps
CPU time 3.14 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 214404 kb
Host smart-47dd9175-690e-4c3e-b4df-e8b2e76320f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357141258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2357141258
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1561811682
Short name T101
Test name
Test status
Simulation time 271930123 ps
CPU time 4.39 seconds
Started Feb 07 02:17:06 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 214480 kb
Host smart-50d78413-5c47-4a99-9ef0-095124a6bfc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561811682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1561811682
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.828407880
Short name T531
Test name
Test status
Simulation time 671651483 ps
CPU time 2.9 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 214112 kb
Host smart-50adf10d-0c22-4130-ba9c-14d0a447f12a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828407880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.828407880
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2368275264
Short name T469
Test name
Test status
Simulation time 45028579 ps
CPU time 1.17 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 205816 kb
Host smart-64ff71e9-ab03-45ee-b8f6-d18cecdc95df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368275264 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2368275264
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.484935183
Short name T551
Test name
Test status
Simulation time 77376004 ps
CPU time 1.03 seconds
Started Feb 07 02:17:07 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 205660 kb
Host smart-9cc9b5ca-dfc2-4ef9-9d3d-74f1442616c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484935183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.484935183
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2623182868
Short name T440
Test name
Test status
Simulation time 11621806 ps
CPU time 0.87 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:12 PM PST 24
Peak memory 205456 kb
Host smart-c3b7d3f3-5275-49ed-a3e7-6b375bc06eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623182868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2623182868
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3629165712
Short name T538
Test name
Test status
Simulation time 88844778 ps
CPU time 1.42 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 205908 kb
Host smart-dd05a59e-b211-4cee-85cd-0e502af725dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629165712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3629165712
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3081513294
Short name T522
Test name
Test status
Simulation time 948987468 ps
CPU time 5.42 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:21 PM PST 24
Peak memory 214416 kb
Host smart-839dcf3b-9111-4dc2-8f4f-6c2f43d715ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081513294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3081513294
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2555349820
Short name T494
Test name
Test status
Simulation time 2314697806 ps
CPU time 10.51 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 220144 kb
Host smart-4e824fad-3f99-4efd-b980-daa4cb935b36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555349820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2555349820
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3663392260
Short name T580
Test name
Test status
Simulation time 759109554 ps
CPU time 3.99 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 216388 kb
Host smart-da0232a9-70bf-4621-a69b-7dd7cfe24889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663392260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3663392260
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1725719158
Short name T569
Test name
Test status
Simulation time 24166080 ps
CPU time 1.58 seconds
Started Feb 07 02:17:10 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 214004 kb
Host smart-de077714-fa83-47e7-b35d-404970d2540f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725719158 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1725719158
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3669607734
Short name T128
Test name
Test status
Simulation time 20036450 ps
CPU time 0.88 seconds
Started Feb 07 02:17:09 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205688 kb
Host smart-bba7b42b-6281-4f56-be95-a3868834b557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669607734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3669607734
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2683957086
Short name T443
Test name
Test status
Simulation time 91774250 ps
CPU time 0.76 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 205576 kb
Host smart-23e7c615-f936-4780-8eef-e9ef98a58109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683957086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2683957086
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2765749750
Short name T525
Test name
Test status
Simulation time 1323331370 ps
CPU time 4.8 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:17 PM PST 24
Peak memory 205896 kb
Host smart-695da52e-eb6c-42a7-874d-da0732303059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765749750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2765749750
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3315670069
Short name T552
Test name
Test status
Simulation time 75493432 ps
CPU time 2.51 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 214308 kb
Host smart-097e42da-17ab-41b8-a174-d524bd65d3da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315670069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3315670069
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1644990955
Short name T570
Test name
Test status
Simulation time 262571440 ps
CPU time 5.37 seconds
Started Feb 07 02:17:15 PM PST 24
Finished Feb 07 02:17:22 PM PST 24
Peak memory 214436 kb
Host smart-b58e65be-177e-4c0e-bdc0-db2561e0348e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644990955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1644990955
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4017412977
Short name T464
Test name
Test status
Simulation time 80664232 ps
CPU time 2.8 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:18 PM PST 24
Peak memory 214056 kb
Host smart-9fbb7dc2-9944-4260-abb4-5d09e1e8d412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017412977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4017412977
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.823078606
Short name T452
Test name
Test status
Simulation time 268831655 ps
CPU time 7.9 seconds
Started Feb 07 02:16:34 PM PST 24
Finished Feb 07 02:16:45 PM PST 24
Peak memory 205904 kb
Host smart-3de851ec-681a-41c2-af62-98cef8be9016
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823078606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.823078606
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2111567796
Short name T473
Test name
Test status
Simulation time 669919674 ps
CPU time 8.04 seconds
Started Feb 07 02:16:34 PM PST 24
Finished Feb 07 02:16:45 PM PST 24
Peak memory 205916 kb
Host smart-31b6b7d6-e7e4-458d-adce-5475abd7cfc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111567796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
111567796
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3187245735
Short name T178
Test name
Test status
Simulation time 32488966 ps
CPU time 1.24 seconds
Started Feb 07 02:16:36 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 205784 kb
Host smart-3738f0f8-d01d-4b37-9f0e-aa975e714c14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187245735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
187245735
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2422742828
Short name T487
Test name
Test status
Simulation time 17404564 ps
CPU time 0.87 seconds
Started Feb 07 02:16:32 PM PST 24
Finished Feb 07 02:16:36 PM PST 24
Peak memory 205688 kb
Host smart-287d06d8-f867-45d5-b251-69e8d80cacb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422742828 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2422742828
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1061946890
Short name T124
Test name
Test status
Simulation time 15094531 ps
CPU time 1.25 seconds
Started Feb 07 02:16:38 PM PST 24
Finished Feb 07 02:16:41 PM PST 24
Peak memory 205876 kb
Host smart-dea300d2-9cea-4984-b595-e204943b786b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061946890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1061946890
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2374658153
Short name T450
Test name
Test status
Simulation time 10983329 ps
CPU time 0.74 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:40 PM PST 24
Peak memory 205572 kb
Host smart-92198073-4924-4ed3-833b-a8b0931b4ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374658153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2374658153
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1420401473
Short name T125
Test name
Test status
Simulation time 42054705 ps
CPU time 1.54 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:48 PM PST 24
Peak memory 205840 kb
Host smart-285a0d93-fa68-40c1-91c3-b6ebce7eded9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420401473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1420401473
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.228357275
Short name T558
Test name
Test status
Simulation time 87580368 ps
CPU time 3.06 seconds
Started Feb 07 02:16:35 PM PST 24
Finished Feb 07 02:16:40 PM PST 24
Peak memory 214284 kb
Host smart-9800f686-27ab-46ef-9341-475f79596653
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228357275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.228357275
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.275456052
Short name T172
Test name
Test status
Simulation time 89018955 ps
CPU time 3.44 seconds
Started Feb 07 02:16:32 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 213980 kb
Host smart-6ddb157d-3bd9-47aa-885d-68e39c9d5cac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275456052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.275456052
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4010765349
Short name T159
Test name
Test status
Simulation time 1681629073 ps
CPU time 13.49 seconds
Started Feb 07 02:16:35 PM PST 24
Finished Feb 07 02:16:51 PM PST 24
Peak memory 208384 kb
Host smart-85496d72-9f4d-4964-a152-6bb39ea8f89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010765349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4010765349
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2151315754
Short name T127
Test name
Test status
Simulation time 26010123 ps
CPU time 0.71 seconds
Started Feb 07 02:17:15 PM PST 24
Finished Feb 07 02:17:17 PM PST 24
Peak memory 205484 kb
Host smart-cc4eef71-fc84-48b5-a052-46c36b44f817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151315754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2151315754
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1657303408
Short name T516
Test name
Test status
Simulation time 25049537 ps
CPU time 0.7 seconds
Started Feb 07 02:17:08 PM PST 24
Finished Feb 07 02:17:11 PM PST 24
Peak memory 205452 kb
Host smart-e7bbf4c9-4058-43b6-be35-757de9ec8563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657303408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1657303408
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1722892788
Short name T475
Test name
Test status
Simulation time 53847774 ps
CPU time 0.89 seconds
Started Feb 07 02:17:17 PM PST 24
Finished Feb 07 02:17:19 PM PST 24
Peak memory 205784 kb
Host smart-23ec9c1e-e60c-4fbb-a540-826b786d87e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722892788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1722892788
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1826195922
Short name T130
Test name
Test status
Simulation time 24334406 ps
CPU time 0.9 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 205516 kb
Host smart-04ac2299-da70-4fae-aca3-13b8d8e833aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826195922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1826195922
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.350081950
Short name T447
Test name
Test status
Simulation time 37410824 ps
CPU time 0.75 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 205500 kb
Host smart-2fc4a525-ae66-4efe-b909-3897e31ecec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350081950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.350081950
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1414875701
Short name T556
Test name
Test status
Simulation time 49110869 ps
CPU time 0.85 seconds
Started Feb 07 02:17:16 PM PST 24
Finished Feb 07 02:17:18 PM PST 24
Peak memory 205504 kb
Host smart-4006e17f-5024-4220-bd64-982ea75d9ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414875701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1414875701
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2888362890
Short name T449
Test name
Test status
Simulation time 32929582 ps
CPU time 0.7 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:25 PM PST 24
Peak memory 205436 kb
Host smart-f0f27cc6-01ea-4b64-9e8f-13b038361b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888362890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2888362890
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2189445465
Short name T574
Test name
Test status
Simulation time 9712366 ps
CPU time 0.72 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205632 kb
Host smart-97c2af81-a5a7-4576-b06f-5098726c13af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189445465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2189445465
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2017755238
Short name T560
Test name
Test status
Simulation time 116472838 ps
CPU time 0.71 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205504 kb
Host smart-ff3745f9-18f2-4d3c-a4bd-7e799bcbf517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017755238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2017755238
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4215765132
Short name T175
Test name
Test status
Simulation time 19309448 ps
CPU time 0.75 seconds
Started Feb 07 02:17:13 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 205428 kb
Host smart-e1e8f571-086c-426b-a86d-4a1acd0c7898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215765132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4215765132
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3653119848
Short name T121
Test name
Test status
Simulation time 1494939087 ps
CPU time 14.98 seconds
Started Feb 07 02:16:42 PM PST 24
Finished Feb 07 02:17:01 PM PST 24
Peak memory 205868 kb
Host smart-1698b493-fe7c-495e-99c5-6eab427917b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653119848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
653119848
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3759614321
Short name T123
Test name
Test status
Simulation time 562049275 ps
CPU time 16.24 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:17:02 PM PST 24
Peak memory 205984 kb
Host smart-1c7b7506-390a-4dbf-a5b5-5300d9ae28c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759614321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
759614321
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2092400271
Short name T122
Test name
Test status
Simulation time 23152210 ps
CPU time 1.26 seconds
Started Feb 07 02:16:42 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205904 kb
Host smart-7969f166-afb4-4457-9928-3cdd205444cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092400271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
092400271
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4244944256
Short name T108
Test name
Test status
Simulation time 109622306 ps
CPU time 2.01 seconds
Started Feb 07 02:16:43 PM PST 24
Finished Feb 07 02:16:48 PM PST 24
Peak memory 205920 kb
Host smart-8f310cfa-f1b4-4f59-b78c-a78417e63396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244944256 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4244944256
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.626220681
Short name T399
Test name
Test status
Simulation time 23498988 ps
CPU time 0.88 seconds
Started Feb 07 02:16:42 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205612 kb
Host smart-33d3aa25-e3c0-4ed4-a291-bb7ac98d610f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626220681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.626220681
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1902415874
Short name T543
Test name
Test status
Simulation time 19886362 ps
CPU time 0.92 seconds
Started Feb 07 02:16:34 PM PST 24
Finished Feb 07 02:16:38 PM PST 24
Peak memory 205776 kb
Host smart-4d8ce435-975b-4013-8200-99744c2145aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902415874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1902415874
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2490676582
Short name T582
Test name
Test status
Simulation time 206759062 ps
CPU time 2.14 seconds
Started Feb 07 02:16:42 PM PST 24
Finished Feb 07 02:16:48 PM PST 24
Peak memory 205976 kb
Host smart-ad380a30-e42e-481e-9edb-69df47f2e1ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490676582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2490676582
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.618568529
Short name T493
Test name
Test status
Simulation time 91723528 ps
CPU time 2.9 seconds
Started Feb 07 02:16:38 PM PST 24
Finished Feb 07 02:16:42 PM PST 24
Peak memory 214300 kb
Host smart-89297e5d-a4d8-4732-8393-ce380037e4dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618568529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.618568529
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.27927171
Short name T461
Test name
Test status
Simulation time 904710008 ps
CPU time 10.89 seconds
Started Feb 07 02:16:32 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 214512 kb
Host smart-d6a0d8b6-d184-4d4a-8ed5-9dab67c33197
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27927171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ke
ymgr_shadow_reg_errors_with_csr_rw.27927171
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2222058430
Short name T110
Test name
Test status
Simulation time 51128148 ps
CPU time 1.79 seconds
Started Feb 07 02:16:36 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 221828 kb
Host smart-fc2ed8f7-6af2-4ff4-8f22-d2f96dc4c726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222058430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2222058430
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.542439613
Short name T158
Test name
Test status
Simulation time 193253165 ps
CPU time 5.4 seconds
Started Feb 07 02:16:37 PM PST 24
Finished Feb 07 02:16:44 PM PST 24
Peak memory 208696 kb
Host smart-359d29a0-f96e-4f68-8686-3fd8a13e5015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542439613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
542439613
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2060938779
Short name T445
Test name
Test status
Simulation time 20088391 ps
CPU time 0.77 seconds
Started Feb 07 02:17:17 PM PST 24
Finished Feb 07 02:17:19 PM PST 24
Peak memory 205604 kb
Host smart-5535f669-8383-4eb3-bf87-13cf8da4f240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060938779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2060938779
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.844877955
Short name T462
Test name
Test status
Simulation time 50362023 ps
CPU time 0.84 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205560 kb
Host smart-d02cffc0-50a7-4dda-86d7-698cd1f8608e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844877955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.844877955
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.76443600
Short name T444
Test name
Test status
Simulation time 11033061 ps
CPU time 0.75 seconds
Started Feb 07 02:17:18 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 205500 kb
Host smart-4d733b1d-9eb3-4bc7-8278-107da0039295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76443600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.76443600
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2041763212
Short name T565
Test name
Test status
Simulation time 25512935 ps
CPU time 0.71 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205436 kb
Host smart-d2611db1-daf7-4895-8bc4-b8e07697a734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041763212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2041763212
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2853160549
Short name T478
Test name
Test status
Simulation time 36998986 ps
CPU time 0.75 seconds
Started Feb 07 02:17:18 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 205556 kb
Host smart-61224a41-6b2b-4d20-94dc-8224dcebe8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853160549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2853160549
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1369489797
Short name T498
Test name
Test status
Simulation time 71069812 ps
CPU time 0.86 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205564 kb
Host smart-a4229226-e491-41e1-8c47-71ae1c31101d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369489797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1369489797
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1698748083
Short name T454
Test name
Test status
Simulation time 77479322 ps
CPU time 0.72 seconds
Started Feb 07 02:17:18 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 205484 kb
Host smart-9b73cdba-4436-4596-b2ff-913f0817c332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698748083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1698748083
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3262617288
Short name T460
Test name
Test status
Simulation time 27818724 ps
CPU time 0.74 seconds
Started Feb 07 02:17:14 PM PST 24
Finished Feb 07 02:17:16 PM PST 24
Peak memory 205584 kb
Host smart-45d9fea2-4b2f-4043-b185-eee2d28b56e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262617288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3262617288
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1116757464
Short name T472
Test name
Test status
Simulation time 17491974 ps
CPU time 0.81 seconds
Started Feb 07 02:17:19 PM PST 24
Finished Feb 07 02:17:21 PM PST 24
Peak memory 205532 kb
Host smart-eb388893-07e5-484b-8ba0-15ef4fc47a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116757464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1116757464
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2720802928
Short name T468
Test name
Test status
Simulation time 32980550 ps
CPU time 0.77 seconds
Started Feb 07 02:17:15 PM PST 24
Finished Feb 07 02:17:18 PM PST 24
Peak memory 205612 kb
Host smart-2ddf1893-4a8d-4e6a-9110-1fb2d04089ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720802928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2720802928
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1061819604
Short name T477
Test name
Test status
Simulation time 977805752 ps
CPU time 7.22 seconds
Started Feb 07 02:16:47 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205860 kb
Host smart-57504634-899e-4bca-91fa-084ce1ff15cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061819604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
061819604
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.770931538
Short name T541
Test name
Test status
Simulation time 458472765 ps
CPU time 6.72 seconds
Started Feb 07 02:16:44 PM PST 24
Finished Feb 07 02:16:53 PM PST 24
Peak memory 205904 kb
Host smart-42f6d5bc-e64b-4824-8b25-ef0bb8cc31f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770931538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.770931538
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3880581626
Short name T499
Test name
Test status
Simulation time 34862409 ps
CPU time 1.38 seconds
Started Feb 07 02:16:42 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205776 kb
Host smart-cb500377-6159-4a96-a632-e4e0d3c9e415
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880581626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
880581626
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.612333612
Short name T107
Test name
Test status
Simulation time 18195266 ps
CPU time 1.43 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 214000 kb
Host smart-3a100c55-ce26-4b76-9ae6-f549183a123c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612333612 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.612333612
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1953894687
Short name T120
Test name
Test status
Simulation time 24117744 ps
CPU time 0.92 seconds
Started Feb 07 02:16:43 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205640 kb
Host smart-b4eb5dc2-f411-46d8-9870-64e60522ae12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953894687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1953894687
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.266988523
Short name T441
Test name
Test status
Simulation time 19693836 ps
CPU time 0.72 seconds
Started Feb 07 02:16:43 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 205516 kb
Host smart-48b78c7c-c925-4571-a82e-001b857ca21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266988523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.266988523
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2004729409
Short name T501
Test name
Test status
Simulation time 235443541 ps
CPU time 1.75 seconds
Started Feb 07 02:16:40 PM PST 24
Finished Feb 07 02:16:47 PM PST 24
Peak memory 205992 kb
Host smart-bd56b68e-078e-4505-ae5f-105a0a7b8b01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004729409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2004729409
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1712552530
Short name T505
Test name
Test status
Simulation time 265343804 ps
CPU time 3.05 seconds
Started Feb 07 02:16:41 PM PST 24
Finished Feb 07 02:16:49 PM PST 24
Peak memory 214428 kb
Host smart-fb6d55b6-1137-4724-af5a-9c1078cb264d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712552530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1712552530
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.306849594
Short name T559
Test name
Test status
Simulation time 515610459 ps
CPU time 10.71 seconds
Started Feb 07 02:16:43 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 214476 kb
Host smart-93456ab6-1718-43db-8ba1-d52223edec12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306849594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.306849594
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.540957579
Short name T488
Test name
Test status
Simulation time 104697826 ps
CPU time 2.54 seconds
Started Feb 07 02:16:43 PM PST 24
Finished Feb 07 02:16:48 PM PST 24
Peak memory 213960 kb
Host smart-eca831cc-3787-4149-bddf-eec717997bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540957579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.540957579
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2700900541
Short name T149
Test name
Test status
Simulation time 230554737 ps
CPU time 3.64 seconds
Started Feb 07 02:16:41 PM PST 24
Finished Feb 07 02:16:49 PM PST 24
Peak memory 209424 kb
Host smart-c5ccba05-352b-431e-ada5-90ac5618c84f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700900541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2700900541
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.878850197
Short name T176
Test name
Test status
Simulation time 42631920 ps
CPU time 0.73 seconds
Started Feb 07 02:17:11 PM PST 24
Finished Feb 07 02:17:13 PM PST 24
Peak memory 205572 kb
Host smart-c55c0b0a-af94-4aec-88ac-cb7ce4f22ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878850197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.878850197
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2302202123
Short name T567
Test name
Test status
Simulation time 11568368 ps
CPU time 0.72 seconds
Started Feb 07 02:17:12 PM PST 24
Finished Feb 07 02:17:14 PM PST 24
Peak memory 205524 kb
Host smart-ce6aa1fe-15d9-4db5-a464-7db76727240a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302202123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2302202123
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4146812979
Short name T491
Test name
Test status
Simulation time 39009606 ps
CPU time 0.72 seconds
Started Feb 07 02:17:20 PM PST 24
Finished Feb 07 02:17:22 PM PST 24
Peak memory 205528 kb
Host smart-7c2878e0-27a7-483f-990e-ee7f89e8b955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146812979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4146812979
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.199198231
Short name T536
Test name
Test status
Simulation time 25000034 ps
CPU time 0.77 seconds
Started Feb 07 02:17:14 PM PST 24
Finished Feb 07 02:17:17 PM PST 24
Peak memory 205564 kb
Host smart-f5514def-10ef-4df1-8c23-507b95f8af35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199198231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.199198231
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1295842219
Short name T528
Test name
Test status
Simulation time 19339935 ps
CPU time 0.76 seconds
Started Feb 07 02:17:27 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 205556 kb
Host smart-da6df461-f4f5-4306-a469-b37eb48cde60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295842219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1295842219
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.197269277
Short name T496
Test name
Test status
Simulation time 13743571 ps
CPU time 0.69 seconds
Started Feb 07 02:17:23 PM PST 24
Finished Feb 07 02:17:25 PM PST 24
Peak memory 205564 kb
Host smart-0b1af1f0-35a7-4eaa-aaca-472bd24050f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197269277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.197269277
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1302313124
Short name T479
Test name
Test status
Simulation time 12045296 ps
CPU time 0.78 seconds
Started Feb 07 02:17:20 PM PST 24
Finished Feb 07 02:17:22 PM PST 24
Peak memory 205528 kb
Host smart-63ac0c66-b051-45cd-be20-5c89b288c9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302313124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1302313124
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3185424376
Short name T549
Test name
Test status
Simulation time 9535300 ps
CPU time 0.81 seconds
Started Feb 07 02:17:28 PM PST 24
Finished Feb 07 02:17:30 PM PST 24
Peak memory 205624 kb
Host smart-9dc6917e-d098-40fd-bba7-5908ea494a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185424376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3185424376
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2580165101
Short name T517
Test name
Test status
Simulation time 112009249 ps
CPU time 0.85 seconds
Started Feb 07 02:17:23 PM PST 24
Finished Feb 07 02:17:25 PM PST 24
Peak memory 205480 kb
Host smart-186a2ee0-b2e5-47a5-b6fd-74d8d48e6d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580165101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2580165101
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2255203549
Short name T566
Test name
Test status
Simulation time 14126722 ps
CPU time 0.87 seconds
Started Feb 07 02:17:26 PM PST 24
Finished Feb 07 02:17:27 PM PST 24
Peak memory 205596 kb
Host smart-71843785-af3e-407e-bd73-6a75c341179e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255203549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2255203549
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2571679034
Short name T495
Test name
Test status
Simulation time 96407422 ps
CPU time 1.1 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:04 PM PST 24
Peak memory 205800 kb
Host smart-344133ad-2078-4393-ab77-363cee61f144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571679034 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2571679034
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2619928111
Short name T553
Test name
Test status
Simulation time 36692875 ps
CPU time 1.22 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205868 kb
Host smart-00e101ba-384a-4a5d-8b2c-87bf8ae846f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619928111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2619928111
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.5147216
Short name T554
Test name
Test status
Simulation time 36564016 ps
CPU time 0.77 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205528 kb
Host smart-288807ae-497c-4e4b-86bc-f73d20eba6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5147216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.5147216
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.20936847
Short name T482
Test name
Test status
Simulation time 1609326814 ps
CPU time 3.48 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:58 PM PST 24
Peak memory 205964 kb
Host smart-4d18ba97-03b4-4bf9-b8d1-bf1b5553a7b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20936847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same
_csr_outstanding.20936847
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1232226176
Short name T534
Test name
Test status
Simulation time 218227060 ps
CPU time 5 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:07 PM PST 24
Peak memory 214404 kb
Host smart-f0f84e05-5a16-4922-b795-931abbe44ed2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232226176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1232226176
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3471449857
Short name T546
Test name
Test status
Simulation time 659086513 ps
CPU time 8.88 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 214404 kb
Host smart-4ec65d7a-9e99-4aa4-8e16-c347a98467df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471449857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3471449857
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2709971466
Short name T476
Test name
Test status
Simulation time 122834396 ps
CPU time 1.7 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 214088 kb
Host smart-26cb3608-cab4-4a55-bb50-173e68c2328a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709971466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2709971466
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1128948565
Short name T146
Test name
Test status
Simulation time 142174769 ps
CPU time 5.85 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:09 PM PST 24
Peak memory 208864 kb
Host smart-02fbe208-da44-42ee-923e-88693c07645c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128948565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1128948565
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3595218196
Short name T455
Test name
Test status
Simulation time 79251043 ps
CPU time 1.35 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 214032 kb
Host smart-a5cf9c8f-3e32-4a14-9c0d-41d4d4c58ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595218196 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3595218196
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.897376415
Short name T524
Test name
Test status
Simulation time 35787959 ps
CPU time 0.87 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205740 kb
Host smart-dbd47c4d-93cf-4390-b55f-b065d656e5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897376415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.897376415
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3679462417
Short name T584
Test name
Test status
Simulation time 13110102 ps
CPU time 0.83 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 205632 kb
Host smart-472c4a3f-4916-4199-8533-7f620f670175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679462417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3679462417
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3807975018
Short name T126
Test name
Test status
Simulation time 86573898 ps
CPU time 1.73 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:02 PM PST 24
Peak memory 205784 kb
Host smart-d7066ca0-9800-4265-8395-947491b18182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807975018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3807975018
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4251196132
Short name T97
Test name
Test status
Simulation time 332338086 ps
CPU time 5.78 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:01 PM PST 24
Peak memory 214364 kb
Host smart-1e0c1a59-3719-4b50-b6b5-412fdad071be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251196132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4251196132
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.510494974
Short name T463
Test name
Test status
Simulation time 778217689 ps
CPU time 4.99 seconds
Started Feb 07 02:16:52 PM PST 24
Finished Feb 07 02:16:58 PM PST 24
Peak memory 220144 kb
Host smart-d9a9215e-e7b5-426a-9857-d89ed4b453a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510494974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.510494974
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2861452761
Short name T583
Test name
Test status
Simulation time 79801612 ps
CPU time 2.5 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:58 PM PST 24
Peak memory 213996 kb
Host smart-843fff4c-1275-4142-a36c-5d017c10edc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861452761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2861452761
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.469828910
Short name T577
Test name
Test status
Simulation time 18074290 ps
CPU time 1.16 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205868 kb
Host smart-20bb082d-982b-47d5-80fa-ffb08dd959b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469828910 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.469828910
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.495296125
Short name T548
Test name
Test status
Simulation time 44979008 ps
CPU time 1.39 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:57 PM PST 24
Peak memory 205772 kb
Host smart-3cfe62b9-65a9-4a82-a252-8e9ed417fdce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495296125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.495296125
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3876324443
Short name T442
Test name
Test status
Simulation time 39255346 ps
CPU time 0.77 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205624 kb
Host smart-cbd9b505-1277-48dc-a4c0-e920e62a5e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876324443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3876324443
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.800249657
Short name T456
Test name
Test status
Simulation time 49837647 ps
CPU time 1.69 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205900 kb
Host smart-fd350653-abef-4f4d-93a3-8ef5c6768e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800249657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.800249657
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.945698606
Short name T99
Test name
Test status
Simulation time 815896276 ps
CPU time 7.73 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 214412 kb
Host smart-005576b1-70b0-4f99-a632-4a259e9f87b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945698606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.945698606
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1039934144
Short name T557
Test name
Test status
Simulation time 227459630 ps
CPU time 5.69 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 214492 kb
Host smart-54f3cefa-ec32-4510-b9a8-86008fd781b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039934144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1039934144
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.714577674
Short name T174
Test name
Test status
Simulation time 725396452 ps
CPU time 1.93 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:16:57 PM PST 24
Peak memory 214016 kb
Host smart-4971fa44-72ee-411b-a035-9fe1511c4126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714577674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.714577674
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.801688837
Short name T506
Test name
Test status
Simulation time 1147872933 ps
CPU time 9.02 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 208640 kb
Host smart-b3a4f9ea-b537-46ab-8d8d-8decebc598d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801688837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
801688837
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4074417974
Short name T562
Test name
Test status
Simulation time 40689589 ps
CPU time 1.62 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 214080 kb
Host smart-e91e1012-d1c4-44f5-98fd-53af76cc3f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074417974 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4074417974
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.21606801
Short name T550
Test name
Test status
Simulation time 15209652 ps
CPU time 1.11 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:56 PM PST 24
Peak memory 205772 kb
Host smart-922b8bc0-6013-4c55-8332-35446a8adf55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21606801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.21606801
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.97352845
Short name T521
Test name
Test status
Simulation time 10273920 ps
CPU time 0.87 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 205556 kb
Host smart-052aff49-c9ba-42c2-a0a9-bcc626a55600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97352845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.97352845
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3401123884
Short name T497
Test name
Test status
Simulation time 51076990 ps
CPU time 2.37 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 205916 kb
Host smart-8b738af8-cc33-420d-9057-46bc81da04f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401123884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3401123884
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1534266806
Short name T168
Test name
Test status
Simulation time 635179417 ps
CPU time 4.12 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:00 PM PST 24
Peak memory 210216 kb
Host smart-52edd729-6637-4c80-aced-9a0288fbb318
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534266806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1534266806
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1618947979
Short name T103
Test name
Test status
Simulation time 836718546 ps
CPU time 6.14 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:08 PM PST 24
Peak memory 214724 kb
Host smart-d96602b1-185c-40aa-9db0-654c2ac217bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618947979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1618947979
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4114560465
Short name T490
Test name
Test status
Simulation time 105474672 ps
CPU time 3 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 216332 kb
Host smart-a3320f9c-e33a-43c6-9689-708a6b682329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114560465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4114560465
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1422195627
Short name T561
Test name
Test status
Simulation time 245868179 ps
CPU time 1.56 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:58 PM PST 24
Peak memory 214068 kb
Host smart-4c63a488-b42b-4c99-b2dd-476b87782934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422195627 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1422195627
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3088421446
Short name T453
Test name
Test status
Simulation time 47176523 ps
CPU time 1.52 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:57 PM PST 24
Peak memory 205940 kb
Host smart-b267b7f4-851e-429a-b431-a6dea6630b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088421446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3088421446
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.530227265
Short name T503
Test name
Test status
Simulation time 11212791 ps
CPU time 0.72 seconds
Started Feb 07 02:16:56 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 205504 kb
Host smart-65adc89d-7108-4dff-9b1e-8c563ab7b4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530227265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.530227265
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.924567296
Short name T537
Test name
Test status
Simulation time 71897995 ps
CPU time 2.59 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:05 PM PST 24
Peak memory 205824 kb
Host smart-da7a0de2-84d9-475e-a6fd-e1a3c6f21496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924567296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.924567296
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1670574242
Short name T573
Test name
Test status
Simulation time 322633988 ps
CPU time 4.88 seconds
Started Feb 07 02:16:55 PM PST 24
Finished Feb 07 02:17:06 PM PST 24
Peak memory 214376 kb
Host smart-1b4661b2-ee57-45d0-a1e3-9550bd2a3e47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670574242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1670574242
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4066378685
Short name T134
Test name
Test status
Simulation time 743238892 ps
CPU time 7.23 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:17:03 PM PST 24
Peak memory 220132 kb
Host smart-ce1a16a5-a1cf-452b-a69d-a3fa13254276
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066378685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4066378685
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4235221103
Short name T458
Test name
Test status
Simulation time 36223624 ps
CPU time 1.8 seconds
Started Feb 07 02:16:54 PM PST 24
Finished Feb 07 02:16:58 PM PST 24
Peak memory 213936 kb
Host smart-eec9f1e0-f271-4e90-9e3e-54208e9ac27e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235221103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4235221103
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1787926951
Short name T150
Test name
Test status
Simulation time 1611049895 ps
CPU time 49.24 seconds
Started Feb 07 02:16:53 PM PST 24
Finished Feb 07 02:17:44 PM PST 24
Peak memory 211444 kb
Host smart-e3bf09d1-1448-4781-8397-2b52b6b5136e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787926951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1787926951
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1346626361
Short name T597
Test name
Test status
Simulation time 232503900 ps
CPU time 0.8 seconds
Started Feb 07 02:10:12 PM PST 24
Finished Feb 07 02:10:16 PM PST 24
Peak memory 206492 kb
Host smart-2fb7ff16-98c7-4fd9-ac6e-0d1ac19b2a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346626361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1346626361
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1347091617
Short name T256
Test name
Test status
Simulation time 101699235 ps
CPU time 4.02 seconds
Started Feb 07 02:10:12 PM PST 24
Finished Feb 07 02:10:18 PM PST 24
Peak memory 215332 kb
Host smart-3102f28f-e326-441e-b1ee-c860a675f7d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347091617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1347091617
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2607629304
Short name T932
Test name
Test status
Simulation time 358985009 ps
CPU time 4.2 seconds
Started Feb 07 02:10:11 PM PST 24
Finished Feb 07 02:10:18 PM PST 24
Peak memory 219876 kb
Host smart-2d1dd2ec-ce59-49f6-9c83-32d35db421c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607629304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2607629304
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3020467685
Short name T389
Test name
Test status
Simulation time 80350943 ps
CPU time 1.71 seconds
Started Feb 07 02:10:10 PM PST 24
Finished Feb 07 02:10:13 PM PST 24
Peak memory 207996 kb
Host smart-0246c864-6228-470b-99f8-96b362cd6af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020467685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3020467685
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.671413014
Short name T83
Test name
Test status
Simulation time 737667946 ps
CPU time 4.37 seconds
Started Feb 07 02:10:10 PM PST 24
Finished Feb 07 02:10:16 PM PST 24
Peak memory 214812 kb
Host smart-85ea5c61-4097-4684-8d64-9544c6290aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671413014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.671413014
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3931732000
Short name T301
Test name
Test status
Simulation time 80934938 ps
CPU time 2.9 seconds
Started Feb 07 02:10:10 PM PST 24
Finished Feb 07 02:10:14 PM PST 24
Peak memory 214816 kb
Host smart-a410e213-687e-4ca3-b32f-7ca691e72bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931732000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3931732000
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3668567040
Short name T1051
Test name
Test status
Simulation time 97917081 ps
CPU time 2.04 seconds
Started Feb 07 02:10:11 PM PST 24
Finished Feb 07 02:10:15 PM PST 24
Peak memory 206640 kb
Host smart-f3f94fc3-0d5a-4d08-ac56-1f9d628b9f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668567040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3668567040
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3557703125
Short name T96
Test name
Test status
Simulation time 493703633 ps
CPU time 6.02 seconds
Started Feb 07 02:09:55 PM PST 24
Finished Feb 07 02:10:04 PM PST 24
Peak memory 207568 kb
Host smart-c4b63630-02ad-452f-8f80-c7b8a018fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557703125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3557703125
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2614775832
Short name T11
Test name
Test status
Simulation time 336985920 ps
CPU time 11.65 seconds
Started Feb 07 02:10:12 PM PST 24
Finished Feb 07 02:10:26 PM PST 24
Peak memory 236588 kb
Host smart-7e1f489a-6bdb-4558-9a27-45c854cbb098
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614775832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2614775832
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.42396707
Short name T251
Test name
Test status
Simulation time 7961901064 ps
CPU time 47.56 seconds
Started Feb 07 02:09:55 PM PST 24
Finished Feb 07 02:10:45 PM PST 24
Peak memory 208156 kb
Host smart-746e14e9-5787-453a-b5d2-6087617b0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42396707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.42396707
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.656229951
Short name T698
Test name
Test status
Simulation time 1231443443 ps
CPU time 3.41 seconds
Started Feb 07 02:09:59 PM PST 24
Finished Feb 07 02:10:03 PM PST 24
Peak memory 208956 kb
Host smart-279266f5-f0c2-4116-9c91-f12db815056b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656229951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.656229951
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2677819982
Short name T608
Test name
Test status
Simulation time 213086709 ps
CPU time 3.26 seconds
Started Feb 07 02:09:59 PM PST 24
Finished Feb 07 02:10:03 PM PST 24
Peak memory 207184 kb
Host smart-24bde767-a78e-4435-9bf7-6482dc62be7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677819982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2677819982
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3535109357
Short name T907
Test name
Test status
Simulation time 3205103447 ps
CPU time 19.76 seconds
Started Feb 07 02:09:59 PM PST 24
Finished Feb 07 02:10:20 PM PST 24
Peak memory 208092 kb
Host smart-ace44d88-6c4a-4662-9ff6-169e95c650fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535109357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3535109357
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.201241405
Short name T1023
Test name
Test status
Simulation time 170917222 ps
CPU time 3.49 seconds
Started Feb 07 02:10:12 PM PST 24
Finished Feb 07 02:10:18 PM PST 24
Peak memory 214820 kb
Host smart-83df09df-9a50-4456-a431-d7f6ddac7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201241405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.201241405
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3357212065
Short name T942
Test name
Test status
Simulation time 1329728276 ps
CPU time 3.23 seconds
Started Feb 07 02:09:59 PM PST 24
Finished Feb 07 02:10:03 PM PST 24
Peak memory 207068 kb
Host smart-b1b0e2b5-4ef6-45ea-a2c3-03a3e7e34063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357212065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3357212065
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.891289305
Short name T248
Test name
Test status
Simulation time 778931647 ps
CPU time 8.11 seconds
Started Feb 07 02:10:11 PM PST 24
Finished Feb 07 02:10:22 PM PST 24
Peak memory 217752 kb
Host smart-e7265496-9e9e-46cc-885b-b1dbade4b685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891289305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.891289305
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2316646189
Short name T615
Test name
Test status
Simulation time 219293268 ps
CPU time 4.21 seconds
Started Feb 07 02:10:10 PM PST 24
Finished Feb 07 02:10:16 PM PST 24
Peak memory 222992 kb
Host smart-d2817f24-fdc4-4dcf-859d-23dad45964db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316646189 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2316646189
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.57664592
Short name T270
Test name
Test status
Simulation time 1845452645 ps
CPU time 11.49 seconds
Started Feb 07 02:10:11 PM PST 24
Finished Feb 07 02:10:25 PM PST 24
Peak memory 214832 kb
Host smart-23401a7a-8b0d-4a1b-8de8-964951a875ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57664592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.57664592
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3739869794
Short name T838
Test name
Test status
Simulation time 197012812 ps
CPU time 2.72 seconds
Started Feb 07 02:10:13 PM PST 24
Finished Feb 07 02:10:18 PM PST 24
Peak memory 210224 kb
Host smart-cd536318-5e32-4728-b908-4c6f46ceaa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739869794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3739869794
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2488785568
Short name T593
Test name
Test status
Simulation time 10808450 ps
CPU time 0.75 seconds
Started Feb 07 02:10:30 PM PST 24
Finished Feb 07 02:10:32 PM PST 24
Peak memory 206380 kb
Host smart-098d8f52-c405-4d63-918a-15a5d5f9a9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488785568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2488785568
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1580871208
Short name T375
Test name
Test status
Simulation time 193139175 ps
CPU time 3.78 seconds
Started Feb 07 02:10:16 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 215708 kb
Host smart-ca01684e-e606-4479-a89a-d912c511e69b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580871208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1580871208
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3869522196
Short name T61
Test name
Test status
Simulation time 1150090805 ps
CPU time 8.19 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:10:27 PM PST 24
Peak memory 210136 kb
Host smart-320926ce-39ff-4e1d-b916-e9dcdbced154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869522196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3869522196
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1605895729
Short name T734
Test name
Test status
Simulation time 227580070 ps
CPU time 1.75 seconds
Started Feb 07 02:10:16 PM PST 24
Finished Feb 07 02:10:19 PM PST 24
Peak memory 214796 kb
Host smart-ed42c2c6-09df-4c77-acca-02ecd9ec3c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605895729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1605895729
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1888346029
Short name T1022
Test name
Test status
Simulation time 402114307 ps
CPU time 4.78 seconds
Started Feb 07 02:10:18 PM PST 24
Finished Feb 07 02:10:24 PM PST 24
Peak memory 209660 kb
Host smart-23d2817c-5982-426c-b333-2157bc092d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888346029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1888346029
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1651004939
Short name T51
Test name
Test status
Simulation time 49307478 ps
CPU time 3.36 seconds
Started Feb 07 02:10:18 PM PST 24
Finished Feb 07 02:10:22 PM PST 24
Peak memory 214852 kb
Host smart-762ee064-dd7f-43be-bc50-604999a101c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651004939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1651004939
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1748655051
Short name T831
Test name
Test status
Simulation time 1253052789 ps
CPU time 8.71 seconds
Started Feb 07 02:10:15 PM PST 24
Finished Feb 07 02:10:25 PM PST 24
Peak memory 218940 kb
Host smart-fd1b00fe-e12f-4372-9b43-6d127d7ac30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748655051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1748655051
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2669671163
Short name T91
Test name
Test status
Simulation time 2927085011 ps
CPU time 67.7 seconds
Started Feb 07 02:10:27 PM PST 24
Finished Feb 07 02:11:36 PM PST 24
Peak memory 247920 kb
Host smart-63a80c61-d61e-4cd9-b9e9-b492c40c23d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669671163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2669671163
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.144029651
Short name T832
Test name
Test status
Simulation time 889290560 ps
CPU time 2.96 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 208400 kb
Host smart-e7c6a66d-72d3-46e7-a6cd-eeede88e4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144029651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.144029651
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.621267955
Short name T870
Test name
Test status
Simulation time 165256633 ps
CPU time 1.81 seconds
Started Feb 07 02:10:19 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 207180 kb
Host smart-f5bcb639-f38e-4bba-9129-fe19fa15f7e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621267955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.621267955
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1342490970
Short name T961
Test name
Test status
Simulation time 34554984 ps
CPU time 2.36 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:10:20 PM PST 24
Peak memory 207152 kb
Host smart-ebb5d48a-53ab-4a0d-888a-72e858c6837b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342490970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1342490970
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1810822740
Short name T293
Test name
Test status
Simulation time 109792840 ps
CPU time 2.34 seconds
Started Feb 07 02:10:18 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 209036 kb
Host smart-15ad004d-16a1-431c-8b80-15f1acb2556a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810822740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1810822740
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2119189578
Short name T890
Test name
Test status
Simulation time 118788333 ps
CPU time 1.94 seconds
Started Feb 07 02:10:19 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 208084 kb
Host smart-0bed2c29-4fe6-491d-a756-071f72a9a825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119189578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2119189578
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.621180046
Short name T800
Test name
Test status
Simulation time 249494585 ps
CPU time 3.02 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:10:21 PM PST 24
Peak memory 208620 kb
Host smart-4872ee14-bbeb-4793-9ff2-da056189fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621180046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.621180046
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.35225424
Short name T52
Test name
Test status
Simulation time 2335988992 ps
CPU time 25.6 seconds
Started Feb 07 02:10:29 PM PST 24
Finished Feb 07 02:10:55 PM PST 24
Peak memory 214900 kb
Host smart-ea9e4c30-ab23-4872-aae0-a09d692f6837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35225424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.35225424
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2800347743
Short name T405
Test name
Test status
Simulation time 241679092 ps
CPU time 4.29 seconds
Started Feb 07 02:10:17 PM PST 24
Finished Feb 07 02:10:23 PM PST 24
Peak memory 214688 kb
Host smart-e98da40f-6cc2-431f-bfeb-e8fefd233f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800347743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2800347743
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.283479971
Short name T1078
Test name
Test status
Simulation time 180218835 ps
CPU time 2.19 seconds
Started Feb 07 02:10:31 PM PST 24
Finished Feb 07 02:10:34 PM PST 24
Peak memory 210332 kb
Host smart-4775ba1d-ae3d-43df-92fa-7a5da15aded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283479971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.283479971
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.957231822
Short name T989
Test name
Test status
Simulation time 13403674 ps
CPU time 0.91 seconds
Started Feb 07 02:12:01 PM PST 24
Finished Feb 07 02:12:02 PM PST 24
Peak memory 206316 kb
Host smart-a1e9a1e8-df9b-4dbb-b54e-80e5cac315b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957231822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.957231822
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2120517502
Short name T246
Test name
Test status
Simulation time 421830961 ps
CPU time 6.28 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:17 PM PST 24
Peak memory 215832 kb
Host smart-b77c479b-c821-4943-8ecd-b6a002e4591d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120517502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2120517502
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3946924590
Short name T335
Test name
Test status
Simulation time 703918906 ps
CPU time 21.2 seconds
Started Feb 07 02:12:02 PM PST 24
Finished Feb 07 02:12:24 PM PST 24
Peak memory 214788 kb
Host smart-1f7b1f94-a6f4-428c-b8df-b91a1bbf0dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946924590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3946924590
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1293522785
Short name T888
Test name
Test status
Simulation time 28251328 ps
CPU time 2.02 seconds
Started Feb 07 02:12:02 PM PST 24
Finished Feb 07 02:12:05 PM PST 24
Peak memory 209796 kb
Host smart-8c25500b-caa4-46c0-b25d-73aa66b05cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293522785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1293522785
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1821224461
Short name T18
Test name
Test status
Simulation time 144239795 ps
CPU time 5.73 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:15 PM PST 24
Peak memory 220300 kb
Host smart-0253ca30-5194-46a7-9a19-d08525f2cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821224461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1821224461
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1142126838
Short name T931
Test name
Test status
Simulation time 70196876 ps
CPU time 3.54 seconds
Started Feb 07 02:12:06 PM PST 24
Finished Feb 07 02:12:11 PM PST 24
Peak memory 211300 kb
Host smart-3be59d86-1a28-4acb-abe8-b85f3897a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142126838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1142126838
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.1691392498
Short name T766
Test name
Test status
Simulation time 2637406008 ps
CPU time 28.53 seconds
Started Feb 07 02:11:51 PM PST 24
Finished Feb 07 02:12:24 PM PST 24
Peak memory 208884 kb
Host smart-d93c580e-ab3f-4c2e-afef-2ecd95b4f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691392498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1691392498
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.695461378
Short name T646
Test name
Test status
Simulation time 426492310 ps
CPU time 10.85 seconds
Started Feb 07 02:11:51 PM PST 24
Finished Feb 07 02:12:07 PM PST 24
Peak memory 208988 kb
Host smart-c38e7a89-846e-46e4-a8e4-740c9033105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695461378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.695461378
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.468476051
Short name T835
Test name
Test status
Simulation time 217945044 ps
CPU time 3.02 seconds
Started Feb 07 02:11:55 PM PST 24
Finished Feb 07 02:12:00 PM PST 24
Peak memory 207028 kb
Host smart-97f326e5-5d9d-41ce-b92c-669c94094c03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468476051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.468476051
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3630158443
Short name T1010
Test name
Test status
Simulation time 240183621 ps
CPU time 3.2 seconds
Started Feb 07 02:11:54 PM PST 24
Finished Feb 07 02:12:00 PM PST 24
Peak memory 207020 kb
Host smart-664c7c25-7e7a-40f2-b8b7-0942f03d66a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630158443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3630158443
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2422494798
Short name T707
Test name
Test status
Simulation time 2941634408 ps
CPU time 9.81 seconds
Started Feb 07 02:11:51 PM PST 24
Finished Feb 07 02:12:06 PM PST 24
Peak memory 209320 kb
Host smart-6c5cecdf-f58d-4a71-918e-042144c258d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422494798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2422494798
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.462052056
Short name T954
Test name
Test status
Simulation time 164953928 ps
CPU time 2.35 seconds
Started Feb 07 02:12:04 PM PST 24
Finished Feb 07 02:12:07 PM PST 24
Peak memory 214892 kb
Host smart-d037062c-702b-45fd-80a7-3ddadb66d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462052056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.462052056
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3075201165
Short name T839
Test name
Test status
Simulation time 2884166511 ps
CPU time 45.72 seconds
Started Feb 07 02:11:48 PM PST 24
Finished Feb 07 02:12:34 PM PST 24
Peak memory 209372 kb
Host smart-ea3d2827-90cb-413e-b3c9-26d6bf2484f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075201165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3075201165
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.489936087
Short name T349
Test name
Test status
Simulation time 2758846679 ps
CPU time 19.86 seconds
Started Feb 07 02:12:05 PM PST 24
Finished Feb 07 02:12:26 PM PST 24
Peak memory 223036 kb
Host smart-f3c312a0-8c51-4e3f-955c-ea7dd11ce0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489936087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.489936087
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.19973930
Short name T854
Test name
Test status
Simulation time 340771527 ps
CPU time 11.22 seconds
Started Feb 07 02:12:01 PM PST 24
Finished Feb 07 02:12:13 PM PST 24
Peak memory 223136 kb
Host smart-4ddfee61-1028-4815-97e8-451dddc20709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973930 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.19973930
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2967841641
Short name T218
Test name
Test status
Simulation time 1120143983 ps
CPU time 11.27 seconds
Started Feb 07 02:12:04 PM PST 24
Finished Feb 07 02:12:17 PM PST 24
Peak memory 207616 kb
Host smart-c39b3826-3133-4119-a9c3-aaf239dd3794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967841641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2967841641
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.531452363
Short name T710
Test name
Test status
Simulation time 64715227 ps
CPU time 3.24 seconds
Started Feb 07 02:12:04 PM PST 24
Finished Feb 07 02:12:08 PM PST 24
Peak memory 210416 kb
Host smart-98cf278e-b668-4552-9492-6de43c6b444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531452363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.531452363
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3026662050
Short name T1041
Test name
Test status
Simulation time 38097098 ps
CPU time 0.79 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:12 PM PST 24
Peak memory 206456 kb
Host smart-9179427e-418f-4287-8de5-d1317ccaf79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026662050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3026662050
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.100710704
Short name T1029
Test name
Test status
Simulation time 327156208 ps
CPU time 3.1 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 214812 kb
Host smart-d1f93679-afb2-4490-8730-7b15f0564afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100710704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.100710704
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2245831006
Short name T841
Test name
Test status
Simulation time 846660740 ps
CPU time 5.49 seconds
Started Feb 07 02:12:10 PM PST 24
Finished Feb 07 02:12:21 PM PST 24
Peak memory 210824 kb
Host smart-8fe9e11b-8ec4-4370-8cf5-3e4aaff842a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245831006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2245831006
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4271903099
Short name T43
Test name
Test status
Simulation time 101985372 ps
CPU time 3.12 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 209056 kb
Host smart-29b55e0e-a869-417f-b2f8-1b9defab465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271903099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4271903099
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1996967227
Short name T306
Test name
Test status
Simulation time 525473907 ps
CPU time 5.42 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:22 PM PST 24
Peak memory 214836 kb
Host smart-1c79f25c-7134-4958-b41c-cf87b2c76498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996967227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1996967227
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3147999736
Short name T1085
Test name
Test status
Simulation time 896209001 ps
CPU time 7.26 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:24 PM PST 24
Peak memory 222876 kb
Host smart-e846d10b-f55b-42a1-a099-c0760d1a1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147999736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3147999736
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1245746227
Short name T728
Test name
Test status
Simulation time 581753542 ps
CPU time 8.75 seconds
Started Feb 07 02:12:15 PM PST 24
Finished Feb 07 02:12:26 PM PST 24
Peak memory 209652 kb
Host smart-78125ed1-f915-42cd-afc0-2a485e3a7be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245746227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1245746227
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1269943400
Short name T247
Test name
Test status
Simulation time 35133476 ps
CPU time 2.43 seconds
Started Feb 07 02:12:01 PM PST 24
Finished Feb 07 02:12:04 PM PST 24
Peak memory 208988 kb
Host smart-23431ac2-7fcb-4229-b13f-69baf864e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269943400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1269943400
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3747394036
Short name T585
Test name
Test status
Simulation time 273897247 ps
CPU time 5.45 seconds
Started Feb 07 02:12:10 PM PST 24
Finished Feb 07 02:12:17 PM PST 24
Peak memory 209060 kb
Host smart-ea279b9a-ba03-4fdc-a832-484faac9cd9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747394036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3747394036
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.753500044
Short name T1086
Test name
Test status
Simulation time 375955722 ps
CPU time 3.15 seconds
Started Feb 07 02:12:10 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 207024 kb
Host smart-e2990fea-22e4-4aa7-9155-e3399e8e4e0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753500044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.753500044
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.288576197
Short name T1012
Test name
Test status
Simulation time 135985430 ps
CPU time 4.29 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:21 PM PST 24
Peak memory 208920 kb
Host smart-006a59c7-c987-4471-9324-aeb55b3e45e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288576197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.288576197
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3099909082
Short name T236
Test name
Test status
Simulation time 7965367777 ps
CPU time 35.06 seconds
Started Feb 07 02:12:12 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 219388 kb
Host smart-77c1e641-e228-404b-8464-5802ae9a81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099909082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3099909082
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4160205504
Short name T885
Test name
Test status
Simulation time 125262098 ps
CPU time 3.15 seconds
Started Feb 07 02:12:03 PM PST 24
Finished Feb 07 02:12:07 PM PST 24
Peak memory 208716 kb
Host smart-1e4405bc-c21b-44c9-a11c-5560af602491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160205504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4160205504
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4136673791
Short name T312
Test name
Test status
Simulation time 24159447868 ps
CPU time 233.52 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:16:04 PM PST 24
Peak memory 223200 kb
Host smart-b5d75ca2-b946-43ef-b181-cce31bbfae9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136673791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4136673791
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.4289972837
Short name T702
Test name
Test status
Simulation time 75217130 ps
CPU time 3.24 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 223152 kb
Host smart-a085a4d6-63b8-43e7-be04-8279eda79247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289972837 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.4289972837
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.663205879
Short name T252
Test name
Test status
Simulation time 726314554 ps
CPU time 4.29 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 218868 kb
Host smart-bb3428b7-7fe6-42ee-b94a-0fcdbfa99382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663205879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.663205879
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3216223676
Short name T1068
Test name
Test status
Simulation time 66568826 ps
CPU time 1.83 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:12 PM PST 24
Peak memory 209660 kb
Host smart-293e8446-42ee-4978-8c54-8898a7cb0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216223676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3216223676
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1584832085
Short name T747
Test name
Test status
Simulation time 9769906 ps
CPU time 0.82 seconds
Started Feb 07 02:12:19 PM PST 24
Finished Feb 07 02:12:22 PM PST 24
Peak memory 206184 kb
Host smart-46e116ec-d3c3-433d-9905-88d67183f08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584832085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1584832085
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1645350836
Short name T372
Test name
Test status
Simulation time 2390084714 ps
CPU time 9.87 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:21 PM PST 24
Peak memory 223176 kb
Host smart-43c441aa-c62c-44b7-b933-ed38e1a5187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645350836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1645350836
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1488049994
Short name T298
Test name
Test status
Simulation time 462717095 ps
CPU time 2.83 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 214980 kb
Host smart-4911a88b-6126-424f-a5f0-36d1187d80d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488049994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1488049994
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1666718845
Short name T402
Test name
Test status
Simulation time 2428659140 ps
CPU time 73.72 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:13:31 PM PST 24
Peak memory 214892 kb
Host smart-9be2e626-7b27-40f2-9215-ad94e0e30362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666718845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1666718845
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2194640022
Short name T762
Test name
Test status
Simulation time 2337008082 ps
CPU time 7.54 seconds
Started Feb 07 02:12:10 PM PST 24
Finished Feb 07 02:12:19 PM PST 24
Peak memory 222992 kb
Host smart-293b3421-35a4-4d24-aabd-8fa9d9cbe47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194640022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2194640022
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1093333621
Short name T401
Test name
Test status
Simulation time 65767613 ps
CPU time 2.73 seconds
Started Feb 07 02:12:16 PM PST 24
Finished Feb 07 02:12:20 PM PST 24
Peak memory 208176 kb
Host smart-179601e4-7006-4aa3-a3e1-d106ecd31afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093333621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1093333621
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.161380536
Short name T725
Test name
Test status
Simulation time 478500561 ps
CPU time 5.65 seconds
Started Feb 07 02:12:12 PM PST 24
Finished Feb 07 02:12:23 PM PST 24
Peak memory 218764 kb
Host smart-256ab0bf-1bf0-4e5e-8fae-551da194b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161380536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.161380536
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2972655997
Short name T815
Test name
Test status
Simulation time 551184015 ps
CPU time 3.25 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 208860 kb
Host smart-195fd572-fcb3-4c41-b95c-83b22a7d560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972655997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2972655997
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3468201609
Short name T822
Test name
Test status
Simulation time 213899132 ps
CPU time 6.49 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:22 PM PST 24
Peak memory 208144 kb
Host smart-d895a6a4-185c-41a2-a55f-d77be80ca043
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468201609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3468201609
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3830185122
Short name T1006
Test name
Test status
Simulation time 62039286 ps
CPU time 3.14 seconds
Started Feb 07 02:12:09 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 208656 kb
Host smart-08d2f608-f1de-4f3a-838e-a6d0ef1c162c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830185122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3830185122
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1075031883
Short name T630
Test name
Test status
Simulation time 1008363442 ps
CPU time 36.57 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:47 PM PST 24
Peak memory 208588 kb
Host smart-08af7d10-4dfa-4e79-95b5-34e6d6e07034
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075031883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1075031883
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3259642194
Short name T680
Test name
Test status
Simulation time 138154614 ps
CPU time 2.71 seconds
Started Feb 07 02:12:10 PM PST 24
Finished Feb 07 02:12:14 PM PST 24
Peak memory 218956 kb
Host smart-ccd7e9a2-0eb8-4f1d-8415-890d2cbf10c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259642194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3259642194
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1586125682
Short name T695
Test name
Test status
Simulation time 1360901971 ps
CPU time 4.46 seconds
Started Feb 07 02:12:11 PM PST 24
Finished Feb 07 02:12:21 PM PST 24
Peak memory 207100 kb
Host smart-cec4d6e5-2cde-49bc-9455-96df6c0c090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586125682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1586125682
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.958258380
Short name T1036
Test name
Test status
Simulation time 212730611 ps
CPU time 3.75 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 223092 kb
Host smart-ba3f829f-983a-45d1-83d6-73a64b96378d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958258380 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.958258380
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2597137699
Short name T913
Test name
Test status
Simulation time 133767281 ps
CPU time 4.35 seconds
Started Feb 07 02:12:07 PM PST 24
Finished Feb 07 02:12:12 PM PST 24
Peak memory 207492 kb
Host smart-4fc3dbcb-0eb2-4c80-9a2c-72e0f8a60018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597137699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2597137699
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1190931445
Short name T975
Test name
Test status
Simulation time 44141913 ps
CPU time 2.57 seconds
Started Feb 07 02:12:08 PM PST 24
Finished Feb 07 02:12:12 PM PST 24
Peak memory 210380 kb
Host smart-0db375cb-f7d7-46ed-a711-f3bcec71af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190931445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1190931445
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1924303228
Short name T654
Test name
Test status
Simulation time 43603769 ps
CPU time 0.79 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:29 PM PST 24
Peak memory 205968 kb
Host smart-93b7eea3-f65b-46ab-9f64-8a763ad4ac49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924303228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1924303228
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2027749218
Short name T944
Test name
Test status
Simulation time 1413632915 ps
CPU time 16.79 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:45 PM PST 24
Peak memory 223132 kb
Host smart-3ff2d4f1-899c-485b-ae43-496a36415d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027749218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2027749218
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2085138979
Short name T884
Test name
Test status
Simulation time 587403002 ps
CPU time 5.85 seconds
Started Feb 07 02:12:20 PM PST 24
Finished Feb 07 02:12:27 PM PST 24
Peak memory 208852 kb
Host smart-175ed1cf-6c15-48d1-95c6-618c26fa9b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085138979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2085138979
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2840641707
Short name T81
Test name
Test status
Simulation time 317056802 ps
CPU time 8.71 seconds
Started Feb 07 02:12:22 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 214776 kb
Host smart-33c8dfdf-6635-4d68-96c0-54a04e746097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840641707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2840641707
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.193638195
Short name T279
Test name
Test status
Simulation time 224211782 ps
CPU time 4.3 seconds
Started Feb 07 02:12:26 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 212000 kb
Host smart-27747a59-257f-4a91-ab09-9abf496f7743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193638195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.193638195
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2204957569
Short name T194
Test name
Test status
Simulation time 338101328 ps
CPU time 4.51 seconds
Started Feb 07 02:12:23 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 215756 kb
Host smart-c34929bd-d55e-4986-a708-4909026fc69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204957569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2204957569
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2958009929
Short name T818
Test name
Test status
Simulation time 292587586 ps
CPU time 3.78 seconds
Started Feb 07 02:12:27 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 207912 kb
Host smart-11b37563-48a2-4fdb-9aca-766317627b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958009929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2958009929
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2417447318
Short name T826
Test name
Test status
Simulation time 470996245 ps
CPU time 4.18 seconds
Started Feb 07 02:12:20 PM PST 24
Finished Feb 07 02:12:26 PM PST 24
Peak memory 208724 kb
Host smart-9d837c60-9dcf-4a2f-b612-1486d2a6169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417447318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2417447318
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3583978015
Short name T724
Test name
Test status
Simulation time 109302359 ps
CPU time 3.71 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 208836 kb
Host smart-38caf853-f20f-40d6-ac78-996b83fcfeea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583978015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3583978015
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2540734833
Short name T889
Test name
Test status
Simulation time 1893043733 ps
CPU time 42.86 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 208784 kb
Host smart-874b3b20-a5f0-4dc7-9d72-0b6383cc2fba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540734833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2540734833
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2395637499
Short name T652
Test name
Test status
Simulation time 525903547 ps
CPU time 6.89 seconds
Started Feb 07 02:12:20 PM PST 24
Finished Feb 07 02:12:28 PM PST 24
Peak memory 214900 kb
Host smart-761af21f-af05-41ba-a0f9-944726f170de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395637499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2395637499
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3353981547
Short name T1064
Test name
Test status
Simulation time 78142112 ps
CPU time 3.1 seconds
Started Feb 07 02:12:22 PM PST 24
Finished Feb 07 02:12:26 PM PST 24
Peak memory 207016 kb
Host smart-2dfb10ee-2d27-496a-9ffb-0c17de72c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353981547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3353981547
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.663872777
Short name T365
Test name
Test status
Simulation time 598641231 ps
CPU time 19.41 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:47 PM PST 24
Peak memory 216828 kb
Host smart-73554580-c202-4b38-8d1c-02bb504556d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663872777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.663872777
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1479778572
Short name T89
Test name
Test status
Simulation time 306203433 ps
CPU time 3.35 seconds
Started Feb 07 02:12:27 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 222952 kb
Host smart-64ce5a4d-676b-4467-aefc-b5a065bd4984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479778572 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1479778572
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1117444206
Short name T943
Test name
Test status
Simulation time 300577929 ps
CPU time 4.36 seconds
Started Feb 07 02:12:23 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 214804 kb
Host smart-89a91a48-a33d-442f-8f7b-f07324a82eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117444206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1117444206
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1240889657
Short name T827
Test name
Test status
Simulation time 13452934 ps
CPU time 0.73 seconds
Started Feb 07 02:12:31 PM PST 24
Finished Feb 07 02:12:33 PM PST 24
Peak memory 206520 kb
Host smart-73be46a2-0176-4220-9644-a163738a16f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240889657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1240889657
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2443698898
Short name T934
Test name
Test status
Simulation time 136867989 ps
CPU time 2.72 seconds
Started Feb 07 02:12:18 PM PST 24
Finished Feb 07 02:12:23 PM PST 24
Peak memory 214840 kb
Host smart-b4c8a772-94f7-478e-b89c-d6c621bbe174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443698898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2443698898
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.523709511
Short name T24
Test name
Test status
Simulation time 142157239 ps
CPU time 5.11 seconds
Started Feb 07 02:12:30 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 222052 kb
Host smart-b527b417-39ad-4e0a-9e16-a0a38dfd28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523709511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.523709511
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1867833775
Short name T939
Test name
Test status
Simulation time 165926631 ps
CPU time 2.35 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:30 PM PST 24
Peak memory 207740 kb
Host smart-5023f7e3-0470-42f2-a14f-9e8470e93620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867833775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1867833775
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.926978537
Short name T78
Test name
Test status
Simulation time 6141216014 ps
CPU time 34.77 seconds
Started Feb 07 02:12:29 PM PST 24
Finished Feb 07 02:13:06 PM PST 24
Peak memory 223228 kb
Host smart-4cfdd988-55a9-4ab6-aa3a-a25d0f6a4c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926978537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.926978537
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3218054774
Short name T201
Test name
Test status
Simulation time 139233466 ps
CPU time 3.89 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 217480 kb
Host smart-e70b9ee0-bac0-49c7-b29f-7cee0ac13b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218054774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3218054774
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1956572121
Short name T344
Test name
Test status
Simulation time 637802444 ps
CPU time 6.45 seconds
Started Feb 07 02:12:19 PM PST 24
Finished Feb 07 02:12:28 PM PST 24
Peak memory 208524 kb
Host smart-d9b510ae-582b-410f-ba8f-a6c082d361b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956572121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1956572121
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.539866768
Short name T676
Test name
Test status
Simulation time 987724078 ps
CPU time 3.34 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 207164 kb
Host smart-136aecb2-114e-4c76-b6fd-2fd610319f62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539866768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.539866768
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.57023439
Short name T920
Test name
Test status
Simulation time 212573122 ps
CPU time 3.08 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 207232 kb
Host smart-e8aebaf4-eefa-40db-9253-119e524dfff1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57023439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.57023439
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1903090461
Short name T307
Test name
Test status
Simulation time 41909798 ps
CPU time 2.92 seconds
Started Feb 07 02:12:23 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 209200 kb
Host smart-648f484a-2910-4d89-8579-5ca0856c12b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903090461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1903090461
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3221993275
Short name T117
Test name
Test status
Simulation time 108834042 ps
CPU time 2.17 seconds
Started Feb 07 02:12:28 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 214856 kb
Host smart-37430d26-5d10-44cb-ae2f-d74cd1c86256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221993275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3221993275
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.454289784
Short name T614
Test name
Test status
Simulation time 145505691 ps
CPU time 2.83 seconds
Started Feb 07 02:12:25 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 206884 kb
Host smart-c29c22d4-4f21-4d99-be25-8534c062ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454289784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.454289784
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3228267115
Short name T276
Test name
Test status
Simulation time 1163415638 ps
CPU time 31.95 seconds
Started Feb 07 02:12:30 PM PST 24
Finished Feb 07 02:13:04 PM PST 24
Peak memory 221752 kb
Host smart-f448114e-d2c2-4ba6-a8be-ddac24f1ff20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228267115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3228267115
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.4047684753
Short name T313
Test name
Test status
Simulation time 186869598 ps
CPU time 3.15 seconds
Started Feb 07 02:12:24 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 210040 kb
Host smart-ade22582-8f96-482f-b2f9-4cc4fbcaa94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047684753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.4047684753
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.269246120
Short name T966
Test name
Test status
Simulation time 69980112 ps
CPU time 1.98 seconds
Started Feb 07 02:12:29 PM PST 24
Finished Feb 07 02:12:31 PM PST 24
Peak memory 209840 kb
Host smart-66f8486f-236e-4cc9-8a29-c90630d66f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269246120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.269246120
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.654751167
Short name T981
Test name
Test status
Simulation time 14166601 ps
CPU time 0.93 seconds
Started Feb 07 02:12:35 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 206392 kb
Host smart-d9cc7fbd-1044-4080-a19f-cc1499107f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654751167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.654751167
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1361017240
Short name T416
Test name
Test status
Simulation time 102326649 ps
CPU time 3.97 seconds
Started Feb 07 02:12:32 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 214776 kb
Host smart-78f42429-46d2-4974-b075-427efafd4735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361017240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1361017240
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.902114064
Short name T340
Test name
Test status
Simulation time 93772368 ps
CPU time 3.44 seconds
Started Feb 07 02:12:33 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 208440 kb
Host smart-19e5010e-0f52-49f4-89b9-ee0df94dc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902114064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.902114064
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.345266564
Short name T355
Test name
Test status
Simulation time 226936512 ps
CPU time 4.32 seconds
Started Feb 07 02:12:30 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 214816 kb
Host smart-26805892-501d-4d7b-b1a8-bd284ee7e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345266564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.345266564
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.486593275
Short name T899
Test name
Test status
Simulation time 890222204 ps
CPU time 2.42 seconds
Started Feb 07 02:12:33 PM PST 24
Finished Feb 07 02:12:36 PM PST 24
Peak memory 209820 kb
Host smart-cd629a16-d4ea-4e7f-ac0f-278734e27e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486593275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.486593275
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.138694295
Short name T1001
Test name
Test status
Simulation time 272734899 ps
CPU time 4.56 seconds
Started Feb 07 02:12:30 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 208848 kb
Host smart-bffa2362-2610-475f-9639-7a9ad9c89ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138694295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.138694295
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.771523550
Short name T1004
Test name
Test status
Simulation time 216539939 ps
CPU time 3.9 seconds
Started Feb 07 02:12:29 PM PST 24
Finished Feb 07 02:12:36 PM PST 24
Peak memory 208700 kb
Host smart-35629d8f-7293-46cb-acf7-f780258c638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771523550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.771523550
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.525868909
Short name T811
Test name
Test status
Simulation time 212378558 ps
CPU time 3.14 seconds
Started Feb 07 02:12:33 PM PST 24
Finished Feb 07 02:12:37 PM PST 24
Peak memory 208972 kb
Host smart-20e002b7-6196-4d66-8b64-669bf46d4b98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525868909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.525868909
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4104849386
Short name T780
Test name
Test status
Simulation time 59223223 ps
CPU time 2.95 seconds
Started Feb 07 02:12:30 PM PST 24
Finished Feb 07 02:12:35 PM PST 24
Peak memory 207024 kb
Host smart-6a1f552c-b51c-4333-a3b4-987d5e55e1fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104849386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4104849386
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.870005068
Short name T760
Test name
Test status
Simulation time 204649664 ps
CPU time 5.27 seconds
Started Feb 07 02:12:37 PM PST 24
Finished Feb 07 02:12:43 PM PST 24
Peak memory 209112 kb
Host smart-0e8ef6c6-827e-4adb-9d54-777eddff2136
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870005068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.870005068
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.49219122
Short name T1032
Test name
Test status
Simulation time 159365212 ps
CPU time 3.01 seconds
Started Feb 07 02:12:35 PM PST 24
Finished Feb 07 02:12:39 PM PST 24
Peak memory 214880 kb
Host smart-77d04de3-7979-4e39-9af4-6f6191255f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49219122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.49219122
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2482146630
Short name T184
Test name
Test status
Simulation time 722430770 ps
CPU time 4.86 seconds
Started Feb 07 02:12:29 PM PST 24
Finished Feb 07 02:12:35 PM PST 24
Peak memory 207508 kb
Host smart-420128af-a977-442a-a476-f907a936a8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482146630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2482146630
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3160355888
Short name T859
Test name
Test status
Simulation time 411286780 ps
CPU time 3.38 seconds
Started Feb 07 02:12:36 PM PST 24
Finished Feb 07 02:12:41 PM PST 24
Peak memory 214860 kb
Host smart-4f192adb-5ec6-45c0-a20a-2ddde5dba903
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160355888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3160355888
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3225093079
Short name T736
Test name
Test status
Simulation time 497675777 ps
CPU time 7.06 seconds
Started Feb 07 02:12:33 PM PST 24
Finished Feb 07 02:12:41 PM PST 24
Peak memory 210480 kb
Host smart-19db3c99-4f68-4549-9d04-685b2a0c6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225093079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3225093079
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4002504969
Short name T828
Test name
Test status
Simulation time 147884908 ps
CPU time 1.62 seconds
Started Feb 07 02:12:32 PM PST 24
Finished Feb 07 02:12:34 PM PST 24
Peak memory 209996 kb
Host smart-d8bbc005-37fa-4466-8449-bf51ac02dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002504969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4002504969
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2933014565
Short name T587
Test name
Test status
Simulation time 12048050 ps
CPU time 0.88 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:12:44 PM PST 24
Peak memory 206448 kb
Host smart-13cf0566-62bb-4beb-8f4c-fb199cc83828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933014565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2933014565
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.915639115
Short name T852
Test name
Test status
Simulation time 2676298509 ps
CPU time 38.2 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 223392 kb
Host smart-be0a5f39-5873-4fb9-a963-7f58d2ec280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915639115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.915639115
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1611578816
Short name T829
Test name
Test status
Simulation time 102779803 ps
CPU time 4.21 seconds
Started Feb 07 02:12:37 PM PST 24
Finished Feb 07 02:12:42 PM PST 24
Peak memory 210916 kb
Host smart-f4df41a3-ffba-402b-9944-afe3b5d38889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611578816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1611578816
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1989111479
Short name T323
Test name
Test status
Simulation time 837104289 ps
CPU time 8.27 seconds
Started Feb 07 02:12:36 PM PST 24
Finished Feb 07 02:12:45 PM PST 24
Peak memory 208956 kb
Host smart-8d38eb6f-1559-4ca5-9d07-3998e04815a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989111479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1989111479
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3283511238
Short name T59
Test name
Test status
Simulation time 295465613 ps
CPU time 3.51 seconds
Started Feb 07 02:12:44 PM PST 24
Finished Feb 07 02:12:49 PM PST 24
Peak memory 209516 kb
Host smart-cf360414-25ca-447a-aab6-b3ac29fd8dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283511238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3283511238
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1347882024
Short name T987
Test name
Test status
Simulation time 71318392 ps
CPU time 4.26 seconds
Started Feb 07 02:12:45 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 214760 kb
Host smart-41e051fa-b109-4a39-b44d-21b8d59c3499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347882024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1347882024
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1444153665
Short name T227
Test name
Test status
Simulation time 78905693 ps
CPU time 1.78 seconds
Started Feb 07 02:12:40 PM PST 24
Finished Feb 07 02:12:42 PM PST 24
Peak memory 207072 kb
Host smart-40a8af1f-749d-407e-96ef-3f36fd062dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444153665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1444153665
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1586948993
Short name T600
Test name
Test status
Simulation time 68449370 ps
CPU time 3.37 seconds
Started Feb 07 02:12:36 PM PST 24
Finished Feb 07 02:12:41 PM PST 24
Peak memory 207252 kb
Host smart-c0091cab-0b3f-4b3c-a738-1fc6bc106136
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586948993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1586948993
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.104203197
Short name T1084
Test name
Test status
Simulation time 36974060 ps
CPU time 2.59 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:12:45 PM PST 24
Peak memory 208884 kb
Host smart-a17bc98a-a7e9-4094-9c65-d47b29f84159
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104203197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.104203197
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.141150473
Short name T601
Test name
Test status
Simulation time 213581199 ps
CPU time 7.83 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:12:51 PM PST 24
Peak memory 208368 kb
Host smart-c52b74b4-1ba2-41ae-8ec7-970fdc7492cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141150473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.141150473
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2713874793
Short name T181
Test name
Test status
Simulation time 282281495 ps
CPU time 6.21 seconds
Started Feb 07 02:12:44 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 214904 kb
Host smart-54b466be-7c50-4ead-9cc2-ea17ebd31512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713874793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2713874793
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2083722997
Short name T1002
Test name
Test status
Simulation time 71466200 ps
CPU time 2.62 seconds
Started Feb 07 02:12:38 PM PST 24
Finished Feb 07 02:12:41 PM PST 24
Peak memory 208716 kb
Host smart-1604c12d-28d8-4604-bf81-42ebaf85c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083722997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2083722997
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2120239333
Short name T684
Test name
Test status
Simulation time 89250885 ps
CPU time 2.98 seconds
Started Feb 07 02:12:37 PM PST 24
Finished Feb 07 02:12:41 PM PST 24
Peak memory 223024 kb
Host smart-29158cf1-ea70-4445-81aa-0fe49aa8c222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120239333 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2120239333
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2874507812
Short name T847
Test name
Test status
Simulation time 186634874 ps
CPU time 7.41 seconds
Started Feb 07 02:12:42 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 208928 kb
Host smart-b286c06c-7862-4591-a723-d36bb1167fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874507812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2874507812
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.168123382
Short name T649
Test name
Test status
Simulation time 67040980 ps
CPU time 2.22 seconds
Started Feb 07 02:12:37 PM PST 24
Finished Feb 07 02:12:40 PM PST 24
Peak memory 210196 kb
Host smart-a3177fdc-41c0-4677-9cb8-5c51d9f0dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168123382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.168123382
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2392205890
Short name T1043
Test name
Test status
Simulation time 66946810 ps
CPU time 1.01 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:12:48 PM PST 24
Peak memory 206616 kb
Host smart-443f4444-e954-4189-8b01-34bfdcbb5e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392205890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2392205890
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3804835043
Short name T1021
Test name
Test status
Simulation time 34763457 ps
CPU time 2.73 seconds
Started Feb 07 02:12:49 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 214772 kb
Host smart-e94dc2c3-0115-4cc8-bf34-a686c0d131ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804835043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3804835043
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1690047745
Short name T19
Test name
Test status
Simulation time 641159576 ps
CPU time 2.51 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 210508 kb
Host smart-b7c3b8de-4bb0-47b1-9469-a0bdf8b7ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690047745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1690047745
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.481842952
Short name T315
Test name
Test status
Simulation time 59499282 ps
CPU time 3.12 seconds
Started Feb 07 02:12:48 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 207856 kb
Host smart-4dfc0cf4-0ed5-474d-aafa-4eb213c1206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481842952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.481842952
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3874834303
Short name T903
Test name
Test status
Simulation time 355372928 ps
CPU time 3.66 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 210084 kb
Host smart-8514170d-2e68-41da-9c7b-c946dcd3c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874834303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3874834303
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1497075810
Short name T390
Test name
Test status
Simulation time 614974431 ps
CPU time 18.61 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:13:06 PM PST 24
Peak memory 221548 kb
Host smart-341cadf3-02ae-4613-a38e-7ef6f7c716ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497075810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1497075810
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2824575575
Short name T755
Test name
Test status
Simulation time 430580902 ps
CPU time 4.81 seconds
Started Feb 07 02:12:47 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 214960 kb
Host smart-f62156b1-bf48-4402-a7c6-c4005fd4b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824575575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2824575575
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.534188679
Short name T716
Test name
Test status
Simulation time 1068760854 ps
CPU time 7.95 seconds
Started Feb 07 02:12:47 PM PST 24
Finished Feb 07 02:12:56 PM PST 24
Peak memory 208676 kb
Host smart-3b6802d5-6b44-457c-a3a9-002c9ce3ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534188679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.534188679
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2592601241
Short name T291
Test name
Test status
Simulation time 73829163 ps
CPU time 2.22 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:12:49 PM PST 24
Peak memory 207080 kb
Host smart-3c8155db-38c7-4c32-bd4a-73cbf4bb26c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592601241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2592601241
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.975048131
Short name T672
Test name
Test status
Simulation time 88482819 ps
CPU time 1.99 seconds
Started Feb 07 02:12:47 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 207788 kb
Host smart-ca7c03d2-d34b-4fa6-a765-4c756eaebd51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975048131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.975048131
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1686248276
Short name T667
Test name
Test status
Simulation time 134724420 ps
CPU time 2.79 seconds
Started Feb 07 02:12:49 PM PST 24
Finished Feb 07 02:12:53 PM PST 24
Peak memory 207128 kb
Host smart-9fa20774-2f7a-42c0-a2fe-13bbf8615e5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686248276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1686248276
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.10382279
Short name T588
Test name
Test status
Simulation time 56459620 ps
CPU time 1.92 seconds
Started Feb 07 02:12:52 PM PST 24
Finished Feb 07 02:12:54 PM PST 24
Peak memory 207144 kb
Host smart-5452de42-4849-4a16-80f0-2bd016504e9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.10382279
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.254932001
Short name T1009
Test name
Test status
Simulation time 55570426 ps
CPU time 1.7 seconds
Started Feb 07 02:12:56 PM PST 24
Finished Feb 07 02:12:59 PM PST 24
Peak memory 208088 kb
Host smart-39d12a66-51b8-4af9-b3d2-3710f17610cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254932001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.254932001
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3094114097
Short name T435
Test name
Test status
Simulation time 46469367 ps
CPU time 2.58 seconds
Started Feb 07 02:12:44 PM PST 24
Finished Feb 07 02:12:48 PM PST 24
Peak memory 208292 kb
Host smart-1b241c42-fdb9-445d-be54-6c3fad50d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094114097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3094114097
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2630538932
Short name T712
Test name
Test status
Simulation time 185152471 ps
CPU time 3.97 seconds
Started Feb 07 02:12:52 PM PST 24
Finished Feb 07 02:12:56 PM PST 24
Peak memory 223152 kb
Host smart-a72c7141-3897-4e99-9136-449b8b63cb9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630538932 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2630538932
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1852191423
Short name T912
Test name
Test status
Simulation time 179232712 ps
CPU time 6.08 seconds
Started Feb 07 02:12:45 PM PST 24
Finished Feb 07 02:12:52 PM PST 24
Peak memory 209772 kb
Host smart-2adca234-ff0f-4594-bd0e-3bfc7580583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852191423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1852191423
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4050745933
Short name T53
Test name
Test status
Simulation time 245363935 ps
CPU time 3.57 seconds
Started Feb 07 02:12:56 PM PST 24
Finished Feb 07 02:13:01 PM PST 24
Peak memory 210832 kb
Host smart-8912552b-cc4b-48ed-a53e-40c92e94af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050745933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4050745933
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.542302432
Short name T1039
Test name
Test status
Simulation time 14888434 ps
CPU time 0.89 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:08 PM PST 24
Peak memory 206660 kb
Host smart-e49477ba-1493-4f28-89d6-fb9c95426eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542302432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.542302432
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2343801761
Short name T249
Test name
Test status
Simulation time 55788808 ps
CPU time 3.85 seconds
Started Feb 07 02:12:58 PM PST 24
Finished Feb 07 02:13:03 PM PST 24
Peak memory 214736 kb
Host smart-4d580c09-5cf2-4a74-944e-73bda0208ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343801761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2343801761
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2237165627
Short name T8
Test name
Test status
Simulation time 95056212 ps
CPU time 4.84 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:07 PM PST 24
Peak memory 209756 kb
Host smart-690c2dea-47a2-4a82-a9f2-e4537a2a3069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237165627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2237165627
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4063144049
Short name T219
Test name
Test status
Simulation time 25102151 ps
CPU time 1.63 seconds
Started Feb 07 02:13:04 PM PST 24
Finished Feb 07 02:13:07 PM PST 24
Peak memory 207528 kb
Host smart-72b67c70-e177-4a3e-be7e-f882acefa478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063144049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4063144049
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3688861036
Short name T770
Test name
Test status
Simulation time 4481231210 ps
CPU time 33.94 seconds
Started Feb 07 02:12:58 PM PST 24
Finished Feb 07 02:13:33 PM PST 24
Peak memory 210372 kb
Host smart-e4eee92b-5b04-4042-ab5f-f44b3e618bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688861036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3688861036
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4247506233
Short name T640
Test name
Test status
Simulation time 74396298 ps
CPU time 2.96 seconds
Started Feb 07 02:13:00 PM PST 24
Finished Feb 07 02:13:04 PM PST 24
Peak memory 210356 kb
Host smart-e4aaa77c-b545-4610-bd17-033d79f532b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247506233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4247506233
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1595701101
Short name T268
Test name
Test status
Simulation time 2217083632 ps
CPU time 52.05 seconds
Started Feb 07 02:12:48 PM PST 24
Finished Feb 07 02:13:41 PM PST 24
Peak memory 209272 kb
Host smart-5297326b-5c0d-47d1-b8d9-a5f9be39d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595701101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1595701101
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.12652120
Short name T722
Test name
Test status
Simulation time 103514551 ps
CPU time 2.47 seconds
Started Feb 07 02:12:57 PM PST 24
Finished Feb 07 02:13:02 PM PST 24
Peak memory 207472 kb
Host smart-c51e7b96-3d46-447f-9508-83a4564bd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12652120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.12652120
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1561000381
Short name T411
Test name
Test status
Simulation time 428571743 ps
CPU time 4.14 seconds
Started Feb 07 02:12:52 PM PST 24
Finished Feb 07 02:12:57 PM PST 24
Peak memory 206972 kb
Host smart-729ee41e-faf7-4ecf-b2df-56042ec2df83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561000381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1561000381
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2657533108
Short name T623
Test name
Test status
Simulation time 1691513693 ps
CPU time 42.95 seconds
Started Feb 07 02:12:46 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 208880 kb
Host smart-c579eac1-4a7e-443e-880c-84605af1decc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657533108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2657533108
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3265284368
Short name T930
Test name
Test status
Simulation time 2761348490 ps
CPU time 30.89 seconds
Started Feb 07 02:12:49 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 208820 kb
Host smart-d026cf35-c24a-41b3-89c4-c6987e93f6a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265284368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3265284368
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1634453624
Short name T429
Test name
Test status
Simulation time 191274797 ps
CPU time 3.67 seconds
Started Feb 07 02:13:02 PM PST 24
Finished Feb 07 02:13:06 PM PST 24
Peak memory 214868 kb
Host smart-ae880b29-ab63-40a9-8bca-f11d9dc99b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634453624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1634453624
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2844786635
Short name T809
Test name
Test status
Simulation time 495620353 ps
CPU time 5.88 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:07 PM PST 24
Peak memory 208440 kb
Host smart-8f8f93ce-f2b3-4712-8795-f5dbe04b8007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844786635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2844786635
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1884909326
Short name T237
Test name
Test status
Simulation time 4701783535 ps
CPU time 52.58 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:55 PM PST 24
Peak memory 208904 kb
Host smart-44b93f95-b0c7-4047-a9a4-a7800af240ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884909326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1884909326
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2622946390
Short name T1048
Test name
Test status
Simulation time 188406046 ps
CPU time 3.53 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 223152 kb
Host smart-ece6086f-7af4-4ed1-8ff8-9711cfcdfdf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622946390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2622946390
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3383515008
Short name T70
Test name
Test status
Simulation time 542762306 ps
CPU time 14.93 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:22 PM PST 24
Peak memory 214828 kb
Host smart-7df1a962-1653-46a1-aa99-2be8b4071111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383515008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3383515008
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3535081717
Short name T892
Test name
Test status
Simulation time 176230390 ps
CPU time 2.29 seconds
Started Feb 07 02:12:58 PM PST 24
Finished Feb 07 02:13:02 PM PST 24
Peak memory 211044 kb
Host smart-6ad3ad97-41ae-4626-923c-d1cf526fa01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535081717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3535081717
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1291016550
Short name T786
Test name
Test status
Simulation time 42019617 ps
CPU time 0.72 seconds
Started Feb 07 02:13:05 PM PST 24
Finished Feb 07 02:13:06 PM PST 24
Peak memory 206376 kb
Host smart-a88224c6-7405-4dce-8d48-5263347e041a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291016550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1291016550
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1207498706
Short name T214
Test name
Test status
Simulation time 146400880 ps
CPU time 2.9 seconds
Started Feb 07 02:13:00 PM PST 24
Finished Feb 07 02:13:04 PM PST 24
Peak memory 214820 kb
Host smart-3f327541-86cd-4424-bfe7-3851fbf0477b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207498706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1207498706
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2499880702
Short name T858
Test name
Test status
Simulation time 318951573 ps
CPU time 1.76 seconds
Started Feb 07 02:13:13 PM PST 24
Finished Feb 07 02:13:15 PM PST 24
Peak memory 208868 kb
Host smart-42d762c2-3091-4e9d-96df-627e988b8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499880702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2499880702
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.867669127
Short name T57
Test name
Test status
Simulation time 168109091 ps
CPU time 4.22 seconds
Started Feb 07 02:13:00 PM PST 24
Finished Feb 07 02:13:05 PM PST 24
Peak memory 209184 kb
Host smart-18a7b447-2137-48cc-8feb-8d1803970c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867669127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.867669127
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2552057020
Short name T605
Test name
Test status
Simulation time 223341150 ps
CPU time 3.36 seconds
Started Feb 07 02:13:03 PM PST 24
Finished Feb 07 02:13:08 PM PST 24
Peak memory 210028 kb
Host smart-b68ca694-86f0-431f-9080-53b4cb19f0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552057020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2552057020
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3450946984
Short name T731
Test name
Test status
Simulation time 301992497 ps
CPU time 6.56 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:08 PM PST 24
Peak memory 210768 kb
Host smart-c25f8f64-72d9-4648-9206-c4f6738d914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450946984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3450946984
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4111987330
Short name T330
Test name
Test status
Simulation time 123151977 ps
CPU time 4.76 seconds
Started Feb 07 02:12:59 PM PST 24
Finished Feb 07 02:13:05 PM PST 24
Peak memory 208608 kb
Host smart-d7d73e0e-ddf0-4955-8ae4-9da0ac9b1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111987330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4111987330
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2039736139
Short name T812
Test name
Test status
Simulation time 3289611366 ps
CPU time 44.54 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:46 PM PST 24
Peak memory 209356 kb
Host smart-5e08dc63-d45c-47f9-96c0-48f72374c3a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039736139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2039736139
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1024312295
Short name T752
Test name
Test status
Simulation time 77726194 ps
CPU time 3.07 seconds
Started Feb 07 02:12:59 PM PST 24
Finished Feb 07 02:13:02 PM PST 24
Peak memory 208232 kb
Host smart-0ce8817c-309d-429b-bd91-1333f209bc38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024312295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1024312295
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1697639921
Short name T950
Test name
Test status
Simulation time 179529803 ps
CPU time 2.02 seconds
Started Feb 07 02:13:04 PM PST 24
Finished Feb 07 02:13:07 PM PST 24
Peak memory 209016 kb
Host smart-78800180-b501-494c-ba29-aa8035664b72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697639921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1697639921
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.710415919
Short name T893
Test name
Test status
Simulation time 91954466 ps
CPU time 1.96 seconds
Started Feb 07 02:13:00 PM PST 24
Finished Feb 07 02:13:03 PM PST 24
Peak memory 209280 kb
Host smart-c634dd0c-0e1e-4dfb-8819-06d4c9b99f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710415919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.710415919
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1625856255
Short name T857
Test name
Test status
Simulation time 967604267 ps
CPU time 23.66 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:25 PM PST 24
Peak memory 208176 kb
Host smart-04e3264e-87f3-4216-9ede-006cdde5a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625856255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1625856255
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.556808671
Short name T64
Test name
Test status
Simulation time 922771492 ps
CPU time 22.94 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:29 PM PST 24
Peak memory 216212 kb
Host smart-707634ac-c7ee-4eb2-ba18-26e48ea6a196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556808671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.556808671
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.363373587
Short name T830
Test name
Test status
Simulation time 1522847502 ps
CPU time 7.23 seconds
Started Feb 07 02:13:01 PM PST 24
Finished Feb 07 02:13:09 PM PST 24
Peak memory 210108 kb
Host smart-b4ff34e6-3c66-4cd0-aa0d-7a631d75f873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363373587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.363373587
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4066024382
Short name T911
Test name
Test status
Simulation time 182802304 ps
CPU time 4.21 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 210492 kb
Host smart-b524814e-c8e9-4c88-a5e9-b3d785d03845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066024382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4066024382
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2598265840
Short name T637
Test name
Test status
Simulation time 16092119 ps
CPU time 0.74 seconds
Started Feb 07 02:10:52 PM PST 24
Finished Feb 07 02:10:53 PM PST 24
Peak memory 206492 kb
Host smart-9715c2df-e4a6-44c4-8c47-a48d6524cb95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598265840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2598265840
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.514880308
Short name T417
Test name
Test status
Simulation time 36467425 ps
CPU time 2.9 seconds
Started Feb 07 02:10:27 PM PST 24
Finished Feb 07 02:10:31 PM PST 24
Peak memory 214912 kb
Host smart-7940c6f2-4cbd-4ffd-a009-65c2b31c2e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514880308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.514880308
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.599392193
Short name T709
Test name
Test status
Simulation time 58910089 ps
CPU time 2.85 seconds
Started Feb 07 02:10:36 PM PST 24
Finished Feb 07 02:10:40 PM PST 24
Peak memory 209944 kb
Host smart-368cc6b6-64e5-428c-adb8-349a1ad0aefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599392193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.599392193
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1388707981
Short name T1030
Test name
Test status
Simulation time 3483842662 ps
CPU time 43.18 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:11:35 PM PST 24
Peak memory 215000 kb
Host smart-d1462c37-2580-4cd9-a8cd-3b4313e0aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388707981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1388707981
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_random.2486884459
Short name T647
Test name
Test status
Simulation time 1484430634 ps
CPU time 27.51 seconds
Started Feb 07 02:10:29 PM PST 24
Finished Feb 07 02:10:57 PM PST 24
Peak memory 209428 kb
Host smart-6ab693d7-f97e-45d3-9892-3d79ea3cb2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486884459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2486884459
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.26236462
Short name T38
Test name
Test status
Simulation time 511984222 ps
CPU time 10.46 seconds
Started Feb 07 02:10:50 PM PST 24
Finished Feb 07 02:11:01 PM PST 24
Peak memory 232064 kb
Host smart-8e9b162f-801c-4628-afc5-297dad838e7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26236462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.26236462
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2461456821
Short name T905
Test name
Test status
Simulation time 57468333 ps
CPU time 3.18 seconds
Started Feb 07 02:10:29 PM PST 24
Finished Feb 07 02:10:33 PM PST 24
Peak memory 208372 kb
Host smart-316a88ac-0761-4e04-9ddc-745e33057722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461456821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2461456821
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.517593263
Short name T844
Test name
Test status
Simulation time 1580016211 ps
CPU time 5.14 seconds
Started Feb 07 02:10:30 PM PST 24
Finished Feb 07 02:10:36 PM PST 24
Peak memory 208840 kb
Host smart-44b0d240-6a2d-45c4-a211-e6e2f0ed9791
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517593263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.517593263
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4261856634
Short name T1025
Test name
Test status
Simulation time 247793277 ps
CPU time 2.71 seconds
Started Feb 07 02:10:28 PM PST 24
Finished Feb 07 02:10:32 PM PST 24
Peak memory 209328 kb
Host smart-896f8527-d3eb-46ad-82cd-939362e13599
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261856634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4261856634
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1126020056
Short name T936
Test name
Test status
Simulation time 124078708 ps
CPU time 2.55 seconds
Started Feb 07 02:10:29 PM PST 24
Finished Feb 07 02:10:33 PM PST 24
Peak memory 207008 kb
Host smart-52d42ae8-599b-4913-a097-d60f33d3c98c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126020056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1126020056
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.405364335
Short name T806
Test name
Test status
Simulation time 2403221530 ps
CPU time 30.19 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:11:22 PM PST 24
Peak memory 223164 kb
Host smart-ab79f162-1465-4f84-bc74-cd56aa017310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405364335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.405364335
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3462426526
Short name T805
Test name
Test status
Simulation time 59366737 ps
CPU time 2.21 seconds
Started Feb 07 02:10:31 PM PST 24
Finished Feb 07 02:10:34 PM PST 24
Peak memory 207076 kb
Host smart-e563b963-9010-4905-9733-235844f2a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462426526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3462426526
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3332884461
Short name T212
Test name
Test status
Simulation time 630632528 ps
CPU time 12.68 seconds
Started Feb 07 02:10:50 PM PST 24
Finished Feb 07 02:11:03 PM PST 24
Peak memory 223064 kb
Host smart-5e5d59fe-43bb-447f-9c6c-9bf6775c27e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332884461 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3332884461
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3628878662
Short name T385
Test name
Test status
Simulation time 427845121 ps
CPU time 3.93 seconds
Started Feb 07 02:10:38 PM PST 24
Finished Feb 07 02:10:43 PM PST 24
Peak memory 214824 kb
Host smart-826e71df-328f-4cc6-9cd4-b3be8631fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628878662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3628878662
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1159521671
Short name T995
Test name
Test status
Simulation time 208300467 ps
CPU time 2.57 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:10:55 PM PST 24
Peak memory 210488 kb
Host smart-27edcb08-6892-4947-a13a-fc8f7dc896f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159521671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1159521671
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4234562736
Short name T774
Test name
Test status
Simulation time 24413055 ps
CPU time 0.85 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:09 PM PST 24
Peak memory 206456 kb
Host smart-019368e5-456c-4042-8bd9-10a332b9228b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234562736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4234562736
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.632346295
Short name T833
Test name
Test status
Simulation time 202476265 ps
CPU time 4.35 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 209680 kb
Host smart-a17f1b85-2479-46e8-896a-d0ad0264ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632346295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.632346295
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.631236365
Short name T856
Test name
Test status
Simulation time 620791823 ps
CPU time 7.48 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:31 PM PST 24
Peak memory 214688 kb
Host smart-7e481067-2a36-4ec0-9c35-d8939f261af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631236365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.631236365
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.197585768
Short name T917
Test name
Test status
Simulation time 99428636 ps
CPU time 5.21 seconds
Started Feb 07 02:13:05 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 211836 kb
Host smart-80fabba6-36ad-4219-b113-b6a9f5440fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197585768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.197585768
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3698360359
Short name T595
Test name
Test status
Simulation time 265667666 ps
CPU time 3.88 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 210236 kb
Host smart-2b186e3e-8dff-4edf-a066-785009d29619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698360359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3698360359
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.393915155
Short name T339
Test name
Test status
Simulation time 608383619 ps
CPU time 8.69 seconds
Started Feb 07 02:13:05 PM PST 24
Finished Feb 07 02:13:14 PM PST 24
Peak memory 210012 kb
Host smart-652599f6-e1ad-4585-8be1-14b8100fdaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393915155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.393915155
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.358466318
Short name T407
Test name
Test status
Simulation time 40049547 ps
CPU time 1.84 seconds
Started Feb 07 02:13:09 PM PST 24
Finished Feb 07 02:13:11 PM PST 24
Peak memory 207076 kb
Host smart-34a8f2b7-a697-4d7d-97b8-851710eb412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358466318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.358466318
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.120050025
Short name T1016
Test name
Test status
Simulation time 117117908 ps
CPU time 2.49 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:26 PM PST 24
Peak memory 207568 kb
Host smart-9f75031c-91f6-419d-ae8b-3aee4c86f13c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120050025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.120050025
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4203341500
Short name T947
Test name
Test status
Simulation time 997098198 ps
CPU time 3.59 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 208932 kb
Host smart-719a9ba0-47ce-4e0d-bfb8-10731902ffe2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203341500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4203341500
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1891201902
Short name T657
Test name
Test status
Simulation time 1083258808 ps
CPU time 7.68 seconds
Started Feb 07 02:13:07 PM PST 24
Finished Feb 07 02:13:15 PM PST 24
Peak memory 208396 kb
Host smart-b8373444-34e8-476b-b5e4-37eb2b786286
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891201902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1891201902
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2731385935
Short name T763
Test name
Test status
Simulation time 687531465 ps
CPU time 10.9 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 214772 kb
Host smart-6367e8de-ce6b-4faa-8b68-44ff1938cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731385935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2731385935
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.787667780
Short name T879
Test name
Test status
Simulation time 55600446 ps
CPU time 2.88 seconds
Started Feb 07 02:13:04 PM PST 24
Finished Feb 07 02:13:08 PM PST 24
Peak memory 208884 kb
Host smart-860720d0-bc63-4148-bd91-c1e55e390d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787667780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.787667780
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2019360984
Short name T216
Test name
Test status
Simulation time 2318289069 ps
CPU time 14.8 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:24 PM PST 24
Peak memory 219660 kb
Host smart-f6a6bccc-5021-45ae-bc80-8d61972c76a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019360984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2019360984
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3356736992
Short name T969
Test name
Test status
Simulation time 586520796 ps
CPU time 11.01 seconds
Started Feb 07 02:13:05 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 222504 kb
Host smart-485fc3c7-db51-4299-ad82-f26f3660e941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356736992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3356736992
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3879781809
Short name T616
Test name
Test status
Simulation time 87125058 ps
CPU time 4.19 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:13 PM PST 24
Peak memory 208840 kb
Host smart-fcfe703f-9659-4bbe-8fa0-a4fa3af9b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879781809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3879781809
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.118744759
Short name T413
Test name
Test status
Simulation time 3169978495 ps
CPU time 10.19 seconds
Started Feb 07 02:13:06 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 211300 kb
Host smart-613c1037-84a1-471c-8151-5df9f9a06d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118744759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.118744759
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1578404077
Short name T928
Test name
Test status
Simulation time 7836846 ps
CPU time 0.77 seconds
Started Feb 07 02:13:18 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 206380 kb
Host smart-b618c1d5-997a-4609-a7fd-a023f10fb4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578404077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1578404077
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1624592745
Short name T271
Test name
Test status
Simulation time 215971348 ps
CPU time 3.61 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 214804 kb
Host smart-781619cf-e976-4b80-928a-75178ba2faa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624592745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1624592745
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1648566149
Short name T28
Test name
Test status
Simulation time 173757642 ps
CPU time 4.93 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:22 PM PST 24
Peak memory 218688 kb
Host smart-b6920368-e721-40f5-b2ad-28c948feab94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648566149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1648566149
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1554555093
Short name T50
Test name
Test status
Simulation time 412466137 ps
CPU time 10.17 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:38 PM PST 24
Peak memory 209064 kb
Host smart-f342bd33-70ea-4432-99a9-0dfedf6f92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554555093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1554555093
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1335620837
Short name T704
Test name
Test status
Simulation time 605868819 ps
CPU time 4.26 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:32 PM PST 24
Peak memory 214488 kb
Host smart-a0c14953-fdc9-40c5-ae0e-8de5a92ae92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335620837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1335620837
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.636446885
Short name T915
Test name
Test status
Simulation time 146852993 ps
CPU time 2.15 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 214880 kb
Host smart-2d66ebf5-47f9-4124-aad2-e38b77ca21ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636446885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.636446885
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1067311222
Short name T586
Test name
Test status
Simulation time 272316219 ps
CPU time 5.95 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:15 PM PST 24
Peak memory 207896 kb
Host smart-f655fe22-6a8d-4d41-b186-21f7709c1bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067311222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1067311222
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1204834723
Short name T1008
Test name
Test status
Simulation time 258822866 ps
CPU time 3.31 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 207124 kb
Host smart-06d13fe3-36ec-4e93-8e73-d24afdd001ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204834723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1204834723
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1295773196
Short name T925
Test name
Test status
Simulation time 246209118 ps
CPU time 2.63 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:26 PM PST 24
Peak memory 209020 kb
Host smart-0d9275fd-85c3-427a-94ea-ea75592a9b87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295773196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1295773196
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1169373148
Short name T990
Test name
Test status
Simulation time 81216060 ps
CPU time 2.04 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:26 PM PST 24
Peak memory 207196 kb
Host smart-62dc2f80-04bf-418e-8a40-0d23c8682d47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169373148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1169373148
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3580135491
Short name T792
Test name
Test status
Simulation time 171670860 ps
CPU time 5.29 seconds
Started Feb 07 02:13:22 PM PST 24
Finished Feb 07 02:13:29 PM PST 24
Peak memory 208064 kb
Host smart-0096de1a-bb9f-4669-9f06-e77081537a8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580135491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3580135491
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.161374909
Short name T266
Test name
Test status
Simulation time 378089435 ps
CPU time 2.16 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 218656 kb
Host smart-2c35f18d-e51f-469d-ac39-70091c8ff433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161374909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.161374909
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2875083353
Short name T768
Test name
Test status
Simulation time 64145516 ps
CPU time 3.11 seconds
Started Feb 07 02:13:08 PM PST 24
Finished Feb 07 02:13:12 PM PST 24
Peak memory 207084 kb
Host smart-e1bbb215-8588-466d-bcf1-9fbe17302955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875083353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2875083353
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1118505066
Short name T819
Test name
Test status
Simulation time 445425410 ps
CPU time 7.34 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:24 PM PST 24
Peak memory 223076 kb
Host smart-61d809cb-d29d-43eb-9ac5-fce5f17aa215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118505066 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1118505066
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3937773595
Short name T186
Test name
Test status
Simulation time 2791978136 ps
CPU time 67.48 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:14:35 PM PST 24
Peak memory 214872 kb
Host smart-cc3b8ce4-bc65-4bcb-95e1-d051f2056119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937773595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3937773595
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1477552380
Short name T909
Test name
Test status
Simulation time 172110928 ps
CPU time 3.81 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:31 PM PST 24
Peak memory 209952 kb
Host smart-9c4f4e25-de1f-4ffd-84ab-a0ce957c9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477552380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1477552380
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2325682129
Short name T367
Test name
Test status
Simulation time 164867240 ps
CPU time 5.11 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:23 PM PST 24
Peak memory 214804 kb
Host smart-ed08fdb6-2620-4869-a075-c7be8c6654dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325682129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2325682129
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4181184416
Short name T26
Test name
Test status
Simulation time 62847838 ps
CPU time 3.58 seconds
Started Feb 07 02:13:15 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 215144 kb
Host smart-73175dea-a407-40c8-ae0f-4f588395c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181184416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4181184416
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.629199288
Short name T959
Test name
Test status
Simulation time 838989569 ps
CPU time 3.31 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 207588 kb
Host smart-6d53aa16-536d-4e73-a32d-3b3938ba37b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629199288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.629199288
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3136059944
Short name T956
Test name
Test status
Simulation time 35983227 ps
CPU time 2.63 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:21 PM PST 24
Peak memory 214708 kb
Host smart-98260aec-fedf-4f8b-a5bb-84affa92962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136059944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3136059944
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2254972412
Short name T703
Test name
Test status
Simulation time 575677757 ps
CPU time 4.93 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 208732 kb
Host smart-a461cc60-d6a1-42c2-a447-8e4910dc0800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254972412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2254972412
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.611982831
Short name T1049
Test name
Test status
Simulation time 323301949 ps
CPU time 4.26 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:32 PM PST 24
Peak memory 209440 kb
Host smart-f9794a76-b1f6-4eb5-9a9d-de4d81e91303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611982831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.611982831
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1779547329
Short name T984
Test name
Test status
Simulation time 200843876 ps
CPU time 5.5 seconds
Started Feb 07 02:13:24 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 208532 kb
Host smart-ee3efb97-5dfc-4bad-ae41-b3fc7926c05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779547329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1779547329
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3680332083
Short name T243
Test name
Test status
Simulation time 10123981297 ps
CPU time 41.08 seconds
Started Feb 07 02:13:25 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 209084 kb
Host smart-a63c5df8-c543-420f-9f77-3ce778d7c36c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680332083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3680332083
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3622777732
Short name T659
Test name
Test status
Simulation time 471798294 ps
CPU time 5.21 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 209068 kb
Host smart-b521a4e5-5c58-4ac1-99ff-8f70bb721dcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622777732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3622777732
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2903119677
Short name T362
Test name
Test status
Simulation time 52110045 ps
CPU time 2.08 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 208932 kb
Host smart-1f23a81b-4806-4b8c-b908-89c100090aaf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903119677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2903119677
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1956030357
Short name T877
Test name
Test status
Simulation time 239808261 ps
CPU time 3.28 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:27 PM PST 24
Peak memory 207944 kb
Host smart-dc6c6971-7b0a-4eb1-be58-5712f47aa3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956030357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1956030357
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3268722546
Short name T1059
Test name
Test status
Simulation time 849814159 ps
CPU time 5.68 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:23 PM PST 24
Peak memory 208840 kb
Host smart-c4880c8e-440b-411d-a66e-c8184bd168b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268722546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3268722546
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2378226160
Short name T191
Test name
Test status
Simulation time 11665627873 ps
CPU time 148.9 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:15:44 PM PST 24
Peak memory 217528 kb
Host smart-2a9d642d-e573-44aa-bb63-9a53223054ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378226160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2378226160
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1717986716
Short name T294
Test name
Test status
Simulation time 329923549 ps
CPU time 4.19 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 209972 kb
Host smart-98b6bcf1-6b79-4855-ac9b-e1205e5986f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717986716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1717986716
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2264287720
Short name T896
Test name
Test status
Simulation time 154211794 ps
CPU time 3.92 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:22 PM PST 24
Peak memory 210708 kb
Host smart-c7dd2c89-841a-41b8-aca7-ddae7efcb0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264287720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2264287720
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3403096391
Short name T1047
Test name
Test status
Simulation time 15034630 ps
CPU time 0.75 seconds
Started Feb 07 02:13:32 PM PST 24
Finished Feb 07 02:13:33 PM PST 24
Peak memory 206440 kb
Host smart-42173a85-f2a9-4bc4-beac-3c00250453c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403096391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3403096391
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1174265869
Short name T923
Test name
Test status
Simulation time 25075244 ps
CPU time 1.82 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 207944 kb
Host smart-0fe62661-dd00-4804-8069-43a2964d79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174265869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1174265869
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.7137992
Short name T628
Test name
Test status
Simulation time 120827497 ps
CPU time 2.49 seconds
Started Feb 07 02:13:24 PM PST 24
Finished Feb 07 02:13:27 PM PST 24
Peak memory 216476 kb
Host smart-c954139e-0190-4b3a-a22d-0d51b8a3c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7137992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.7137992
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.631788586
Short name T253
Test name
Test status
Simulation time 274892529 ps
CPU time 7.65 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:25 PM PST 24
Peak memory 209392 kb
Host smart-043e3e73-3abf-4e44-92c4-c3d35d54f41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631788586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.631788586
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.45305563
Short name T381
Test name
Test status
Simulation time 200547249 ps
CPU time 2.88 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 206984 kb
Host smart-19689c22-7bec-4f77-a30a-82c3a831b112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45305563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.45305563
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3892028336
Short name T962
Test name
Test status
Simulation time 29899039 ps
CPU time 1.9 seconds
Started Feb 07 02:13:17 PM PST 24
Finished Feb 07 02:13:20 PM PST 24
Peak memory 208764 kb
Host smart-79856432-1e2a-477e-8434-7bf6dfcedf9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892028336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3892028336
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3558962681
Short name T691
Test name
Test status
Simulation time 40061517 ps
CPU time 2.51 seconds
Started Feb 07 02:13:23 PM PST 24
Finished Feb 07 02:13:27 PM PST 24
Peak memory 208900 kb
Host smart-1d8ca94f-ab58-4129-a962-8c30f2383371
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558962681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3558962681
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2441350606
Short name T690
Test name
Test status
Simulation time 158170813 ps
CPU time 3.68 seconds
Started Feb 07 02:13:15 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 206868 kb
Host smart-2abf7d3e-5f80-43f6-bb22-7664c82f8ac0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441350606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2441350606
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.825879728
Short name T1007
Test name
Test status
Simulation time 51411867 ps
CPU time 1.99 seconds
Started Feb 07 02:13:24 PM PST 24
Finished Feb 07 02:13:27 PM PST 24
Peak memory 216096 kb
Host smart-61232f8c-9caa-4f25-a5d0-182dca45440d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825879728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.825879728
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3262490766
Short name T891
Test name
Test status
Simulation time 43785234 ps
CPU time 2.22 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:17 PM PST 24
Peak memory 207080 kb
Host smart-9f320acf-a815-4c54-bc0b-620fa12192b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262490766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3262490766
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2522972055
Short name T95
Test name
Test status
Simulation time 187255595 ps
CPU time 3.61 seconds
Started Feb 07 02:13:14 PM PST 24
Finished Feb 07 02:13:18 PM PST 24
Peak memory 209472 kb
Host smart-2708852e-cf27-43ef-95e0-064c059ef3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522972055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2522972055
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.442190828
Short name T705
Test name
Test status
Simulation time 215855654 ps
CPU time 1.81 seconds
Started Feb 07 02:13:16 PM PST 24
Finished Feb 07 02:13:19 PM PST 24
Peak memory 210132 kb
Host smart-654aa5b3-28c9-45ec-afe7-d56383e3ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442190828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.442190828
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.705317940
Short name T598
Test name
Test status
Simulation time 21083027 ps
CPU time 0.87 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:42 PM PST 24
Peak memory 206416 kb
Host smart-00ffe9a2-5f3e-496c-b633-3674f73781ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705317940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.705317940
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2106720386
Short name T304
Test name
Test status
Simulation time 36086649 ps
CPU time 2.89 seconds
Started Feb 07 02:13:29 PM PST 24
Finished Feb 07 02:13:32 PM PST 24
Peak memory 215648 kb
Host smart-41f33b32-6ea3-4ee5-882d-ba07888192ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106720386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2106720386
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.823231934
Short name T1079
Test name
Test status
Simulation time 59854639 ps
CPU time 3.26 seconds
Started Feb 07 02:13:31 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 210328 kb
Host smart-0c7ae37c-924d-4930-9173-0f05eb4fc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823231934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.823231934
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2250671936
Short name T855
Test name
Test status
Simulation time 142101707 ps
CPU time 2.05 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 208772 kb
Host smart-767eaef6-0fcb-40b0-9987-972b149a4536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250671936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2250671936
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.929033228
Short name T1040
Test name
Test status
Simulation time 569429497 ps
CPU time 4.34 seconds
Started Feb 07 02:13:30 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 209212 kb
Host smart-33cd981d-fa79-45a5-9712-92ac911cc55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929033228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.929033228
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3966123307
Short name T4
Test name
Test status
Simulation time 150917945 ps
CPU time 4.26 seconds
Started Feb 07 02:13:30 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 215216 kb
Host smart-9d5ad8e2-dbd3-4da5-a430-413719a03640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966123307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3966123307
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1137197525
Short name T267
Test name
Test status
Simulation time 646068141 ps
CPU time 5.18 seconds
Started Feb 07 02:13:28 PM PST 24
Finished Feb 07 02:13:33 PM PST 24
Peak memory 210584 kb
Host smart-2f947b26-b7be-4897-8860-eb5a146fbb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137197525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1137197525
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.219000595
Short name T94
Test name
Test status
Simulation time 216047715 ps
CPU time 3.06 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 208832 kb
Host smart-c205c9bd-0f61-4c8a-954f-e6516801eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219000595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.219000595
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.145812130
Short name T757
Test name
Test status
Simulation time 256088920 ps
CPU time 7.29 seconds
Started Feb 07 02:13:29 PM PST 24
Finished Feb 07 02:13:37 PM PST 24
Peak memory 208032 kb
Host smart-83fd8db2-0932-459d-b640-5f6cb1b7d0aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145812130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.145812130
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4156062880
Short name T254
Test name
Test status
Simulation time 89792464 ps
CPU time 3.84 seconds
Started Feb 07 02:13:32 PM PST 24
Finished Feb 07 02:13:36 PM PST 24
Peak memory 209076 kb
Host smart-0d188cc4-d8e5-4f90-97b2-bc34fa35ec08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156062880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4156062880
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.728386253
Short name T406
Test name
Test status
Simulation time 233160133 ps
CPU time 2.36 seconds
Started Feb 07 02:13:27 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 207216 kb
Host smart-af440f20-90d7-4d06-904f-98d259e07eb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728386253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.728386253
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.747441939
Short name T778
Test name
Test status
Simulation time 84889042 ps
CPU time 3.73 seconds
Started Feb 07 02:13:30 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 210176 kb
Host smart-4c102c93-3746-4d4e-b6c9-0c1065ceca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747441939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.747441939
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1759748280
Short name T594
Test name
Test status
Simulation time 64630178 ps
CPU time 3.3 seconds
Started Feb 07 02:13:34 PM PST 24
Finished Feb 07 02:13:38 PM PST 24
Peak memory 207056 kb
Host smart-d6b6b03a-ef12-414f-909e-334e92e0c265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759748280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1759748280
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.4122647840
Short name T772
Test name
Test status
Simulation time 387531295 ps
CPU time 2.98 seconds
Started Feb 07 02:13:45 PM PST 24
Finished Feb 07 02:13:49 PM PST 24
Peak memory 214900 kb
Host smart-ccc89a20-6efa-491c-8f68-013ad9625f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122647840 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.4122647840
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2164645037
Short name T677
Test name
Test status
Simulation time 346045472 ps
CPU time 3.39 seconds
Started Feb 07 02:13:31 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 209600 kb
Host smart-7e342cc7-7c65-4530-a610-c95738b428b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164645037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2164645037
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1746109007
Short name T668
Test name
Test status
Simulation time 75641411 ps
CPU time 2.03 seconds
Started Feb 07 02:13:31 PM PST 24
Finished Feb 07 02:13:33 PM PST 24
Peak memory 209964 kb
Host smart-eadbe013-db83-491d-8ede-87d9936f3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746109007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1746109007
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.562155610
Short name T814
Test name
Test status
Simulation time 51585236 ps
CPU time 0.82 seconds
Started Feb 07 02:13:46 PM PST 24
Finished Feb 07 02:13:48 PM PST 24
Peak memory 206392 kb
Host smart-2a320fff-c033-4105-8217-a6fafd587496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562155610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.562155610
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.661807360
Short name T419
Test name
Test status
Simulation time 265436391 ps
CPU time 13.23 seconds
Started Feb 07 02:13:35 PM PST 24
Finished Feb 07 02:13:49 PM PST 24
Peak memory 214828 kb
Host smart-d8860681-77b5-411a-8a62-e06635f916f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661807360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.661807360
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1885334201
Short name T35
Test name
Test status
Simulation time 78254458 ps
CPU time 3.31 seconds
Started Feb 07 02:13:49 PM PST 24
Finished Feb 07 02:13:53 PM PST 24
Peak memory 208720 kb
Host smart-6b6ea65d-daf2-43ae-9f6a-e640ff346c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885334201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1885334201
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1115539388
Short name T738
Test name
Test status
Simulation time 257982933 ps
CPU time 5.21 seconds
Started Feb 07 02:13:44 PM PST 24
Finished Feb 07 02:13:50 PM PST 24
Peak memory 209644 kb
Host smart-efba2001-1409-420c-85fa-d66a63f3ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115539388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1115539388
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2929928105
Short name T297
Test name
Test status
Simulation time 263671490 ps
CPU time 7.15 seconds
Started Feb 07 02:13:34 PM PST 24
Finished Feb 07 02:13:42 PM PST 24
Peak memory 214760 kb
Host smart-7bf3d59c-9600-4ff4-a5e9-07f113f6d3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929928105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2929928105
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.950963000
Short name T180
Test name
Test status
Simulation time 509602592 ps
CPU time 6.74 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:48 PM PST 24
Peak memory 211140 kb
Host smart-ae682917-5175-4e80-9233-c1a4c7332139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950963000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.950963000
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4294752539
Short name T781
Test name
Test status
Simulation time 254458878 ps
CPU time 5.15 seconds
Started Feb 07 02:13:35 PM PST 24
Finished Feb 07 02:13:41 PM PST 24
Peak memory 220572 kb
Host smart-025cbb9e-afd1-48f0-9a38-3632b768f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294752539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4294752539
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2244758110
Short name T295
Test name
Test status
Simulation time 538977063 ps
CPU time 3.81 seconds
Started Feb 07 02:13:36 PM PST 24
Finished Feb 07 02:13:40 PM PST 24
Peak memory 210412 kb
Host smart-1b0dc6aa-6aba-4901-8b50-24577777861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244758110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2244758110
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1562035021
Short name T675
Test name
Test status
Simulation time 65780808 ps
CPU time 2.94 seconds
Started Feb 07 02:13:33 PM PST 24
Finished Feb 07 02:13:36 PM PST 24
Peak memory 208344 kb
Host smart-455a5db5-c097-46d8-bff8-6eef1b6bcbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562035021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1562035021
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1106442701
Short name T791
Test name
Test status
Simulation time 34859517 ps
CPU time 2.25 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:44 PM PST 24
Peak memory 207080 kb
Host smart-45d332f1-fad6-44ae-ab34-b8ed46a285b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106442701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1106442701
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.206763851
Short name T622
Test name
Test status
Simulation time 167130045 ps
CPU time 2.71 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:45 PM PST 24
Peak memory 207140 kb
Host smart-353ae686-4c92-46d3-b7a0-21b7d913a3ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206763851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.206763851
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1217188647
Short name T1033
Test name
Test status
Simulation time 39554053 ps
CPU time 2.65 seconds
Started Feb 07 02:13:43 PM PST 24
Finished Feb 07 02:13:46 PM PST 24
Peak memory 209164 kb
Host smart-fdc0d432-afb3-4679-8123-c27aa45e4b35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217188647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1217188647
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2950787676
Short name T269
Test name
Test status
Simulation time 25919059 ps
CPU time 1.7 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:44 PM PST 24
Peak memory 215008 kb
Host smart-9fc4a845-85b3-4e51-a015-411ff328644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950787676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2950787676
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3008796214
Short name T438
Test name
Test status
Simulation time 584905384 ps
CPU time 3.13 seconds
Started Feb 07 02:13:44 PM PST 24
Finished Feb 07 02:13:47 PM PST 24
Peak memory 208996 kb
Host smart-ca3492b0-aa6a-4200-9d1e-c26298e15c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008796214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3008796214
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2596703174
Short name T244
Test name
Test status
Simulation time 49692013 ps
CPU time 2.81 seconds
Started Feb 07 02:13:39 PM PST 24
Finished Feb 07 02:13:42 PM PST 24
Peak memory 208032 kb
Host smart-90ba0f69-6485-4b99-9f3f-8eb63c34ddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596703174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2596703174
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1756448670
Short name T161
Test name
Test status
Simulation time 95706740 ps
CPU time 3.24 seconds
Started Feb 07 02:13:34 PM PST 24
Finished Feb 07 02:13:38 PM PST 24
Peak memory 211164 kb
Host smart-35d7cae6-f21a-4600-8bcd-a76cb6a223eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756448670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1756448670
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3538749585
Short name T693
Test name
Test status
Simulation time 19168885 ps
CPU time 0.84 seconds
Started Feb 07 02:13:49 PM PST 24
Finished Feb 07 02:13:50 PM PST 24
Peak memory 206352 kb
Host smart-9f0fbce1-cf04-454b-b4ac-13fb33f0f13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538749585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3538749585
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1182111492
Short name T198
Test name
Test status
Simulation time 257717901 ps
CPU time 3.41 seconds
Started Feb 07 02:13:45 PM PST 24
Finished Feb 07 02:13:49 PM PST 24
Peak memory 210704 kb
Host smart-284596dc-11c8-4aee-874b-fe014916cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182111492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1182111492
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2068262149
Short name T978
Test name
Test status
Simulation time 81514238 ps
CPU time 3.83 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:45 PM PST 24
Peak memory 210220 kb
Host smart-8e5f987a-05bb-4e82-9d01-a72bdf9beced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068262149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2068262149
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1382644241
Short name T351
Test name
Test status
Simulation time 90027473 ps
CPU time 4.16 seconds
Started Feb 07 02:13:46 PM PST 24
Finished Feb 07 02:13:51 PM PST 24
Peak memory 220428 kb
Host smart-fc390c32-5434-4929-9cb3-9f97e3f66b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382644241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1382644241
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1166075717
Short name T278
Test name
Test status
Simulation time 244527868 ps
CPU time 4.49 seconds
Started Feb 07 02:13:49 PM PST 24
Finished Feb 07 02:13:54 PM PST 24
Peak memory 214836 kb
Host smart-92672b8f-c7c2-43b9-98da-73f99df8ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166075717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1166075717
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2143405120
Short name T136
Test name
Test status
Simulation time 135142849 ps
CPU time 2.75 seconds
Started Feb 07 02:13:53 PM PST 24
Finished Feb 07 02:13:57 PM PST 24
Peak memory 214872 kb
Host smart-f504929c-5a2b-4e26-ac4b-2f39b9791c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143405120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2143405120
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3524787240
Short name T380
Test name
Test status
Simulation time 162693644 ps
CPU time 4.07 seconds
Started Feb 07 02:13:47 PM PST 24
Finished Feb 07 02:13:52 PM PST 24
Peak memory 207412 kb
Host smart-d062cca4-9dc8-41c2-bbea-6ee8d656f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524787240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3524787240
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2409532580
Short name T92
Test name
Test status
Simulation time 136728990 ps
CPU time 4.52 seconds
Started Feb 07 02:13:42 PM PST 24
Finished Feb 07 02:13:47 PM PST 24
Peak memory 208760 kb
Host smart-c7e6f1c0-1197-44fa-a587-8ea064289885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409532580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2409532580
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2758874279
Short name T343
Test name
Test status
Simulation time 65047757 ps
CPU time 2.43 seconds
Started Feb 07 02:13:41 PM PST 24
Finished Feb 07 02:13:44 PM PST 24
Peak memory 207108 kb
Host smart-6efe1636-7f9d-4237-93ea-157962405bb0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758874279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2758874279
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1625899622
Short name T189
Test name
Test status
Simulation time 349609997 ps
CPU time 4.82 seconds
Started Feb 07 02:13:39 PM PST 24
Finished Feb 07 02:13:44 PM PST 24
Peak memory 207160 kb
Host smart-d2f9f7a8-0fa0-463e-8976-fd3785b1e275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625899622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1625899622
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3778540482
Short name T1071
Test name
Test status
Simulation time 121275207 ps
CPU time 2.44 seconds
Started Feb 07 02:13:46 PM PST 24
Finished Feb 07 02:13:49 PM PST 24
Peak memory 207220 kb
Host smart-0d4e8909-83c6-4c07-935a-8400d958a7ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778540482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3778540482
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2899423828
Short name T871
Test name
Test status
Simulation time 372596604 ps
CPU time 3.42 seconds
Started Feb 07 02:13:35 PM PST 24
Finished Feb 07 02:13:39 PM PST 24
Peak memory 208948 kb
Host smart-cf1e1e72-e637-4e8b-83f2-fffdc345ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899423828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2899423828
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.929306156
Short name T309
Test name
Test status
Simulation time 3874777070 ps
CPU time 38.03 seconds
Started Feb 07 02:13:49 PM PST 24
Finished Feb 07 02:14:28 PM PST 24
Peak memory 223116 kb
Host smart-9dd677df-755d-41d9-956d-9e492e509e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929306156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.929306156
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1858125434
Short name T901
Test name
Test status
Simulation time 1883229830 ps
CPU time 10.24 seconds
Started Feb 07 02:13:50 PM PST 24
Finished Feb 07 02:14:01 PM PST 24
Peak memory 223104 kb
Host smart-d732dede-9415-40f8-a6f8-45ad2a6efd41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858125434 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1858125434
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1111022368
Short name T1091
Test name
Test status
Simulation time 101779563 ps
CPU time 3.46 seconds
Started Feb 07 02:13:49 PM PST 24
Finished Feb 07 02:13:53 PM PST 24
Peak memory 207788 kb
Host smart-977bdb3a-2ed6-4198-ade8-91121705c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111022368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1111022368
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3904291300
Short name T635
Test name
Test status
Simulation time 204104637 ps
CPU time 1.95 seconds
Started Feb 07 02:13:48 PM PST 24
Finished Feb 07 02:13:51 PM PST 24
Peak memory 210276 kb
Host smart-28b88f92-daec-406c-93a5-f6985cb373a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904291300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3904291300
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3309584121
Short name T848
Test name
Test status
Simulation time 10543388 ps
CPU time 0.72 seconds
Started Feb 07 02:14:03 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 206428 kb
Host smart-986b1fd3-6194-49c5-8e4a-e251779820d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309584121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3309584121
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.683309664
Short name T431
Test name
Test status
Simulation time 1043504159 ps
CPU time 9.48 seconds
Started Feb 07 02:13:51 PM PST 24
Finished Feb 07 02:14:01 PM PST 24
Peak memory 214860 kb
Host smart-d0db470d-c859-4abe-8bd2-fb50b2da8782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683309664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.683309664
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.317470579
Short name T1088
Test name
Test status
Simulation time 1162325395 ps
CPU time 2.26 seconds
Started Feb 07 02:14:03 PM PST 24
Finished Feb 07 02:14:09 PM PST 24
Peak memory 210256 kb
Host smart-16899430-befb-429e-8030-73595491029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317470579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.317470579
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3067680708
Short name T910
Test name
Test status
Simulation time 170329537 ps
CPU time 2.46 seconds
Started Feb 07 02:14:00 PM PST 24
Finished Feb 07 02:14:05 PM PST 24
Peak memory 207600 kb
Host smart-48070a53-4761-412f-9d11-7c64450b56ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067680708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3067680708
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2134963286
Short name T853
Test name
Test status
Simulation time 213518251 ps
CPU time 4.91 seconds
Started Feb 07 02:13:59 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 209104 kb
Host smart-b4ff1de9-99fd-4439-a36e-0d2e266d7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134963286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2134963286
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2909352817
Short name T631
Test name
Test status
Simulation time 2604104688 ps
CPU time 80.07 seconds
Started Feb 07 02:13:51 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 214972 kb
Host smart-05dd1d96-c337-4409-b24a-a1d4a819de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909352817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2909352817
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.701825057
Short name T183
Test name
Test status
Simulation time 704226713 ps
CPU time 4.44 seconds
Started Feb 07 02:13:52 PM PST 24
Finished Feb 07 02:13:57 PM PST 24
Peak memory 209172 kb
Host smart-7cd8c168-1e12-4cf4-87f3-27d3ab66a7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701825057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.701825057
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3591817297
Short name T338
Test name
Test status
Simulation time 342833470 ps
CPU time 6.06 seconds
Started Feb 07 02:13:46 PM PST 24
Finished Feb 07 02:13:53 PM PST 24
Peak memory 208156 kb
Host smart-61eccae5-7acc-4382-b32c-d10c161b4d1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591817297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3591817297
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.36162719
Short name T1027
Test name
Test status
Simulation time 19637295 ps
CPU time 1.83 seconds
Started Feb 07 02:13:47 PM PST 24
Finished Feb 07 02:13:50 PM PST 24
Peak memory 207056 kb
Host smart-49700aa3-9900-4597-a3b8-b31992f73706
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36162719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.36162719
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.679414382
Short name T589
Test name
Test status
Simulation time 2383969426 ps
CPU time 25.9 seconds
Started Feb 07 02:13:47 PM PST 24
Finished Feb 07 02:14:14 PM PST 24
Peak memory 209380 kb
Host smart-17d2f3af-c831-431a-a60e-49e32268370f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679414382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.679414382
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3329287743
Short name T678
Test name
Test status
Simulation time 133189155 ps
CPU time 1.89 seconds
Started Feb 07 02:14:00 PM PST 24
Finished Feb 07 02:14:05 PM PST 24
Peak memory 209432 kb
Host smart-c6f08b42-6ea7-425f-b1ab-a03bdbd8d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329287743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3329287743
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.753808902
Short name T612
Test name
Test status
Simulation time 156564615 ps
CPU time 4.37 seconds
Started Feb 07 02:13:50 PM PST 24
Finished Feb 07 02:13:55 PM PST 24
Peak memory 208136 kb
Host smart-1c61d8fa-160f-4297-8b02-55b64dfc09b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753808902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.753808902
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3165123725
Short name T374
Test name
Test status
Simulation time 786093099 ps
CPU time 10.25 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:19 PM PST 24
Peak memory 209020 kb
Host smart-0f3a8974-17b5-4fe8-86d6-00cd20f19a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165123725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3165123725
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2014525173
Short name T324
Test name
Test status
Simulation time 110966391 ps
CPU time 8.05 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:16 PM PST 24
Peak memory 221100 kb
Host smart-ec7faa77-7c57-4491-ba06-a4890ca867d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014525173 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2014525173
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.222142928
Short name T275
Test name
Test status
Simulation time 240972104 ps
CPU time 3.45 seconds
Started Feb 07 02:13:59 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 207764 kb
Host smart-21a7197c-8cc4-4592-a7f0-cf25e3f85428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222142928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.222142928
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2031864100
Short name T32
Test name
Test status
Simulation time 186158621 ps
CPU time 2.09 seconds
Started Feb 07 02:14:00 PM PST 24
Finished Feb 07 02:14:05 PM PST 24
Peak memory 210500 kb
Host smart-bb3fbe99-27a7-45ae-a9fa-1d3c708d034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031864100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2031864100
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4011506707
Short name T764
Test name
Test status
Simulation time 43943745 ps
CPU time 0.72 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 206492 kb
Host smart-4eb2e100-6c68-4c5d-b0f4-442b6df7678b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011506707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4011506707
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2812974556
Short name T359
Test name
Test status
Simulation time 204802379 ps
CPU time 4.39 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 215520 kb
Host smart-6bda8487-6b21-46be-a381-a1198e1ac5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812974556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2812974556
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3721331987
Short name T717
Test name
Test status
Simulation time 48201841 ps
CPU time 2.86 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 210664 kb
Host smart-8409596d-6c6b-4d89-a1c1-d04c2805f5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721331987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3721331987
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3933505063
Short name T898
Test name
Test status
Simulation time 228961814 ps
CPU time 3.95 seconds
Started Feb 07 02:14:10 PM PST 24
Finished Feb 07 02:14:15 PM PST 24
Peak memory 210184 kb
Host smart-2e3c29b3-73c1-4774-8c58-f9107cb21dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933505063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3933505063
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1401506380
Short name T82
Test name
Test status
Simulation time 36934910 ps
CPU time 2.65 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:11 PM PST 24
Peak memory 209716 kb
Host smart-4859c718-ffba-4559-bc8e-d16248a678ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401506380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1401506380
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1143827747
Short name T188
Test name
Test status
Simulation time 70844394 ps
CPU time 3.93 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:07 PM PST 24
Peak memory 211240 kb
Host smart-7b8fa071-f033-44ac-83cb-fdf68b84b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143827747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1143827747
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1015989922
Short name T14
Test name
Test status
Simulation time 298130891 ps
CPU time 4.5 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 210056 kb
Host smart-706659f9-4f60-483b-aa28-1bd8da9e85f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015989922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1015989922
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3558136281
Short name T410
Test name
Test status
Simulation time 1302114129 ps
CPU time 4.93 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 210092 kb
Host smart-37613b64-c698-435e-96ac-210848d6f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558136281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3558136281
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2438518027
Short name T1090
Test name
Test status
Simulation time 105321792 ps
CPU time 4.93 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:08 PM PST 24
Peak memory 208740 kb
Host smart-d1f2c24e-e206-4abc-9881-6a86c2d91605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438518027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2438518027
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.221430831
Short name T823
Test name
Test status
Simulation time 120035173 ps
CPU time 2.6 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 209176 kb
Host smart-693ddf9f-964e-4fb8-8a97-6001876cbb8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221430831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.221430831
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2911521730
Short name T970
Test name
Test status
Simulation time 194468348 ps
CPU time 4.17 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 208720 kb
Host smart-7aedc61c-83d2-4960-ad2a-19ed98124c6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911521730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2911521730
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2337998676
Short name T793
Test name
Test status
Simulation time 102595113 ps
CPU time 2.89 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 209092 kb
Host smart-0e6a022f-c59d-4ae3-b6bf-7c96985d1e9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337998676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2337998676
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.377206091
Short name T1053
Test name
Test status
Simulation time 3951233646 ps
CPU time 34.3 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:37 PM PST 24
Peak memory 209588 kb
Host smart-8e2fb4bc-5643-40f1-a7a5-7a3df4a6aada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377206091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.377206091
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2400806586
Short name T771
Test name
Test status
Simulation time 251434120 ps
CPU time 3.66 seconds
Started Feb 07 02:13:59 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 207072 kb
Host smart-ee734d06-083f-4b6b-aea4-4a6e49d01b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400806586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2400806586
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1435328535
Short name T687
Test name
Test status
Simulation time 491620523 ps
CPU time 4.18 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:07 PM PST 24
Peak memory 219916 kb
Host smart-70983896-3ebd-46e4-a298-fc256664776f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435328535 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1435328535
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3564292488
Short name T226
Test name
Test status
Simulation time 1360951285 ps
CPU time 10.35 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:19 PM PST 24
Peak memory 209424 kb
Host smart-83f2a273-bf78-4ef6-985d-e57fcafbf1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564292488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3564292488
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1169660256
Short name T1037
Test name
Test status
Simulation time 292579292 ps
CPU time 3.26 seconds
Started Feb 07 02:14:03 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 210544 kb
Host smart-564580ee-a3ab-4a7d-90a7-7ced383c5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169660256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1169660256
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.800189100
Short name T591
Test name
Test status
Simulation time 30819777 ps
CPU time 0.75 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:09 PM PST 24
Peak memory 206420 kb
Host smart-04f9d158-bfc7-4fe6-bb2f-fbce2dc10523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800189100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.800189100
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3441466501
Short name T964
Test name
Test status
Simulation time 305026703 ps
CPU time 2.92 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 214808 kb
Host smart-75f1f9c6-1abe-4a4a-9221-67ababf3fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441466501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3441466501
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3684515973
Short name T842
Test name
Test status
Simulation time 177089853 ps
CPU time 4.27 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 216572 kb
Host smart-981f8815-53dd-48a5-b156-3637241a4a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684515973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3684515973
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1641940584
Short name T1072
Test name
Test status
Simulation time 1556088447 ps
CPU time 9.8 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:17 PM PST 24
Peak memory 210292 kb
Host smart-b1089052-b542-435c-980d-3bc047736df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641940584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1641940584
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3460529713
Short name T837
Test name
Test status
Simulation time 327703054 ps
CPU time 3.66 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 207560 kb
Host smart-522b10de-cac7-4edf-9425-c0070f311870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460529713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3460529713
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.483051817
Short name T993
Test name
Test status
Simulation time 547482125 ps
CPU time 6.48 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:15 PM PST 24
Peak memory 208388 kb
Host smart-c608e7b0-1066-447c-902b-63c4b1ce46c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483051817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.483051817
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4016317177
Short name T758
Test name
Test status
Simulation time 3440918138 ps
CPU time 47.02 seconds
Started Feb 07 02:13:59 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 208712 kb
Host smart-7738638c-4dee-48f4-a47f-b048f75b3e45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016317177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4016317177
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3987376066
Short name T655
Test name
Test status
Simulation time 36724607 ps
CPU time 1.76 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 207180 kb
Host smart-001fc880-a312-46c8-98f4-23c78bfb6851
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987376066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3987376066
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2544577006
Short name T627
Test name
Test status
Simulation time 59278647 ps
CPU time 2.13 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 216308 kb
Host smart-859592ab-e151-4975-9fdc-05a456f088e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544577006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2544577006
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2855720632
Short name T71
Test name
Test status
Simulation time 393222921 ps
CPU time 7.53 seconds
Started Feb 07 02:14:01 PM PST 24
Finished Feb 07 02:14:11 PM PST 24
Peak memory 208792 kb
Host smart-6c3a0483-9407-4a8b-acee-58f6c17e221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855720632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2855720632
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.383600960
Short name T723
Test name
Test status
Simulation time 502738475 ps
CPU time 11.89 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:19 PM PST 24
Peak memory 214896 kb
Host smart-e7ea33d9-844b-4d9f-ac7f-fb85d0e77b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383600960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.383600960
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2078812671
Short name T105
Test name
Test status
Simulation time 274460096 ps
CPU time 7.82 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:16 PM PST 24
Peak memory 223068 kb
Host smart-4f843c46-c639-4c94-b48d-ccb6c6cc1e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078812671 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2078812671
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1421330448
Short name T225
Test name
Test status
Simulation time 412973159 ps
CPU time 6.23 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:14 PM PST 24
Peak memory 208172 kb
Host smart-8e03c086-63e2-4e30-bc0b-abc9f7ed66ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421330448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1421330448
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4198312001
Short name T1065
Test name
Test status
Simulation time 219238874 ps
CPU time 2.55 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:10 PM PST 24
Peak memory 210364 kb
Host smart-6581b4b9-4d8e-4c52-9fe5-567dfde49e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198312001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.4198312001
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.253241516
Short name T439
Test name
Test status
Simulation time 19310157 ps
CPU time 0.85 seconds
Started Feb 07 02:11:00 PM PST 24
Finished Feb 07 02:11:02 PM PST 24
Peak memory 206452 kb
Host smart-787fac87-0a13-470c-b0f3-d47447c3fca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253241516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.253241516
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2136583496
Short name T68
Test name
Test status
Simulation time 1243560540 ps
CPU time 26.32 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:23 PM PST 24
Peak memory 209888 kb
Host smart-a269cd3d-e9da-4096-b9ba-aad7f0e5007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136583496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2136583496
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3464922883
Short name T79
Test name
Test status
Simulation time 53318075 ps
CPU time 3.09 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 209332 kb
Host smart-16af3326-0660-4189-a6c6-24ec6bf27134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464922883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3464922883
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2094675783
Short name T262
Test name
Test status
Simulation time 53578574 ps
CPU time 3.32 seconds
Started Feb 07 02:10:57 PM PST 24
Finished Feb 07 02:11:01 PM PST 24
Peak memory 214708 kb
Host smart-8ff1717c-ebb8-402b-9e83-4b2b1b973802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094675783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2094675783
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.615105685
Short name T196
Test name
Test status
Simulation time 184839274 ps
CPU time 9.3 seconds
Started Feb 07 02:10:55 PM PST 24
Finished Feb 07 02:11:05 PM PST 24
Peak memory 209612 kb
Host smart-3c1f4bbf-f010-4e28-bad1-7b2d0833cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615105685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.615105685
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2463460929
Short name T997
Test name
Test status
Simulation time 275645328 ps
CPU time 3.04 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:10:55 PM PST 24
Peak memory 210160 kb
Host smart-6e5bbd8f-19fc-4c6d-8ab4-01636db163a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463460929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2463460929
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1115389264
Short name T820
Test name
Test status
Simulation time 160716755 ps
CPU time 3.85 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:10:55 PM PST 24
Peak memory 208936 kb
Host smart-0c452cb9-dcfa-428a-9b9c-292881c2e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115389264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1115389264
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.580443324
Short name T918
Test name
Test status
Simulation time 221351078 ps
CPU time 3.16 seconds
Started Feb 07 02:10:52 PM PST 24
Finished Feb 07 02:10:56 PM PST 24
Peak memory 207184 kb
Host smart-5516b8a5-4828-4531-9432-04aa6e68479a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580443324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.580443324
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.777761031
Short name T865
Test name
Test status
Simulation time 66729487 ps
CPU time 3.6 seconds
Started Feb 07 02:10:51 PM PST 24
Finished Feb 07 02:10:56 PM PST 24
Peak memory 209092 kb
Host smart-db132c2e-5e57-48be-a907-a6ebcffdfe5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777761031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.777761031
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2512111689
Short name T341
Test name
Test status
Simulation time 2059089778 ps
CPU time 20.27 seconds
Started Feb 07 02:10:50 PM PST 24
Finished Feb 07 02:11:10 PM PST 24
Peak memory 209324 kb
Host smart-f2226614-5497-4b6d-830a-4b7ed8ad434d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512111689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2512111689
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.902672098
Short name T875
Test name
Test status
Simulation time 463924790 ps
CPU time 2.07 seconds
Started Feb 07 02:10:58 PM PST 24
Finished Feb 07 02:11:01 PM PST 24
Peak memory 208536 kb
Host smart-338450f6-f622-48c9-ac1a-f51dc3150481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902672098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.902672098
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.110302667
Short name T663
Test name
Test status
Simulation time 90935154 ps
CPU time 3.63 seconds
Started Feb 07 02:10:53 PM PST 24
Finished Feb 07 02:10:57 PM PST 24
Peak memory 207048 kb
Host smart-33e828bd-1a21-42e5-8361-95fd30fe9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110302667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.110302667
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2566138207
Short name T383
Test name
Test status
Simulation time 891266420 ps
CPU time 8.43 seconds
Started Feb 07 02:10:58 PM PST 24
Finished Feb 07 02:11:07 PM PST 24
Peak memory 216828 kb
Host smart-664b683b-04b5-4231-a5d1-d99b890e03f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566138207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2566138207
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.4166189263
Short name T751
Test name
Test status
Simulation time 90863738 ps
CPU time 3.19 seconds
Started Feb 07 02:10:58 PM PST 24
Finished Feb 07 02:11:02 PM PST 24
Peak memory 214984 kb
Host smart-103cd529-0633-4e3f-9c3f-946072a2005b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166189263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.4166189263
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1932511000
Short name T334
Test name
Test status
Simulation time 814165223 ps
CPU time 20.04 seconds
Started Feb 07 02:11:00 PM PST 24
Finished Feb 07 02:11:21 PM PST 24
Peak memory 209092 kb
Host smart-a9fac515-a5cf-4aff-aa13-66b33c6ef954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932511000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1932511000
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1124369763
Short name T1046
Test name
Test status
Simulation time 351512104 ps
CPU time 4.15 seconds
Started Feb 07 02:10:55 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 219680 kb
Host smart-8d8c6a3d-d60b-4767-87ac-751e2d5d3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124369763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1124369763
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.25213002
Short name T945
Test name
Test status
Simulation time 29262187 ps
CPU time 0.78 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:16 PM PST 24
Peak memory 206456 kb
Host smart-2dfe4301-5326-4e97-a1fc-accb41611192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.25213002
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3421367116
Short name T421
Test name
Test status
Simulation time 99856326 ps
CPU time 4.09 seconds
Started Feb 07 02:14:12 PM PST 24
Finished Feb 07 02:14:17 PM PST 24
Peak memory 214844 kb
Host smart-8662f87d-25bd-4c32-bd07-e2e202ea9726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421367116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3421367116
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1164117462
Short name T610
Test name
Test status
Simulation time 66810226 ps
CPU time 2.14 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 209644 kb
Host smart-7801a170-ed38-4033-bf4a-e5489fbf54fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164117462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1164117462
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3677481535
Short name T1057
Test name
Test status
Simulation time 193910689 ps
CPU time 6.64 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 214808 kb
Host smart-b2460613-550b-44a7-8465-4943cdd1935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677481535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3677481535
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2265364481
Short name T904
Test name
Test status
Simulation time 78982208 ps
CPU time 3.16 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 214888 kb
Host smart-6225703d-6409-465e-8520-cb1abc484fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265364481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2265364481
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3639092189
Short name T1075
Test name
Test status
Simulation time 182765615 ps
CPU time 3.33 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 208148 kb
Host smart-03bc6b07-e7c9-4f5e-8dae-6a8bac3085a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639092189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3639092189
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2241267384
Short name T1074
Test name
Test status
Simulation time 82383674 ps
CPU time 3.98 seconds
Started Feb 07 02:14:05 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 207056 kb
Host smart-baf9cd42-990f-4876-b217-ce708e1d231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241267384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2241267384
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3023918112
Short name T273
Test name
Test status
Simulation time 590240587 ps
CPU time 4.61 seconds
Started Feb 07 02:14:04 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 208224 kb
Host smart-e44690f8-a3de-4ee9-bf11-d83316d6f346
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023918112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3023918112
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1689275184
Short name T861
Test name
Test status
Simulation time 1312445617 ps
CPU time 3.09 seconds
Started Feb 07 02:14:08 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 207180 kb
Host smart-ebbc31dd-fdee-4d05-bdc0-b072827ea13c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689275184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1689275184
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.860618811
Short name T735
Test name
Test status
Simulation time 221880409 ps
CPU time 9.17 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:30 PM PST 24
Peak memory 208292 kb
Host smart-3bdb94d4-d66c-49d9-b898-46e840cb2b90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860618811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.860618811
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1192164833
Short name T641
Test name
Test status
Simulation time 142081112 ps
CPU time 2.4 seconds
Started Feb 07 02:14:10 PM PST 24
Finished Feb 07 02:14:13 PM PST 24
Peak memory 209908 kb
Host smart-7ebdc2de-a8e4-42b3-b96c-f43e362cb6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192164833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1192164833
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3279124486
Short name T400
Test name
Test status
Simulation time 82800487 ps
CPU time 2.23 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:11 PM PST 24
Peak memory 207008 kb
Host smart-51f429de-99ca-4306-8069-99608355d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279124486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3279124486
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3237076728
Short name T378
Test name
Test status
Simulation time 716539691 ps
CPU time 26.34 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:35 PM PST 24
Peak memory 215444 kb
Host smart-40c36b07-22fb-44fb-8e3e-1390a990bc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237076728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3237076728
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.314270014
Short name T620
Test name
Test status
Simulation time 128647022 ps
CPU time 4.22 seconds
Started Feb 07 02:14:12 PM PST 24
Finished Feb 07 02:14:17 PM PST 24
Peak memory 220832 kb
Host smart-ceee47b8-35ad-43d9-8857-5923043051b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314270014 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.314270014
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.463965853
Short name T845
Test name
Test status
Simulation time 354153111 ps
CPU time 8.55 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:17 PM PST 24
Peak memory 207628 kb
Host smart-f9b4fc26-0052-4f32-8170-5cd308adfe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463965853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.463965853
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.843343107
Short name T658
Test name
Test status
Simulation time 104367129 ps
CPU time 1.86 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:11 PM PST 24
Peak memory 209928 kb
Host smart-26489203-f028-469a-937d-b55eb4804c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843343107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.843343107
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.530174213
Short name T625
Test name
Test status
Simulation time 12275978 ps
CPU time 0.86 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:16 PM PST 24
Peak memory 206516 kb
Host smart-68bd487e-8e9f-4f71-8809-e46776c0e8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530174213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.530174213
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3890392782
Short name T217
Test name
Test status
Simulation time 212602020 ps
CPU time 2.27 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:11 PM PST 24
Peak memory 214840 kb
Host smart-c09b7603-111d-42a8-9a60-7da04d06b311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890392782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3890392782
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.964264952
Short name T292
Test name
Test status
Simulation time 2843810181 ps
CPU time 28.05 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:37 PM PST 24
Peak memory 214924 kb
Host smart-b0f9564e-ff28-4d94-8660-0266d8e01f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964264952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.964264952
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3251046407
Short name T84
Test name
Test status
Simulation time 175072326 ps
CPU time 3.07 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:14:21 PM PST 24
Peak memory 209940 kb
Host smart-b13dd95e-5e3c-449e-a5df-dfe0dadb6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251046407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3251046407
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.4061015787
Short name T185
Test name
Test status
Simulation time 1095235019 ps
CPU time 6.13 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:21 PM PST 24
Peak memory 214688 kb
Host smart-44bcd086-8e15-415f-9092-475491011103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061015787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4061015787
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3478251156
Short name T41
Test name
Test status
Simulation time 270015934 ps
CPU time 3.26 seconds
Started Feb 07 02:14:07 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 209128 kb
Host smart-a45b5815-8d9e-485c-a23e-3b3227f1dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478251156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3478251156
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2599882748
Short name T263
Test name
Test status
Simulation time 1635343083 ps
CPU time 6.14 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 209984 kb
Host smart-7ecf93a6-908c-4255-a634-1a0fc7374c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599882748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2599882748
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2868794403
Short name T626
Test name
Test status
Simulation time 151857734 ps
CPU time 2.68 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:18 PM PST 24
Peak memory 207000 kb
Host smart-58508244-63bf-458f-ab14-e898c9dd65eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868794403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2868794403
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3673908899
Short name T408
Test name
Test status
Simulation time 202666351 ps
CPU time 7.32 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:22 PM PST 24
Peak memory 208020 kb
Host smart-541ecc75-1f45-4cf1-a898-3b1dae8460e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673908899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3673908899
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.922849220
Short name T697
Test name
Test status
Simulation time 136314645 ps
CPU time 2.37 seconds
Started Feb 07 02:14:08 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 207600 kb
Host smart-e5664489-eb2a-4480-8017-f2c601039dca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922849220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.922849220
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3028812902
Short name T742
Test name
Test status
Simulation time 101173930 ps
CPU time 2.84 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 207180 kb
Host smart-324940e7-a966-44b4-9556-6c8df1ca3323
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028812902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3028812902
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.592486606
Short name T683
Test name
Test status
Simulation time 42829578 ps
CPU time 2.97 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:18 PM PST 24
Peak memory 210636 kb
Host smart-d8a47ed7-6816-4318-8e35-c392be06311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592486606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.592486606
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2192363730
Short name T1042
Test name
Test status
Simulation time 24023220248 ps
CPU time 58.02 seconds
Started Feb 07 02:14:06 PM PST 24
Finished Feb 07 02:15:07 PM PST 24
Peak memory 207184 kb
Host smart-82aa2501-4260-4dae-84a1-b5bcf0ee2bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192363730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2192363730
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.990131132
Short name T65
Test name
Test status
Simulation time 574038076 ps
CPU time 8.67 seconds
Started Feb 07 02:14:19 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 223036 kb
Host smart-e0b8daca-81b6-4ffc-9939-49dea8f7fc3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990131132 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.990131132
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.744298584
Short name T639
Test name
Test status
Simulation time 1502391020 ps
CPU time 20.41 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:35 PM PST 24
Peak memory 209632 kb
Host smart-95919160-ab1e-4d5f-9f22-145abc4a528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744298584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.744298584
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1595095647
Short name T48
Test name
Test status
Simulation time 211440613 ps
CPU time 2.6 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:14:21 PM PST 24
Peak memory 210636 kb
Host smart-bbf2e2e7-45d6-4cdf-80f1-1a799ca4df88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595095647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1595095647
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3070254121
Short name T765
Test name
Test status
Simulation time 72265686 ps
CPU time 0.78 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:14:26 PM PST 24
Peak memory 206420 kb
Host smart-ddf5e397-4939-4f41-89be-aa32e432109d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070254121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3070254121
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.631429039
Short name T714
Test name
Test status
Simulation time 46003102 ps
CPU time 1.93 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:22 PM PST 24
Peak memory 209888 kb
Host smart-d51b15f3-5acb-4984-bd45-8568dc977600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631429039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.631429039
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1974490931
Short name T346
Test name
Test status
Simulation time 21391047 ps
CPU time 1.67 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:17 PM PST 24
Peak memory 210316 kb
Host smart-b0591866-8928-4b52-be76-f99701bd130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974490931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1974490931
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.665665305
Short name T290
Test name
Test status
Simulation time 42755124 ps
CPU time 2.78 seconds
Started Feb 07 02:14:18 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 209824 kb
Host smart-14c6f092-28af-467f-8d34-3beb98c253f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665665305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.665665305
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1690656457
Short name T300
Test name
Test status
Simulation time 952620502 ps
CPU time 5.62 seconds
Started Feb 07 02:14:20 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 222944 kb
Host smart-d9fe56e9-6163-45fa-9da2-6425d0ffd15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690656457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1690656457
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2983191482
Short name T955
Test name
Test status
Simulation time 68560983 ps
CPU time 3.21 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 210280 kb
Host smart-36424b46-163b-4695-ae32-eaae39fd191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983191482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2983191482
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4292665631
Short name T840
Test name
Test status
Simulation time 808646176 ps
CPU time 6.57 seconds
Started Feb 07 02:14:18 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 208564 kb
Host smart-37decc87-f58f-47b8-b330-8b20c699cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292665631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4292665631
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3771477127
Short name T1028
Test name
Test status
Simulation time 395140942 ps
CPU time 2.79 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 206620 kb
Host smart-b5cdea8e-2d3e-45ef-900b-252da3f1cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771477127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3771477127
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4055826143
Short name T1058
Test name
Test status
Simulation time 81266330 ps
CPU time 2.56 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 207000 kb
Host smart-0f251a58-69d0-42ed-830a-813ce21d3f33
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055826143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4055826143
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2037749800
Short name T745
Test name
Test status
Simulation time 1282670022 ps
CPU time 39.75 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:15:00 PM PST 24
Peak memory 208196 kb
Host smart-8068c240-1ae3-4563-8e33-59be90ea9566
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037749800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2037749800
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2385712779
Short name T114
Test name
Test status
Simulation time 66205965 ps
CPU time 3.39 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 208920 kb
Host smart-800f33b0-9706-4edb-8fd5-c16254daab9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385712779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2385712779
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1937933456
Short name T427
Test name
Test status
Simulation time 1399033081 ps
CPU time 5.78 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:26 PM PST 24
Peak memory 209132 kb
Host smart-792e926b-c9b6-47f8-ab20-58598a868fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937933456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1937933456
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1448374936
Short name T733
Test name
Test status
Simulation time 460974681 ps
CPU time 3.37 seconds
Started Feb 07 02:14:20 PM PST 24
Finished Feb 07 02:14:25 PM PST 24
Peak memory 208824 kb
Host smart-6970e71c-9438-4eeb-bd0a-6377740b1472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448374936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1448374936
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1503786045
Short name T211
Test name
Test status
Simulation time 13955910124 ps
CPU time 168.45 seconds
Started Feb 07 02:14:20 PM PST 24
Finished Feb 07 02:17:10 PM PST 24
Peak memory 223092 kb
Host smart-005277e5-257f-4958-8619-570d38cc4afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503786045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1503786045
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3962992089
Short name T1063
Test name
Test status
Simulation time 580885637 ps
CPU time 8.92 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 223060 kb
Host smart-41f8104b-33b6-49df-a23a-613f6b31408c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962992089 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3962992089
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4053945387
Short name T992
Test name
Test status
Simulation time 259446493 ps
CPU time 6.09 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:14:25 PM PST 24
Peak memory 218912 kb
Host smart-2b7cbba1-85a9-4e38-a0d4-fd49d0c9c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053945387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4053945387
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3051882418
Short name T985
Test name
Test status
Simulation time 206740746 ps
CPU time 2.64 seconds
Started Feb 07 02:14:21 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 210164 kb
Host smart-fccc750c-c540-4acd-a5b0-ad0c77257ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051882418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3051882418
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3941412858
Short name T681
Test name
Test status
Simulation time 39435669 ps
CPU time 0.99 seconds
Started Feb 07 02:14:36 PM PST 24
Finished Feb 07 02:14:40 PM PST 24
Peak memory 206528 kb
Host smart-5be3bb99-648d-4c9d-a831-807d42124acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941412858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3941412858
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.986101878
Short name T432
Test name
Test status
Simulation time 175467181 ps
CPU time 3.33 seconds
Started Feb 07 02:14:26 PM PST 24
Finished Feb 07 02:14:30 PM PST 24
Peak memory 215552 kb
Host smart-7954c523-c3a1-4aad-8d7a-d61a70872681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986101878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.986101878
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3231348932
Short name T779
Test name
Test status
Simulation time 71388450 ps
CPU time 1.57 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:14:26 PM PST 24
Peak memory 216284 kb
Host smart-61ff14f0-df82-4fdb-ade2-aa91faf578b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231348932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3231348932
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1677673184
Short name T887
Test name
Test status
Simulation time 4857823774 ps
CPU time 32.23 seconds
Started Feb 07 02:14:19 PM PST 24
Finished Feb 07 02:14:53 PM PST 24
Peak memory 209496 kb
Host smart-d69af1ee-1838-45c3-8e72-0c6eec3980ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677673184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1677673184
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3544874102
Short name T976
Test name
Test status
Simulation time 1944162026 ps
CPU time 43 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:15:04 PM PST 24
Peak memory 222836 kb
Host smart-6b7139f5-e5ee-4701-bbf1-6b9bfa2319c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544874102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3544874102
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4198707220
Short name T60
Test name
Test status
Simulation time 49626554 ps
CPU time 3.21 seconds
Started Feb 07 02:14:19 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 208688 kb
Host smart-86589a59-02bb-469f-b251-70ba55f2aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198707220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4198707220
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3239626541
Short name T1
Test name
Test status
Simulation time 50649143 ps
CPU time 3.14 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 209368 kb
Host smart-dcb0a840-b80f-4576-9b48-3de54bb975a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239626541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3239626541
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.747558045
Short name T1093
Test name
Test status
Simulation time 59546349 ps
CPU time 3 seconds
Started Feb 07 02:14:16 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 208516 kb
Host smart-e8d7848b-335f-41bf-9600-23334ee8ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747558045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.747558045
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1186230496
Short name T670
Test name
Test status
Simulation time 183397828 ps
CPU time 4.26 seconds
Started Feb 07 02:14:14 PM PST 24
Finished Feb 07 02:14:19 PM PST 24
Peak memory 208996 kb
Host smart-73f34293-46bf-473b-b81e-48801fe471eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186230496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1186230496
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3943005688
Short name T15
Test name
Test status
Simulation time 305237285 ps
CPU time 2.96 seconds
Started Feb 07 02:14:17 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 206960 kb
Host smart-6a2bbfde-6be4-43e3-8b9e-d5e125575949
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943005688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3943005688
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2414104389
Short name T958
Test name
Test status
Simulation time 121379669 ps
CPU time 2.36 seconds
Started Feb 07 02:14:18 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 206984 kb
Host smart-2f480890-a18e-4e87-989f-1b3621dc740c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414104389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2414104389
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3152824605
Short name T1000
Test name
Test status
Simulation time 165833383 ps
CPU time 2.06 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 218648 kb
Host smart-b1be2ff2-6761-4ad3-bcd6-51a2889e277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152824605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3152824605
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2529530152
Short name T789
Test name
Test status
Simulation time 1410523898 ps
CPU time 16.29 seconds
Started Feb 07 02:14:18 PM PST 24
Finished Feb 07 02:14:37 PM PST 24
Peak memory 208932 kb
Host smart-3f3dd30e-c295-45f7-896b-92d771da95cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529530152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2529530152
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2431258735
Short name T1044
Test name
Test status
Simulation time 724948026 ps
CPU time 7.46 seconds
Started Feb 07 02:14:19 PM PST 24
Finished Feb 07 02:14:28 PM PST 24
Peak memory 208436 kb
Host smart-cc9a67a9-8758-46e7-b646-6bccfc03f60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431258735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2431258735
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3140539459
Short name T719
Test name
Test status
Simulation time 159612018 ps
CPU time 3.45 seconds
Started Feb 07 02:14:27 PM PST 24
Finished Feb 07 02:14:31 PM PST 24
Peak memory 222936 kb
Host smart-83e88478-0539-44cc-8336-0906e3ad2371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140539459 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3140539459
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.200794893
Short name T972
Test name
Test status
Simulation time 2527388928 ps
CPU time 34.75 seconds
Started Feb 07 02:14:21 PM PST 24
Finished Feb 07 02:14:58 PM PST 24
Peak memory 208828 kb
Host smart-9e7e0893-4f69-43cf-a228-90d5f8492705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200794893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.200794893
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3255662608
Short name T868
Test name
Test status
Simulation time 240715210 ps
CPU time 1.71 seconds
Started Feb 07 02:14:15 PM PST 24
Finished Feb 07 02:14:20 PM PST 24
Peak memory 210016 kb
Host smart-45053154-d296-4011-8f1e-334c3e13626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255662608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3255662608
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3540076516
Short name T825
Test name
Test status
Simulation time 93091681 ps
CPU time 0.87 seconds
Started Feb 07 02:14:27 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 206520 kb
Host smart-a68e8be6-79aa-4352-8ca6-c20821505118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540076516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3540076516
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.458149678
Short name T761
Test name
Test status
Simulation time 201621687 ps
CPU time 1.9 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:41 PM PST 24
Peak memory 209612 kb
Host smart-086ee5da-f0ef-4580-a12d-7e4a59ff2719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458149678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.458149678
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1404650049
Short name T986
Test name
Test status
Simulation time 219262181 ps
CPU time 4.43 seconds
Started Feb 07 02:14:26 PM PST 24
Finished Feb 07 02:14:32 PM PST 24
Peak memory 209288 kb
Host smart-a154c1de-34ca-490d-968b-5067a85ee29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404650049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1404650049
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1535564713
Short name T282
Test name
Test status
Simulation time 882599757 ps
CPU time 10.56 seconds
Started Feb 07 02:14:24 PM PST 24
Finished Feb 07 02:14:36 PM PST 24
Peak memory 215708 kb
Host smart-b3952f77-1c1f-42fa-b262-96557df359ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535564713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1535564713
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.547442291
Short name T203
Test name
Test status
Simulation time 574478855 ps
CPU time 2.52 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:14:28 PM PST 24
Peak memory 216300 kb
Host smart-86fd4ea8-be12-451e-96b5-cc3c1eb3c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547442291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.547442291
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1135949512
Short name T821
Test name
Test status
Simulation time 163144834 ps
CPU time 6.35 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:45 PM PST 24
Peak memory 219036 kb
Host smart-711f3460-bc84-4e64-a6d7-28c8b2fd418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135949512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1135949512
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2559260475
Short name T983
Test name
Test status
Simulation time 140119504 ps
CPU time 3.23 seconds
Started Feb 07 02:14:23 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 209104 kb
Host smart-a3c4570b-eccf-461a-a40b-073070517b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559260475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2559260475
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2727341979
Short name T824
Test name
Test status
Simulation time 6349486198 ps
CPU time 44.53 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 208796 kb
Host smart-a3816a81-d193-421e-96cf-2e758d057a6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727341979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2727341979
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2267631438
Short name T632
Test name
Test status
Simulation time 1984280535 ps
CPU time 25.82 seconds
Started Feb 07 02:14:36 PM PST 24
Finished Feb 07 02:15:05 PM PST 24
Peak memory 209196 kb
Host smart-3b0aafdf-92dd-4b69-933c-8299abe64e68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267631438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2267631438
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2454084094
Short name T342
Test name
Test status
Simulation time 153524352 ps
CPU time 5.55 seconds
Started Feb 07 02:14:25 PM PST 24
Finished Feb 07 02:14:32 PM PST 24
Peak memory 207304 kb
Host smart-fbe31888-3f29-4f8c-883a-cb314f887971
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454084094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2454084094
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.700969116
Short name T685
Test name
Test status
Simulation time 121649544 ps
CPU time 4.76 seconds
Started Feb 07 02:14:24 PM PST 24
Finished Feb 07 02:14:30 PM PST 24
Peak memory 210972 kb
Host smart-339e83c2-68d3-4d3f-afec-3bd88e96b39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700969116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.700969116
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1358820173
Short name T797
Test name
Test status
Simulation time 380339107 ps
CPU time 4.69 seconds
Started Feb 07 02:14:36 PM PST 24
Finished Feb 07 02:14:43 PM PST 24
Peak memory 206860 kb
Host smart-eeeac645-8635-42e8-9ef1-271f6349d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358820173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1358820173
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1737345495
Short name T808
Test name
Test status
Simulation time 1894167043 ps
CPU time 10.77 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 221332 kb
Host smart-f28d1735-b8e7-4f92-8541-a2aa7045a7c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737345495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1737345495
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2356522859
Short name T817
Test name
Test status
Simulation time 113309717 ps
CPU time 4.64 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:43 PM PST 24
Peak memory 210300 kb
Host smart-f211ead9-8b6d-400e-8b83-7c777cb34852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356522859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2356522859
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.983598719
Short name T1013
Test name
Test status
Simulation time 81994104 ps
CPU time 3.33 seconds
Started Feb 07 02:14:22 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 210308 kb
Host smart-556b5e37-8dee-4d36-ab9a-362bc1b83a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983598719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.983598719
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2320308953
Short name T436
Test name
Test status
Simulation time 32856637 ps
CPU time 0.84 seconds
Started Feb 07 02:14:39 PM PST 24
Finished Feb 07 02:14:43 PM PST 24
Peak memory 206388 kb
Host smart-e2152bf6-75fa-4048-a092-57bd1311457d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320308953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2320308953
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4080275105
Short name T418
Test name
Test status
Simulation time 69386200 ps
CPU time 4.68 seconds
Started Feb 07 02:14:23 PM PST 24
Finished Feb 07 02:14:30 PM PST 24
Peak memory 215656 kb
Host smart-f3d12e34-3a7e-4a61-ab52-b9897547ec67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080275105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4080275105
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3266513638
Short name T29
Test name
Test status
Simulation time 83687993 ps
CPU time 2.41 seconds
Started Feb 07 02:14:39 PM PST 24
Finished Feb 07 02:14:45 PM PST 24
Peak memory 208932 kb
Host smart-098ba5c4-4a58-4016-b864-059e64b76e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266513638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3266513638
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3610661342
Short name T965
Test name
Test status
Simulation time 145435547 ps
CPU time 3.42 seconds
Started Feb 07 02:14:24 PM PST 24
Finished Feb 07 02:14:29 PM PST 24
Peak memory 207688 kb
Host smart-edd91944-c472-4c92-b8be-e0f321a1ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610661342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3610661342
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.117092104
Short name T674
Test name
Test status
Simulation time 356428875 ps
CPU time 3.28 seconds
Started Feb 07 02:14:21 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 220064 kb
Host smart-842468ff-87f1-4043-85bd-525c4d300ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117092104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.117092104
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2480989183
Short name T979
Test name
Test status
Simulation time 1106097665 ps
CPU time 27.42 seconds
Started Feb 07 02:14:28 PM PST 24
Finished Feb 07 02:14:56 PM PST 24
Peak memory 218740 kb
Host smart-798f4df0-51e6-4a47-a230-c8b89a08fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480989183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2480989183
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4186120532
Short name T1038
Test name
Test status
Simulation time 78620264 ps
CPU time 2.38 seconds
Started Feb 07 02:14:37 PM PST 24
Finished Feb 07 02:14:41 PM PST 24
Peak memory 207064 kb
Host smart-451e95b8-8838-4450-a614-9a7e526399e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186120532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4186120532
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.483442051
Short name T115
Test name
Test status
Simulation time 58261855 ps
CPU time 3 seconds
Started Feb 07 02:14:20 PM PST 24
Finished Feb 07 02:14:25 PM PST 24
Peak memory 208928 kb
Host smart-305fd6ee-4019-4d5c-bf7b-6991e731306f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483442051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.483442051
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2758422337
Short name T264
Test name
Test status
Simulation time 256638956 ps
CPU time 5.39 seconds
Started Feb 07 02:14:26 PM PST 24
Finished Feb 07 02:14:32 PM PST 24
Peak memory 208872 kb
Host smart-b6167553-15ab-4c79-90de-bbef19cb0dbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758422337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2758422337
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2639016730
Short name T1062
Test name
Test status
Simulation time 334290311 ps
CPU time 4.1 seconds
Started Feb 07 02:14:24 PM PST 24
Finished Feb 07 02:14:30 PM PST 24
Peak memory 208920 kb
Host smart-2df5de52-75e9-4090-bc17-7e7e9a774774
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639016730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2639016730
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.769675239
Short name T373
Test name
Test status
Simulation time 97533078 ps
CPU time 2.19 seconds
Started Feb 07 02:14:40 PM PST 24
Finished Feb 07 02:14:45 PM PST 24
Peak memory 214944 kb
Host smart-ceb69a84-1931-4fda-af29-b78745b11e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769675239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.769675239
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2697173012
Short name T754
Test name
Test status
Simulation time 182140798 ps
CPU time 2.46 seconds
Started Feb 07 02:14:24 PM PST 24
Finished Feb 07 02:14:28 PM PST 24
Peak memory 207136 kb
Host smart-3371a3d2-4f41-4432-8ed5-a794fc34a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697173012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2697173012
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4082091859
Short name T56
Test name
Test status
Simulation time 1023268448 ps
CPU time 14.89 seconds
Started Feb 07 02:14:35 PM PST 24
Finished Feb 07 02:14:54 PM PST 24
Peak memory 221580 kb
Host smart-614fdf4e-db9c-40c0-bedc-4e3eb9279f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082091859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4082091859
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1936483964
Short name T785
Test name
Test status
Simulation time 201104512 ps
CPU time 3.32 seconds
Started Feb 07 02:14:33 PM PST 24
Finished Feb 07 02:14:40 PM PST 24
Peak memory 218320 kb
Host smart-5ad7fc89-ae0b-48f1-90ac-7f9e7e51d857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936483964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1936483964
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2032037894
Short name T382
Test name
Test status
Simulation time 670610635 ps
CPU time 15.91 seconds
Started Feb 07 02:14:44 PM PST 24
Finished Feb 07 02:15:00 PM PST 24
Peak memory 208380 kb
Host smart-405be434-c595-477e-8241-3ee3fdb8760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032037894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2032037894
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2437652506
Short name T1024
Test name
Test status
Simulation time 527331175 ps
CPU time 7.52 seconds
Started Feb 07 02:14:38 PM PST 24
Finished Feb 07 02:14:47 PM PST 24
Peak memory 210580 kb
Host smart-35140db5-f9f0-4582-a375-c838f6307cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437652506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2437652506
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.96417111
Short name T1020
Test name
Test status
Simulation time 23562969 ps
CPU time 0.76 seconds
Started Feb 07 02:14:42 PM PST 24
Finished Feb 07 02:14:44 PM PST 24
Peak memory 206452 kb
Host smart-fbaf81f4-a9f6-41d9-8c41-2b923c28bc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96417111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.96417111
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.61308757
Short name T242
Test name
Test status
Simulation time 67264702 ps
CPU time 2.82 seconds
Started Feb 07 02:14:42 PM PST 24
Finished Feb 07 02:14:46 PM PST 24
Peak memory 215444 kb
Host smart-d2d13215-f264-4b72-843f-b25fc7c40bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61308757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.61308757
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2118505562
Short name T1045
Test name
Test status
Simulation time 480855367 ps
CPU time 4.1 seconds
Started Feb 07 02:14:43 PM PST 24
Finished Feb 07 02:14:49 PM PST 24
Peak memory 210788 kb
Host smart-199c3eb1-6d36-4765-bf4a-afcec0b1c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118505562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2118505562
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3612057362
Short name T39
Test name
Test status
Simulation time 350444717 ps
CPU time 3.14 seconds
Started Feb 07 02:14:38 PM PST 24
Finished Feb 07 02:14:42 PM PST 24
Peak memory 214736 kb
Host smart-602caad0-f0e3-4464-a0c8-6269182d1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612057362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3612057362
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1030417033
Short name T665
Test name
Test status
Simulation time 485728775 ps
CPU time 3.93 seconds
Started Feb 07 02:14:37 PM PST 24
Finished Feb 07 02:14:43 PM PST 24
Peak memory 219672 kb
Host smart-dfc92932-c483-4cf6-9c54-9a7285b12a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030417033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1030417033
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2830142972
Short name T851
Test name
Test status
Simulation time 4168526834 ps
CPU time 8.9 seconds
Started Feb 07 02:14:37 PM PST 24
Finished Feb 07 02:14:48 PM PST 24
Peak memory 209892 kb
Host smart-7522df7c-8e26-4cec-b6d4-ca38c705cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830142972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2830142972
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1848112579
Short name T634
Test name
Test status
Simulation time 55882355 ps
CPU time 3.08 seconds
Started Feb 07 02:14:33 PM PST 24
Finished Feb 07 02:14:41 PM PST 24
Peak memory 207152 kb
Host smart-546f37a7-51c9-48f2-b598-40af466e28e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848112579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1848112579
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3717550652
Short name T664
Test name
Test status
Simulation time 265426355 ps
CPU time 6.78 seconds
Started Feb 07 02:14:38 PM PST 24
Finished Feb 07 02:14:47 PM PST 24
Peak memory 208048 kb
Host smart-c71f6ad9-4bad-4dc3-bbe7-9e84c62bbb42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717550652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3717550652
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2399382220
Short name T644
Test name
Test status
Simulation time 49165252 ps
CPU time 2.53 seconds
Started Feb 07 02:14:41 PM PST 24
Finished Feb 07 02:14:46 PM PST 24
Peak memory 207240 kb
Host smart-6afa2cd8-b02b-4f30-942c-ba884ef65f38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399382220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2399382220
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.40021903
Short name T756
Test name
Test status
Simulation time 1418567071 ps
CPU time 7.39 seconds
Started Feb 07 02:14:39 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 208944 kb
Host smart-4f511385-5fec-412f-9140-7e51f05300ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40021903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.40021903
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3127069482
Short name T377
Test name
Test status
Simulation time 20106399 ps
CPU time 1.62 seconds
Started Feb 07 02:14:42 PM PST 24
Finished Feb 07 02:14:45 PM PST 24
Peak memory 208108 kb
Host smart-403f81c7-c27b-4f49-abb4-a0dbab6785e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127069482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3127069482
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3879565313
Short name T1034
Test name
Test status
Simulation time 3180299155 ps
CPU time 19.56 seconds
Started Feb 07 02:14:35 PM PST 24
Finished Feb 07 02:14:58 PM PST 24
Peak memory 208724 kb
Host smart-60f3942a-e2a8-4770-92d1-2812f39a9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879565313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3879565313
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3699094786
Short name T67
Test name
Test status
Simulation time 681405979 ps
CPU time 11.25 seconds
Started Feb 07 02:14:42 PM PST 24
Finished Feb 07 02:14:54 PM PST 24
Peak memory 223092 kb
Host smart-6378b535-dbd4-4a0f-8138-056fa3316659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699094786 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3699094786
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1798112927
Short name T284
Test name
Test status
Simulation time 1105201551 ps
CPU time 11.92 seconds
Started Feb 07 02:14:34 PM PST 24
Finished Feb 07 02:14:51 PM PST 24
Peak memory 218800 kb
Host smart-79863122-a4c7-4ca2-9210-c15a60747311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798112927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1798112927
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3661998822
Short name T706
Test name
Test status
Simulation time 84029965 ps
CPU time 3.55 seconds
Started Feb 07 02:14:39 PM PST 24
Finished Feb 07 02:14:46 PM PST 24
Peak memory 210108 kb
Host smart-94a2a6d5-2d54-42e5-acbe-d687708124de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661998822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3661998822
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3096064071
Short name T1060
Test name
Test status
Simulation time 17786791 ps
CPU time 0.82 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 206400 kb
Host smart-d4ed055e-44f2-4301-845e-5dcefef478c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096064071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3096064071
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2023928240
Short name T894
Test name
Test status
Simulation time 250414915 ps
CPU time 2.11 seconds
Started Feb 07 02:14:45 PM PST 24
Finished Feb 07 02:14:48 PM PST 24
Peak memory 215232 kb
Host smart-58d43b15-f494-41d3-98dc-614f5d0b7a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023928240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2023928240
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.934068026
Short name T994
Test name
Test status
Simulation time 39905991 ps
CPU time 2.12 seconds
Started Feb 07 02:14:47 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 208908 kb
Host smart-e6ee7de5-e649-49c7-a354-ef1a5bc8ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934068026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.934068026
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2772463628
Short name T876
Test name
Test status
Simulation time 153257730 ps
CPU time 6.02 seconds
Started Feb 07 02:14:44 PM PST 24
Finished Feb 07 02:14:52 PM PST 24
Peak memory 220604 kb
Host smart-4dc6b166-2be9-42cb-859d-62079e3b9f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772463628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2772463628
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2125051951
Short name T187
Test name
Test status
Simulation time 234220285 ps
CPU time 7.53 seconds
Started Feb 07 02:14:48 PM PST 24
Finished Feb 07 02:14:56 PM PST 24
Peak memory 210512 kb
Host smart-43e388f6-39ea-486f-8863-4490a28d777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125051951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2125051951
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4151701241
Short name T688
Test name
Test status
Simulation time 279927054 ps
CPU time 4.02 seconds
Started Feb 07 02:14:48 PM PST 24
Finished Feb 07 02:14:53 PM PST 24
Peak memory 219200 kb
Host smart-a22dfff7-b303-4664-a76b-33f132b13238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151701241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4151701241
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.726721976
Short name T392
Test name
Test status
Simulation time 188880232 ps
CPU time 2.65 seconds
Started Feb 07 02:14:43 PM PST 24
Finished Feb 07 02:14:46 PM PST 24
Peak memory 207560 kb
Host smart-980259a3-589f-4f33-a510-f2266a4f4ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726721976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.726721976
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1820258496
Short name T592
Test name
Test status
Simulation time 839065392 ps
CPU time 5.98 seconds
Started Feb 07 02:14:49 PM PST 24
Finished Feb 07 02:14:56 PM PST 24
Peak memory 208168 kb
Host smart-a87774a1-cca1-465c-9ea5-799322af612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820258496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1820258496
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3973433639
Short name T356
Test name
Test status
Simulation time 95134717 ps
CPU time 2.05 seconds
Started Feb 07 02:14:48 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 208776 kb
Host smart-2f502eb5-e490-476c-aa2b-1e01eae1e201
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973433639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3973433639
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3743177042
Short name T880
Test name
Test status
Simulation time 293939547 ps
CPU time 3.88 seconds
Started Feb 07 02:14:44 PM PST 24
Finished Feb 07 02:14:49 PM PST 24
Peak memory 208728 kb
Host smart-388c8532-6046-48f4-9181-19aa50fddf30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743177042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3743177042
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.702664290
Short name T384
Test name
Test status
Simulation time 163416531 ps
CPU time 5.09 seconds
Started Feb 07 02:14:45 PM PST 24
Finished Feb 07 02:14:51 PM PST 24
Peak memory 207028 kb
Host smart-6df0e7e2-aa16-40b3-9ee7-007420ae94f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702664290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.702664290
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.128188042
Short name T850
Test name
Test status
Simulation time 61984328 ps
CPU time 2.31 seconds
Started Feb 07 02:14:44 PM PST 24
Finished Feb 07 02:14:47 PM PST 24
Peak memory 215908 kb
Host smart-ed7d54e5-9597-4d0d-a6a0-0b916073d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128188042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.128188042
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1214846355
Short name T599
Test name
Test status
Simulation time 473829051 ps
CPU time 2.41 seconds
Started Feb 07 02:14:44 PM PST 24
Finished Feb 07 02:14:48 PM PST 24
Peak memory 207032 kb
Host smart-b27258ec-997c-4714-9f63-986aee945bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214846355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1214846355
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2623912185
Short name T195
Test name
Test status
Simulation time 1037111630 ps
CPU time 12.73 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:21 PM PST 24
Peak memory 223052 kb
Host smart-9b15cf11-e25d-4cf8-b0fa-66892deae334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623912185 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2623912185
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1225034452
Short name T224
Test name
Test status
Simulation time 16184689553 ps
CPU time 30.81 seconds
Started Feb 07 02:14:43 PM PST 24
Finished Feb 07 02:15:15 PM PST 24
Peak memory 209544 kb
Host smart-c0c0c168-06de-428a-8fab-834b69f48eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225034452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1225034452
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1853865711
Short name T940
Test name
Test status
Simulation time 174037675 ps
CPU time 2.7 seconds
Started Feb 07 02:14:45 PM PST 24
Finished Feb 07 02:14:49 PM PST 24
Peak memory 210200 kb
Host smart-8ad2add3-2868-4256-ac9a-6a3928d1bb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853865711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1853865711
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.230233881
Short name T784
Test name
Test status
Simulation time 48459713 ps
CPU time 0.88 seconds
Started Feb 07 02:14:55 PM PST 24
Finished Feb 07 02:14:57 PM PST 24
Peak memory 206660 kb
Host smart-56d1f8aa-f472-4acf-b661-13cb9f15a36c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230233881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.230233881
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.842817308
Short name T25
Test name
Test status
Simulation time 1679079536 ps
CPU time 10.76 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 215132 kb
Host smart-e3f167ae-4d6b-4fe9-866e-b11f14ff6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842817308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.842817308
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3070358737
Short name T743
Test name
Test status
Simulation time 76591901 ps
CPU time 1.8 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:14:59 PM PST 24
Peak memory 208528 kb
Host smart-d2b5f598-7967-4e4f-a4c7-ca200c8561ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070358737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3070358737
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1626304523
Short name T241
Test name
Test status
Simulation time 411948734 ps
CPU time 6.6 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:05 PM PST 24
Peak memory 222260 kb
Host smart-587955d7-ff17-439f-8ada-b348f6117fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626304523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1626304523
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2267132680
Short name T1031
Test name
Test status
Simulation time 140339612 ps
CPU time 6.09 seconds
Started Feb 07 02:14:59 PM PST 24
Finished Feb 07 02:15:06 PM PST 24
Peak memory 220692 kb
Host smart-d0d3d26f-5b5e-4973-8f29-1026653e6e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267132680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2267132680
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.454399055
Short name T404
Test name
Test status
Simulation time 244826758 ps
CPU time 7.39 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:05 PM PST 24
Peak memory 218736 kb
Host smart-8a5354d3-e493-49e5-a139-4c3fce7dad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454399055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.454399055
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3793010805
Short name T1035
Test name
Test status
Simulation time 545127109 ps
CPU time 6.59 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:04 PM PST 24
Peak memory 207164 kb
Host smart-96d41664-64e5-447a-97e5-9e24054e9ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793010805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3793010805
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.74356569
Short name T999
Test name
Test status
Simulation time 138075749 ps
CPU time 2.68 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:01 PM PST 24
Peak memory 208864 kb
Host smart-d0c5a19d-774a-490b-8bb2-837bfb278b02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74356569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.74356569
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4047735638
Short name T368
Test name
Test status
Simulation time 33099323 ps
CPU time 2.54 seconds
Started Feb 07 02:14:55 PM PST 24
Finished Feb 07 02:14:58 PM PST 24
Peak memory 207064 kb
Host smart-2d709122-9d91-4c43-93aa-a260905e5620
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047735638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4047735638
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2644472989
Short name T1080
Test name
Test status
Simulation time 34987627 ps
CPU time 2.38 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:14:59 PM PST 24
Peak memory 207196 kb
Host smart-2a774a60-3f9a-43b2-854b-d908bd4c1534
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644472989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2644472989
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2881946452
Short name T328
Test name
Test status
Simulation time 3606367976 ps
CPU time 34.33 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 221236 kb
Host smart-caafbe26-3a35-4f9d-942e-7eaae45aff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881946452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2881946452
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1640866962
Short name T682
Test name
Test status
Simulation time 35225549 ps
CPU time 2.45 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208632 kb
Host smart-7d5b4474-7ecb-4e29-b942-bb452a76be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640866962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1640866962
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.557896147
Short name T319
Test name
Test status
Simulation time 190485032 ps
CPU time 6.03 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:04 PM PST 24
Peak memory 220428 kb
Host smart-bbd1cff7-97fb-44e4-9211-6785add6757a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557896147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.557896147
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.158845411
Short name T192
Test name
Test status
Simulation time 468114104 ps
CPU time 2.23 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:00 PM PST 24
Peak memory 223032 kb
Host smart-5ce9f44b-f778-4311-836b-acfa9dcc460c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158845411 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.158845411
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.558541574
Short name T332
Test name
Test status
Simulation time 157787666 ps
CPU time 7.05 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:05 PM PST 24
Peak memory 210376 kb
Host smart-929cdee8-c49f-4710-bf60-9c3ed6197942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558541574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.558541574
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2893037135
Short name T1015
Test name
Test status
Simulation time 92949190 ps
CPU time 1.97 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:14:59 PM PST 24
Peak memory 210092 kb
Host smart-f2d22336-960f-418c-9a68-b12eac579966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893037135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2893037135
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3752932574
Short name T746
Test name
Test status
Simulation time 130553627 ps
CPU time 0.83 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 206456 kb
Host smart-6b824449-1f9a-49e7-94dc-44020851e632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752932574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3752932574
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2490044998
Short name T769
Test name
Test status
Simulation time 86438577 ps
CPU time 2.83 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 210024 kb
Host smart-a0d513c0-f28d-41c5-adb7-d933ef25f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490044998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2490044998
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3949568932
Short name T336
Test name
Test status
Simulation time 417927659 ps
CPU time 3.35 seconds
Started Feb 07 02:15:02 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 207960 kb
Host smart-136826cb-140f-405e-8159-03c82e84f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949568932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3949568932
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3366971785
Short name T261
Test name
Test status
Simulation time 375282331 ps
CPU time 11.76 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 212240 kb
Host smart-d8172df7-e695-4ee0-88b6-33a9c36a20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366971785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3366971785
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1032759139
Short name T422
Test name
Test status
Simulation time 107612251 ps
CPU time 2.85 seconds
Started Feb 07 02:14:58 PM PST 24
Finished Feb 07 02:15:02 PM PST 24
Peak memory 215472 kb
Host smart-af80ffcf-889d-465c-bf41-e2610a1dcacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032759139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1032759139
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2163010567
Short name T951
Test name
Test status
Simulation time 135429827 ps
CPU time 5.98 seconds
Started Feb 07 02:14:55 PM PST 24
Finished Feb 07 02:15:02 PM PST 24
Peak memory 209532 kb
Host smart-34358947-7407-4efa-a0d5-18adc97d77dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163010567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2163010567
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.501528014
Short name T740
Test name
Test status
Simulation time 137231309 ps
CPU time 5.62 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 207568 kb
Host smart-d624ba68-284b-430b-8bd7-c0473006853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501528014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.501528014
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4242594158
Short name T679
Test name
Test status
Simulation time 881521802 ps
CPU time 10.01 seconds
Started Feb 07 02:14:58 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 208448 kb
Host smart-2ee5532e-43a8-40ba-94f2-e8163cb13c04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242594158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4242594158
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.856535472
Short name T671
Test name
Test status
Simulation time 1244506462 ps
CPU time 7.67 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:06 PM PST 24
Peak memory 208904 kb
Host smart-a3e74c20-825c-4d94-be95-2387dfb5dad4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856535472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.856535472
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4174667467
Short name T720
Test name
Test status
Simulation time 1440388991 ps
CPU time 10.1 seconds
Started Feb 07 02:14:59 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208984 kb
Host smart-cf671ccf-3bc1-4690-8729-06b07647f9ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174667467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4174667467
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1995470677
Short name T991
Test name
Test status
Simulation time 23809886 ps
CPU time 1.83 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 215628 kb
Host smart-039fa6b4-4452-4f8a-859c-e8fa67a7aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995470677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1995470677
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2516130720
Short name T617
Test name
Test status
Simulation time 88237047 ps
CPU time 3.33 seconds
Started Feb 07 02:14:57 PM PST 24
Finished Feb 07 02:15:01 PM PST 24
Peak memory 206640 kb
Host smart-3b99b9e2-3701-448b-ae6a-073d967f6fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516130720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2516130720
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2767077207
Short name T1054
Test name
Test status
Simulation time 5649418445 ps
CPU time 71.52 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:16:08 PM PST 24
Peak memory 216536 kb
Host smart-8f72eb9a-442a-4be8-bd1b-2e486ba9dcd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767077207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2767077207
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2659415917
Short name T106
Test name
Test status
Simulation time 84748962 ps
CPU time 6.18 seconds
Started Feb 07 02:15:01 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 223080 kb
Host smart-c25f99d5-ffa9-41da-8d74-86fede8322a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659415917 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2659415917
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.411226197
Short name T748
Test name
Test status
Simulation time 77713540 ps
CPU time 4.65 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:02 PM PST 24
Peak memory 210540 kb
Host smart-6703d02b-3a8f-4d9a-b8cb-60174f898067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411226197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.411226197
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.312091448
Short name T732
Test name
Test status
Simulation time 51141526 ps
CPU time 2.73 seconds
Started Feb 07 02:15:01 PM PST 24
Finished Feb 07 02:15:06 PM PST 24
Peak memory 210080 kb
Host smart-09f7ec88-9cca-4826-b77c-a67f450abec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312091448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.312091448
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1311517138
Short name T87
Test name
Test status
Simulation time 34052299 ps
CPU time 0.76 seconds
Started Feb 07 02:11:16 PM PST 24
Finished Feb 07 02:11:17 PM PST 24
Peak memory 206508 kb
Host smart-e74faf5c-4ac4-41bb-8e90-b316a5b2de03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311517138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1311517138
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1384877369
Short name T393
Test name
Test status
Simulation time 4369694675 ps
CPU time 59.31 seconds
Started Feb 07 02:11:00 PM PST 24
Finished Feb 07 02:12:00 PM PST 24
Peak memory 217664 kb
Host smart-a0a7c86b-5882-4a64-94b2-81b54e9875a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384877369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1384877369
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.570835569
Short name T694
Test name
Test status
Simulation time 384160402 ps
CPU time 4.64 seconds
Started Feb 07 02:11:27 PM PST 24
Finished Feb 07 02:11:32 PM PST 24
Peak memory 218912 kb
Host smart-1211799f-489a-473d-a241-e29d54694983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570835569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.570835569
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1573649548
Short name T618
Test name
Test status
Simulation time 32051928 ps
CPU time 2.33 seconds
Started Feb 07 02:10:58 PM PST 24
Finished Feb 07 02:11:01 PM PST 24
Peak memory 210692 kb
Host smart-0734a3ca-ea33-4c16-bcf8-a9f94acf8ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573649548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1573649548
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.712521668
Short name T209
Test name
Test status
Simulation time 310591741 ps
CPU time 6.27 seconds
Started Feb 07 02:11:01 PM PST 24
Finished Feb 07 02:11:08 PM PST 24
Peak memory 210132 kb
Host smart-d2ec2803-4328-4ffd-a342-9f6df3f9559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712521668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.712521668
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2023538513
Short name T388
Test name
Test status
Simulation time 161550492 ps
CPU time 3.28 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 208552 kb
Host smart-d8f828d8-cbdd-415c-adf1-f2d8ed1f5976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023538513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2023538513
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2731047077
Short name T10
Test name
Test status
Simulation time 5759258827 ps
CPU time 161.28 seconds
Started Feb 07 02:11:15 PM PST 24
Finished Feb 07 02:13:57 PM PST 24
Peak memory 243420 kb
Host smart-6e3188a7-78af-4103-b718-6ed1c1be0449
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731047077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2731047077
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.530407775
Short name T790
Test name
Test status
Simulation time 1272517022 ps
CPU time 6.9 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:03 PM PST 24
Peak memory 207536 kb
Host smart-92343fca-0eea-4559-9315-f452834f4143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530407775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.530407775
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3550032064
Short name T288
Test name
Test status
Simulation time 55099161 ps
CPU time 2.43 seconds
Started Feb 07 02:10:57 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 208888 kb
Host smart-9a100a1f-c8c6-48d1-89d6-2a9e638d13bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550032064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3550032064
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3041528277
Short name T602
Test name
Test status
Simulation time 53595878 ps
CPU time 2.99 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 207192 kb
Host smart-23587150-0656-494b-ad86-8996b04f7271
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041528277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3041528277
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4064245909
Short name T767
Test name
Test status
Simulation time 134780806 ps
CPU time 4.21 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:11:01 PM PST 24
Peak memory 208196 kb
Host smart-2fbffd73-15ae-48b5-ac0c-3a13f9dccbdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064245909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4064245909
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1975679371
Short name T973
Test name
Test status
Simulation time 39444884 ps
CPU time 1.83 seconds
Started Feb 07 02:11:16 PM PST 24
Finished Feb 07 02:11:19 PM PST 24
Peak memory 207520 kb
Host smart-dc55d0b2-fab0-45ee-ba5b-a653470a4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975679371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1975679371
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1453136913
Short name T924
Test name
Test status
Simulation time 117020836 ps
CPU time 3.06 seconds
Started Feb 07 02:10:56 PM PST 24
Finished Feb 07 02:10:59 PM PST 24
Peak memory 206944 kb
Host smart-a08f7af7-5801-4b9f-81c7-951dc2f4c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453136913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1453136913
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.826147953
Short name T222
Test name
Test status
Simulation time 275706012 ps
CPU time 7.92 seconds
Started Feb 07 02:11:00 PM PST 24
Finished Feb 07 02:11:09 PM PST 24
Peak memory 214812 kb
Host smart-65df0ab7-b520-463b-87bc-a67f72dff0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826147953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.826147953
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3817105098
Short name T701
Test name
Test status
Simulation time 49981705 ps
CPU time 1.98 seconds
Started Feb 07 02:11:16 PM PST 24
Finished Feb 07 02:11:19 PM PST 24
Peak memory 210316 kb
Host smart-5b6b0904-09c2-4031-9bf9-ddaa50e49c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817105098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3817105098
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2481904302
Short name T611
Test name
Test status
Simulation time 47106583 ps
CPU time 0.74 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 206448 kb
Host smart-aeebffeb-fc5d-4180-b495-f253b2bb8144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481904302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2481904302
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2201908983
Short name T118
Test name
Test status
Simulation time 60124864 ps
CPU time 3.45 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:00 PM PST 24
Peak memory 215904 kb
Host smart-c0a4378d-fb0d-457f-939c-0a7c68ba9043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201908983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2201908983
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2188145721
Short name T58
Test name
Test status
Simulation time 71792134 ps
CPU time 3.99 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 210908 kb
Host smart-202f1229-6cb4-4bc0-9526-be18e377daa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188145721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2188145721
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1234262055
Short name T257
Test name
Test status
Simulation time 752595992 ps
CPU time 20.09 seconds
Started Feb 07 02:15:03 PM PST 24
Finished Feb 07 02:15:27 PM PST 24
Peak memory 209980 kb
Host smart-b862e403-77fe-49a2-b230-442a18bca930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234262055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1234262055
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4227722024
Short name T869
Test name
Test status
Simulation time 116434082 ps
CPU time 3.51 seconds
Started Feb 07 02:14:55 PM PST 24
Finished Feb 07 02:14:59 PM PST 24
Peak memory 209484 kb
Host smart-1f861d5d-ffd2-4afb-a9f9-b940185cc0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227722024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4227722024
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.897439631
Short name T836
Test name
Test status
Simulation time 225810667 ps
CPU time 2.9 seconds
Started Feb 07 02:14:58 PM PST 24
Finished Feb 07 02:15:02 PM PST 24
Peak memory 206892 kb
Host smart-c02c1900-19ac-45ec-a6a3-81f172dcf082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897439631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.897439631
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1333171198
Short name T274
Test name
Test status
Simulation time 386069925 ps
CPU time 4.43 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 210280 kb
Host smart-cd17eca8-dfb1-4aea-9bf6-2574bf54aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333171198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1333171198
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4098251737
Short name T1056
Test name
Test status
Simulation time 167454016 ps
CPU time 1.89 seconds
Started Feb 07 02:15:03 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 207240 kb
Host smart-c2fbba16-cd6d-40ca-963f-239e8006fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098251737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4098251737
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1162721009
Short name T802
Test name
Test status
Simulation time 186568634 ps
CPU time 4.2 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:01 PM PST 24
Peak memory 209160 kb
Host smart-cd95e318-468d-449c-8ce3-ba78a71e8509
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162721009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1162721009
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3155509678
Short name T878
Test name
Test status
Simulation time 43610996 ps
CPU time 1.83 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 207100 kb
Host smart-50cb9dc6-f67d-4e90-bd98-3d9375b8f943
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155509678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3155509678
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3953841103
Short name T689
Test name
Test status
Simulation time 106345093 ps
CPU time 2.94 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 207688 kb
Host smart-45c76833-6cc2-425a-85da-6a8fe96f052d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953841103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3953841103
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1588748003
Short name T666
Test name
Test status
Simulation time 185218106 ps
CPU time 4.51 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 209556 kb
Host smart-6bb3d0d5-687d-492f-bfc5-e9ae81b0c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588748003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1588748003
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1994730363
Short name T613
Test name
Test status
Simulation time 472015726 ps
CPU time 5.63 seconds
Started Feb 07 02:14:56 PM PST 24
Finished Feb 07 02:15:02 PM PST 24
Peak memory 206664 kb
Host smart-bdcac31a-a2d8-4e24-b53a-12bcaf2a7bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994730363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1994730363
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2235103344
Short name T46
Test name
Test status
Simulation time 1346218727 ps
CPU time 28.17 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:35 PM PST 24
Peak memory 215852 kb
Host smart-6dea1358-afe4-4a61-8770-1d646b1d2795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235103344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2235103344
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.532513880
Short name T759
Test name
Test status
Simulation time 657515487 ps
CPU time 8.12 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:15 PM PST 24
Peak memory 222984 kb
Host smart-a35755e5-8212-4b9b-8575-c5d43ce3cfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532513880 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.532513880
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1652228364
Short name T741
Test name
Test status
Simulation time 241031158 ps
CPU time 4.19 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 207648 kb
Host smart-174f7a71-4ee4-4520-ae34-2ae51ba2fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652228364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1652228364
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3446744842
Short name T33
Test name
Test status
Simulation time 132018070 ps
CPU time 1.63 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 209960 kb
Host smart-17bfbdec-e991-41e9-9bab-65d03aa3a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446744842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3446744842
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3429934765
Short name T636
Test name
Test status
Simulation time 42899040 ps
CPU time 0.76 seconds
Started Feb 07 02:15:18 PM PST 24
Finished Feb 07 02:15:19 PM PST 24
Peak memory 206312 kb
Host smart-bbd63190-d781-4a09-8ff5-0e92f2a0ad3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429934765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3429934765
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3000816635
Short name T310
Test name
Test status
Simulation time 95892792 ps
CPU time 5.46 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:15:16 PM PST 24
Peak memory 215144 kb
Host smart-0c6ddb83-aed4-4621-a020-ecb4c873360a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000816635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3000816635
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1889018749
Short name T996
Test name
Test status
Simulation time 158088915 ps
CPU time 1.67 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 209704 kb
Host smart-97f00366-4128-4e5f-b456-ad89ec4b2dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889018749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1889018749
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2681027159
Short name T396
Test name
Test status
Simulation time 57631814 ps
CPU time 2.16 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 209280 kb
Host smart-8ee98746-b857-4313-b894-036fe40ba20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681027159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2681027159
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3833556038
Short name T231
Test name
Test status
Simulation time 759194258 ps
CPU time 3.92 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 223004 kb
Host smart-f5f73840-94a2-4b19-95fa-3d48e2e9a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833556038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3833556038
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3598921813
Short name T5
Test name
Test status
Simulation time 72626344 ps
CPU time 2.69 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 216904 kb
Host smart-d1e6ba92-96bb-414f-85e5-8d6ef107eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598921813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3598921813
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2898705949
Short name T329
Test name
Test status
Simulation time 414684258 ps
CPU time 4.21 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:25 PM PST 24
Peak memory 209248 kb
Host smart-d6caf20c-127f-47cc-8246-5e6ca98d1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898705949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2898705949
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3467955806
Short name T796
Test name
Test status
Simulation time 246282048 ps
CPU time 3.35 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208992 kb
Host smart-155b0c50-83d8-45ea-a7db-d277d28a4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467955806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3467955806
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.742277817
Short name T750
Test name
Test status
Simulation time 208788967 ps
CPU time 6.36 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:17 PM PST 24
Peak memory 208640 kb
Host smart-c893d0c8-c55b-476b-868b-5c31c5abdfab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742277817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.742277817
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1353389263
Short name T864
Test name
Test status
Simulation time 37496536 ps
CPU time 2.46 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:09 PM PST 24
Peak memory 209012 kb
Host smart-6738e24a-24ce-46f6-88b8-17915533ebf0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353389263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1353389263
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4191540738
Short name T971
Test name
Test status
Simulation time 161826367 ps
CPU time 3.47 seconds
Started Feb 07 02:15:10 PM PST 24
Finished Feb 07 02:15:15 PM PST 24
Peak memory 208968 kb
Host smart-d4afc077-b299-412f-ab16-e54577996c42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191540738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4191540738
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3726788716
Short name T621
Test name
Test status
Simulation time 270429341 ps
CPU time 5.59 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 208980 kb
Host smart-4eb6a17a-d8cc-4bca-9317-c1ea0284bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726788716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3726788716
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3862677105
Short name T673
Test name
Test status
Simulation time 523155818 ps
CPU time 2.98 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 206920 kb
Host smart-323e4eba-33e8-4655-80b6-f60169f580d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862677105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3862677105
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1922297987
Short name T69
Test name
Test status
Simulation time 9152028601 ps
CPU time 11.37 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:18 PM PST 24
Peak memory 217380 kb
Host smart-c596f8cb-78e6-4a6a-8bb6-7275d0b8e21e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922297987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1922297987
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3804880810
Short name T773
Test name
Test status
Simulation time 75344457 ps
CPU time 5.85 seconds
Started Feb 07 02:15:10 PM PST 24
Finished Feb 07 02:15:17 PM PST 24
Peak memory 219752 kb
Host smart-080bfa2e-26a3-46d5-9752-51c3c414009a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804880810 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3804880810
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.599018560
Short name T881
Test name
Test status
Simulation time 724918115 ps
CPU time 5.12 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:12 PM PST 24
Peak memory 210252 kb
Host smart-91513dc9-eea5-4d32-beb7-37bb342525e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599018560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.599018560
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1394213479
Short name T650
Test name
Test status
Simulation time 125477086 ps
CPU time 2.04 seconds
Started Feb 07 02:15:02 PM PST 24
Finished Feb 07 02:15:08 PM PST 24
Peak memory 210272 kb
Host smart-deddde1e-8318-4492-a99a-5a26e7051af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394213479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1394213479
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3815205577
Short name T596
Test name
Test status
Simulation time 25253702 ps
CPU time 0.81 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 206440 kb
Host smart-20c3a23d-e11a-4f46-8925-5e3b64def0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815205577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3815205577
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2779923889
Short name T607
Test name
Test status
Simulation time 216674743 ps
CPU time 2.86 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208156 kb
Host smart-97c37e85-9b86-4c00-8192-83cb2c424450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779923889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2779923889
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1305958092
Short name T963
Test name
Test status
Simulation time 846191813 ps
CPU time 3.9 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 209312 kb
Host smart-a37505d6-e310-4484-bb2f-0b3eace43132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305958092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1305958092
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1232379246
Short name T281
Test name
Test status
Simulation time 93507069 ps
CPU time 4.66 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 211200 kb
Host smart-a65e08e8-1b60-4bcf-bb7b-cbb1f96e41e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232379246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1232379246
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3813798775
Short name T379
Test name
Test status
Simulation time 267507775 ps
CPU time 2.78 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:15:14 PM PST 24
Peak memory 209660 kb
Host smart-39195c80-ee20-47da-930a-2cafa1786b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813798775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3813798775
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.197821279
Short name T816
Test name
Test status
Simulation time 455226672 ps
CPU time 4.87 seconds
Started Feb 07 02:15:11 PM PST 24
Finished Feb 07 02:15:17 PM PST 24
Peak memory 210072 kb
Host smart-d8ddab05-cf8d-4c3d-9871-a9d136448665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197821279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.197821279
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.832906530
Short name T223
Test name
Test status
Simulation time 47951066 ps
CPU time 2.66 seconds
Started Feb 07 02:15:05 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208900 kb
Host smart-f20903ed-b03a-4ed5-b2e5-037d919f8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832906530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.832906530
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3304729137
Short name T696
Test name
Test status
Simulation time 159451034 ps
CPU time 2.4 seconds
Started Feb 07 02:15:07 PM PST 24
Finished Feb 07 02:15:12 PM PST 24
Peak memory 207228 kb
Host smart-89adf05e-0710-41ed-95e5-d82e9996f9af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304729137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3304729137
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1186016232
Short name T803
Test name
Test status
Simulation time 480403880 ps
CPU time 9.03 seconds
Started Feb 07 02:15:09 PM PST 24
Finished Feb 07 02:15:20 PM PST 24
Peak memory 208340 kb
Host smart-3fa70ff3-c3e2-4be2-83da-b6c26341291e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186016232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1186016232
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1400544107
Short name T974
Test name
Test status
Simulation time 556301446 ps
CPU time 4.08 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 207080 kb
Host smart-adf10927-e4dc-4df3-8fcc-af680775c59f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400544107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1400544107
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.946414586
Short name T352
Test name
Test status
Simulation time 382363361 ps
CPU time 9.29 seconds
Started Feb 07 02:15:18 PM PST 24
Finished Feb 07 02:15:28 PM PST 24
Peak memory 218880 kb
Host smart-62cf7c92-22d2-49fe-b9fb-0f3ac4083038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946414586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.946414586
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4194224396
Short name T801
Test name
Test status
Simulation time 2297744924 ps
CPU time 40.54 seconds
Started Feb 07 02:15:10 PM PST 24
Finished Feb 07 02:15:52 PM PST 24
Peak memory 209404 kb
Host smart-ae3ceb1e-47c4-4419-8cef-2d8e0015e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194224396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4194224396
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2471340343
Short name T1061
Test name
Test status
Simulation time 522939426 ps
CPU time 7.19 seconds
Started Feb 07 02:15:18 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 208324 kb
Host smart-3389ffd8-5dbd-4f9d-989d-733ac2129d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471340343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2471340343
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3513709966
Short name T798
Test name
Test status
Simulation time 2427756167 ps
CPU time 8.15 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:15 PM PST 24
Peak memory 219736 kb
Host smart-d2786c0c-4cc0-480d-9b7f-393bd8f24c92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513709966 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3513709966
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.336416013
Short name T648
Test name
Test status
Simulation time 119705987 ps
CPU time 5.14 seconds
Started Feb 07 02:15:06 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 218760 kb
Host smart-157c8b51-aab3-47f2-ad17-638b45fc06be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336416013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.336416013
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.283892518
Short name T849
Test name
Test status
Simulation time 6152785155 ps
CPU time 12.84 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 211804 kb
Host smart-f0f5ae61-9ca6-4a3f-9e8d-12aba360b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283892518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.283892518
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.225435330
Short name T937
Test name
Test status
Simulation time 18496450 ps
CPU time 0.74 seconds
Started Feb 07 02:15:18 PM PST 24
Finished Feb 07 02:15:20 PM PST 24
Peak memory 206388 kb
Host smart-829db704-e58f-477c-82a8-a839d0717eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225435330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.225435330
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3498404008
Short name T333
Test name
Test status
Simulation time 58843356 ps
CPU time 4.37 seconds
Started Feb 07 02:15:24 PM PST 24
Finished Feb 07 02:15:29 PM PST 24
Peak memory 215184 kb
Host smart-e15e4753-fec6-419d-85f8-0fbe68bb231d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498404008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3498404008
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1803178629
Short name T952
Test name
Test status
Simulation time 217897987 ps
CPU time 4.08 seconds
Started Feb 07 02:15:21 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 223280 kb
Host smart-48ecea43-f517-48e2-9dba-c44e0fec73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803178629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1803178629
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2316124799
Short name T119
Test name
Test status
Simulation time 99678161 ps
CPU time 2.05 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 223072 kb
Host smart-880a510c-c900-431c-b8e1-78b5b7070a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316124799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2316124799
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1177086997
Short name T353
Test name
Test status
Simulation time 150975831 ps
CPU time 4.79 seconds
Started Feb 07 02:15:26 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 214888 kb
Host smart-412b6f90-6680-4fc0-925b-ccef8c9c1b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177086997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1177086997
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3224330321
Short name T280
Test name
Test status
Simulation time 201512897 ps
CPU time 8.65 seconds
Started Feb 07 02:15:21 PM PST 24
Finished Feb 07 02:15:30 PM PST 24
Peak memory 222904 kb
Host smart-9bd849d8-ee19-4a5f-9d65-7843eb36cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224330321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3224330321
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.402729344
Short name T862
Test name
Test status
Simulation time 125986230 ps
CPU time 3.06 seconds
Started Feb 07 02:15:19 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 214832 kb
Host smart-f8ae53ac-fc96-4416-8b8f-a1b014e8c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402729344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.402729344
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3304063003
Short name T371
Test name
Test status
Simulation time 328700838 ps
CPU time 5.25 seconds
Started Feb 07 02:15:22 PM PST 24
Finished Feb 07 02:15:28 PM PST 24
Peak memory 210400 kb
Host smart-37a156f5-e502-45c5-bb57-87b6a2fe9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304063003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3304063003
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.841027075
Short name T872
Test name
Test status
Simulation time 2044046492 ps
CPU time 37.07 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:48 PM PST 24
Peak memory 208436 kb
Host smart-31f5135e-74ed-43e9-8fd8-4dcf7fd6a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841027075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.841027075
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2659593458
Short name T749
Test name
Test status
Simulation time 107575687 ps
CPU time 2.95 seconds
Started Feb 07 02:15:08 PM PST 24
Finished Feb 07 02:15:13 PM PST 24
Peak memory 207180 kb
Host smart-8fb9f176-af7c-4009-95ed-4032b8b61641
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659593458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2659593458
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2356382674
Short name T739
Test name
Test status
Simulation time 665006814 ps
CPU time 5.65 seconds
Started Feb 07 02:15:18 PM PST 24
Finished Feb 07 02:15:24 PM PST 24
Peak memory 208000 kb
Host smart-20075d13-7c00-45c2-9d6f-4932581d329a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356382674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2356382674
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3437294155
Short name T804
Test name
Test status
Simulation time 4443582039 ps
CPU time 38.12 seconds
Started Feb 07 02:15:23 PM PST 24
Finished Feb 07 02:16:01 PM PST 24
Peak memory 214956 kb
Host smart-820ad38a-2bd2-449a-ad77-7eaa7a73d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437294155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3437294155
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3613115582
Short name T603
Test name
Test status
Simulation time 107044392 ps
CPU time 3.01 seconds
Started Feb 07 02:15:04 PM PST 24
Finished Feb 07 02:15:10 PM PST 24
Peak memory 208448 kb
Host smart-268dcac6-d2a9-467d-8ba4-c286539de52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613115582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3613115582
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1604357306
Short name T376
Test name
Test status
Simulation time 887328910 ps
CPU time 25 seconds
Started Feb 07 02:15:24 PM PST 24
Finished Feb 07 02:15:49 PM PST 24
Peak memory 217476 kb
Host smart-0428686e-0c6e-4ab7-b623-3986f0490779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604357306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1604357306
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4211975946
Short name T1018
Test name
Test status
Simulation time 2050524046 ps
CPU time 4.84 seconds
Started Feb 07 02:15:26 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 223088 kb
Host smart-08793e8b-7351-42cb-b39a-5280e8fe1403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211975946 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4211975946
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3463831192
Short name T777
Test name
Test status
Simulation time 62237395 ps
CPU time 3.39 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:33 PM PST 24
Peak memory 210304 kb
Host smart-6ad674f0-6ac4-48f3-baab-5a7523b61fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463831192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3463831192
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3108896203
Short name T794
Test name
Test status
Simulation time 47678884 ps
CPU time 0.72 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 206492 kb
Host smart-1acf00a6-e31f-40c5-9180-61fe61368806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108896203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3108896203
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1876414038
Short name T425
Test name
Test status
Simulation time 59846379 ps
CPU time 4.15 seconds
Started Feb 07 02:15:21 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 215388 kb
Host smart-778adb73-9e99-4ab6-895b-5101f049982e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876414038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1876414038
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.692367654
Short name T34
Test name
Test status
Simulation time 94467722 ps
CPU time 3.49 seconds
Started Feb 07 02:15:23 PM PST 24
Finished Feb 07 02:15:27 PM PST 24
Peak memory 214712 kb
Host smart-1b8d14f1-501f-4f7e-8610-9ac6b4e25c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692367654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.692367654
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3069235353
Short name T63
Test name
Test status
Simulation time 702126039 ps
CPU time 23.34 seconds
Started Feb 07 02:15:26 PM PST 24
Finished Feb 07 02:15:50 PM PST 24
Peak memory 218920 kb
Host smart-f60eac0f-351b-4dfb-a9fe-b8f5b84e3511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069235353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3069235353
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3099913855
Short name T80
Test name
Test status
Simulation time 1017576417 ps
CPU time 10.68 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 210004 kb
Host smart-b46bf073-b7e8-4a5c-9b35-caca6057cbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099913855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3099913855
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.259576882
Short name T232
Test name
Test status
Simulation time 88229431 ps
CPU time 4.22 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:25 PM PST 24
Peak memory 214780 kb
Host smart-0403b7f7-ed83-4eba-89d5-ead44a835442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259576882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.259576882
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1197630581
Short name T795
Test name
Test status
Simulation time 471631127 ps
CPU time 5.95 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:27 PM PST 24
Peak memory 215508 kb
Host smart-b49c917a-e3f8-4aec-a418-1ef04ef31be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197630581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1197630581
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.609747561
Short name T345
Test name
Test status
Simulation time 272681272 ps
CPU time 6.72 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:37 PM PST 24
Peak memory 209376 kb
Host smart-d6449478-ed9d-4ef0-8cfb-936ebe46a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609747561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.609747561
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.390171000
Short name T645
Test name
Test status
Simulation time 41722926 ps
CPU time 2.45 seconds
Started Feb 07 02:15:19 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 207208 kb
Host smart-f18a74a1-86b3-4d58-ac3d-d42a3fef460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390171000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.390171000
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3672686776
Short name T782
Test name
Test status
Simulation time 18799538 ps
CPU time 1.82 seconds
Started Feb 07 02:15:25 PM PST 24
Finished Feb 07 02:15:28 PM PST 24
Peak memory 207028 kb
Host smart-c759c959-9281-4e70-88e4-1994faee519c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672686776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3672686776
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3689153939
Short name T296
Test name
Test status
Simulation time 208373954 ps
CPU time 6.07 seconds
Started Feb 07 02:15:19 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 208084 kb
Host smart-4e3ac9ad-be3c-4d16-acf3-97d6d520e0b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689153939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3689153939
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.921882153
Short name T977
Test name
Test status
Simulation time 47227451 ps
CPU time 2.74 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:24 PM PST 24
Peak memory 207092 kb
Host smart-51da2f28-b3cd-43ba-abe5-7d4e9264e656
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921882153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.921882153
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.895747292
Short name T1089
Test name
Test status
Simulation time 363630619 ps
CPU time 4.48 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 210128 kb
Host smart-ee3ba16f-8c80-4d29-8caf-277e7ac254a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895747292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.895747292
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3578770661
Short name T902
Test name
Test status
Simulation time 206209185 ps
CPU time 7.63 seconds
Started Feb 07 02:15:25 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 208828 kb
Host smart-df195599-74c9-463b-ab81-1056b78b8f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578770661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3578770661
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2326208545
Short name T289
Test name
Test status
Simulation time 23256175655 ps
CPU time 744.42 seconds
Started Feb 07 02:15:21 PM PST 24
Finished Feb 07 02:27:47 PM PST 24
Peak memory 223020 kb
Host smart-51482df7-ef56-4728-b319-fa9c53927d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326208545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2326208545
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2039906406
Short name T1026
Test name
Test status
Simulation time 356496065 ps
CPU time 9.76 seconds
Started Feb 07 02:15:19 PM PST 24
Finished Feb 07 02:15:30 PM PST 24
Peak memory 221320 kb
Host smart-956cd2e7-f667-401d-9dce-11010bf0a948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039906406 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2039906406
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3644840254
Short name T619
Test name
Test status
Simulation time 27374510025 ps
CPU time 59.32 seconds
Started Feb 07 02:15:22 PM PST 24
Finished Feb 07 02:16:22 PM PST 24
Peak memory 214864 kb
Host smart-57897c10-b13b-4457-86aa-83e448609e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644840254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3644840254
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1631664349
Short name T776
Test name
Test status
Simulation time 73589987 ps
CPU time 1.48 seconds
Started Feb 07 02:15:24 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 210312 kb
Host smart-387b3bfe-9570-459b-9972-f94f77e9bb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631664349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1631664349
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3168300864
Short name T980
Test name
Test status
Simulation time 43863391 ps
CPU time 0.89 seconds
Started Feb 07 02:15:32 PM PST 24
Finished Feb 07 02:15:33 PM PST 24
Peak memory 206396 kb
Host smart-386fe7ef-8691-46cf-9f23-da6effe90cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168300864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3168300864
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1806464145
Short name T718
Test name
Test status
Simulation time 226209916 ps
CPU time 3.05 seconds
Started Feb 07 02:15:31 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 215124 kb
Host smart-41a7c23e-0a87-4525-8e0c-c13ff34cc190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806464145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1806464145
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4160234614
Short name T1070
Test name
Test status
Simulation time 35918404 ps
CPU time 1.98 seconds
Started Feb 07 02:15:27 PM PST 24
Finished Feb 07 02:15:30 PM PST 24
Peak memory 208972 kb
Host smart-eea0625c-094f-4737-833a-00bcc45c4ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160234614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4160234614
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1531773605
Short name T370
Test name
Test status
Simulation time 3385904000 ps
CPU time 10.76 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:40 PM PST 24
Peak memory 215116 kb
Host smart-6dbaa3db-4987-4918-8889-cf1106d892ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531773605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1531773605
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.891273634
Short name T233
Test name
Test status
Simulation time 84518830 ps
CPU time 3.91 seconds
Started Feb 07 02:15:26 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 222776 kb
Host smart-e470032a-3a9e-42c6-ac93-33e276812e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891273634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.891273634
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.995010775
Short name T895
Test name
Test status
Simulation time 324486004 ps
CPU time 3.98 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:35 PM PST 24
Peak memory 209840 kb
Host smart-09322ee8-9474-4364-b8e6-bc28f75348a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995010775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.995010775
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1205022310
Short name T660
Test name
Test status
Simulation time 434369000 ps
CPU time 8.94 seconds
Started Feb 07 02:15:34 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 209472 kb
Host smart-8fa7a729-7855-4ae6-9ecf-046db98d47a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205022310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1205022310
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2879643383
Short name T916
Test name
Test status
Simulation time 47408349 ps
CPU time 2.91 seconds
Started Feb 07 02:15:24 PM PST 24
Finished Feb 07 02:15:28 PM PST 24
Peak memory 208876 kb
Host smart-3934506c-e4f2-40cf-b587-56e9b7a5a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879643383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2879643383
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2842371136
Short name T906
Test name
Test status
Simulation time 53285224 ps
CPU time 2.82 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:24 PM PST 24
Peak memory 207236 kb
Host smart-0bb348e0-4651-4621-aa39-a1ac7699e646
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842371136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2842371136
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3707977150
Short name T669
Test name
Test status
Simulation time 103301274 ps
CPU time 3.82 seconds
Started Feb 07 02:15:20 PM PST 24
Finished Feb 07 02:15:25 PM PST 24
Peak memory 207656 kb
Host smart-937047d0-4dc4-4a27-ad37-13fde60c3c07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707977150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3707977150
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3869327024
Short name T1069
Test name
Test status
Simulation time 850336263 ps
CPU time 21.65 seconds
Started Feb 07 02:15:24 PM PST 24
Finished Feb 07 02:15:47 PM PST 24
Peak memory 208372 kb
Host smart-692d2765-e1e0-4049-88f1-5ab3475f59dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869327024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3869327024
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2051776840
Short name T700
Test name
Test status
Simulation time 136914515 ps
CPU time 3.47 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 209432 kb
Host smart-02227834-eefd-4827-a85f-c0cd40f3f297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051776840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2051776840
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2916001388
Short name T173
Test name
Test status
Simulation time 106482198 ps
CPU time 2.83 seconds
Started Feb 07 02:15:22 PM PST 24
Finished Feb 07 02:15:26 PM PST 24
Peak memory 208228 kb
Host smart-10d0668e-7d01-4936-a1b5-08fbeac5f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916001388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2916001388
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3591407906
Short name T44
Test name
Test status
Simulation time 240262371 ps
CPU time 5.15 seconds
Started Feb 07 02:15:27 PM PST 24
Finished Feb 07 02:15:33 PM PST 24
Peak memory 223188 kb
Host smart-ef9f1491-e8d3-40f5-9ef4-ca3e4a17a765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591407906 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3591407906
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2380753450
Short name T886
Test name
Test status
Simulation time 1259114917 ps
CPU time 9.97 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:39 PM PST 24
Peak memory 209064 kb
Host smart-88e1e07a-cbb4-49f1-887b-0ccf3aa5980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380753450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2380753450
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1211276060
Short name T692
Test name
Test status
Simulation time 199179698 ps
CPU time 1.36 seconds
Started Feb 07 02:15:32 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 209940 kb
Host smart-27864c85-da88-4cdd-8d1b-a0c796b12910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211276060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1211276060
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.959324009
Short name T604
Test name
Test status
Simulation time 41868299 ps
CPU time 0.84 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 206400 kb
Host smart-a90ed54a-dd96-4182-af38-a0507a39c7df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959324009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.959324009
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.892453146
Short name T366
Test name
Test status
Simulation time 49756584 ps
CPU time 3.56 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 223064 kb
Host smart-b0ea41f8-94c0-4d3b-9cac-96942b016043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892453146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.892453146
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2667241299
Short name T258
Test name
Test status
Simulation time 77239404 ps
CPU time 2.74 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 208516 kb
Host smart-c4dde14c-9f81-4f2c-a79b-5243847f75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667241299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2667241299
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2041432969
Short name T929
Test name
Test status
Simulation time 636437306 ps
CPU time 17.9 seconds
Started Feb 07 02:15:32 PM PST 24
Finished Feb 07 02:15:50 PM PST 24
Peak memory 214772 kb
Host smart-2db4a7db-8c68-454f-9b9b-a32725a9ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041432969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2041432969
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2177112974
Short name T968
Test name
Test status
Simulation time 353745686 ps
CPU time 4.84 seconds
Started Feb 07 02:15:32 PM PST 24
Finished Feb 07 02:15:37 PM PST 24
Peak memory 220516 kb
Host smart-2a0aecfe-50d8-4c7c-ab57-3ec81b0256c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177112974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2177112974
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3338105649
Short name T1011
Test name
Test status
Simulation time 168863715 ps
CPU time 4.14 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:35 PM PST 24
Peak memory 209388 kb
Host smart-143a7e52-2ec4-4a1c-ba45-05a4d2ec4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338105649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3338105649
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3262212372
Short name T277
Test name
Test status
Simulation time 1564016079 ps
CPU time 11.82 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:42 PM PST 24
Peak memory 209244 kb
Host smart-4ba96d55-33ef-4f56-9550-39b799055349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262212372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3262212372
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.878618851
Short name T737
Test name
Test status
Simulation time 483866130 ps
CPU time 5.51 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 209000 kb
Host smart-c1283791-e0ca-4c64-b08f-daadc3e88e70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878618851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.878618851
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1695324900
Short name T387
Test name
Test status
Simulation time 60500957 ps
CPU time 2.08 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:40 PM PST 24
Peak memory 209004 kb
Host smart-9ddcf694-533e-407e-908a-23f3c53e98ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695324900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1695324900
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1410737524
Short name T182
Test name
Test status
Simulation time 187043490 ps
CPU time 2.36 seconds
Started Feb 07 02:15:28 PM PST 24
Finished Feb 07 02:15:31 PM PST 24
Peak memory 215936 kb
Host smart-43b48897-c469-4539-928d-7f6502fde929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410737524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1410737524
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.735273312
Short name T643
Test name
Test status
Simulation time 191467351 ps
CPU time 2.05 seconds
Started Feb 07 02:15:31 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 206952 kb
Host smart-af3f6dc0-68ca-43c5-83fc-d834b1219686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735273312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.735273312
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2634588089
Short name T753
Test name
Test status
Simulation time 223531212 ps
CPU time 8.26 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:39 PM PST 24
Peak memory 223020 kb
Host smart-05c70893-31c1-491b-ac34-fb8936b728fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634588089 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2634588089
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.188654426
Short name T727
Test name
Test status
Simulation time 125416173 ps
CPU time 4.75 seconds
Started Feb 07 02:15:30 PM PST 24
Finished Feb 07 02:15:35 PM PST 24
Peak memory 209640 kb
Host smart-9831f3d3-2f68-4129-bf3a-adc65f16b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188654426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.188654426
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3689845868
Short name T629
Test name
Test status
Simulation time 86214613 ps
CPU time 1.95 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 210960 kb
Host smart-d17719b4-d37e-4ad6-a84f-e364af7bd800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689845868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3689845868
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3996356783
Short name T624
Test name
Test status
Simulation time 28081660 ps
CPU time 0.81 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:39 PM PST 24
Peak memory 206364 kb
Host smart-37516e37-dc53-4d9f-a273-60c720b3ecda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996356783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3996356783
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.964880815
Short name T897
Test name
Test status
Simulation time 72772801 ps
CPU time 3.27 seconds
Started Feb 07 02:15:39 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 209376 kb
Host smart-2d4ee898-c7d4-4ff3-bb5a-d0fc096316a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964880815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.964880815
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.498278862
Short name T1081
Test name
Test status
Simulation time 110060327 ps
CPU time 2.01 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:41 PM PST 24
Peak memory 214936 kb
Host smart-32c46f78-53ce-4c73-b695-0bba531f4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498278862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.498278862
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3857593598
Short name T395
Test name
Test status
Simulation time 174602455 ps
CPU time 5.89 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:42 PM PST 24
Peak memory 221472 kb
Host smart-5bd21f12-7f64-473c-be07-a66bd40a1dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857593598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3857593598
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.661269173
Short name T347
Test name
Test status
Simulation time 249992907 ps
CPU time 2.61 seconds
Started Feb 07 02:15:41 PM PST 24
Finished Feb 07 02:15:44 PM PST 24
Peak memory 223032 kb
Host smart-c48d86fc-e914-4561-b4cd-6e9f424a215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661269173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.661269173
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2811948696
Short name T202
Test name
Test status
Simulation time 44672488 ps
CPU time 2.24 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:40 PM PST 24
Peak memory 216100 kb
Host smart-d491e6bc-3dc3-4e7c-b520-4b38c81d0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811948696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2811948696
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1946905615
Short name T1087
Test name
Test status
Simulation time 382779521 ps
CPU time 5.81 seconds
Started Feb 07 02:15:52 PM PST 24
Finished Feb 07 02:15:59 PM PST 24
Peak memory 218720 kb
Host smart-2745298b-1848-4685-89cd-adde04245c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946905615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1946905615
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1034603347
Short name T953
Test name
Test status
Simulation time 233651942 ps
CPU time 2.88 seconds
Started Feb 07 02:15:29 PM PST 24
Finished Feb 07 02:15:32 PM PST 24
Peak memory 207100 kb
Host smart-bf487303-9fed-4af1-8e3b-2c6cfe05e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034603347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1034603347
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1540376189
Short name T360
Test name
Test status
Simulation time 1957025769 ps
CPU time 22.13 seconds
Started Feb 07 02:15:43 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 208716 kb
Host smart-3ab6f503-583f-490c-a2f3-c81f7e6efd56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540376189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1540376189
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1405907810
Short name T908
Test name
Test status
Simulation time 2890651032 ps
CPU time 6.03 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:44 PM PST 24
Peak memory 207312 kb
Host smart-dba7c33f-37f5-4923-b176-894e4ecd80c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405907810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1405907810
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1764341618
Short name T1017
Test name
Test status
Simulation time 578269569 ps
CPU time 4.97 seconds
Started Feb 07 02:15:39 PM PST 24
Finished Feb 07 02:15:45 PM PST 24
Peak memory 207160 kb
Host smart-22055476-6499-4ae3-9b05-23f69f8b8cb3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764341618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1764341618
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3782590163
Short name T946
Test name
Test status
Simulation time 399400945 ps
CPU time 2.87 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:40 PM PST 24
Peak memory 207700 kb
Host smart-04c8b2c0-7a93-443c-8737-c9d4115ce7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782590163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3782590163
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.449884036
Short name T437
Test name
Test status
Simulation time 24875148 ps
CPU time 2.16 seconds
Started Feb 07 02:15:31 PM PST 24
Finished Feb 07 02:15:34 PM PST 24
Peak memory 208848 kb
Host smart-bdcd1eca-6b94-4a7a-88f7-41eba0382c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449884036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.449884036
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3761412364
Short name T403
Test name
Test status
Simulation time 140851171 ps
CPU time 2.29 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:39 PM PST 24
Peak memory 207448 kb
Host smart-818f8266-f978-42a6-88f3-6d9878ab4301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761412364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3761412364
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2046970205
Short name T321
Test name
Test status
Simulation time 615542481 ps
CPU time 11.77 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:49 PM PST 24
Peak memory 223064 kb
Host smart-5241f9b8-e636-4be5-8c6f-244d060cec9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046970205 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2046970205
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3431001005
Short name T1092
Test name
Test status
Simulation time 273597359 ps
CPU time 10.9 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:48 PM PST 24
Peak memory 210144 kb
Host smart-5dc74aed-df91-4302-8a72-4b514a566924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431001005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3431001005
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.312032590
Short name T49
Test name
Test status
Simulation time 380596247 ps
CPU time 3.11 seconds
Started Feb 07 02:15:42 PM PST 24
Finished Feb 07 02:15:46 PM PST 24
Peak memory 210412 kb
Host smart-08ce0e98-ff24-4fe6-9134-c5b9497b3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312032590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.312032590
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4028092874
Short name T88
Test name
Test status
Simulation time 29956257 ps
CPU time 0.71 seconds
Started Feb 07 02:15:40 PM PST 24
Finished Feb 07 02:15:41 PM PST 24
Peak memory 206476 kb
Host smart-425d0bdd-eefa-4b85-8953-5000eec93121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028092874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4028092874
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2329914132
Short name T305
Test name
Test status
Simulation time 183905750 ps
CPU time 4.65 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 223324 kb
Host smart-2b575c82-2d60-4d1a-9ec4-48effb5a616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329914132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2329914132
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2358683926
Short name T317
Test name
Test status
Simulation time 375676713 ps
CPU time 3.29 seconds
Started Feb 07 02:15:44 PM PST 24
Finished Feb 07 02:15:48 PM PST 24
Peak memory 218640 kb
Host smart-3ac2d9f0-63ed-436d-861d-756a6f66832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358683926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2358683926
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1737784245
Short name T322
Test name
Test status
Simulation time 1317525595 ps
CPU time 24.93 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:16:03 PM PST 24
Peak memory 222884 kb
Host smart-7547a031-5672-4d36-85b5-f8dd6162e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737784245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1737784245
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1169024577
Short name T715
Test name
Test status
Simulation time 128655710 ps
CPU time 4.61 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 212112 kb
Host smart-460e551a-3dee-4717-8912-af782eaebc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169024577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1169024577
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.238285521
Short name T998
Test name
Test status
Simulation time 402754129 ps
CPU time 3.49 seconds
Started Feb 07 02:15:44 PM PST 24
Finished Feb 07 02:15:48 PM PST 24
Peak memory 210832 kb
Host smart-a5339134-dea5-4fd1-9645-32ca8a4fe3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238285521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.238285521
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.149785967
Short name T988
Test name
Test status
Simulation time 251005266 ps
CPU time 4.67 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 210508 kb
Host smart-7f544ce5-92b3-4cfa-a5de-3c3d170cae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149785967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.149785967
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.168194457
Short name T867
Test name
Test status
Simulation time 186863963 ps
CPU time 4.47 seconds
Started Feb 07 02:15:41 PM PST 24
Finished Feb 07 02:15:46 PM PST 24
Peak memory 209168 kb
Host smart-3d0ac5d6-d20c-4d04-953b-10acb07e2945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168194457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.168194457
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.471496379
Short name T982
Test name
Test status
Simulation time 1115752854 ps
CPU time 7.77 seconds
Started Feb 07 02:15:39 PM PST 24
Finished Feb 07 02:15:47 PM PST 24
Peak memory 209212 kb
Host smart-915dd603-f059-4113-a24d-fb2b7040e9c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471496379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.471496379
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2583242569
Short name T721
Test name
Test status
Simulation time 1002750099 ps
CPU time 9.23 seconds
Started Feb 07 02:15:41 PM PST 24
Finished Feb 07 02:15:51 PM PST 24
Peak memory 208236 kb
Host smart-1370d7b5-29ec-4d56-bfc8-b8cb73fb4ad2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583242569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2583242569
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3367820548
Short name T926
Test name
Test status
Simulation time 65941402 ps
CPU time 3.44 seconds
Started Feb 07 02:15:40 PM PST 24
Finished Feb 07 02:15:44 PM PST 24
Peak memory 209276 kb
Host smart-d4e516eb-48e8-4566-b41e-4e720dc7e5d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367820548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3367820548
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4182016040
Short name T787
Test name
Test status
Simulation time 130374042 ps
CPU time 2.3 seconds
Started Feb 07 02:15:36 PM PST 24
Finished Feb 07 02:15:39 PM PST 24
Peak memory 209612 kb
Host smart-5390885b-1641-45cc-b445-b86f68a9eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182016040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4182016040
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.184419014
Short name T1077
Test name
Test status
Simulation time 214642838 ps
CPU time 6.76 seconds
Started Feb 07 02:15:41 PM PST 24
Finished Feb 07 02:15:49 PM PST 24
Peak memory 208920 kb
Host smart-094801fa-8cc3-49e3-94da-cd4efa4bcd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184419014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.184419014
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.35946220
Short name T1067
Test name
Test status
Simulation time 143975182 ps
CPU time 2.97 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:41 PM PST 24
Peak memory 218584 kb
Host smart-a964673a-2f00-4452-ba17-ac3103d501d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946220 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.35946220
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3942707956
Short name T708
Test name
Test status
Simulation time 209815395 ps
CPU time 3.57 seconds
Started Feb 07 02:15:40 PM PST 24
Finished Feb 07 02:15:44 PM PST 24
Peak memory 210656 kb
Host smart-8d832bcf-4a9a-4bf8-ae90-970ad1d491d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942707956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3942707956
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1474284084
Short name T699
Test name
Test status
Simulation time 53933816 ps
CPU time 2.74 seconds
Started Feb 07 02:15:46 PM PST 24
Finished Feb 07 02:15:49 PM PST 24
Peak memory 210368 kb
Host smart-d4623924-8bce-4b01-bd2f-cf9848804053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474284084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1474284084
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2542964992
Short name T1082
Test name
Test status
Simulation time 15883456 ps
CPU time 0.93 seconds
Started Feb 07 02:16:09 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 206636 kb
Host smart-b33f0b8b-475b-425c-b0b5-6361279fa6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542964992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2542964992
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.409876164
Short name T420
Test name
Test status
Simulation time 966516061 ps
CPU time 13.02 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:15 PM PST 24
Peak memory 214912 kb
Host smart-51c255de-3529-474b-bdcb-668ac8411843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409876164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.409876164
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.173097995
Short name T21
Test name
Test status
Simulation time 49089945 ps
CPU time 1.97 seconds
Started Feb 07 02:15:57 PM PST 24
Finished Feb 07 02:16:00 PM PST 24
Peak memory 223220 kb
Host smart-3305fdc3-6035-48ef-a2d8-3ec4b5919f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173097995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.173097995
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3418859507
Short name T846
Test name
Test status
Simulation time 143409434 ps
CPU time 2.21 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 210312 kb
Host smart-51c4f3e1-dbf8-485b-a281-0227ce31d3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418859507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3418859507
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2460013161
Short name T239
Test name
Test status
Simulation time 116748348 ps
CPU time 4.94 seconds
Started Feb 07 02:15:57 PM PST 24
Finished Feb 07 02:16:03 PM PST 24
Peak memory 214864 kb
Host smart-b1982134-0344-43b4-bf16-c339d306565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460013161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2460013161
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2960695240
Short name T1005
Test name
Test status
Simulation time 301670169 ps
CPU time 9.02 seconds
Started Feb 07 02:16:01 PM PST 24
Finished Feb 07 02:16:11 PM PST 24
Peak memory 222952 kb
Host smart-8f579f50-d7a7-4530-9dfc-2c9225ee0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960695240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2960695240
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1813543401
Short name T1076
Test name
Test status
Simulation time 58351211 ps
CPU time 3.26 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 214892 kb
Host smart-a4e4a097-89e7-413a-9449-e10ab0d33375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813543401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1813543401
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1352737213
Short name T93
Test name
Test status
Simulation time 361191263 ps
CPU time 9.74 seconds
Started Feb 07 02:15:55 PM PST 24
Finished Feb 07 02:16:05 PM PST 24
Peak memory 214880 kb
Host smart-b430d792-c432-41f9-b4d6-bb50e7045906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352737213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1352737213
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3987117023
Short name T316
Test name
Test status
Simulation time 98809765 ps
CPU time 2.71 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:42 PM PST 24
Peak memory 207096 kb
Host smart-8c32d12a-27da-45bd-b324-57d6a0fcb9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987117023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3987117023
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2735970938
Short name T686
Test name
Test status
Simulation time 2204901991 ps
CPU time 15.7 seconds
Started Feb 07 02:15:55 PM PST 24
Finished Feb 07 02:16:13 PM PST 24
Peak memory 209116 kb
Host smart-0bd70bb5-1f76-4bab-be28-350c97bc586b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735970938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2735970938
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1658767961
Short name T730
Test name
Test status
Simulation time 47267223 ps
CPU time 2.61 seconds
Started Feb 07 02:15:38 PM PST 24
Finished Feb 07 02:15:42 PM PST 24
Peak memory 207164 kb
Host smart-b656192b-2157-48f4-b236-72ee2dc1b619
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658767961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1658767961
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3616685818
Short name T957
Test name
Test status
Simulation time 221100170 ps
CPU time 6.69 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 208312 kb
Host smart-8ee19f8a-96b5-44bc-abed-3645c2a78fea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616685818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3616685818
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3281584333
Short name T834
Test name
Test status
Simulation time 933541538 ps
CPU time 4.07 seconds
Started Feb 07 02:16:03 PM PST 24
Finished Feb 07 02:16:09 PM PST 24
Peak memory 209588 kb
Host smart-735f643a-2f9b-4f3c-a94a-5acaf89685a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281584333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3281584333
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2247095643
Short name T799
Test name
Test status
Simulation time 132282499 ps
CPU time 3.92 seconds
Started Feb 07 02:15:37 PM PST 24
Finished Feb 07 02:15:42 PM PST 24
Peak memory 208772 kb
Host smart-a3614b79-2352-48ed-89a7-0411f693120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247095643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2247095643
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1240170988
Short name T1055
Test name
Test status
Simulation time 1908006946 ps
CPU time 18.43 seconds
Started Feb 07 02:16:06 PM PST 24
Finished Feb 07 02:16:27 PM PST 24
Peak memory 216764 kb
Host smart-1a1fc347-6f02-4a43-a5c8-864eb9b64dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240170988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1240170988
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3980047271
Short name T16
Test name
Test status
Simulation time 113056503 ps
CPU time 5.25 seconds
Started Feb 07 02:15:56 PM PST 24
Finished Feb 07 02:16:02 PM PST 24
Peak memory 209672 kb
Host smart-f7deea60-a5aa-444a-9378-494da7aa4c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980047271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3980047271
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.858130232
Short name T866
Test name
Test status
Simulation time 18512537 ps
CPU time 0.72 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:11:34 PM PST 24
Peak memory 206320 kb
Host smart-57af3415-ceca-47fc-b447-a4b199947a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858130232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.858130232
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2590301748
Short name T66
Test name
Test status
Simulation time 120030104 ps
CPU time 3.53 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:32 PM PST 24
Peak memory 214816 kb
Host smart-80f42448-3c21-4cf2-a659-8c3e01708338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590301748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2590301748
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2171934145
Short name T1050
Test name
Test status
Simulation time 197724636 ps
CPU time 6.91 seconds
Started Feb 07 02:11:22 PM PST 24
Finished Feb 07 02:11:30 PM PST 24
Peak memory 214824 kb
Host smart-aad7bbe6-96a3-403a-8386-e886eecd61cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171934145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2171934145
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.194242188
Short name T919
Test name
Test status
Simulation time 769258003 ps
CPU time 6.82 seconds
Started Feb 07 02:11:34 PM PST 24
Finished Feb 07 02:11:41 PM PST 24
Peak memory 215160 kb
Host smart-ea184b52-3297-40cc-9a72-016039da7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194242188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.194242188
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.709792816
Short name T744
Test name
Test status
Simulation time 63658519 ps
CPU time 3.82 seconds
Started Feb 07 02:11:20 PM PST 24
Finished Feb 07 02:11:24 PM PST 24
Peak memory 219036 kb
Host smart-265679ac-7179-4220-b338-aa28622a0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709792816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.709792816
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3660819538
Short name T1014
Test name
Test status
Simulation time 48085372 ps
CPU time 2.33 seconds
Started Feb 07 02:11:22 PM PST 24
Finished Feb 07 02:11:25 PM PST 24
Peak memory 206888 kb
Host smart-6e93e6f1-9ac3-424d-87ec-c605c677a987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660819538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3660819538
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2339343878
Short name T1083
Test name
Test status
Simulation time 188956908 ps
CPU time 3.02 seconds
Started Feb 07 02:11:20 PM PST 24
Finished Feb 07 02:11:24 PM PST 24
Peak memory 209012 kb
Host smart-a9a462bf-7f8a-46b8-9e30-2b2ea2ab3b0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339343878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2339343878
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4076782252
Short name T633
Test name
Test status
Simulation time 8588290691 ps
CPU time 59.02 seconds
Started Feb 07 02:11:23 PM PST 24
Finished Feb 07 02:12:23 PM PST 24
Peak memory 208332 kb
Host smart-454cde59-dd03-4b8b-909f-5bf7b6911e85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076782252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4076782252
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.898768942
Short name T713
Test name
Test status
Simulation time 608983297 ps
CPU time 3.86 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:33 PM PST 24
Peak memory 209084 kb
Host smart-8fec8b52-1e84-4c4e-b321-b4def0ef7a9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898768942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.898768942
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3061243973
Short name T882
Test name
Test status
Simulation time 162922953 ps
CPU time 3.19 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 218608 kb
Host smart-360ef614-2b85-474c-acb0-3f6b14f8d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061243973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3061243973
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.381588201
Short name T434
Test name
Test status
Simulation time 557842089 ps
CPU time 4.09 seconds
Started Feb 07 02:11:21 PM PST 24
Finished Feb 07 02:11:26 PM PST 24
Peak memory 206972 kb
Host smart-f7cdb410-d459-4d3d-b6a5-d1f38cf2e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381588201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.381588201
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2720387292
Short name T204
Test name
Test status
Simulation time 1689861160 ps
CPU time 31.26 seconds
Started Feb 07 02:11:19 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 217736 kb
Host smart-c5755498-b367-45ad-bd30-68b3a5e396f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720387292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2720387292
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.909282441
Short name T662
Test name
Test status
Simulation time 287720337 ps
CPU time 6.13 seconds
Started Feb 07 02:11:18 PM PST 24
Finished Feb 07 02:11:25 PM PST 24
Peak memory 222536 kb
Host smart-79602e8d-7b26-4866-9a96-140f389cc339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909282441 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.909282441
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.344620917
Short name T863
Test name
Test status
Simulation time 3419781879 ps
CPU time 9.77 seconds
Started Feb 07 02:11:27 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 208560 kb
Host smart-2faf91ae-4ca9-4400-b9ed-da107d8d3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344620917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.344620917
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2594603058
Short name T397
Test name
Test status
Simulation time 409642781 ps
CPU time 6.62 seconds
Started Feb 07 02:11:29 PM PST 24
Finished Feb 07 02:11:36 PM PST 24
Peak memory 210140 kb
Host smart-59343b27-ee0a-4e0f-bce4-ff46130e1ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594603058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2594603058
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1742318896
Short name T927
Test name
Test status
Simulation time 37723974 ps
CPU time 0.73 seconds
Started Feb 07 02:11:38 PM PST 24
Finished Feb 07 02:11:39 PM PST 24
Peak memory 206384 kb
Host smart-8ce7ddfc-e3f4-4774-9f90-22a85551e661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742318896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1742318896
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2253840183
Short name T433
Test name
Test status
Simulation time 264174521 ps
CPU time 14.66 seconds
Started Feb 07 02:11:22 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 215132 kb
Host smart-8d94c7e9-0cf0-4cb0-8b8f-ff568a92ef4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253840183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2253840183
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1151563952
Short name T428
Test name
Test status
Simulation time 35070920 ps
CPU time 1.76 seconds
Started Feb 07 02:11:18 PM PST 24
Finished Feb 07 02:11:20 PM PST 24
Peak memory 207864 kb
Host smart-54a0afbb-19d7-4cfb-a4ab-c76342738419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151563952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1151563952
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3271268382
Short name T287
Test name
Test status
Simulation time 113383412 ps
CPU time 3.05 seconds
Started Feb 07 02:11:31 PM PST 24
Finished Feb 07 02:11:34 PM PST 24
Peak memory 208800 kb
Host smart-cd61aaa3-26fa-46f6-ab24-04575e98e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271268382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3271268382
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1306834437
Short name T299
Test name
Test status
Simulation time 136040405 ps
CPU time 5.67 seconds
Started Feb 07 02:11:18 PM PST 24
Finished Feb 07 02:11:24 PM PST 24
Peak memory 223040 kb
Host smart-69977866-0ace-4092-9cb8-e39ad8f4c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306834437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1306834437
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3141000928
Short name T941
Test name
Test status
Simulation time 445079951 ps
CPU time 1.85 seconds
Started Feb 07 02:11:19 PM PST 24
Finished Feb 07 02:11:22 PM PST 24
Peak memory 215636 kb
Host smart-634e62d1-89e1-4a0d-9e91-91f8f06eec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141000928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3141000928
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.459238942
Short name T860
Test name
Test status
Simulation time 52452742 ps
CPU time 3.41 seconds
Started Feb 07 02:11:26 PM PST 24
Finished Feb 07 02:11:30 PM PST 24
Peak memory 210316 kb
Host smart-52abb2c3-f6ab-43f9-bba3-2246f946aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459238942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.459238942
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2134871961
Short name T935
Test name
Test status
Simulation time 41129982 ps
CPU time 1.8 seconds
Started Feb 07 02:11:15 PM PST 24
Finished Feb 07 02:11:18 PM PST 24
Peak memory 208816 kb
Host smart-c9ae8cb5-e1fd-4953-9e80-0ca4fdb28c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134871961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2134871961
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2058480513
Short name T337
Test name
Test status
Simulation time 106286508 ps
CPU time 3.88 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:32 PM PST 24
Peak memory 208976 kb
Host smart-a3031e16-5da9-4724-a285-93a5b5d1a2b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058480513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2058480513
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2210905241
Short name T651
Test name
Test status
Simulation time 138701773 ps
CPU time 3.66 seconds
Started Feb 07 02:11:27 PM PST 24
Finished Feb 07 02:11:31 PM PST 24
Peak memory 209024 kb
Host smart-cc5af52f-e99d-41dd-8c0e-f527161e505b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210905241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2210905241
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1234515653
Short name T1003
Test name
Test status
Simulation time 71259688 ps
CPU time 1.76 seconds
Started Feb 07 02:11:38 PM PST 24
Finished Feb 07 02:11:40 PM PST 24
Peak memory 207148 kb
Host smart-ad2af984-52c0-44eb-b75c-50bcd4c22539
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234515653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1234515653
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1612875200
Short name T358
Test name
Test status
Simulation time 116149628 ps
CPU time 3.23 seconds
Started Feb 07 02:11:21 PM PST 24
Finished Feb 07 02:11:25 PM PST 24
Peak memory 208888 kb
Host smart-931574b7-ba74-408d-8c89-84da5c1d29c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612875200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1612875200
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4266228618
Short name T729
Test name
Test status
Simulation time 132157515 ps
CPU time 2.92 seconds
Started Feb 07 02:11:29 PM PST 24
Finished Feb 07 02:11:33 PM PST 24
Peak memory 208628 kb
Host smart-80873b9b-41d0-4599-b530-d8da4f91853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266228618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4266228618
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1810687024
Short name T874
Test name
Test status
Simulation time 268690655 ps
CPU time 8.35 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 208428 kb
Host smart-109a4989-9117-4608-aa28-135c931068b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810687024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1810687024
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.367750931
Short name T813
Test name
Test status
Simulation time 157084994 ps
CPU time 1.55 seconds
Started Feb 07 02:11:23 PM PST 24
Finished Feb 07 02:11:25 PM PST 24
Peak memory 209792 kb
Host smart-b4af0d6f-88c4-4946-9979-d9d1b356610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367750931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.367750931
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.203625706
Short name T642
Test name
Test status
Simulation time 17712206 ps
CPU time 0.7 seconds
Started Feb 07 02:11:40 PM PST 24
Finished Feb 07 02:11:41 PM PST 24
Peak memory 206440 kb
Host smart-c6fecaf4-bff1-4153-bfdb-bf6857bbf2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203625706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.203625706
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3403689475
Short name T17
Test name
Test status
Simulation time 199027408 ps
CPU time 3.92 seconds
Started Feb 07 02:11:27 PM PST 24
Finished Feb 07 02:11:32 PM PST 24
Peak memory 215444 kb
Host smart-cdbdfb57-9dc9-4de9-9f58-29acbd14724d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403689475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3403689475
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3363861348
Short name T873
Test name
Test status
Simulation time 114947860 ps
CPU time 3.57 seconds
Started Feb 07 02:11:34 PM PST 24
Finished Feb 07 02:11:38 PM PST 24
Peak memory 218876 kb
Host smart-337e75a2-5c02-4494-a475-c0832e81afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363861348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3363861348
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.677617756
Short name T286
Test name
Test status
Simulation time 1014603610 ps
CPU time 5.97 seconds
Started Feb 07 02:11:36 PM PST 24
Finished Feb 07 02:11:43 PM PST 24
Peak memory 214900 kb
Host smart-5f36def5-8bf4-49df-9dcb-792465c03b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677617756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.677617756
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.811169083
Short name T1052
Test name
Test status
Simulation time 503573037 ps
CPU time 11.56 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:11:45 PM PST 24
Peak memory 223000 kb
Host smart-835a5c22-1631-4428-b382-6ce6686af43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811169083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.811169083
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2596486975
Short name T938
Test name
Test status
Simulation time 658416873 ps
CPU time 4.51 seconds
Started Feb 07 02:11:30 PM PST 24
Finished Feb 07 02:11:35 PM PST 24
Peak memory 210328 kb
Host smart-13dac054-9d2c-4a39-9add-03ec1ee54f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596486975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2596486975
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.43594325
Short name T220
Test name
Test status
Simulation time 119669818 ps
CPU time 4.39 seconds
Started Feb 07 02:11:32 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 214732 kb
Host smart-661b80ce-651d-4e0b-a10d-b7d07ba6b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43594325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.43594325
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1089561976
Short name T960
Test name
Test status
Simulation time 78053287 ps
CPU time 3.04 seconds
Started Feb 07 02:11:33 PM PST 24
Finished Feb 07 02:11:37 PM PST 24
Peak memory 206976 kb
Host smart-b7ac875f-3dea-48d9-a410-7060c9669b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089561976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1089561976
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3552234455
Short name T921
Test name
Test status
Simulation time 46747392 ps
CPU time 2.7 seconds
Started Feb 07 02:11:32 PM PST 24
Finished Feb 07 02:11:35 PM PST 24
Peak memory 207044 kb
Host smart-859d5d63-68f5-4ed4-91c6-e8a47e513b6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552234455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3552234455
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2679937107
Short name T656
Test name
Test status
Simulation time 52199261 ps
CPU time 2.98 seconds
Started Feb 07 02:11:27 PM PST 24
Finished Feb 07 02:11:31 PM PST 24
Peak memory 207280 kb
Host smart-22aba250-f657-4d63-a2c9-b912f75a461c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679937107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2679937107
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3220808624
Short name T255
Test name
Test status
Simulation time 111066351 ps
CPU time 2.39 seconds
Started Feb 07 02:11:32 PM PST 24
Finished Feb 07 02:11:35 PM PST 24
Peak memory 207180 kb
Host smart-32abaf83-f73c-4f5d-b0b3-de7abcc71285
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220808624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3220808624
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2919991843
Short name T386
Test name
Test status
Simulation time 205481967 ps
CPU time 2.68 seconds
Started Feb 07 02:11:36 PM PST 24
Finished Feb 07 02:11:40 PM PST 24
Peak memory 215968 kb
Host smart-9627f966-7891-49bc-90c4-2f90820d3d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919991843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2919991843
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2567124486
Short name T116
Test name
Test status
Simulation time 74483821 ps
CPU time 1.77 seconds
Started Feb 07 02:11:31 PM PST 24
Finished Feb 07 02:11:33 PM PST 24
Peak memory 206568 kb
Host smart-7aa9f086-1f98-46bf-9e8a-708f5a5bcb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567124486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2567124486
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.750124951
Short name T40
Test name
Test status
Simulation time 355899061 ps
CPU time 12.64 seconds
Started Feb 07 02:11:36 PM PST 24
Finished Feb 07 02:11:49 PM PST 24
Peak memory 217124 kb
Host smart-f3023b27-9fc1-451e-a3d5-4ece5ca8a31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750124951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.750124951
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3856401879
Short name T205
Test name
Test status
Simulation time 457894494 ps
CPU time 13.42 seconds
Started Feb 07 02:11:28 PM PST 24
Finished Feb 07 02:11:42 PM PST 24
Peak memory 220868 kb
Host smart-ec4ab9af-da33-42e5-ad09-77019906eb7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856401879 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3856401879
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2535756090
Short name T914
Test name
Test status
Simulation time 7604136699 ps
CPU time 15.43 seconds
Started Feb 07 02:11:31 PM PST 24
Finished Feb 07 02:11:47 PM PST 24
Peak memory 209132 kb
Host smart-96afcaec-83f0-4dcc-8b48-8d01ea9ba280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535756090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2535756090
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3213305506
Short name T163
Test name
Test status
Simulation time 76960466 ps
CPU time 2.89 seconds
Started Feb 07 02:11:39 PM PST 24
Finished Feb 07 02:11:43 PM PST 24
Peak memory 210368 kb
Host smart-11d1e45f-cac2-4981-9260-5d86b1d8b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213305506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3213305506
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2067836919
Short name T590
Test name
Test status
Simulation time 15949604 ps
CPU time 0.73 seconds
Started Feb 07 02:11:46 PM PST 24
Finished Feb 07 02:11:47 PM PST 24
Peak memory 206400 kb
Host smart-2c8a4d41-d861-4304-9cef-6aa3c66fe24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067836919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2067836919
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3342287622
Short name T426
Test name
Test status
Simulation time 203559423 ps
CPU time 3.12 seconds
Started Feb 07 02:11:41 PM PST 24
Finished Feb 07 02:11:44 PM PST 24
Peak memory 215532 kb
Host smart-4d1e3eea-8dd3-439b-9178-7d6dcdbbee96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342287622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3342287622
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.255238704
Short name T1066
Test name
Test status
Simulation time 534434799 ps
CPU time 1.9 seconds
Started Feb 07 02:11:45 PM PST 24
Finished Feb 07 02:11:48 PM PST 24
Peak memory 209004 kb
Host smart-8220d955-697a-4290-b10e-9d7194918126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255238704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.255238704
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3804731494
Short name T883
Test name
Test status
Simulation time 294921004 ps
CPU time 6.33 seconds
Started Feb 07 02:11:42 PM PST 24
Finished Feb 07 02:11:49 PM PST 24
Peak memory 208404 kb
Host smart-75027382-088a-491d-9a62-ebf4685eab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804731494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3804731494
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2126864116
Short name T22
Test name
Test status
Simulation time 119805429 ps
CPU time 2.95 seconds
Started Feb 07 02:11:44 PM PST 24
Finished Feb 07 02:11:47 PM PST 24
Peak memory 210788 kb
Host smart-36204865-38e6-4595-a5b6-735ed339a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126864116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2126864116
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1489106245
Short name T259
Test name
Test status
Simulation time 193913557 ps
CPU time 5.24 seconds
Started Feb 07 02:11:49 PM PST 24
Finished Feb 07 02:11:56 PM PST 24
Peak memory 214652 kb
Host smart-c7185855-923b-446a-bda5-41bb614aa3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489106245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1489106245
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.882961806
Short name T135
Test name
Test status
Simulation time 190670081 ps
CPU time 2.75 seconds
Started Feb 07 02:11:43 PM PST 24
Finished Feb 07 02:11:47 PM PST 24
Peak memory 208136 kb
Host smart-d731bf15-0b19-4739-855f-cc581036f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882961806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.882961806
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3740307290
Short name T783
Test name
Test status
Simulation time 107189501 ps
CPU time 4.98 seconds
Started Feb 07 02:11:42 PM PST 24
Finished Feb 07 02:11:48 PM PST 24
Peak memory 209432 kb
Host smart-46d6c884-1bda-432d-b8a1-a0c0cb96b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740307290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3740307290
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3193063074
Short name T283
Test name
Test status
Simulation time 137309858 ps
CPU time 2.8 seconds
Started Feb 07 02:11:43 PM PST 24
Finished Feb 07 02:11:46 PM PST 24
Peak memory 208900 kb
Host smart-da81dfd6-1aa0-4c53-9eac-b6912c6b77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193063074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3193063074
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3938139069
Short name T933
Test name
Test status
Simulation time 320171472 ps
CPU time 4.72 seconds
Started Feb 07 02:11:40 PM PST 24
Finished Feb 07 02:11:46 PM PST 24
Peak memory 209280 kb
Host smart-addfb3cc-d63c-4f4b-8581-792ba648e290
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938139069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3938139069
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2471624836
Short name T900
Test name
Test status
Simulation time 139445446 ps
CPU time 2.91 seconds
Started Feb 07 02:11:38 PM PST 24
Finished Feb 07 02:11:41 PM PST 24
Peak memory 209140 kb
Host smart-6157dbc8-a08b-4862-ae3c-f35c79244e12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471624836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2471624836
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3087132343
Short name T190
Test name
Test status
Simulation time 163042664 ps
CPU time 4.01 seconds
Started Feb 07 02:11:42 PM PST 24
Finished Feb 07 02:11:47 PM PST 24
Peak memory 207244 kb
Host smart-47077c8e-b64a-4962-b611-6b0982148bc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087132343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3087132343
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1951216229
Short name T810
Test name
Test status
Simulation time 536577141 ps
CPU time 5.95 seconds
Started Feb 07 02:11:45 PM PST 24
Finished Feb 07 02:11:52 PM PST 24
Peak memory 215792 kb
Host smart-7c79aabe-91b4-40e8-9164-ced751398f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951216229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1951216229
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2065090581
Short name T948
Test name
Test status
Simulation time 1291146260 ps
CPU time 32.42 seconds
Started Feb 07 02:11:40 PM PST 24
Finished Feb 07 02:12:13 PM PST 24
Peak memory 208492 kb
Host smart-6bbe8778-d64d-40b0-8785-f39685c87f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065090581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2065090581
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1932928990
Short name T285
Test name
Test status
Simulation time 903917140 ps
CPU time 19.56 seconds
Started Feb 07 02:11:54 PM PST 24
Finished Feb 07 02:12:16 PM PST 24
Peak memory 221076 kb
Host smart-4e70a9f1-db99-45a0-be54-3e3f7e527ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932928990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1932928990
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3953688419
Short name T788
Test name
Test status
Simulation time 869515712 ps
CPU time 5.17 seconds
Started Feb 07 02:11:46 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 219568 kb
Host smart-d9b8a705-1c35-4cc8-9f46-c1f82632dd64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953688419 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3953688419
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.535046805
Short name T775
Test name
Test status
Simulation time 681710749 ps
CPU time 4.33 seconds
Started Feb 07 02:11:44 PM PST 24
Finished Feb 07 02:11:49 PM PST 24
Peak memory 207560 kb
Host smart-738d0924-f44e-424f-ae5d-698f15256e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535046805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.535046805
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3016044073
Short name T711
Test name
Test status
Simulation time 116133180 ps
CPU time 1.79 seconds
Started Feb 07 02:11:51 PM PST 24
Finished Feb 07 02:11:58 PM PST 24
Peak memory 210040 kb
Host smart-db66a74e-4710-488a-8cdf-1b19ba5097d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016044073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3016044073
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3240303986
Short name T661
Test name
Test status
Simulation time 98101944 ps
CPU time 0.86 seconds
Started Feb 07 02:11:48 PM PST 24
Finished Feb 07 02:11:50 PM PST 24
Peak memory 206404 kb
Host smart-683cb069-382c-4825-ac0c-10f93958de0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240303986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3240303986
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1852227860
Short name T394
Test name
Test status
Simulation time 1066545399 ps
CPU time 8.08 seconds
Started Feb 07 02:11:51 PM PST 24
Finished Feb 07 02:12:04 PM PST 24
Peak memory 214760 kb
Host smart-04a299e1-4707-4fae-b263-0024adae2bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852227860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1852227860
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1866838655
Short name T20
Test name
Test status
Simulation time 99658645 ps
CPU time 3.97 seconds
Started Feb 07 02:11:55 PM PST 24
Finished Feb 07 02:12:01 PM PST 24
Peak memory 210580 kb
Host smart-1e564b86-4a67-4344-8b55-fa66b5b1d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866838655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1866838655
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1244503062
Short name T949
Test name
Test status
Simulation time 23440285 ps
CPU time 1.87 seconds
Started Feb 07 02:11:48 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 214808 kb
Host smart-9c8ac126-19cd-4d5c-843d-1302d60de8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244503062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1244503062
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.638697614
Short name T75
Test name
Test status
Simulation time 139274870 ps
CPU time 5.25 seconds
Started Feb 07 02:11:45 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 214832 kb
Host smart-682f36cf-9ffa-4ab2-8979-57b9da7d9d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638697614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.638697614
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.82932315
Short name T726
Test name
Test status
Simulation time 137866922 ps
CPU time 4.68 seconds
Started Feb 07 02:11:54 PM PST 24
Finished Feb 07 02:12:01 PM PST 24
Peak memory 211896 kb
Host smart-e2260579-7971-48d1-9253-d068511e30cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82932315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.82932315
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1254484327
Short name T200
Test name
Test status
Simulation time 65119152 ps
CPU time 3.7 seconds
Started Feb 07 02:11:47 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 214904 kb
Host smart-f6b03111-b090-47a5-8a70-99f215ae6a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254484327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1254484327
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.4288328490
Short name T369
Test name
Test status
Simulation time 429017403 ps
CPU time 4.55 seconds
Started Feb 07 02:11:47 PM PST 24
Finished Feb 07 02:11:52 PM PST 24
Peak memory 210084 kb
Host smart-d12e6179-99a4-456e-b819-5e69b6c782e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288328490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4288328490
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4220249853
Short name T361
Test name
Test status
Simulation time 83037956 ps
CPU time 3.61 seconds
Started Feb 07 02:11:48 PM PST 24
Finished Feb 07 02:11:52 PM PST 24
Peak memory 208852 kb
Host smart-b1815533-2f99-4452-8be1-f492de71257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220249853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4220249853
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1024253997
Short name T363
Test name
Test status
Simulation time 1076146974 ps
CPU time 8.54 seconds
Started Feb 07 02:11:46 PM PST 24
Finished Feb 07 02:11:56 PM PST 24
Peak memory 209068 kb
Host smart-a482a566-50a1-42ac-9fa4-5b9162889100
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024253997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1024253997
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1698252917
Short name T72
Test name
Test status
Simulation time 397494918 ps
CPU time 9.11 seconds
Started Feb 07 02:11:47 PM PST 24
Finished Feb 07 02:11:57 PM PST 24
Peak memory 209152 kb
Host smart-ccf24beb-7301-467a-a932-76e08db030fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698252917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1698252917
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3283569557
Short name T967
Test name
Test status
Simulation time 275199243 ps
CPU time 3.37 seconds
Started Feb 07 02:11:50 PM PST 24
Finished Feb 07 02:11:54 PM PST 24
Peak memory 208980 kb
Host smart-866a53f8-5074-43b7-894f-485c2465fa15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283569557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3283569557
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2159331477
Short name T922
Test name
Test status
Simulation time 230155758 ps
CPU time 2.24 seconds
Started Feb 07 02:11:56 PM PST 24
Finished Feb 07 02:12:00 PM PST 24
Peak memory 214744 kb
Host smart-c15e2d93-ebb9-4a02-8b81-9df61af981dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159331477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2159331477
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.4261464686
Short name T609
Test name
Test status
Simulation time 25491414 ps
CPU time 1.75 seconds
Started Feb 07 02:11:45 PM PST 24
Finished Feb 07 02:11:48 PM PST 24
Peak memory 207536 kb
Host smart-62e04dd3-e24f-42bd-8946-84e766d50729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261464686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.4261464686
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1338532420
Short name T843
Test name
Test status
Simulation time 877875055 ps
CPU time 7.41 seconds
Started Feb 07 02:11:49 PM PST 24
Finished Feb 07 02:11:58 PM PST 24
Peak memory 209024 kb
Host smart-32b2262e-c492-496b-ba97-19cfa272b759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338532420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1338532420
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2361592447
Short name T409
Test name
Test status
Simulation time 394117557 ps
CPU time 7.76 seconds
Started Feb 07 02:11:50 PM PST 24
Finished Feb 07 02:11:59 PM PST 24
Peak memory 223072 kb
Host smart-f2ed59ab-eadc-491b-b8cf-d31f01afca26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361592447 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2361592447
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2412661135
Short name T606
Test name
Test status
Simulation time 5731900383 ps
CPU time 20.43 seconds
Started Feb 07 02:11:47 PM PST 24
Finished Feb 07 02:12:08 PM PST 24
Peak memory 209228 kb
Host smart-0c5ca10c-76de-40d0-aa7f-62a9a2f7d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412661135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2412661135
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2764413448
Short name T412
Test name
Test status
Simulation time 3582252589 ps
CPU time 18.72 seconds
Started Feb 07 02:11:57 PM PST 24
Finished Feb 07 02:12:18 PM PST 24
Peak memory 211916 kb
Host smart-04f2f231-3d08-4f78-bc44-1d92a33724c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764413448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2764413448
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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