Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10801

1

T1

1

T3

22

T4

12

auto[Attestation]

7573

1

T3

23

T4

10

T14

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2657	1			T3	5		T4	4		T14	4
auto[Aes]	3324	1			T3	6		T4	3		T14	2
auto[Kmac]	3340	1			T3	12		T4	6		T14	6
auto[Otbn]	3317	1			T3	7		T4	3		T14	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7421	1			T1	3		T3	8		T4	8
auto[OpGenId]	5736	1			T1	1		T3	15		T4	6
auto[OpGenSwOut]	5734	1			T3	14		T4	9		T14	11
auto[OpGenHwOut]	6904	1			T3	16		T4	7		T14	7
auto[OpDisable]	124	1			T5	3		T6	3		T44	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9838

1

T1

3

T3

1

T4

1

auto[OpDoneFail]

16081

1

T1

1

T3

52

T4

29

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5640	1			T1	1		T3	18		T4	3
auto[StInit]	4120	1			T1	2		T3	5		T4	27
auto[StCreatorRootKey]	2956	1			T1	1		T14	5		T15	2
auto[StOwnerIntKey]	2534	1			T14	2		T15	2		T17	2
auto[StOwnerKey]	2334	1			T14	3		T15	2		T17	2
auto[StDisabled]	7240	1			T14	17		T15	7		T17	16
auto[StInvalid]	1095	1			T3	30		T35	16		T48	32

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	296	1			T19	1		T5	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T4	1		T19	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T41	1		T5	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	58	1			T34	1		T63	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T14	1		T133	1		T213	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T34	1		T5	5		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	39	1			T3	1		T48	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	287	1			T3	2		T4	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	107	1			T63	1		T35	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T19	1		T41	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T81	1		T5	2		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T39	1		T116	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	199	1			T63	1		T215	2		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T25	2		T216	1		T217	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	282	1			T3	1		T14	3		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T4	2		T5	4		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T14	1		T41	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T5	2		T133	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T5	2		T42	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	218	1			T34	1		T5	3		T116	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T3	2		T35	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	296	1			T4	1		T17	3		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	99	1			T3	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	61	1			T5	2		T42	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T5	1		T133	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T34	1		T82	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	210	1			T14	1		T17	2		T5	8
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T48	1		T25	2		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T3	1		T5	3		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	121	1			T4	1		T34	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T14	1		T81	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T5	1		T7	2		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T5	1		T133	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	201	1			T81	2		T5	6		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	45	1			T3	2		T35	2		T196	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	60	1			T5	2		T42	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T19	2		T5	4		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	74	1			T16	1		T5	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	67	1			T5	2		T42	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T5	1		T215	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	198	1			T14	1		T17	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T35	1		T48	1		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T3	1		T6	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T4	1		T138	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T17	1		T5	3		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	51	1			T6	3		T218	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T214	1		T129	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	170	1			T14	1		T5	5		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T3	2		T35	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T5	3		T6	3		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T4	2		T5	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T42	2		T6	3		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T5	1		T82	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T5	3		T83	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	190	1			T14	1		T17	2		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T3	1		T35	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	236	1			T3	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	90	1			T4	2		T14	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T42	1		T60	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	51	1			T5	1		T214	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T17	1		T214	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T14	1		T17	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	25	1			T48	1		T216	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	402	1			T3	1		T17	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	149	1			T3	1		T4	1		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T19	1		T5	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	105	1			T5	1		T214	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	100	1			T5	2		T219	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	250	1			T5	3		T82	3		T219	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	27	1			T3	2		T26	1		T86	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	430	1			T19	1		T5	3		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	130	1			T3	1		T4	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T17	1		T5	2		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T5	2		T137	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	90	1			T137	1		T6	2		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	277	1			T14	1		T17	1		T5	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T48	3		T25	4		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	437	1			T3	1		T15	15		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T14	1		T15	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T5	2		T7	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T15	1		T19	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	90	1			T14	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	258	1			T14	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T3	1		T48	2		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	49	1			T5	3		T6	1		T54	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T214	1		T221	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T5	2		T214	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	49	1			T17	1		T5	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T5	2		T42	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T17	1		T5	11		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	36	1			T35	1		T25	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T5	4		T6	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	137	1			T4	1		T5	5		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T16	1		T5	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T5	1		T219	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	77	1			T5	1		T63	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T14	1		T17	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	31	1			T35	1		T196	2		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	46	1			T3	3		T6	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T4	1		T81	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T5	3		T133	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T63	1		T60	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T42	1		T6	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	250	1			T17	1		T5	3		T137	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T3	2		T48	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T3	3		T5	4		T6	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	142	1			T18	1		T63	1		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T15	1		T18	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T18	1		T5	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T5	2		T133	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	251	1			T15	3		T18	3		T80	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	41	1			T35	1		T48	2		T86	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T14	1		T34	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	653	1			T3	1		T4	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	192	1			T19	1		T41	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	640	1			T3	2		T4	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T14	1		T41	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	671	1			T3	3		T4	2		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	167	1			T34	1		T5	3		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	647	1			T3	1		T4	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	190	1			T14	1		T81	1		T5	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	436	1			T3	3		T4	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	176	1			T16	1		T5	4		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	407	1			T14	1		T17	1		T19	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	178	1			T17	1		T5	3		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	381	1			T3	3		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T5	2		T82	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	421	1			T3	1		T4	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	157	1			T17	1		T5	1		T214	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	530	1			T3	1		T4	2		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	289	1			T19	1		T5	4		T219	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	846	1			T3	4		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T17	1		T5	4		T137	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	890	1			T3	1		T4	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T14	1		T15	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	868	1			T3	2		T14	2		T15	17
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	144	1			T17	1		T5	5		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	372	1			T17	1		T5	14		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	252	1			T16	1		T5	2		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	522	1			T4	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T5	3		T133	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	471	1			T3	5		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	239	1			T15	1		T18	2		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	510	1			T3	3		T15	3		T18	4