Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29680

1

T1

8

T3

56

T4

34

auto[1]

257

1

T17

5

T139

1

T140

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	29688	1			T1	8		T3	56		T4	34
auto[134217728:268435455]	11	1			T140	1		T282	1		T407	1
auto[268435456:402653183]	3	1			T242	1		T426	1		T427	1
auto[402653184:536870911]	7	1			T282	1		T241	1		T312	1
auto[536870912:671088639]	2	1			T17	1		T312	1		-	-
auto[671088640:805306367]	3	1			T310	1		T428	1		T429	1
auto[805306368:939524095]	9	1			T241	1		T296	1		T242	1
auto[939524096:1073741823]	8	1			T141	1		T319	1		T296	1
auto[1073741824:1207959551]	4	1			T141	1		T312	1		T430	1
auto[1207959552:1342177279]	7	1			T140	1		T141	1		T312	1
auto[1342177280:1476395007]	9	1			T406	1		T431	2		T249	1
auto[1476395008:1610612735]	11	1			T140	1		T400	1		T431	1
auto[1610612736:1744830463]	8	1			T140	1		T319	1		T241	1
auto[1744830464:1879048191]	11	1			T400	1		T391	1		T426	1
auto[1879048192:2013265919]	11	1			T17	1		T319	2		T282	1
auto[2013265920:2147483647]	11	1			T17	1		T241	1		T400	1
auto[2147483648:2281701375]	9	1			T296	1		T317	1		T430	1
auto[2281701376:2415919103]	7	1			T319	1		T282	1		T362	2
auto[2415919104:2550136831]	8	1			T241	1		T296	3		T317	1
auto[2550136832:2684354559]	4	1			T426	1		T432	1		T429	1
auto[2684354560:2818572287]	12	1			T282	2		T400	1		T406	1
auto[2818572288:2952790015]	13	1			T17	1		T140	1		T319	1
auto[2952790016:3087007743]	5	1			T296	2		T433	1		T434	1
auto[3087007744:3221225471]	4	1			T319	1		T430	1		T435	1
auto[3221225472:3355443199]	8	1			T282	1		T400	1		T407	1
auto[3355443200:3489660927]	8	1			T140	1		T319	1		T296	1
auto[3489660928:3623878655]	12	1			T141	1		T406	1		T391	1
auto[3623878656:3758096383]	7	1			T312	1		T406	1		T433	1
auto[3758096384:3892314111]	4	1			T246	1		T426	1		T436	1
auto[3892314112:4026531839]	9	1			T141	1		T426	1		T430	1
auto[4026531840:4160749567]	8	1			T282	1		T241	1		T317	2
auto[4160749568:4294967295]	16	1			T139	1		T140	1		T310	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29680	1			T1	8		T3	56		T4	34
auto[0:134217727]	auto[1]	8	1			T17	1		T282	1		T400	1
auto[134217728:268435455]	auto[1]	11	1			T140	1		T282	1		T407	1
auto[268435456:402653183]	auto[1]	3	1			T242	1		T426	1		T427	1
auto[402653184:536870911]	auto[1]	7	1			T282	1		T241	1		T312	1
auto[536870912:671088639]	auto[1]	2	1			T17	1		T312	1		-	-
auto[671088640:805306367]	auto[1]	3	1			T310	1		T428	1		T429	1
auto[805306368:939524095]	auto[1]	9	1			T241	1		T296	1		T242	1
auto[939524096:1073741823]	auto[1]	8	1			T141	1		T319	1		T296	1
auto[1073741824:1207959551]	auto[1]	4	1			T141	1		T312	1		T430	1
auto[1207959552:1342177279]	auto[1]	7	1			T140	1		T141	1		T312	1
auto[1342177280:1476395007]	auto[1]	9	1			T406	1		T431	2		T249	1
auto[1476395008:1610612735]	auto[1]	11	1			T140	1		T400	1		T431	1
auto[1610612736:1744830463]	auto[1]	8	1			T140	1		T319	1		T241	1
auto[1744830464:1879048191]	auto[1]	11	1			T400	1		T391	1		T426	1
auto[1879048192:2013265919]	auto[1]	11	1			T17	1		T319	2		T282	1
auto[2013265920:2147483647]	auto[1]	11	1			T17	1		T241	1		T400	1
auto[2147483648:2281701375]	auto[1]	9	1			T296	1		T317	1		T430	1
auto[2281701376:2415919103]	auto[1]	7	1			T319	1		T282	1		T362	2
auto[2415919104:2550136831]	auto[1]	8	1			T241	1		T296	3		T317	1
auto[2550136832:2684354559]	auto[1]	4	1			T426	1		T432	1		T429	1
auto[2684354560:2818572287]	auto[1]	12	1			T282	2		T400	1		T406	1
auto[2818572288:2952790015]	auto[1]	13	1			T17	1		T140	1		T319	1
auto[2952790016:3087007743]	auto[1]	5	1			T296	2		T433	1		T434	1
auto[3087007744:3221225471]	auto[1]	4	1			T319	1		T430	1		T435	1
auto[3221225472:3355443199]	auto[1]	8	1			T282	1		T400	1		T407	1
auto[3355443200:3489660927]	auto[1]	8	1			T140	1		T319	1		T296	1
auto[3489660928:3623878655]	auto[1]	12	1			T141	1		T406	1		T391	1
auto[3623878656:3758096383]	auto[1]	7	1			T312	1		T406	1		T433	1
auto[3758096384:3892314111]	auto[1]	4	1			T246	1		T426	1		T436	1
auto[3892314112:4026531839]	auto[1]	9	1			T141	1		T426	1		T430	1
auto[4026531840:4160749567]	auto[1]	8	1			T282	1		T241	1		T317	2
auto[4160749568:4294967295]	auto[1]	16	1			T139	1		T140	1		T310	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1523

1

T3

9

T4

4

T17

3

auto[1]

1567

1

T1

1

T3

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	80	1			T5	2		T63	1		T213	1
auto[134217728:268435455]	114	1			T34	1		T83	1		T133	1
auto[268435456:402653183]	98	1			T5	1		T127	1		T6	1
auto[402653184:536870911]	92	1			T5	2		T138	1		T48	1
auto[536870912:671088639]	88	1			T5	4		T138	1		T35	1
auto[671088640:805306367]	92	1			T3	1		T5	2		T27	1
auto[805306368:939524095]	94	1			T3	1		T14	1		T5	5
auto[939524096:1073741823]	95	1			T41	1		T5	1		T133	1
auto[1073741824:1207959551]	95	1			T3	1		T14	1		T5	1
auto[1207959552:1342177279]	83	1			T1	1		T5	1		T35	1
auto[1342177280:1476395007]	96	1			T4	1		T5	1		T214	1
auto[1476395008:1610612735]	100	1			T41	1		T5	2		T214	1
auto[1610612736:1744830463]	103	1			T4	1		T14	1		T5	2
auto[1744830464:1879048191]	83	1			T63	1		T35	1		T48	1
auto[1879048192:2013265919]	89	1			T3	1		T17	1		T5	3
auto[2013265920:2147483647]	105	1			T3	1		T5	4		T133	1
auto[2147483648:2281701375]	95	1			T3	2		T82	1		T6	1
auto[2281701376:2415919103]	97	1			T5	1		T133	1		T213	1
auto[2415919104:2550136831]	88	1			T5	4		T224	1		T8	1
auto[2550136832:2684354559]	98	1			T3	2		T4	1		T5	1
auto[2684354560:2818572287]	117	1			T17	1		T214	1		T47	1
auto[2818572288:2952790015]	99	1			T34	1		T41	1		T5	4
auto[2952790016:3087007743]	113	1			T3	1		T5	3		T83	1
auto[3087007744:3221225471]	97	1			T17	1		T41	1		T5	2
auto[3221225472:3355443199]	104	1			T5	1		T82	1		T214	1
auto[3355443200:3489660927]	97	1			T5	5		T48	1		T42	2
auto[3489660928:3623878655]	115	1			T3	1		T17	1		T34	1
auto[3623878656:3758096383]	101	1			T17	1		T41	1		T5	1
auto[3758096384:3892314111]	102	1			T138	1		T116	1		T42	1
auto[3892314112:4026531839]	77	1			T4	1		T17	1		T5	2
auto[4026531840:4160749567]	89	1			T27	1		T51	1		T42	1
auto[4160749568:4294967295]	94	1			T82	1		T51	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T5	1		T213	1		T64	1
auto[0:134217727]	auto[1]	42	1			T5	1		T63	1		T28	1
auto[134217728:268435455]	auto[0]	58	1			T34	1		T47	1		T6	1
auto[134217728:268435455]	auto[1]	56	1			T83	1		T133	1		T7	1
auto[268435456:402653183]	auto[0]	57	1			T6	1		T43	1		T62	1
auto[268435456:402653183]	auto[1]	41	1			T5	1		T127	1		T44	1
auto[402653184:536870911]	auto[0]	52	1			T5	2		T138	1		T48	1
auto[402653184:536870911]	auto[1]	40	1			T6	2		T7	2		T375	2
auto[536870912:671088639]	auto[0]	38	1			T5	1		T138	1		T35	1
auto[536870912:671088639]	auto[1]	50	1			T5	3		T6	1		T199	1
auto[671088640:805306367]	auto[0]	44	1			T3	1		T196	1		T7	1
auto[671088640:805306367]	auto[1]	48	1			T5	2		T27	1		T6	2
auto[805306368:939524095]	auto[0]	54	1			T3	1		T5	4		T27	1
auto[805306368:939524095]	auto[1]	40	1			T14	1		T5	1		T116	1
auto[939524096:1073741823]	auto[0]	44	1			T5	1		T214	1		T116	1
auto[939524096:1073741823]	auto[1]	51	1			T41	1		T133	1		T138	1
auto[1073741824:1207959551]	auto[0]	52	1			T116	1		T6	2		T149	1
auto[1073741824:1207959551]	auto[1]	43	1			T3	1		T14	1		T5	1
auto[1207959552:1342177279]	auto[0]	43	1			T6	2		T61	2		T26	1
auto[1207959552:1342177279]	auto[1]	40	1			T1	1		T5	1		T35	1
auto[1342177280:1476395007]	auto[0]	44	1			T4	1		T5	1		T42	1
auto[1342177280:1476395007]	auto[1]	52	1			T214	1		T36	1		T7	1
auto[1476395008:1610612735]	auto[0]	48	1			T41	1		T214	1		T48	1
auto[1476395008:1610612735]	auto[1]	52	1			T5	2		T42	1		T127	1
auto[1610612736:1744830463]	auto[0]	60	1			T4	1		T25	1		T47	2
auto[1610612736:1744830463]	auto[1]	43	1			T14	1		T5	2		T6	1
auto[1744830464:1879048191]	auto[0]	41	1			T63	1		T35	1		T86	2
auto[1744830464:1879048191]	auto[1]	42	1			T48	1		T47	1		T7	1
auto[1879048192:2013265919]	auto[0]	48	1			T3	1		T17	1		T5	2
auto[1879048192:2013265919]	auto[1]	41	1			T5	1		T63	1		T6	2
auto[2013265920:2147483647]	auto[0]	55	1			T3	1		T5	2		T213	1
auto[2013265920:2147483647]	auto[1]	50	1			T5	2		T133	1		T7	1
auto[2147483648:2281701375]	auto[0]	50	1			T3	2		T6	1		T43	1
auto[2147483648:2281701375]	auto[1]	45	1			T82	1		T224	1		T84	1
auto[2281701376:2415919103]	auto[0]	54	1			T213	1		T42	1		T85	1
auto[2281701376:2415919103]	auto[1]	43	1			T5	1		T133	1		T7	3
auto[2415919104:2550136831]	auto[0]	46	1			T5	2		T86	1		T54	1
auto[2415919104:2550136831]	auto[1]	42	1			T5	2		T224	1		T8	1
auto[2550136832:2684354559]	auto[0]	54	1			T3	2		T4	1		T63	1
auto[2550136832:2684354559]	auto[1]	44	1			T5	1		T214	1		T116	1
auto[2684354560:2818572287]	auto[0]	54	1			T17	1		T47	1		T6	2
auto[2684354560:2818572287]	auto[1]	63	1			T214	1		T139	1		T7	3
auto[2818572288:2952790015]	auto[0]	38	1			T41	1		T5	1		T83	1
auto[2818572288:2952790015]	auto[1]	61	1			T34	1		T5	3		T196	3
auto[2952790016:3087007743]	auto[0]	49	1			T3	1		T83	1		T47	1
auto[2952790016:3087007743]	auto[1]	64	1			T5	3		T63	1		T214	1
auto[3087007744:3221225471]	auto[0]	46	1			T41	1		T5	1		T7	1
auto[3087007744:3221225471]	auto[1]	51	1			T17	1		T5	1		T6	1
auto[3221225472:3355443199]	auto[0]	50	1			T5	1		T82	1		T214	1
auto[3221225472:3355443199]	auto[1]	54	1			T127	2		T38	1		T307	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	3		T226	1		T45	1
auto[3355443200:3489660927]	auto[1]	50	1			T5	2		T48	1		T42	2
auto[3489660928:3623878655]	auto[0]	55	1			T34	1		T5	1		T214	1
auto[3489660928:3623878655]	auto[1]	60	1			T3	1		T17	1		T5	1
auto[3623878656:3758096383]	auto[0]	49	1			T17	1		T41	1		T27	1
auto[3623878656:3758096383]	auto[1]	52	1			T5	1		T6	1		T64	1
auto[3758096384:3892314111]	auto[0]	52	1			T116	1		T7	3		T26	1
auto[3758096384:3892314111]	auto[1]	50	1			T138	1		T42	1		T127	1
auto[3892314112:4026531839]	auto[0]	32	1			T4	1		T5	2		T25	1
auto[3892314112:4026531839]	auto[1]	45	1			T17	1		T138	1		T27	1
auto[4026531840:4160749567]	auto[0]	35	1			T27	1		T139	1		T7	2
auto[4026531840:4160749567]	auto[1]	54	1			T51	1		T42	1		T6	1
auto[4160749568:4294967295]	auto[0]	36	1			T51	1		T6	1		T61	1
auto[4160749568:4294967295]	auto[1]	58	1			T82	1		T7	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1488

1

T3

10

T4

3

T17

4

auto[1]

1603

1

T1

1

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T83	1		T37	1		T6	2
auto[134217728:268435455]	113	1			T5	2		T27	1		T6	1
auto[268435456:402653183]	97	1			T5	3		T27	1		T42	1
auto[402653184:536870911]	100	1			T41	1		T5	2		T214	1
auto[536870912:671088639]	105	1			T3	2		T4	1		T14	1
auto[671088640:805306367]	90	1			T14	1		T5	2		T42	1
auto[805306368:939524095]	102	1			T5	2		T116	1		T47	1
auto[939524096:1073741823]	100	1			T3	2		T5	1		T214	1
auto[1073741824:1207959551]	92	1			T5	2		T35	1		T116	1
auto[1207959552:1342177279]	91	1			T5	2		T42	1		T6	1
auto[1342177280:1476395007]	97	1			T4	1		T5	2		T27	1
auto[1476395008:1610612735]	93	1			T41	1		T5	1		T116	1
auto[1610612736:1744830463]	95	1			T4	1		T34	1		T214	1
auto[1744830464:1879048191]	100	1			T34	1		T5	2		T82	1
auto[1879048192:2013265919]	100	1			T3	1		T41	1		T5	4
auto[2013265920:2147483647]	88	1			T34	1		T5	2		T133	1
auto[2147483648:2281701375]	105	1			T3	1		T17	1		T5	1
auto[2281701376:2415919103]	96	1			T5	2		T213	1		T6	1
auto[2415919104:2550136831]	98	1			T5	2		T82	1		T51	1
auto[2550136832:2684354559]	94	1			T5	2		T133	1		T138	1
auto[2684354560:2818572287]	84	1			T3	1		T41	1		T63	1
auto[2818572288:2952790015]	79	1			T3	1		T17	1		T5	4
auto[2952790016:3087007743]	97	1			T1	1		T5	1		T83	1
auto[3087007744:3221225471]	92	1			T17	2		T5	2		T6	1
auto[3221225472:3355443199]	96	1			T5	2		T35	1		T47	1
auto[3355443200:3489660927]	93	1			T3	1		T5	1		T63	1
auto[3489660928:3623878655]	109	1			T3	1		T5	2		T82	1
auto[3623878656:3758096383]	107	1			T14	1		T17	1		T5	1
auto[3758096384:3892314111]	100	1			T3	1		T5	5		T133	1
auto[3892314112:4026531839]	103	1			T17	1		T41	1		T5	3
auto[4026531840:4160749567]	88	1			T5	1		T36	1		T42	1
auto[4160749568:4294967295]	97	1			T4	1		T5	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T37	1		T6	2		T50	1
auto[0:134217727]	auto[1]	37	1			T83	1		T50	1		T392	1
auto[134217728:268435455]	auto[0]	50	1			T5	1		T27	1		T6	1
auto[134217728:268435455]	auto[1]	63	1			T5	1		T28	1		T196	1
auto[268435456:402653183]	auto[0]	49	1			T5	2		T43	1		T216	1
auto[268435456:402653183]	auto[1]	48	1			T5	1		T27	1		T42	1
auto[402653184:536870911]	auto[0]	40	1			T6	1		T7	1		T156	1
auto[402653184:536870911]	auto[1]	60	1			T41	1		T5	2		T214	1
auto[536870912:671088639]	auto[0]	53	1			T3	2		T27	1		T127	1
auto[536870912:671088639]	auto[1]	52	1			T4	1		T14	1		T6	1
auto[671088640:805306367]	auto[0]	43	1			T5	1		T47	1		T6	1
auto[671088640:805306367]	auto[1]	47	1			T14	1		T5	1		T42	1
auto[805306368:939524095]	auto[0]	55	1			T47	1		T6	1		T50	1
auto[805306368:939524095]	auto[1]	47	1			T5	2		T116	1		T61	1
auto[939524096:1073741823]	auto[0]	47	1			T3	2		T214	1		T25	1
auto[939524096:1073741823]	auto[1]	53	1			T5	1		T42	1		T268	1
auto[1073741824:1207959551]	auto[0]	43	1			T5	1		T35	1		T48	1
auto[1073741824:1207959551]	auto[1]	49	1			T5	1		T116	1		T47	1
auto[1207959552:1342177279]	auto[0]	36	1			T6	1		T7	1		T61	1
auto[1207959552:1342177279]	auto[1]	55	1			T5	2		T42	1		T7	1
auto[1342177280:1476395007]	auto[0]	52	1			T4	1		T5	1		T116	1
auto[1342177280:1476395007]	auto[1]	45	1			T5	1		T27	1		T6	1
auto[1476395008:1610612735]	auto[0]	48	1			T41	1		T116	1		T25	1
auto[1476395008:1610612735]	auto[1]	45	1			T5	1		T6	1		T7	1
auto[1610612736:1744830463]	auto[0]	53	1			T4	1		T34	1		T214	1
auto[1610612736:1744830463]	auto[1]	42	1			T42	1		T61	1		T62	1
auto[1744830464:1879048191]	auto[0]	52	1			T6	1		T196	2		T64	1
auto[1744830464:1879048191]	auto[1]	48	1			T34	1		T5	2		T82	1
auto[1879048192:2013265919]	auto[0]	54	1			T3	1		T41	1		T5	3
auto[1879048192:2013265919]	auto[1]	46	1			T5	1		T6	2		T199	1
auto[2013265920:2147483647]	auto[0]	32	1			T34	1		T5	1		T35	1
auto[2013265920:2147483647]	auto[1]	56	1			T5	1		T133	1		T63	1
auto[2147483648:2281701375]	auto[0]	48	1			T3	1		T17	1		T6	2
auto[2147483648:2281701375]	auto[1]	57	1			T5	1		T133	1		T214	1
auto[2281701376:2415919103]	auto[0]	37	1			T5	1		T213	1		T6	1
auto[2281701376:2415919103]	auto[1]	59	1			T5	1		T61	3		T62	1
auto[2415919104:2550136831]	auto[0]	49	1			T5	1		T7	3		T425	2
auto[2415919104:2550136831]	auto[1]	49	1			T5	1		T82	1		T51	1
auto[2550136832:2684354559]	auto[0]	36	1			T5	2		T27	1		T213	1
auto[2550136832:2684354559]	auto[1]	58	1			T133	1		T138	1		T214	1
auto[2684354560:2818572287]	auto[0]	44	1			T3	1		T41	1		T213	1
auto[2684354560:2818572287]	auto[1]	40	1			T63	1		T138	1		T48	1
auto[2818572288:2952790015]	auto[0]	44	1			T3	1		T5	4		T25	1
auto[2818572288:2952790015]	auto[1]	35	1			T17	1		T48	1		T213	1
auto[2952790016:3087007743]	auto[0]	49	1			T83	1		T6	1		T78	1
auto[2952790016:3087007743]	auto[1]	48	1			T1	1		T5	1		T7	1
auto[3087007744:3221225471]	auto[0]	48	1			T17	2		T196	1		T149	1
auto[3087007744:3221225471]	auto[1]	44	1			T5	2		T6	1		T7	1
auto[3221225472:3355443199]	auto[0]	46	1			T35	1		T47	1		T6	2
auto[3221225472:3355443199]	auto[1]	50	1			T5	2		T64	1		T224	1
auto[3355443200:3489660927]	auto[0]	48	1			T3	1		T63	1		T47	1
auto[3355443200:3489660927]	auto[1]	45	1			T5	1		T214	1		T6	2
auto[3489660928:3623878655]	auto[0]	48	1			T25	1		T6	2		T7	1
auto[3489660928:3623878655]	auto[1]	61	1			T3	1		T5	2		T82	1
auto[3623878656:3758096383]	auto[0]	53	1			T6	1		T7	2		T61	1
auto[3623878656:3758096383]	auto[1]	54	1			T14	1		T17	1		T5	1
auto[3758096384:3892314111]	auto[0]	44	1			T3	1		T42	2		T66	1
auto[3758096384:3892314111]	auto[1]	56	1			T5	5		T133	1		T63	1
auto[3892314112:4026531839]	auto[0]	47	1			T17	1		T41	1		T5	2
auto[3892314112:4026531839]	auto[1]	56	1			T5	1		T138	1		T6	1
auto[4026531840:4160749567]	auto[0]	40	1			T6	2		T7	1		T78	1
auto[4026531840:4160749567]	auto[1]	48	1			T5	1		T36	1		T42	1
auto[4160749568:4294967295]	auto[0]	47	1			T4	1		T48	1		T42	1
auto[4160749568:4294967295]	auto[1]	50	1			T5	1		T7	2		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1495

1

T3

9

T4

3

T17

3

auto[1]

1594

1

T1

1

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T5	3		T214	1		T42	1
auto[134217728:268435455]	96	1			T5	2		T42	1		T6	1
auto[268435456:402653183]	89	1			T5	1		T63	1		T213	1
auto[402653184:536870911]	89	1			T83	1		T27	1		T25	1
auto[536870912:671088639]	108	1			T4	2		T14	1		T5	4
auto[671088640:805306367]	105	1			T41	1		T5	2		T48	1
auto[805306368:939524095]	90	1			T17	1		T41	1		T5	2
auto[939524096:1073741823]	109	1			T3	1		T27	1		T35	1
auto[1073741824:1207959551]	103	1			T5	2		T133	1		T6	1
auto[1207959552:1342177279]	91	1			T34	2		T5	1		T63	1
auto[1342177280:1476395007]	101	1			T5	1		T82	1		T133	1
auto[1476395008:1610612735]	105	1			T3	1		T14	1		T5	2
auto[1610612736:1744830463]	105	1			T6	3		T7	3		T224	1
auto[1744830464:1879048191]	95	1			T3	1		T4	1		T17	1
auto[1879048192:2013265919]	107	1			T5	2		T82	1		T42	1
auto[2013265920:2147483647]	93	1			T3	1		T5	1		T133	1
auto[2147483648:2281701375]	100	1			T4	1		T5	1		T138	1
auto[2281701376:2415919103]	105	1			T5	3		T42	1		T127	1
auto[2415919104:2550136831]	102	1			T5	3		T138	1		T116	1
auto[2550136832:2684354559]	88	1			T5	2		T127	1		T66	1
auto[2684354560:2818572287]	84	1			T5	2		T83	1		T214	1
auto[2818572288:2952790015]	89	1			T6	2		T196	2		T50	1
auto[2952790016:3087007743]	87	1			T5	2		T116	1		T48	1
auto[3087007744:3221225471]	91	1			T3	1		T5	1		T63	1
auto[3221225472:3355443199]	104	1			T138	1		T116	1		T6	1
auto[3355443200:3489660927]	87	1			T41	1		T5	1		T213	1
auto[3489660928:3623878655]	108	1			T1	1		T17	1		T5	4
auto[3623878656:3758096383]	101	1			T3	1		T5	3		T213	2
auto[3758096384:3892314111]	87	1			T3	1		T17	1		T41	1
auto[3892314112:4026531839]	86	1			T17	1		T5	1		T48	1
auto[4026531840:4160749567]	100	1			T3	1		T14	1		T34	1
auto[4160749568:4294967295]	95	1			T3	3		T17	1		T41	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T5	1		T214	1		T42	1
auto[0:134217727]	auto[1]	44	1			T5	2		T6	1		T196	1
auto[134217728:268435455]	auto[0]	44	1			T6	1		T86	1		T226	1
auto[134217728:268435455]	auto[1]	52	1			T5	2		T42	1		T61	1
auto[268435456:402653183]	auto[0]	44	1			T5	1		T6	2		T61	1
auto[268435456:402653183]	auto[1]	45	1			T63	1		T213	1		T25	1
auto[402653184:536870911]	auto[0]	42	1			T83	1		T25	1		T6	2
auto[402653184:536870911]	auto[1]	47	1			T27	1		T7	2		T62	1
auto[536870912:671088639]	auto[0]	52	1			T4	1		T27	1		T6	2
auto[536870912:671088639]	auto[1]	56	1			T4	1		T14	1		T5	4
auto[671088640:805306367]	auto[0]	53	1			T41	1		T5	2		T25	1
auto[671088640:805306367]	auto[1]	52	1			T48	1		T42	1		T6	1
auto[805306368:939524095]	auto[0]	47	1			T17	1		T41	1		T5	1
auto[805306368:939524095]	auto[1]	43	1			T5	1		T61	1		T224	2
auto[939524096:1073741823]	auto[0]	49	1			T3	1		T35	1		T42	1
auto[939524096:1073741823]	auto[1]	60	1			T27	1		T6	1		T28	1
auto[1073741824:1207959551]	auto[0]	57	1			T5	2		T6	1		T139	1
auto[1073741824:1207959551]	auto[1]	46	1			T133	1		T139	1		T7	1
auto[1207959552:1342177279]	auto[0]	36	1			T34	1		T6	1		T78	1
auto[1207959552:1342177279]	auto[1]	55	1			T34	1		T5	1		T63	1
auto[1342177280:1476395007]	auto[0]	48	1			T6	1		T7	1		T9	1
auto[1342177280:1476395007]	auto[1]	53	1			T5	1		T82	1		T133	1
auto[1476395008:1610612735]	auto[0]	50	1			T3	1		T5	2		T27	1
auto[1476395008:1610612735]	auto[1]	55	1			T14	1		T42	1		T47	1
auto[1610612736:1744830463]	auto[0]	41	1			T6	1		T85	1		T289	1
auto[1610612736:1744830463]	auto[1]	64	1			T6	2		T7	3		T224	1
auto[1744830464:1879048191]	auto[0]	45	1			T3	1		T4	1		T116	1
auto[1744830464:1879048191]	auto[1]	50	1			T17	1		T5	2		T127	1
auto[1879048192:2013265919]	auto[0]	45	1			T7	1		T89	1		T425	1
auto[1879048192:2013265919]	auto[1]	62	1			T5	2		T82	1		T42	1
auto[2013265920:2147483647]	auto[0]	49	1			T3	1		T5	1		T51	1
auto[2013265920:2147483647]	auto[1]	44	1			T133	1		T6	1		T61	1
auto[2147483648:2281701375]	auto[0]	41	1			T4	1		T5	1		T47	1
auto[2147483648:2281701375]	auto[1]	59	1			T138	1		T51	1		T6	1
auto[2281701376:2415919103]	auto[0]	54	1			T5	3		T47	2		T6	2
auto[2281701376:2415919103]	auto[1]	51	1			T42	1		T127	1		T392	1
auto[2415919104:2550136831]	auto[0]	52	1			T138	1		T6	3		T149	1
auto[2415919104:2550136831]	auto[1]	50	1			T5	3		T116	1		T61	2
auto[2550136832:2684354559]	auto[0]	42	1			T5	2		T156	1		T257	1
auto[2550136832:2684354559]	auto[1]	46	1			T127	1		T66	1		T156	1
auto[2684354560:2818572287]	auto[0]	36	1			T5	1		T83	1		T7	1
auto[2684354560:2818572287]	auto[1]	48	1			T5	1		T214	1		T127	1
auto[2818572288:2952790015]	auto[0]	48	1			T6	2		T196	1		T50	1
auto[2818572288:2952790015]	auto[1]	41	1			T196	1		T7	1		T54	1
auto[2952790016:3087007743]	auto[0]	39	1			T116	1		T6	3		T7	1
auto[2952790016:3087007743]	auto[1]	48	1			T5	2		T48	1		T36	1
auto[3087007744:3221225471]	auto[0]	44	1			T3	1		T5	1		T63	1
auto[3087007744:3221225471]	auto[1]	47	1			T138	1		T214	1		T116	1
auto[3221225472:3355443199]	auto[0]	56	1			T138	1		T6	1		T149	1
auto[3221225472:3355443199]	auto[1]	48	1			T116	1		T7	2		T61	1
auto[3355443200:3489660927]	auto[0]	40	1			T41	1		T213	1		T196	1
auto[3355443200:3489660927]	auto[1]	47	1			T5	1		T6	1		T149	1
auto[3489660928:3623878655]	auto[0]	50	1			T17	1		T5	1		T214	1
auto[3489660928:3623878655]	auto[1]	58	1			T1	1		T5	3		T82	1
auto[3623878656:3758096383]	auto[0]	46	1			T5	2		T213	2		T6	2
auto[3623878656:3758096383]	auto[1]	55	1			T3	1		T5	1		T6	1
auto[3758096384:3892314111]	auto[0]	48	1			T3	1		T17	1		T41	1
auto[3758096384:3892314111]	auto[1]	39	1			T5	1		T63	1		T6	1
auto[3892314112:4026531839]	auto[0]	45	1			T5	1		T48	1		T196	2
auto[3892314112:4026531839]	auto[1]	41	1			T17	1		T61	1		T20	1
auto[4026531840:4160749567]	auto[0]	49	1			T83	1		T214	1		T7	2
auto[4026531840:4160749567]	auto[1]	51	1			T3	1		T14	1		T34	1
auto[4160749568:4294967295]	auto[0]	58	1			T3	3		T5	5		T6	1
auto[4160749568:4294967295]	auto[1]	37	1			T17	1		T41	1		T214	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1474

1

T3

10

T4

4

T17

3

auto[1]

1618

1

T1

1

T3

1

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T5	1		T25	1		T47	1
auto[134217728:268435455]	86	1			T5	2		T133	1		T48	1
auto[268435456:402653183]	97	1			T41	1		T5	1		T83	1
auto[402653184:536870911]	97	1			T3	1		T41	1		T48	1
auto[536870912:671088639]	88	1			T14	1		T48	1		T127	1
auto[671088640:805306367]	100	1			T34	1		T83	1		T42	1
auto[805306368:939524095]	91	1			T4	1		T5	5		T63	1
auto[939524096:1073741823]	84	1			T4	1		T5	3		T35	1
auto[1073741824:1207959551]	82	1			T4	1		T42	1		T127	1
auto[1207959552:1342177279]	92	1			T3	1		T5	2		T82	1
auto[1342177280:1476395007]	91	1			T17	1		T5	3		T83	1
auto[1476395008:1610612735]	106	1			T5	2		T42	1		T6	1
auto[1610612736:1744830463]	93	1			T34	1		T5	2		T82	1
auto[1744830464:1879048191]	92	1			T3	1		T5	5		T214	1
auto[1879048192:2013265919]	91	1			T3	1		T5	1		T127	1
auto[2013265920:2147483647]	103	1			T3	1		T41	2		T5	3
auto[2147483648:2281701375]	97	1			T5	2		T42	1		T149	1
auto[2281701376:2415919103]	107	1			T5	1		T35	1		T214	1
auto[2415919104:2550136831]	101	1			T3	1		T4	1		T14	1
auto[2550136832:2684354559]	105	1			T5	3		T214	1		T196	1
auto[2684354560:2818572287]	101	1			T5	1		T27	1		T214	1
auto[2818572288:2952790015]	89	1			T17	1		T5	1		T213	2
auto[2952790016:3087007743]	95	1			T5	1		T82	1		T138	1
auto[3087007744:3221225471]	106	1			T5	2		T63	1		T127	1
auto[3221225472:3355443199]	107	1			T3	3		T5	3		T133	1
auto[3355443200:3489660927]	106	1			T5	1		T42	1		T47	1
auto[3489660928:3623878655]	91	1			T17	2		T214	1		T6	1
auto[3623878656:3758096383]	92	1			T3	1		T34	1		T5	3
auto[3758096384:3892314111]	106	1			T14	1		T17	1		T41	1
auto[3892314112:4026531839]	100	1			T17	1		T5	3		T138	2
auto[4026531840:4160749567]	93	1			T3	1		T5	3		T133	1
auto[4160749568:4294967295]	104	1			T1	1		T5	2		T27	1