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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2701 1 T1 1 T3 11 T4 4
auto[1] 297 1 T17 2 T139 1 T140 8


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 92 1 T3 1 T5 1 T51 1
auto[134217728:268435455] 77 1 T3 1 T5 1 T213 1
auto[268435456:402653183] 106 1 T5 1 T133 1 T138 1
auto[402653184:536870911] 100 1 T3 2 T4 1 T5 2
auto[536870912:671088639] 105 1 T5 2 T82 1 T214 1
auto[671088640:805306367] 78 1 T1 1 T5 2 T133 1
auto[805306368:939524095] 78 1 T5 1 T48 1 T127 1
auto[939524096:1073741823] 98 1 T5 2 T6 2 T7 1
auto[1073741824:1207959551] 102 1 T17 1 T5 2 T42 1
auto[1207959552:1342177279] 79 1 T5 1 T116 2 T7 1
auto[1342177280:1476395007] 99 1 T17 1 T5 2 T63 1
auto[1476395008:1610612735] 116 1 T4 1 T17 1 T5 2
auto[1610612736:1744830463] 93 1 T4 1 T17 1 T34 1
auto[1744830464:1879048191] 100 1 T5 2 T82 1 T220 1
auto[1879048192:2013265919] 93 1 T17 1 T5 1 T63 1
auto[2013265920:2147483647] 97 1 T3 2 T5 3 T6 1
auto[2147483648:2281701375] 91 1 T17 1 T5 3 T42 1
auto[2281701376:2415919103] 88 1 T41 1 T5 3 T138 1
auto[2415919104:2550136831] 82 1 T3 1 T63 1 T6 1
auto[2550136832:2684354559] 109 1 T3 1 T5 1 T35 1
auto[2684354560:2818572287] 92 1 T5 1 T47 1 T7 2
auto[2818572288:2952790015] 103 1 T4 1 T14 1 T138 1
auto[2952790016:3087007743] 109 1 T5 4 T63 1 T213 1
auto[3087007744:3221225471] 101 1 T5 3 T138 1 T35 1
auto[3221225472:3355443199] 100 1 T5 1 T213 1 T196 2
auto[3355443200:3489660927] 87 1 T14 1 T41 1 T5 2
auto[3489660928:3623878655] 87 1 T35 1 T42 1 T6 2
auto[3623878656:3758096383] 76 1 T3 1 T27 1 T214 1
auto[3758096384:3892314111] 94 1 T3 1 T5 1 T133 1
auto[3892314112:4026531839] 87 1 T14 1 T5 2 T82 1
auto[4026531840:4160749567] 84 1 T3 1 T17 2 T5 2
auto[4160749568:4294967295] 95 1 T5 2 T83 1 T133 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 89 1 T3 1 T5 1 T51 1
auto[0:134217727] auto[1] 3 1 T426 1 T430 1 T362 1
auto[134217728:268435455] auto[0] 71 1 T3 1 T5 1 T213 1
auto[134217728:268435455] auto[1] 6 1 T400 1 T312 1 T406 1
auto[268435456:402653183] auto[0] 97 1 T5 1 T133 1 T138 1
auto[268435456:402653183] auto[1] 9 1 T141 1 T400 1 T426 2
auto[402653184:536870911] auto[0] 86 1 T3 2 T4 1 T5 2
auto[402653184:536870911] auto[1] 14 1 T282 1 T406 1 T431 1
auto[536870912:671088639] auto[0] 97 1 T5 2 T82 1 T214 1
auto[536870912:671088639] auto[1] 8 1 T317 1 T426 1 T352 1
auto[671088640:805306367] auto[0] 70 1 T1 1 T5 2 T133 1
auto[671088640:805306367] auto[1] 8 1 T310 1 T241 1 T312 1
auto[805306368:939524095] auto[0] 73 1 T5 1 T48 1 T127 1
auto[805306368:939524095] auto[1] 5 1 T310 1 T282 1 T267 1
auto[939524096:1073741823] auto[0] 89 1 T5 2 T6 2 T7 1
auto[939524096:1073741823] auto[1] 9 1 T241 1 T249 2 T435 1
auto[1073741824:1207959551] auto[0] 91 1 T17 1 T5 2 T42 1
auto[1073741824:1207959551] auto[1] 11 1 T141 1 T310 1 T282 1
auto[1207959552:1342177279] auto[0] 74 1 T5 1 T116 2 T7 1
auto[1207959552:1342177279] auto[1] 5 1 T241 1 T267 1 T346 1
auto[1342177280:1476395007] auto[0] 84 1 T17 1 T5 2 T63 1
auto[1342177280:1476395007] auto[1] 15 1 T140 1 T319 1 T400 1
auto[1476395008:1610612735] auto[0] 97 1 T4 1 T5 2 T6 4
auto[1476395008:1610612735] auto[1] 19 1 T17 1 T139 1 T141 1
auto[1610612736:1744830463] auto[0] 90 1 T4 1 T17 1 T34 1
auto[1610612736:1744830463] auto[1] 3 1 T313 1 T362 1 T440 1
auto[1744830464:1879048191] auto[0] 91 1 T5 2 T82 1 T220 1
auto[1744830464:1879048191] auto[1] 9 1 T282 1 T317 1 T313 1
auto[1879048192:2013265919] auto[0] 82 1 T17 1 T5 1 T63 1
auto[1879048192:2013265919] auto[1] 11 1 T140 2 T400 2 T431 1
auto[2013265920:2147483647] auto[0] 82 1 T3 2 T5 3 T6 1
auto[2013265920:2147483647] auto[1] 15 1 T140 1 T141 1 T244 1
auto[2147483648:2281701375] auto[0] 84 1 T17 1 T5 3 T42 1
auto[2147483648:2281701375] auto[1] 7 1 T407 1 T317 1 T391 1
auto[2281701376:2415919103] auto[0] 79 1 T41 1 T5 3 T138 1
auto[2281701376:2415919103] auto[1] 9 1 T140 1 T317 1 T426 1
auto[2415919104:2550136831] auto[0] 69 1 T3 1 T63 1 T6 1
auto[2415919104:2550136831] auto[1] 13 1 T241 1 T312 1 T407 2
auto[2550136832:2684354559] auto[0] 95 1 T3 1 T5 1 T35 1
auto[2550136832:2684354559] auto[1] 14 1 T319 1 T244 1 T310 1
auto[2684354560:2818572287] auto[0] 81 1 T5 1 T47 1 T7 2
auto[2684354560:2818572287] auto[1] 11 1 T140 1 T282 1 T400 1
auto[2818572288:2952790015] auto[0] 93 1 T4 1 T14 1 T138 1
auto[2818572288:2952790015] auto[1] 10 1 T313 2 T430 2 T435 1
auto[2952790016:3087007743] auto[0] 100 1 T5 4 T63 1 T213 1
auto[2952790016:3087007743] auto[1] 9 1 T317 1 T313 1 T426 1
auto[3087007744:3221225471] auto[0] 91 1 T5 3 T138 1 T35 1
auto[3087007744:3221225471] auto[1] 10 1 T310 2 T296 1 T249 3
auto[3221225472:3355443199] auto[0] 94 1 T5 1 T213 1 T196 2
auto[3221225472:3355443199] auto[1] 6 1 T319 1 T352 1 T346 1
auto[3355443200:3489660927] auto[0] 81 1 T14 1 T41 1 T5 2
auto[3355443200:3489660927] auto[1] 6 1 T140 1 T435 1 T256 2
auto[3489660928:3623878655] auto[0] 77 1 T35 1 T42 1 T6 2
auto[3489660928:3623878655] auto[1] 10 1 T407 1 T296 1 T249 1
auto[3623878656:3758096383] auto[0] 67 1 T3 1 T27 1 T214 1
auto[3623878656:3758096383] auto[1] 9 1 T319 2 T310 1 T241 1
auto[3758096384:3892314111] auto[0] 86 1 T3 1 T5 1 T133 1
auto[3758096384:3892314111] auto[1] 8 1 T310 2 T282 1 T426 1
auto[3892314112:4026531839] auto[0] 76 1 T14 1 T5 2 T82 1
auto[3892314112:4026531839] auto[1] 11 1 T140 1 T141 1 T319 1
auto[4026531840:4160749567] auto[0] 75 1 T3 1 T17 1 T5 2
auto[4026531840:4160749567] auto[1] 9 1 T17 1 T282 1 T312 1
auto[4160749568:4294967295] auto[0] 90 1 T5 2 T83 1 T133 1
auto[4160749568:4294967295] auto[1] 5 1 T241 1 T312 1 T296 2

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