Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6378

1

T1

2

T3

25

T4

14

auto[1]

285

1

T17

2

T139

1

T140

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2696	1			T1	1		T3	14		T4	7
auto[134217728:268435455]	164	1			T3	1		T5	2		T138	1
auto[268435456:402653183]	142	1			T3	1		T5	2		T63	2
auto[402653184:536870911]	124	1			T14	1		T5	3		T133	1
auto[536870912:671088639]	162	1			T3	1		T4	1		T5	2
auto[671088640:805306367]	138	1			T5	3		T82	1		T63	1
auto[805306368:939524095]	121	1			T3	1		T17	1		T5	2
auto[939524096:1073741823]	122	1			T3	1		T17	1		T82	1
auto[1073741824:1207959551]	126	1			T5	4		T138	1		T214	2
auto[1207959552:1342177279]	126	1			T5	3		T35	1		T48	1
auto[1342177280:1476395007]	141	1			T3	2		T5	1		T82	1
auto[1476395008:1610612735]	119	1			T5	3		T36	1		T127	1
auto[1610612736:1744830463]	125	1			T5	1		T42	1		T127	1
auto[1744830464:1879048191]	131	1			T4	1		T17	1		T82	1
auto[1879048192:2013265919]	112	1			T5	5		T133	2		T63	1
auto[2013265920:2147483647]	109	1			T5	3		T27	1		T213	1
auto[2147483648:2281701375]	106	1			T1	1		T5	1		T82	1
auto[2281701376:2415919103]	108	1			T3	1		T5	2		T6	2
auto[2415919104:2550136831]	110	1			T5	4		T83	1		T51	1
auto[2550136832:2684354559]	116	1			T5	1		T133	1		T35	1
auto[2684354560:2818572287]	121	1			T3	1		T5	1		T42	1
auto[2818572288:2952790015]	114	1			T5	2		T82	1		T214	1
auto[2952790016:3087007743]	133	1			T5	2		T35	1		T213	1
auto[3087007744:3221225471]	121	1			T4	1		T5	2		T82	2
auto[3221225472:3355443199]	112	1			T116	1		T213	1		T6	1
auto[3355443200:3489660927]	125	1			T5	1		T138	1		T35	1
auto[3489660928:3623878655]	144	1			T4	1		T14	1		T17	1
auto[3623878656:3758096383]	157	1			T41	1		T5	4		T214	1
auto[3758096384:3892314111]	111	1			T3	1		T14	1		T25	1
auto[3892314112:4026531839]	140	1			T4	1		T5	6		T82	1
auto[4026531840:4160749567]	137	1			T3	1		T4	1		T41	1
auto[4160749568:4294967295]	150	1			T4	1		T5	3		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2680	1			T1	1		T3	14		T4	7
auto[0:134217727]	auto[1]	16	1			T140	1		T141	2		T282	1
auto[134217728:268435455]	auto[0]	158	1			T3	1		T5	2		T138	1
auto[134217728:268435455]	auto[1]	6	1			T310	1		T407	1		T430	1
auto[268435456:402653183]	auto[0]	133	1			T3	1		T5	2		T63	2
auto[268435456:402653183]	auto[1]	9	1			T249	2		T256	2		T428	2
auto[402653184:536870911]	auto[0]	115	1			T14	1		T5	3		T133	1
auto[402653184:536870911]	auto[1]	9	1			T310	1		T282	1		T400	1
auto[536870912:671088639]	auto[0]	154	1			T3	1		T4	1		T5	2
auto[536870912:671088639]	auto[1]	8	1			T296	1		T317	1		T313	1
auto[671088640:805306367]	auto[0]	130	1			T5	3		T82	1		T63	1
auto[671088640:805306367]	auto[1]	8	1			T140	1		T296	1		T426	1
auto[805306368:939524095]	auto[0]	116	1			T3	1		T5	2		T82	1
auto[805306368:939524095]	auto[1]	5	1			T17	1		T406	1		T435	1
auto[939524096:1073741823]	auto[0]	115	1			T3	1		T17	1		T82	1
auto[939524096:1073741823]	auto[1]	7	1			T319	1		T296	1		T430	1
auto[1073741824:1207959551]	auto[0]	114	1			T5	4		T138	1		T214	2
auto[1073741824:1207959551]	auto[1]	12	1			T141	1		T282	2		T400	1
auto[1207959552:1342177279]	auto[0]	117	1			T5	3		T35	1		T48	1
auto[1207959552:1342177279]	auto[1]	9	1			T140	1		T317	2		T242	1
auto[1342177280:1476395007]	auto[0]	132	1			T3	2		T5	1		T82	1
auto[1342177280:1476395007]	auto[1]	9	1			T310	1		T282	1		T249	1
auto[1476395008:1610612735]	auto[0]	111	1			T5	3		T36	1		T127	1
auto[1476395008:1610612735]	auto[1]	8	1			T437	1		T391	1		T438	1
auto[1610612736:1744830463]	auto[0]	113	1			T5	1		T42	1		T127	1
auto[1610612736:1744830463]	auto[1]	12	1			T246	1		T248	1		T317	1
auto[1744830464:1879048191]	auto[0]	124	1			T4	1		T82	1		T214	2
auto[1744830464:1879048191]	auto[1]	7	1			T17	1		T140	1		T241	1
auto[1879048192:2013265919]	auto[0]	100	1			T5	5		T133	2		T63	1
auto[1879048192:2013265919]	auto[1]	12	1			T140	2		T406	1		T248	1
auto[2013265920:2147483647]	auto[0]	106	1			T5	3		T27	1		T213	1
auto[2013265920:2147483647]	auto[1]	3	1			T241	1		T430	1		T333	1
auto[2147483648:2281701375]	auto[0]	101	1			T1	1		T5	1		T82	1
auto[2147483648:2281701375]	auto[1]	5	1			T310	1		T282	1		T313	1
auto[2281701376:2415919103]	auto[0]	99	1			T3	1		T5	2		T6	2
auto[2281701376:2415919103]	auto[1]	9	1			T139	1		T400	1		T312	1
auto[2415919104:2550136831]	auto[0]	97	1			T5	4		T83	1		T51	1
auto[2415919104:2550136831]	auto[1]	13	1			T241	2		T312	1		T296	1
auto[2550136832:2684354559]	auto[0]	104	1			T5	1		T133	1		T35	1
auto[2550136832:2684354559]	auto[1]	12	1			T141	1		T282	1		T249	2
auto[2684354560:2818572287]	auto[0]	115	1			T3	1		T5	1		T42	1
auto[2684354560:2818572287]	auto[1]	6	1			T400	2		T267	2		T347	1
auto[2818572288:2952790015]	auto[0]	107	1			T5	2		T82	1		T214	1
auto[2818572288:2952790015]	auto[1]	7	1			T249	1		T317	1		T430	1
auto[2952790016:3087007743]	auto[0]	118	1			T5	2		T35	1		T213	1
auto[2952790016:3087007743]	auto[1]	15	1			T282	1		T406	1		T391	1
auto[3087007744:3221225471]	auto[0]	114	1			T4	1		T5	2		T82	2
auto[3087007744:3221225471]	auto[1]	7	1			T248	1		T317	1		T435	2
auto[3221225472:3355443199]	auto[0]	104	1			T116	1		T213	1		T6	1
auto[3221225472:3355443199]	auto[1]	8	1			T141	1		T310	1		T426	1
auto[3355443200:3489660927]	auto[0]	117	1			T5	1		T138	1		T35	1
auto[3355443200:3489660927]	auto[1]	8	1			T282	1		T407	1		T431	1
auto[3489660928:3623878655]	auto[0]	134	1			T4	1		T14	1		T17	1
auto[3489660928:3623878655]	auto[1]	10	1			T282	1		T430	3		T434	1
auto[3623878656:3758096383]	auto[0]	150	1			T41	1		T5	4		T214	1
auto[3623878656:3758096383]	auto[1]	7	1			T140	1		T246	1		T352	1
auto[3758096384:3892314111]	auto[0]	103	1			T3	1		T14	1		T25	1
auto[3758096384:3892314111]	auto[1]	8	1			T313	1		T435	1		T256	1
auto[3892314112:4026531839]	auto[0]	132	1			T4	1		T5	6		T82	1
auto[3892314112:4026531839]	auto[1]	8	1			T319	1		T296	1		T433	1
auto[4026531840:4160749567]	auto[0]	128	1			T3	1		T4	1		T41	1
auto[4026531840:4160749567]	auto[1]	9	1			T246	1		T431	1		T249	1
auto[4160749568:4294967295]	auto[0]	137	1			T4	1		T5	3		T27	1
auto[4160749568:4294967295]	auto[1]	13	1			T406	2		T242	1		T313	1