Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.82 99.07 98.14 98.44 100.00 99.11 98.41 91.56


Total test records in report: 1060
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1004 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1759469283 Feb 18 12:29:58 PM PST 24 Feb 18 12:30:12 PM PST 24 286999056 ps
T1005 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3198068046 Feb 18 12:29:50 PM PST 24 Feb 18 12:30:01 PM PST 24 16776380 ps
T181 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3807557439 Feb 18 12:31:01 PM PST 24 Feb 18 12:31:12 PM PST 24 235553005 ps
T1006 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3993206292 Feb 18 12:29:28 PM PST 24 Feb 18 12:29:40 PM PST 24 368362636 ps
T1007 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2424364393 Feb 18 12:29:33 PM PST 24 Feb 18 12:29:38 PM PST 24 129328889 ps
T1008 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.528526267 Feb 18 12:31:22 PM PST 24 Feb 18 12:31:26 PM PST 24 289228305 ps
T1009 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3276071117 Feb 18 12:29:57 PM PST 24 Feb 18 12:30:20 PM PST 24 406861629 ps
T1010 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3545216850 Feb 18 12:29:42 PM PST 24 Feb 18 12:29:44 PM PST 24 12518072 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4126434064 Feb 18 12:29:50 PM PST 24 Feb 18 12:29:54 PM PST 24 42199581 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1344890197 Feb 18 12:29:36 PM PST 24 Feb 18 12:29:39 PM PST 24 35322332 ps
T1013 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3123242456 Feb 18 12:29:54 PM PST 24 Feb 18 12:30:03 PM PST 24 57793425 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1555807535 Feb 18 12:29:48 PM PST 24 Feb 18 12:29:51 PM PST 24 242040397 ps
T1015 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3360057921 Feb 18 12:31:01 PM PST 24 Feb 18 12:31:06 PM PST 24 105147904 ps
T1016 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.474153170 Feb 18 12:30:01 PM PST 24 Feb 18 12:30:12 PM PST 24 24919130 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2146525507 Feb 18 12:29:44 PM PST 24 Feb 18 12:29:49 PM PST 24 58250283 ps
T1018 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3534269747 Feb 18 12:30:02 PM PST 24 Feb 18 12:30:12 PM PST 24 10446085 ps
T1019 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4226312963 Feb 18 12:29:54 PM PST 24 Feb 18 12:30:06 PM PST 24 78306766 ps
T1020 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3017335425 Feb 18 12:29:50 PM PST 24 Feb 18 12:29:56 PM PST 24 787000367 ps
T1021 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3925309018 Feb 18 12:30:05 PM PST 24 Feb 18 12:30:15 PM PST 24 42728938 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3010337778 Feb 18 12:29:55 PM PST 24 Feb 18 12:30:03 PM PST 24 41433543 ps
T1023 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1351500520 Feb 18 12:29:39 PM PST 24 Feb 18 12:29:42 PM PST 24 53105664 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.756365778 Feb 18 12:30:09 PM PST 24 Feb 18 12:30:22 PM PST 24 93788524 ps
T1025 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2368870555 Feb 18 12:29:58 PM PST 24 Feb 18 12:30:08 PM PST 24 151678388 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3919750445 Feb 18 12:29:47 PM PST 24 Feb 18 12:29:56 PM PST 24 726667669 ps
T1027 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.201308750 Feb 18 12:29:57 PM PST 24 Feb 18 12:30:09 PM PST 24 26963853 ps
T1028 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2384092654 Feb 18 12:30:06 PM PST 24 Feb 18 12:30:16 PM PST 24 21286639 ps
T1029 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1530749753 Feb 18 12:29:55 PM PST 24 Feb 18 12:30:06 PM PST 24 129457916 ps
T1030 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.793959947 Feb 18 12:29:50 PM PST 24 Feb 18 12:29:56 PM PST 24 254292211 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3837486848 Feb 18 12:29:50 PM PST 24 Feb 18 12:30:02 PM PST 24 1746478409 ps
T1032 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.406416120 Feb 18 12:29:40 PM PST 24 Feb 18 12:29:43 PM PST 24 28166793 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.756109166 Feb 18 12:29:37 PM PST 24 Feb 18 12:29:42 PM PST 24 138740561 ps
T1034 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1922664005 Feb 18 12:30:05 PM PST 24 Feb 18 12:30:16 PM PST 24 112931504 ps
T1035 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1721797811 Feb 18 12:29:55 PM PST 24 Feb 18 12:30:04 PM PST 24 67680805 ps
T1036 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3215899905 Feb 18 12:29:33 PM PST 24 Feb 18 12:29:35 PM PST 24 191885298 ps
T1037 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2076868908 Feb 18 12:29:52 PM PST 24 Feb 18 12:30:00 PM PST 24 503277393 ps
T1038 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4174504558 Feb 18 12:29:41 PM PST 24 Feb 18 12:29:47 PM PST 24 269195848 ps
T1039 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1022620370 Feb 18 12:30:17 PM PST 24 Feb 18 12:30:24 PM PST 24 14170957 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.635282798 Feb 18 12:29:52 PM PST 24 Feb 18 12:30:03 PM PST 24 275873420 ps
T1041 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.631707891 Feb 18 12:30:18 PM PST 24 Feb 18 12:30:25 PM PST 24 41159475 ps
T1042 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.486543912 Feb 18 12:30:12 PM PST 24 Feb 18 12:30:30 PM PST 24 399036472 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3259382511 Feb 18 12:29:42 PM PST 24 Feb 18 12:29:44 PM PST 24 127918167 ps
T1044 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1205773918 Feb 18 12:30:09 PM PST 24 Feb 18 12:30:19 PM PST 24 13976277 ps
T1045 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4043982909 Feb 18 12:29:34 PM PST 24 Feb 18 12:29:43 PM PST 24 30474721 ps
T1046 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1085146740 Feb 18 12:30:08 PM PST 24 Feb 18 12:30:26 PM PST 24 162232578 ps
T1047 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2727727135 Feb 18 12:30:04 PM PST 24 Feb 18 12:30:15 PM PST 24 18244561 ps
T1048 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3889158928 Feb 18 12:30:00 PM PST 24 Feb 18 12:30:11 PM PST 24 13461896 ps
T1049 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3798075848 Feb 18 12:31:01 PM PST 24 Feb 18 12:31:07 PM PST 24 91995816 ps
T1050 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3357039488 Feb 18 12:30:29 PM PST 24 Feb 18 12:30:41 PM PST 24 109416596 ps
T170 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.553747826 Feb 18 12:29:28 PM PST 24 Feb 18 12:29:38 PM PST 24 214774157 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3130975001 Feb 18 12:29:54 PM PST 24 Feb 18 12:30:04 PM PST 24 550325139 ps
T1052 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1284573044 Feb 18 12:29:53 PM PST 24 Feb 18 12:29:59 PM PST 24 35645114 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2774543504 Feb 18 12:29:51 PM PST 24 Feb 18 12:29:55 PM PST 24 45315165 ps
T1054 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.222722206 Feb 18 12:29:50 PM PST 24 Feb 18 12:29:55 PM PST 24 746090173 ps
T1055 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.249795520 Feb 18 12:30:06 PM PST 24 Feb 18 12:30:16 PM PST 24 8943917 ps
T165 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1362757046 Feb 18 12:29:51 PM PST 24 Feb 18 12:29:58 PM PST 24 333298304 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1026342836 Feb 18 12:30:11 PM PST 24 Feb 18 12:30:27 PM PST 24 1193561807 ps
T1057 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.122774811 Feb 18 12:29:36 PM PST 24 Feb 18 12:29:41 PM PST 24 415801067 ps
T1058 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2277322133 Feb 18 12:29:50 PM PST 24 Feb 18 12:29:53 PM PST 24 20316031 ps
T1059 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3219804570 Feb 18 12:29:57 PM PST 24 Feb 18 12:30:11 PM PST 24 206772546 ps
T1060 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4065841800 Feb 18 12:29:27 PM PST 24 Feb 18 12:29:33 PM PST 24 1017514338 ps

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3686955344
Short name T17
Test name
Test status
Simulation time 107558816 ps
CPU time 4.14 seconds
Started Feb 18 01:54:51 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 214812 kb
Host smart-94b58997-bdbc-427b-a24d-e768d51a4fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686955344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3686955344
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3021468718
Short name T5
Test name
Test status
Simulation time 24783755095 ps
CPU time 716.56 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 02:06:55 PM PST 24
Peak memory 230156 kb
Host smart-01844cf9-82b5-4458-b8ce-5880d2b287c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021468718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3021468718
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2846486629
Short name T54
Test name
Test status
Simulation time 2256752509 ps
CPU time 72.68 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:56:09 PM PST 24
Peak memory 216316 kb
Host smart-e2894748-049d-4341-85e6-ec520536c695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846486629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2846486629
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.593403818
Short name T13
Test name
Test status
Simulation time 1023758815 ps
CPU time 9.51 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:42 PM PST 24
Peak memory 230000 kb
Host smart-2b403e0b-e81c-45ee-9f9f-e46240720dc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593403818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.593403818
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2243262007
Short name T117
Test name
Test status
Simulation time 849515513 ps
CPU time 14.55 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 213700 kb
Host smart-a29fa547-2356-44a9-a5f2-fb5600b89e55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243262007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2243262007
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1517664597
Short name T42
Test name
Test status
Simulation time 964248858 ps
CPU time 19.47 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 222828 kb
Host smart-fe3ca9b1-fc53-46e6-881d-f0024a40c544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517664597 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1517664597
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1485388355
Short name T16
Test name
Test status
Simulation time 70328628 ps
CPU time 2.05 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 209092 kb
Host smart-9540259e-c9af-41e1-87c4-3e9ec6e150a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485388355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1485388355
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3430601798
Short name T6
Test name
Test status
Simulation time 5598639065 ps
CPU time 130.37 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:57:01 PM PST 24
Peak memory 215736 kb
Host smart-76dfa9ba-3b7c-4213-82b3-405ee89ec3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430601798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3430601798
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4189488825
Short name T28
Test name
Test status
Simulation time 370136295 ps
CPU time 8.17 seconds
Started Feb 18 01:54:10 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 222744 kb
Host smart-7f43793d-072b-412a-a2ca-ee5849602f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189488825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4189488825
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.978000452
Short name T8
Test name
Test status
Simulation time 445997552 ps
CPU time 4.29 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:46 PM PST 24
Peak memory 221492 kb
Host smart-adfa18f2-acd5-4295-896a-68b045c82edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978000452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.978000452
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1451253443
Short name T45
Test name
Test status
Simulation time 110607049 ps
CPU time 3.16 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:15 PM PST 24
Peak memory 206144 kb
Host smart-8fbec139-f9ad-4be1-a848-c3d3f50d88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451253443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1451253443
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2050165439
Short name T256
Test name
Test status
Simulation time 2009523204 ps
CPU time 28.31 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 222624 kb
Host smart-26eeef1c-c18e-4871-ba95-57d8681045ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050165439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2050165439
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.122049412
Short name T4
Test name
Test status
Simulation time 1157844800 ps
CPU time 6.81 seconds
Started Feb 18 01:55:11 PM PST 24
Finished Feb 18 01:55:23 PM PST 24
Peak memory 221400 kb
Host smart-ab22387e-b246-48a0-a02b-4b939a2eea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122049412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.122049412
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2916857129
Short name T282
Test name
Test status
Simulation time 478328967 ps
CPU time 12.88 seconds
Started Feb 18 01:53:22 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 215220 kb
Host smart-58be6531-0166-46f3-90c2-24ca581376bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916857129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2916857129
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1873535417
Short name T7
Test name
Test status
Simulation time 5985179144 ps
CPU time 60.84 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:56:04 PM PST 24
Peak memory 215280 kb
Host smart-bebd2c0e-753c-4b74-bdd6-42ba6278903c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873535417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1873535417
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.689812385
Short name T430
Test name
Test status
Simulation time 1589459299 ps
CPU time 85.62 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 215244 kb
Host smart-4602df4c-b390-42bb-b59f-710700ad5d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689812385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.689812385
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.754696391
Short name T319
Test name
Test status
Simulation time 445365926 ps
CPU time 12.3 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 215056 kb
Host smart-9b2cd8bc-15d1-42fe-9773-2888d447f86d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754696391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.754696391
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.315711750
Short name T3
Test name
Test status
Simulation time 190306239 ps
CPU time 3.89 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 222612 kb
Host smart-091ff52d-29cc-4042-9cc9-5bf0353fc631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315711750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.315711750
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2447953809
Short name T429
Test name
Test status
Simulation time 1006986694 ps
CPU time 14.84 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 214488 kb
Host smart-a98199b2-b85e-4883-b0df-009b00527657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447953809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2447953809
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3358966327
Short name T231
Test name
Test status
Simulation time 672418724 ps
CPU time 33.23 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:54:08 PM PST 24
Peak memory 222640 kb
Host smart-b669394b-3db2-492d-8e21-f9146d030f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358966327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3358966327
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2598243317
Short name T38
Test name
Test status
Simulation time 1815068091 ps
CPU time 7.16 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 209312 kb
Host smart-fad13774-62da-4fe5-a388-0d90ada94b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598243317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2598243317
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2088651783
Short name T312
Test name
Test status
Simulation time 552511589 ps
CPU time 8.83 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 214420 kb
Host smart-9d9dce1d-aefd-4a86-9a42-ea9c104f9562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088651783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2088651783
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2975873702
Short name T69
Test name
Test status
Simulation time 4081340717 ps
CPU time 77.86 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 216372 kb
Host smart-0a542685-70af-4a6f-ae19-5ebbe47908c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975873702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2975873702
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1201659486
Short name T118
Test name
Test status
Simulation time 323633446 ps
CPU time 3.95 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 221668 kb
Host smart-9c472198-534a-461c-b987-4cc4cf001da4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201659486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1201659486
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4151442903
Short name T801
Test name
Test status
Simulation time 917656321 ps
CPU time 4.81 seconds
Started Feb 18 01:53:55 PM PST 24
Finished Feb 18 01:54:03 PM PST 24
Peak memory 209552 kb
Host smart-8a8bc8e9-1418-484d-9f7a-f6c9fcfef46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151442903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4151442903
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3134882093
Short name T440
Test name
Test status
Simulation time 888698052 ps
CPU time 14.36 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:27 PM PST 24
Peak memory 214464 kb
Host smart-fb00db06-668f-4e01-8623-7b563abefde5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134882093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3134882093
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.197684808
Short name T90
Test name
Test status
Simulation time 73378463 ps
CPU time 4.04 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 214428 kb
Host smart-4a77e425-a435-4766-96bc-9dc586ae59c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197684808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.197684808
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.694028764
Short name T92
Test name
Test status
Simulation time 173105461 ps
CPU time 4.48 seconds
Started Feb 18 01:52:53 PM PST 24
Finished Feb 18 01:52:59 PM PST 24
Peak memory 208564 kb
Host smart-7ff27e79-5b56-4e7e-9e93-4b5ffd2ec9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694028764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.694028764
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1416306507
Short name T154
Test name
Test status
Simulation time 958741787 ps
CPU time 8.35 seconds
Started Feb 18 12:29:35 PM PST 24
Finished Feb 18 12:29:46 PM PST 24
Peak memory 208756 kb
Host smart-984afdaa-b9cc-4da4-81a5-507f401164d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416306507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1416306507
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3795101076
Short name T51
Test name
Test status
Simulation time 387021464 ps
CPU time 6.81 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 217584 kb
Host smart-fd21e50e-775a-4c5e-b555-644ce22f56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795101076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3795101076
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3229308880
Short name T296
Test name
Test status
Simulation time 3970528729 ps
CPU time 107.42 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:54:24 PM PST 24
Peak memory 214468 kb
Host smart-480562b0-d7d9-4786-8cca-1ee62d542d31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229308880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3229308880
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1245809650
Short name T96
Test name
Test status
Simulation time 228247772 ps
CPU time 4.04 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:21 PM PST 24
Peak memory 209164 kb
Host smart-48d13c46-7597-484f-970c-6eceef22d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245809650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1245809650
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.103070636
Short name T304
Test name
Test status
Simulation time 294201561 ps
CPU time 4.46 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 211200 kb
Host smart-fe4a20ba-0019-4dd8-8f53-1387b6e7c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103070636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.103070636
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4145202252
Short name T79
Test name
Test status
Simulation time 15978802 ps
CPU time 1 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:44 PM PST 24
Peak memory 206396 kb
Host smart-dcf0106a-63c1-4a11-8503-97682c2f8e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145202252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4145202252
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1396664616
Short name T161
Test name
Test status
Simulation time 179735516 ps
CPU time 4.83 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213468 kb
Host smart-c95c8ff9-2cf4-4b25-9e2d-d18a98d94d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396664616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1396664616
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3752329785
Short name T67
Test name
Test status
Simulation time 2129031865 ps
CPU time 39.3 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:55:16 PM PST 24
Peak memory 216228 kb
Host smart-c5011bc0-6d79-4d5c-af80-e9f334db1ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752329785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3752329785
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1376178214
Short name T24
Test name
Test status
Simulation time 253322189 ps
CPU time 3.21 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:54:39 PM PST 24
Peak memory 221588 kb
Host smart-58994988-6a0a-4db5-a613-143f3f8c9c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376178214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1376178214
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.615358450
Short name T435
Test name
Test status
Simulation time 689322354 ps
CPU time 9.77 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 214412 kb
Host smart-ba46d252-3634-463c-9969-66aacc9119dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615358450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.615358450
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1587620447
Short name T235
Test name
Test status
Simulation time 855823880 ps
CPU time 32.24 seconds
Started Feb 18 01:55:09 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 222572 kb
Host smart-e44677f2-fbd1-4640-954f-f17f9686c838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587620447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1587620447
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1048582378
Short name T61
Test name
Test status
Simulation time 6007033676 ps
CPU time 42.24 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:56:00 PM PST 24
Peak memory 217648 kb
Host smart-2d3ee812-ca33-476d-8fc3-75ee0c49cab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048582378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1048582378
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1518822554
Short name T195
Test name
Test status
Simulation time 74322773768 ps
CPU time 270.74 seconds
Started Feb 18 01:54:39 PM PST 24
Finished Feb 18 01:59:12 PM PST 24
Peak memory 220368 kb
Host smart-2349cf01-c9ed-4fba-bcd3-9e830d7fba95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518822554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1518822554
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3817713832
Short name T427
Test name
Test status
Simulation time 1073297057 ps
CPU time 13.65 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 214396 kb
Host smart-b024e8b5-0047-4e27-988d-9b35f9eda421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817713832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3817713832
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3481462600
Short name T276
Test name
Test status
Simulation time 227559975 ps
CPU time 3.31 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:36 PM PST 24
Peak memory 214424 kb
Host smart-45c675f4-6796-4d80-b5ea-4a43d0b402eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481462600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3481462600
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.759626208
Short name T253
Test name
Test status
Simulation time 78048578 ps
CPU time 3.17 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 208184 kb
Host smart-0a615c77-03f9-4f24-bc1e-1449f0dfbc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759626208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.759626208
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1262342716
Short name T270
Test name
Test status
Simulation time 82978581270 ps
CPU time 531.59 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 02:03:27 PM PST 24
Peak memory 220888 kb
Host smart-57bd78d3-d554-4db1-be92-168bb8d0e48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262342716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1262342716
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2531493156
Short name T163
Test name
Test status
Simulation time 1874631064 ps
CPU time 12.76 seconds
Started Feb 18 12:29:41 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 208724 kb
Host smart-d60c21e3-6f86-44fa-867b-9975888ceb55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531493156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2531493156
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2361627585
Short name T85
Test name
Test status
Simulation time 94559057 ps
CPU time 3.8 seconds
Started Feb 18 01:52:42 PM PST 24
Finished Feb 18 01:52:47 PM PST 24
Peak memory 209516 kb
Host smart-c41913e6-9b81-4f20-9f61-4b83284ddf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361627585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2361627585
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1575891717
Short name T179
Test name
Test status
Simulation time 1291964856 ps
CPU time 19.57 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:42 PM PST 24
Peak memory 210876 kb
Host smart-08b8451a-c943-465c-9208-c9ce6d27f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575891717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1575891717
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3651183307
Short name T153
Test name
Test status
Simulation time 1692202844 ps
CPU time 5.83 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 222836 kb
Host smart-a418db12-776d-4205-9bf3-8855743a1275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651183307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3651183307
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3637258057
Short name T150
Test name
Test status
Simulation time 261653144 ps
CPU time 2.08 seconds
Started Feb 18 01:55:03 PM PST 24
Finished Feb 18 01:55:11 PM PST 24
Peak memory 216096 kb
Host smart-bee016fb-1026-4638-a504-c502548a05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637258057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3637258057
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1896810094
Short name T151
Test name
Test status
Simulation time 168826335 ps
CPU time 5.73 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 217064 kb
Host smart-08b3b3a3-9053-45a1-9320-cd2777e43766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896810094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1896810094
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2011418092
Short name T141
Test name
Test status
Simulation time 177635320 ps
CPU time 3.76 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 214416 kb
Host smart-44843ecd-58d1-434f-8de4-1b77381b507c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011418092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2011418092
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1688172180
Short name T196
Test name
Test status
Simulation time 129375777 ps
CPU time 6.28 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:54:59 PM PST 24
Peak memory 222504 kb
Host smart-39cf3008-e83c-49ed-b6de-8860ea857e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688172180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1688172180
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2103273022
Short name T350
Test name
Test status
Simulation time 675083013 ps
CPU time 18.41 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:55:11 PM PST 24
Peak memory 222648 kb
Host smart-45c8d27a-0484-44fc-a8e9-3dcda17bd841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103273022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2103273022
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.402303896
Short name T1
Test name
Test status
Simulation time 138200675 ps
CPU time 4.89 seconds
Started Feb 18 01:55:17 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 218240 kb
Host smart-9c93f7a3-fc93-464a-9a89-e9d198ace59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402303896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.402303896
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.553747826
Short name T170
Test name
Test status
Simulation time 214774157 ps
CPU time 8.8 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:38 PM PST 24
Peak memory 208560 kb
Host smart-84447a0d-a43e-42b7-aab5-a1aa9b3afb96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553747826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
553747826
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3221639331
Short name T182
Test name
Test status
Simulation time 705449037 ps
CPU time 12.72 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:30:46 PM PST 24
Peak memory 208844 kb
Host smart-db8f6a41-e08e-462a-af4b-2eeb02f562e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221639331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3221639331
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.37167100
Short name T262
Test name
Test status
Simulation time 1202029839 ps
CPU time 30.13 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 216000 kb
Host smart-817a2544-e3f0-491f-b95b-f359e9fd2dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37167100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.37167100
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2348925303
Short name T234
Test name
Test status
Simulation time 627115702 ps
CPU time 24.87 seconds
Started Feb 18 01:54:04 PM PST 24
Finished Feb 18 01:54:33 PM PST 24
Peak memory 217000 kb
Host smart-f52359a1-7da0-4843-ab08-d53f687fc4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348925303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2348925303
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3464488233
Short name T278
Test name
Test status
Simulation time 253476994 ps
CPU time 7.46 seconds
Started Feb 18 01:54:05 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 210764 kb
Host smart-f0997513-3524-47d3-b9d4-ee8293c633b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464488233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3464488233
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1683019333
Short name T23
Test name
Test status
Simulation time 972627844 ps
CPU time 5.38 seconds
Started Feb 18 01:53:58 PM PST 24
Finished Feb 18 01:54:06 PM PST 24
Peak memory 222840 kb
Host smart-2f3bb71d-2d35-4129-99cf-e35bf5876fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683019333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1683019333
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3536576279
Short name T152
Test name
Test status
Simulation time 258314290 ps
CPU time 9.22 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:23 PM PST 24
Peak memory 218144 kb
Host smart-f293cdba-d23d-468d-be99-43e55bff83a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536576279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3536576279
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1757765811
Short name T32
Test name
Test status
Simulation time 143103380 ps
CPU time 6.21 seconds
Started Feb 18 01:52:25 PM PST 24
Finished Feb 18 01:52:32 PM PST 24
Peak memory 221804 kb
Host smart-21fa3113-abf1-4d7e-9a9c-2f07c75f5e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757765811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1757765811
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3553379157
Short name T259
Test name
Test status
Simulation time 278111257 ps
CPU time 5.68 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:36 PM PST 24
Peak memory 214428 kb
Host smart-c4035643-501b-4ac9-9570-c7adbe44821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553379157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3553379157
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4057683484
Short name T192
Test name
Test status
Simulation time 1161073553 ps
CPU time 41.83 seconds
Started Feb 18 01:53:50 PM PST 24
Finished Feb 18 01:54:33 PM PST 24
Peak memory 221368 kb
Host smart-69af6bac-70a3-4812-b794-5677e2ef337d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057683484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4057683484
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1226213445
Short name T271
Test name
Test status
Simulation time 538304271 ps
CPU time 7.98 seconds
Started Feb 18 01:52:36 PM PST 24
Finished Feb 18 01:52:45 PM PST 24
Peak memory 214252 kb
Host smart-52da6148-b7cf-4fed-a05a-2f952563482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226213445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1226213445
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3498741502
Short name T346
Test name
Test status
Simulation time 67684270 ps
CPU time 4.73 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:50 PM PST 24
Peak memory 222556 kb
Host smart-a21a7aa3-ed8f-4535-85f0-814e01f9f753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498741502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3498741502
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1198880187
Short name T140
Test name
Test status
Simulation time 650642701 ps
CPU time 8.57 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:55:14 PM PST 24
Peak memory 215344 kb
Host smart-cb212bb9-b3c0-4de8-9f8d-756711af7ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198880187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1198880187
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1835372224
Short name T610
Test name
Test status
Simulation time 44028905 ps
CPU time 1.96 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:08 PM PST 24
Peak memory 207404 kb
Host smart-197721e0-337c-459b-adbe-826db72050c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835372224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1835372224
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1785762979
Short name T362
Test name
Test status
Simulation time 2840122236 ps
CPU time 14.18 seconds
Started Feb 18 01:53:05 PM PST 24
Finished Feb 18 01:53:20 PM PST 24
Peak memory 215064 kb
Host smart-0f2898ba-fa26-4ba3-876f-5110294342c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785762979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1785762979
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1872687013
Short name T162
Test name
Test status
Simulation time 379692204 ps
CPU time 5.37 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:19 PM PST 24
Peak memory 208548 kb
Host smart-c0cd65ba-562b-488a-bb15-65aa5dd1ce04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872687013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1872687013
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1555122370
Short name T174
Test name
Test status
Simulation time 395364927 ps
CPU time 5.47 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 208952 kb
Host smart-5f8af7c4-aad5-4c4d-b5d3-daadcdf42006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555122370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1555122370
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4155533252
Short name T183
Test name
Test status
Simulation time 268690986 ps
CPU time 9.1 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 208816 kb
Host smart-b02fa5fa-a290-4a2b-b48f-61fc588c6d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155533252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4155533252
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2772900285
Short name T176
Test name
Test status
Simulation time 352046581 ps
CPU time 5.06 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:50 PM PST 24
Peak memory 208276 kb
Host smart-d722624c-87c1-486f-acd1-c6bff64a8b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772900285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2772900285
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1036687037
Short name T455
Test name
Test status
Simulation time 33919460 ps
CPU time 1.47 seconds
Started Feb 18 01:52:23 PM PST 24
Finished Feb 18 01:52:26 PM PST 24
Peak memory 209720 kb
Host smart-f17ea15f-f74b-4f2e-a0dd-0a9abf65fdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036687037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1036687037
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.569169299
Short name T248
Test name
Test status
Simulation time 114400848 ps
CPU time 2.58 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 214492 kb
Host smart-39f4fef0-afea-4054-bdcc-5528f9d168a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569169299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.569169299
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_random.1938662553
Short name T268
Test name
Test status
Simulation time 63794718 ps
CPU time 4.2 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:33 PM PST 24
Peak memory 207964 kb
Host smart-e4678818-6a32-48b2-b72d-b814db58e23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938662553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1938662553
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1219519424
Short name T364
Test name
Test status
Simulation time 793244516 ps
CPU time 13.96 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 208508 kb
Host smart-ecdf1a35-35cc-4516-9a8e-b7ee516c4022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219519424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1219519424
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1888317059
Short name T824
Test name
Test status
Simulation time 5634120704 ps
CPU time 40.28 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:54:12 PM PST 24
Peak memory 214436 kb
Host smart-091fc501-3d3b-4882-9756-4ba3a4b3e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888317059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1888317059
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.405313882
Short name T330
Test name
Test status
Simulation time 608914838 ps
CPU time 4.52 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:42 PM PST 24
Peak memory 208688 kb
Host smart-4d4a2f57-ea84-4ff0-9eb3-97bb74244002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405313882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.405313882
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3822097804
Short name T341
Test name
Test status
Simulation time 614852237 ps
CPU time 16.66 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 214420 kb
Host smart-adefd3d1-3590-4baa-89c6-bbf9fb0592d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822097804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3822097804
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.32269482
Short name T338
Test name
Test status
Simulation time 535820179 ps
CPU time 9.78 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:53:51 PM PST 24
Peak memory 207492 kb
Host smart-80304764-9476-4b13-b3fc-f4c4ba4b2e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32269482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.32269482
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1330639749
Short name T241
Test name
Test status
Simulation time 607691466 ps
CPU time 17.12 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 214412 kb
Host smart-3a482c78-a1c4-46b4-bd9f-9050ae23c213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330639749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1330639749
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.809873023
Short name T227
Test name
Test status
Simulation time 314125596 ps
CPU time 2.67 seconds
Started Feb 18 01:53:43 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 215236 kb
Host smart-e81b01e2-ab55-43f9-bcee-5aa3815428b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809873023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.809873023
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2713335
Short name T110
Test name
Test status
Simulation time 147132551 ps
CPU time 10.85 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:42 PM PST 24
Peak memory 222732 kb
Host smart-be07e287-7183-446a-ab30-27fbc0f8dd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713335 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2713335
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2502166785
Short name T387
Test name
Test status
Simulation time 118699803 ps
CPU time 5.28 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 209448 kb
Host smart-48ac10d9-97fc-4c7e-9db0-186c8a404d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502166785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2502166785
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2918272210
Short name T273
Test name
Test status
Simulation time 302988697 ps
CPU time 11.67 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:11 PM PST 24
Peak memory 210808 kb
Host smart-df355293-798c-49c8-8bde-02b58e5ae9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918272210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2918272210
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1715335348
Short name T71
Test name
Test status
Simulation time 1154989780 ps
CPU time 23.54 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:41 PM PST 24
Peak memory 222544 kb
Host smart-aa0d1017-22a3-46c5-85ad-e8a7a7d25ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715335348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1715335348
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1960603639
Short name T323
Test name
Test status
Simulation time 59686784 ps
CPU time 2.46 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 206788 kb
Host smart-627f196e-18ca-4844-856e-abf83031f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960603639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1960603639
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.173718247
Short name T139
Test name
Test status
Simulation time 158463374 ps
CPU time 3.12 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 215304 kb
Host smart-01d3b793-98a1-452d-9d59-c49ccd5e365e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173718247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.173718247
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1070782858
Short name T358
Test name
Test status
Simulation time 160861185 ps
CPU time 6.48 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 222460 kb
Host smart-d9fb1277-645b-485e-b4ee-cf39228fb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070782858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1070782858
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.228188023
Short name T226
Test name
Test status
Simulation time 46693731 ps
CPU time 3.33 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 220488 kb
Host smart-5c7eb89c-622b-40e3-9836-99c89ce30bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228188023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.228188023
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1314190058
Short name T223
Test name
Test status
Simulation time 764361401 ps
CPU time 3.78 seconds
Started Feb 18 01:55:11 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 221712 kb
Host smart-46815b82-fcf3-4eac-805e-314ed3320f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314190058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1314190058
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.310809809
Short name T35
Test name
Test status
Simulation time 138789600 ps
CPU time 3.36 seconds
Started Feb 18 01:53:18 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 210852 kb
Host smart-17e3c3af-ccb2-4a6f-b8ef-ff67e9753e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310809809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.310809809
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3394527812
Short name T991
Test name
Test status
Simulation time 744083460 ps
CPU time 13.16 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 205160 kb
Host smart-47ed42c2-634e-4287-9360-42c3813a6baa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394527812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
394527812
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2710334187
Short name T188
Test name
Test status
Simulation time 5145221233 ps
CPU time 18.37 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:30:08 PM PST 24
Peak memory 205188 kb
Host smart-bfa5b257-0106-4938-b59b-2d365ec338b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710334187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
710334187
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3036884913
Short name T964
Test name
Test status
Simulation time 206983502 ps
CPU time 1.43 seconds
Started Feb 18 12:29:39 PM PST 24
Finished Feb 18 12:29:41 PM PST 24
Peak memory 205180 kb
Host smart-ff76d7fa-c907-4b35-bc82-9aeab4d55721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036884913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
036884913
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4043982909
Short name T1045
Test name
Test status
Simulation time 30474721 ps
CPU time 1.96 seconds
Started Feb 18 12:29:34 PM PST 24
Finished Feb 18 12:29:43 PM PST 24
Peak memory 213476 kb
Host smart-ecab14a2-c872-4bff-bc53-d865ab237483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043982909 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4043982909
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.182703310
Short name T973
Test name
Test status
Simulation time 79311561 ps
CPU time 1.13 seconds
Started Feb 18 12:29:25 PM PST 24
Finished Feb 18 12:29:26 PM PST 24
Peak memory 205060 kb
Host smart-906fcc71-ae6d-41d5-9a5f-db08cb2baca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182703310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.182703310
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3259382511
Short name T1043
Test name
Test status
Simulation time 127918167 ps
CPU time 0.73 seconds
Started Feb 18 12:29:42 PM PST 24
Finished Feb 18 12:29:44 PM PST 24
Peak memory 204928 kb
Host smart-4104ef59-ab5b-4f7b-bd99-9438df4ea692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259382511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3259382511
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4103216511
Short name T142
Test name
Test status
Simulation time 1281909432 ps
CPU time 3.22 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 205192 kb
Host smart-b189aa57-08a1-4d7c-9323-34b7233a14b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103216511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4103216511
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3921866039
Short name T954
Test name
Test status
Simulation time 372625543 ps
CPU time 3.54 seconds
Started Feb 18 12:29:45 PM PST 24
Finished Feb 18 12:29:51 PM PST 24
Peak memory 221728 kb
Host smart-afd7bed0-47fa-4b28-87a2-3e2a97aa01db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921866039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3921866039
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3837486848
Short name T1031
Test name
Test status
Simulation time 1746478409 ps
CPU time 10.75 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:30:02 PM PST 24
Peak memory 219336 kb
Host smart-6fc6e0d4-600f-47e8-90db-a1f667568e9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837486848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3837486848
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3323405644
Short name T955
Test name
Test status
Simulation time 21507421 ps
CPU time 1.7 seconds
Started Feb 18 12:29:49 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 214268 kb
Host smart-cf0911d9-1186-4d3f-a101-cbae1d6e7887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323405644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3323405644
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3993206292
Short name T1006
Test name
Test status
Simulation time 368362636 ps
CPU time 10.08 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 205136 kb
Host smart-10ce9403-0511-4123-8ffe-168d4cf69649
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993206292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
993206292
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3013517043
Short name T957
Test name
Test status
Simulation time 3911826026 ps
CPU time 25.98 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 205216 kb
Host smart-0b733ed4-5a23-4109-9dcd-a85828af5471
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013517043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
013517043
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1961464811
Short name T972
Test name
Test status
Simulation time 49041216 ps
CPU time 0.91 seconds
Started Feb 18 12:29:27 PM PST 24
Finished Feb 18 12:29:34 PM PST 24
Peak memory 205000 kb
Host smart-e94af3af-f5ea-4c5f-baf2-d68422f3be0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961464811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
961464811
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2424364393
Short name T1007
Test name
Test status
Simulation time 129328889 ps
CPU time 2.25 seconds
Started Feb 18 12:29:33 PM PST 24
Finished Feb 18 12:29:38 PM PST 24
Peak memory 212632 kb
Host smart-7c1f42c6-a752-45cc-8872-26425eec1846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424364393 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2424364393
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3881847421
Short name T971
Test name
Test status
Simulation time 94730665 ps
CPU time 0.9 seconds
Started Feb 18 12:29:46 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 204936 kb
Host smart-a5006b88-25b5-4fa3-8972-78393d9a16c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881847421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3881847421
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3010337778
Short name T1022
Test name
Test status
Simulation time 41433543 ps
CPU time 0.69 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 204964 kb
Host smart-15de2c77-3701-4a20-8662-8a11842374b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010337778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3010337778
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.216062436
Short name T985
Test name
Test status
Simulation time 160495533 ps
CPU time 1.42 seconds
Started Feb 18 12:29:40 PM PST 24
Finished Feb 18 12:29:43 PM PST 24
Peak memory 205240 kb
Host smart-39ae37e7-cb10-4d18-85d4-714bcfadedfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216062436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.216062436
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2965087429
Short name T120
Test name
Test status
Simulation time 151662111 ps
CPU time 2.28 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 213436 kb
Host smart-441a716f-71de-46c3-8f43-9707f141066f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965087429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2965087429
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3710222809
Short name T981
Test name
Test status
Simulation time 139124911 ps
CPU time 3.73 seconds
Started Feb 18 12:29:45 PM PST 24
Finished Feb 18 12:29:51 PM PST 24
Peak memory 219128 kb
Host smart-0877aefb-1f28-4620-84ac-c96535e540aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710222809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3710222809
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3102067343
Short name T933
Test name
Test status
Simulation time 68940343 ps
CPU time 1.94 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 213404 kb
Host smart-f09e2180-0d40-480f-814e-23b509c17fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102067343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3102067343
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.381252543
Short name T948
Test name
Test status
Simulation time 33033989 ps
CPU time 2.14 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:20 PM PST 24
Peak memory 213532 kb
Host smart-24953881-2997-4aff-955b-e41af94d93fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381252543 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.381252543
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.519602676
Short name T148
Test name
Test status
Simulation time 19157552 ps
CPU time 0.95 seconds
Started Feb 18 12:30:06 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 204920 kb
Host smart-fc63d060-5f9a-4aed-ab0d-3e20a17f281f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519602676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.519602676
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2368870555
Short name T1025
Test name
Test status
Simulation time 151678388 ps
CPU time 0.75 seconds
Started Feb 18 12:29:58 PM PST 24
Finished Feb 18 12:30:08 PM PST 24
Peak memory 204900 kb
Host smart-3b1d32f7-ba49-4500-a2ae-ebc07062a7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368870555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2368870555
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2154704848
Short name T949
Test name
Test status
Simulation time 131864745 ps
CPU time 1.92 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:30:38 PM PST 24
Peak memory 205228 kb
Host smart-cc97cf62-3e38-4793-9e67-313d30ce5fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154704848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2154704848
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1218765392
Short name T940
Test name
Test status
Simulation time 74421930 ps
CPU time 1.85 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:47 PM PST 24
Peak memory 213552 kb
Host smart-f7e64971-6354-41be-ab1b-39987e6f87d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218765392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1218765392
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3795551251
Short name T930
Test name
Test status
Simulation time 323649396 ps
CPU time 5.55 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:30:06 PM PST 24
Peak memory 213680 kb
Host smart-002b2531-b13a-498a-b34b-e26a48d5626a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795551251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3795551251
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3844489781
Short name T187
Test name
Test status
Simulation time 340657542 ps
CPU time 4.66 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:51 PM PST 24
Peak memory 215364 kb
Host smart-14ec01b6-1e5b-470e-a626-f1383dfd17b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844489781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3844489781
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1983308782
Short name T923
Test name
Test status
Simulation time 253381025 ps
CPU time 3.3 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 213596 kb
Host smart-c713306d-a896-4bef-96d8-607420411945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983308782 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1983308782
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2987670176
Short name T942
Test name
Test status
Simulation time 97647541 ps
CPU time 0.98 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 205152 kb
Host smart-0cd0b1b8-ca26-484d-bb62-1d95fa697c0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987670176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2987670176
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3545216850
Short name T1010
Test name
Test status
Simulation time 12518072 ps
CPU time 0.72 seconds
Started Feb 18 12:29:42 PM PST 24
Finished Feb 18 12:29:44 PM PST 24
Peak memory 205016 kb
Host smart-0b748be5-3aa9-4860-8c6e-e35b0452ab6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545216850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3545216850
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1344890197
Short name T1012
Test name
Test status
Simulation time 35322332 ps
CPU time 1.37 seconds
Started Feb 18 12:29:36 PM PST 24
Finished Feb 18 12:29:39 PM PST 24
Peak memory 205192 kb
Host smart-bfed83f8-40bf-4d61-a6cf-cd29fc750c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344890197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1344890197
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1284847450
Short name T115
Test name
Test status
Simulation time 206423058 ps
CPU time 3.13 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 213596 kb
Host smart-3b0b7495-5662-46f0-812c-0e4e45a66083
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284847450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1284847450
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1779585030
Short name T990
Test name
Test status
Simulation time 285107008 ps
CPU time 6.98 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:30:02 PM PST 24
Peak memory 213672 kb
Host smart-42ce5051-f82e-4224-81e9-07dc1cc96383
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779585030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1779585030
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2539625433
Short name T932
Test name
Test status
Simulation time 336146330 ps
CPU time 1.97 seconds
Started Feb 18 12:29:40 PM PST 24
Finished Feb 18 12:29:44 PM PST 24
Peak memory 214292 kb
Host smart-0364e89c-4d3c-4301-9cf9-c22f41ea6dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539625433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2539625433
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1362757046
Short name T165
Test name
Test status
Simulation time 333298304 ps
CPU time 3.9 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 208760 kb
Host smart-8a75fb61-ffc5-4fd6-a2a7-311c5a62895e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362757046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1362757046
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.635282798
Short name T1040
Test name
Test status
Simulation time 275873420 ps
CPU time 5.11 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 213496 kb
Host smart-94df944d-49fd-465b-8c94-06312537d59d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635282798 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.635282798
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.535763718
Short name T977
Test name
Test status
Simulation time 16869893 ps
CPU time 1.14 seconds
Started Feb 18 12:30:13 PM PST 24
Finished Feb 18 12:30:22 PM PST 24
Peak memory 205168 kb
Host smart-a75e961b-a1d8-457c-b84c-2d2b9d58d20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535763718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.535763718
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.631707891
Short name T1041
Test name
Test status
Simulation time 41159475 ps
CPU time 0.83 seconds
Started Feb 18 12:30:18 PM PST 24
Finished Feb 18 12:30:25 PM PST 24
Peak memory 205016 kb
Host smart-aef17b0d-0ff6-4211-8b76-c67f7b91c9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631707891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.631707891
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1530749753
Short name T1029
Test name
Test status
Simulation time 129457916 ps
CPU time 2.35 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:06 PM PST 24
Peak memory 205324 kb
Host smart-ee2a4e29-56d3-466e-8dc0-5bf53d95ea82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530749753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1530749753
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3632929978
Short name T919
Test name
Test status
Simulation time 116183977 ps
CPU time 2.43 seconds
Started Feb 18 12:29:35 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 213404 kb
Host smart-6f0ee13a-553f-44dc-9388-9c72da4a0b02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632929978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3632929978
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4226312963
Short name T1019
Test name
Test status
Simulation time 78306766 ps
CPU time 4.55 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:06 PM PST 24
Peak memory 213600 kb
Host smart-bd08f0fc-5c22-40d5-9094-a7b0091d28f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226312963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4226312963
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.98083333
Short name T969
Test name
Test status
Simulation time 186960237 ps
CPU time 1.65 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213108 kb
Host smart-a58972e5-434a-48d4-a646-2797e9cf09fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98083333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.98083333
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.756365778
Short name T1024
Test name
Test status
Simulation time 93788524 ps
CPU time 3.37 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:22 PM PST 24
Peak memory 213520 kb
Host smart-51b88056-1d17-4269-956f-66dfae99cd9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756365778 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.756365778
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.657208645
Short name T996
Test name
Test status
Simulation time 42464851 ps
CPU time 1.03 seconds
Started Feb 18 12:30:03 PM PST 24
Finished Feb 18 12:30:14 PM PST 24
Peak memory 205020 kb
Host smart-9aff3b93-abfb-47d0-ab2e-967c05237cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657208645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.657208645
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1721797811
Short name T1035
Test name
Test status
Simulation time 67680805 ps
CPU time 0.75 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 205008 kb
Host smart-de03f9c2-f013-475b-8370-b0bb93f45bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721797811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1721797811
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4126434064
Short name T1011
Test name
Test status
Simulation time 42199581 ps
CPU time 2.14 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:54 PM PST 24
Peak memory 205212 kb
Host smart-80b6fd84-4d74-4a5e-b549-6472599d9738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126434064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4126434064
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1483984618
Short name T997
Test name
Test status
Simulation time 269172491 ps
CPU time 7.52 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 213676 kb
Host smart-ee800809-be1d-4fc8-b8f0-aacdc42fc7ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483984618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1483984618
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3276071117
Short name T1009
Test name
Test status
Simulation time 406861629 ps
CPU time 13.47 seconds
Started Feb 18 12:29:57 PM PST 24
Finished Feb 18 12:30:20 PM PST 24
Peak memory 213680 kb
Host smart-0b6e2623-a86a-44f6-8786-43e90cf5d84a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276071117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3276071117
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.222722206
Short name T1054
Test name
Test status
Simulation time 746090173 ps
CPU time 3.48 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 215508 kb
Host smart-6cee063c-32bc-44fe-ad77-add653b51379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222722206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.222722206
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1292348666
Short name T929
Test name
Test status
Simulation time 165519252 ps
CPU time 6.11 seconds
Started Feb 18 12:30:31 PM PST 24
Finished Feb 18 12:30:46 PM PST 24
Peak memory 213520 kb
Host smart-516e9e4a-05c7-4891-8fe9-9e8c503feb8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292348666 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1292348666
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2216276560
Short name T144
Test name
Test status
Simulation time 9585466 ps
CPU time 0.89 seconds
Started Feb 18 12:29:32 PM PST 24
Finished Feb 18 12:29:34 PM PST 24
Peak memory 205056 kb
Host smart-bf343c69-7b7d-4743-a8b8-82d0ee8589f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216276560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2216276560
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2955707998
Short name T918
Test name
Test status
Simulation time 18984206 ps
CPU time 0.83 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:54 PM PST 24
Peak memory 204872 kb
Host smart-8c1614ad-2ed5-432f-8566-0a8c8e6b3afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955707998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2955707998
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1169450844
Short name T928
Test name
Test status
Simulation time 325768981 ps
CPU time 1.77 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 205216 kb
Host smart-9e18b72d-9786-4fd4-a0b2-44349347a85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169450844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1169450844
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3478218571
Short name T920
Test name
Test status
Simulation time 720013726 ps
CPU time 3.46 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 213624 kb
Host smart-42604302-09a2-421d-89c9-474072e74dc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478218571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3478218571
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3653742386
Short name T114
Test name
Test status
Simulation time 704220528 ps
CPU time 4.93 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:54 PM PST 24
Peak memory 219592 kb
Host smart-32f7e04b-142f-46f5-af10-8361127764ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653742386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3653742386
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3424442496
Short name T983
Test name
Test status
Simulation time 202909126 ps
CPU time 2.83 seconds
Started Feb 18 12:30:03 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 215964 kb
Host smart-03be80bf-7957-4694-aa23-1a79acd11c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424442496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3424442496
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3634567470
Short name T935
Test name
Test status
Simulation time 1615871859 ps
CPU time 9.61 seconds
Started Feb 18 12:30:18 PM PST 24
Finished Feb 18 12:30:34 PM PST 24
Peak memory 208636 kb
Host smart-6b39937c-ebb2-4b72-9e63-4503f9ab52ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634567470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3634567470
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.729849130
Short name T922
Test name
Test status
Simulation time 53241218 ps
CPU time 2.67 seconds
Started Feb 18 12:29:59 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 213476 kb
Host smart-8c85e529-e89b-473c-bef0-6f1e4bb9cee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729849130 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.729849130
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3602357780
Short name T926
Test name
Test status
Simulation time 26666060 ps
CPU time 1.21 seconds
Started Feb 18 12:30:00 PM PST 24
Finished Feb 18 12:30:10 PM PST 24
Peak memory 205092 kb
Host smart-a0541b53-7a64-4503-9122-bca124b2739a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602357780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3602357780
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4156060871
Short name T937
Test name
Test status
Simulation time 12190326 ps
CPU time 0.89 seconds
Started Feb 18 12:30:03 PM PST 24
Finished Feb 18 12:30:13 PM PST 24
Peak memory 205084 kb
Host smart-e140381b-dfa0-48b5-bd8d-74ca48fa874e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156060871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4156060871
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3834242720
Short name T963
Test name
Test status
Simulation time 120426977 ps
CPU time 4.07 seconds
Started Feb 18 12:29:49 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 205208 kb
Host smart-5896b227-e2d4-4888-ad04-2a16c56bd0d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834242720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3834242720
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.111184973
Short name T965
Test name
Test status
Simulation time 1940816170 ps
CPU time 11.26 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:30:00 PM PST 24
Peak memory 213644 kb
Host smart-251cfb7b-2c7b-4ffb-937f-3588ff4fee7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111184973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.111184973
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1085146740
Short name T1046
Test name
Test status
Simulation time 162232578 ps
CPU time 8.55 seconds
Started Feb 18 12:30:08 PM PST 24
Finished Feb 18 12:30:26 PM PST 24
Peak memory 213580 kb
Host smart-823f46ce-9d37-43e7-9332-7d0d1ff6dffd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085146740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1085146740
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.793959947
Short name T1030
Test name
Test status
Simulation time 254292211 ps
CPU time 3.16 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213460 kb
Host smart-e4631257-ed95-4a25-bc9e-e7fb436b987b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793959947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.793959947
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2047108649
Short name T172
Test name
Test status
Simulation time 793001442 ps
CPU time 8.39 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 208620 kb
Host smart-3909e2c5-6ef6-4f70-9747-bf5dd19283a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047108649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2047108649
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1490241639
Short name T938
Test name
Test status
Simulation time 237104734 ps
CPU time 3.93 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 213416 kb
Host smart-34d95148-1db4-42fe-8c71-1aadddcaa92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490241639 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1490241639
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3123242456
Short name T1013
Test name
Test status
Simulation time 57793425 ps
CPU time 1.22 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 205148 kb
Host smart-a74ef5a8-e595-42fa-83c0-e2979239c0f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123242456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3123242456
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3147630095
Short name T906
Test name
Test status
Simulation time 13169646 ps
CPU time 0.78 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:54 PM PST 24
Peak memory 205004 kb
Host smart-65999973-c999-47cc-b432-9fb7c130aadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147630095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3147630095
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3266682791
Short name T960
Test name
Test status
Simulation time 34607775 ps
CPU time 2.38 seconds
Started Feb 18 12:30:03 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 205168 kb
Host smart-404a7c6b-b19a-4a34-9295-0d5fd3b62803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266682791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3266682791
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.781244186
Short name T1003
Test name
Test status
Simulation time 333655634 ps
CPU time 3.13 seconds
Started Feb 18 12:29:53 PM PST 24
Finished Feb 18 12:30:01 PM PST 24
Peak memory 213656 kb
Host smart-f542654a-352c-42c5-af1d-0222a4ada099
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781244186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.781244186
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2076868908
Short name T1037
Test name
Test status
Simulation time 503277393 ps
CPU time 2.54 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:30:00 PM PST 24
Peak memory 216448 kb
Host smart-5374bd04-6466-443d-93db-dcffd4ffe992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076868908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2076868908
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3691489052
Short name T164
Test name
Test status
Simulation time 4276373876 ps
CPU time 15.93 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:30:10 PM PST 24
Peak memory 208672 kb
Host smart-b0bd60ef-c180-43eb-9926-2d26c9040c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691489052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3691489052
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3257811415
Short name T976
Test name
Test status
Simulation time 80486522 ps
CPU time 2.03 seconds
Started Feb 18 12:30:07 PM PST 24
Finished Feb 18 12:30:18 PM PST 24
Peak memory 217900 kb
Host smart-3a9bd839-6eb6-4479-aeef-de3c6f948c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257811415 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3257811415
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2101553372
Short name T992
Test name
Test status
Simulation time 71972382 ps
CPU time 0.96 seconds
Started Feb 18 12:30:03 PM PST 24
Finished Feb 18 12:30:14 PM PST 24
Peak memory 205100 kb
Host smart-811948f5-3cfe-40c7-9ea9-7f17942077ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101553372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2101553372
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.303318789
Short name T993
Test name
Test status
Simulation time 14240691 ps
CPU time 0.79 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:30:37 PM PST 24
Peak memory 204928 kb
Host smart-00599eed-f68f-43f1-8b23-7d5e4336e3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303318789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.303318789
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3736232401
Short name T200
Test name
Test status
Simulation time 56202972 ps
CPU time 2.49 seconds
Started Feb 18 12:29:49 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 205188 kb
Host smart-b22a669a-04d8-4f5f-92d0-2a7f5ad30c85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736232401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3736232401
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1026342836
Short name T1056
Test name
Test status
Simulation time 1193561807 ps
CPU time 6.85 seconds
Started Feb 18 12:30:11 PM PST 24
Finished Feb 18 12:30:27 PM PST 24
Peak memory 213684 kb
Host smart-344cb2c6-764d-4e2d-8bb4-169bda616e2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026342836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1026342836
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3318083029
Short name T944
Test name
Test status
Simulation time 575893622 ps
CPU time 6.46 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 219972 kb
Host smart-955e337f-65ab-450e-bda7-849489e4c868
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318083029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3318083029
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2462434082
Short name T136
Test name
Test status
Simulation time 165047801 ps
CPU time 1.85 seconds
Started Feb 18 12:29:57 PM PST 24
Finished Feb 18 12:30:08 PM PST 24
Peak memory 213376 kb
Host smart-f7b229bf-63a3-4f72-9470-067d62ed9b51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462434082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2462434082
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.430543704
Short name T980
Test name
Test status
Simulation time 143052941 ps
CPU time 3.44 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:06 PM PST 24
Peak memory 213380 kb
Host smart-c48e489d-7324-4557-8cdb-f37339df1ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430543704 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.430543704
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1479482374
Short name T951
Test name
Test status
Simulation time 86008983 ps
CPU time 1.07 seconds
Started Feb 18 12:30:01 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 205200 kb
Host smart-d3def5c3-9416-4cab-84f6-0d9088672a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479482374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1479482374
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.809015095
Short name T979
Test name
Test status
Simulation time 34416022 ps
CPU time 0.7 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 204896 kb
Host smart-8f354441-9df0-42ed-aab7-8cf266d856ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809015095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.809015095
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2406461300
Short name T190
Test name
Test status
Simulation time 486842167 ps
CPU time 2.64 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:47 PM PST 24
Peak memory 205300 kb
Host smart-b32126b6-4c3b-43c5-8b3a-868c13589287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406461300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2406461300
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3357039488
Short name T1050
Test name
Test status
Simulation time 109416596 ps
CPU time 1.98 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:30:41 PM PST 24
Peak memory 220684 kb
Host smart-a22dc81b-5443-4d30-bc22-2cfb8a25acb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357039488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3357039488
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2769324393
Short name T961
Test name
Test status
Simulation time 1043284949 ps
CPU time 3.95 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:30:43 PM PST 24
Peak memory 213548 kb
Host smart-6695c759-23b0-42a6-9ea2-ae536396944d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769324393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2769324393
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.201308750
Short name T1027
Test name
Test status
Simulation time 26963853 ps
CPU time 1.84 seconds
Started Feb 18 12:29:57 PM PST 24
Finished Feb 18 12:30:09 PM PST 24
Peak memory 213472 kb
Host smart-cbd7d603-1cbf-4e62-a00c-ff930728176a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201308750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.201308750
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2024863604
Short name T936
Test name
Test status
Simulation time 850954100 ps
CPU time 6.91 seconds
Started Feb 18 12:29:42 PM PST 24
Finished Feb 18 12:29:50 PM PST 24
Peak memory 213380 kb
Host smart-eedece7e-a159-492f-bc1d-047f5703ebea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024863604 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2024863604
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.522557198
Short name T914
Test name
Test status
Simulation time 25941916 ps
CPU time 1.17 seconds
Started Feb 18 12:30:07 PM PST 24
Finished Feb 18 12:30:17 PM PST 24
Peak memory 205132 kb
Host smart-ef3fcec1-d7ad-42bd-bab9-3094b54fb3e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522557198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.522557198
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1321843261
Short name T988
Test name
Test status
Simulation time 11406663 ps
CPU time 0.82 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 205020 kb
Host smart-908fa611-0b48-473f-a973-62513c5c4bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321843261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1321843261
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3576027013
Short name T968
Test name
Test status
Simulation time 185019694 ps
CPU time 3.65 seconds
Started Feb 18 12:29:49 PM PST 24
Finished Feb 18 12:29:54 PM PST 24
Peak memory 205204 kb
Host smart-32e2f581-8171-4bd0-a509-b5fe7d5dcdad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576027013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3576027013
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1211948239
Short name T113
Test name
Test status
Simulation time 661247421 ps
CPU time 2.88 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:48 PM PST 24
Peak memory 213572 kb
Host smart-b4f09082-879a-443a-b97a-d14b15ad19a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211948239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1211948239
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.486543912
Short name T1042
Test name
Test status
Simulation time 399036472 ps
CPU time 9.11 seconds
Started Feb 18 12:30:12 PM PST 24
Finished Feb 18 12:30:30 PM PST 24
Peak memory 213600 kb
Host smart-94197fe5-550f-4464-8bc9-14524cd01319
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486543912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.486543912
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1922664005
Short name T1034
Test name
Test status
Simulation time 112931504 ps
CPU time 1.85 seconds
Started Feb 18 12:30:05 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 213340 kb
Host smart-ccc76d1e-f9e6-4db2-92d2-eb236effe46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922664005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1922664005
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3242071103
Short name T404
Test name
Test status
Simulation time 290866340 ps
CPU time 5.62 seconds
Started Feb 18 12:30:14 PM PST 24
Finished Feb 18 12:30:27 PM PST 24
Peak memory 208244 kb
Host smart-58133535-4457-4bf3-b932-fa0d03029eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242071103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3242071103
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4174504558
Short name T1038
Test name
Test status
Simulation time 269195848 ps
CPU time 4.88 seconds
Started Feb 18 12:29:41 PM PST 24
Finished Feb 18 12:29:47 PM PST 24
Peak memory 205140 kb
Host smart-880b2837-aab6-4e2d-b9ad-caee9f1cedbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174504558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
174504558
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2991595902
Short name T959
Test name
Test status
Simulation time 1309871977 ps
CPU time 14.25 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:37 PM PST 24
Peak memory 205168 kb
Host smart-c761946e-96ad-4426-862d-28eee8d5e533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991595902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
991595902
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1515173738
Short name T186
Test name
Test status
Simulation time 36252828 ps
CPU time 1.32 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 205156 kb
Host smart-79c9be89-4461-430f-9e05-ed931e998304
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515173738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
515173738
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2955085464
Short name T987
Test name
Test status
Simulation time 104638545 ps
CPU time 4.07 seconds
Started Feb 18 12:32:20 PM PST 24
Finished Feb 18 12:32:26 PM PST 24
Peak memory 219256 kb
Host smart-924ff483-86f2-46fa-9ac0-3ba9ec3f2f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955085464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2955085464
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3215899905
Short name T1036
Test name
Test status
Simulation time 191885298 ps
CPU time 0.85 seconds
Started Feb 18 12:29:33 PM PST 24
Finished Feb 18 12:29:35 PM PST 24
Peak memory 205092 kb
Host smart-1e327170-b701-44c5-8e88-6e7363111243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215899905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3215899905
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2270291890
Short name T902
Test name
Test status
Simulation time 8316154 ps
CPU time 0.84 seconds
Started Feb 18 12:29:35 PM PST 24
Finished Feb 18 12:29:38 PM PST 24
Peak memory 204988 kb
Host smart-1920d7f8-64a2-40f4-927b-201a4e8f840f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270291890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2270291890
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1179563538
Short name T1002
Test name
Test status
Simulation time 219902888 ps
CPU time 3.79 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 205180 kb
Host smart-b5742470-d17b-476e-ad04-ef609d7b99b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179563538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1179563538
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1228148259
Short name T962
Test name
Test status
Simulation time 1384829419 ps
CPU time 5.82 seconds
Started Feb 18 12:29:57 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 213676 kb
Host smart-5e0c9d6b-7da6-4a3b-958c-5cd163f3b667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228148259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1228148259
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3082503149
Short name T950
Test name
Test status
Simulation time 151615106 ps
CPU time 4.74 seconds
Started Feb 18 12:29:29 PM PST 24
Finished Feb 18 12:29:35 PM PST 24
Peak memory 213584 kb
Host smart-3d90c5e9-7cf7-4bd1-a87d-21f38e0c7591
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082503149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3082503149
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.894113328
Short name T970
Test name
Test status
Simulation time 145395267 ps
CPU time 3.01 seconds
Started Feb 18 12:29:26 PM PST 24
Finished Feb 18 12:29:30 PM PST 24
Peak memory 213404 kb
Host smart-1c232acf-d0c5-46f0-9902-7921747ab9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894113328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.894113328
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.577634272
Short name T168
Test name
Test status
Simulation time 121300765 ps
CPU time 5.23 seconds
Started Feb 18 12:29:36 PM PST 24
Finished Feb 18 12:29:44 PM PST 24
Peak memory 208516 kb
Host smart-acc8deba-8a22-48a3-b56f-e61feb877e43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577634272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
577634272
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3524579797
Short name T958
Test name
Test status
Simulation time 13533627 ps
CPU time 0.68 seconds
Started Feb 18 12:29:56 PM PST 24
Finished Feb 18 12:30:07 PM PST 24
Peak memory 205024 kb
Host smart-c5dbbfa5-2371-43ad-9c7b-9774fe2f865c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524579797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3524579797
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3876702271
Short name T909
Test name
Test status
Simulation time 18109346 ps
CPU time 0.69 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 204852 kb
Host smart-3084ac95-28dc-4f5f-8de1-d65005e94736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876702271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3876702271
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3147326592
Short name T917
Test name
Test status
Simulation time 11342006 ps
CPU time 0.82 seconds
Started Feb 18 12:30:08 PM PST 24
Finished Feb 18 12:30:18 PM PST 24
Peak memory 205020 kb
Host smart-4cd082b6-4e74-438c-9a3c-d6f204c9dc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147326592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3147326592
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1022620370
Short name T1039
Test name
Test status
Simulation time 14170957 ps
CPU time 0.76 seconds
Started Feb 18 12:30:17 PM PST 24
Finished Feb 18 12:30:24 PM PST 24
Peak memory 205012 kb
Host smart-bf749e11-4913-4088-9287-8cf8865b8c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022620370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1022620370
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1991398222
Short name T999
Test name
Test status
Simulation time 24067956 ps
CPU time 0.75 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:19 PM PST 24
Peak memory 204912 kb
Host smart-459ec9f4-abaf-4a16-b2db-5d948752ff27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991398222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1991398222
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2979278454
Short name T913
Test name
Test status
Simulation time 40246225 ps
CPU time 0.84 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 204956 kb
Host smart-960b4ee4-d97d-4f1d-bdf8-3e9303fcee7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979278454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2979278454
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2742645607
Short name T989
Test name
Test status
Simulation time 39006918 ps
CPU time 0.83 seconds
Started Feb 18 12:30:00 PM PST 24
Finished Feb 18 12:30:09 PM PST 24
Peak memory 205004 kb
Host smart-5b11c527-878f-49e8-8a41-fb35e1ed0f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742645607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2742645607
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2277322133
Short name T1058
Test name
Test status
Simulation time 20316031 ps
CPU time 0.72 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 204996 kb
Host smart-adccfa84-04c7-4b68-8893-ade9a5060a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277322133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2277322133
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1687443657
Short name T901
Test name
Test status
Simulation time 16038885 ps
CPU time 0.75 seconds
Started Feb 18 12:30:05 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 205020 kb
Host smart-b1bc6578-bf3b-4ea4-93cc-695de3638bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687443657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1687443657
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3534269747
Short name T1018
Test name
Test status
Simulation time 10446085 ps
CPU time 0.75 seconds
Started Feb 18 12:30:02 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 205012 kb
Host smart-d2a84b2e-33a9-43b4-a67d-eadf02f7f819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534269747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3534269747
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3781779738
Short name T925
Test name
Test status
Simulation time 271287801 ps
CPU time 4.05 seconds
Started Feb 18 12:29:45 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 205092 kb
Host smart-b874b7f2-0a8f-4e62-8e44-2666575877e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781779738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
781779738
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2655469666
Short name T998
Test name
Test status
Simulation time 434719936 ps
CPU time 8.21 seconds
Started Feb 18 12:29:39 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 205148 kb
Host smart-ebd5eaa1-8ee4-4c33-abfe-4bf02485081d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655469666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
655469666
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.406416120
Short name T1032
Test name
Test status
Simulation time 28166793 ps
CPU time 0.99 seconds
Started Feb 18 12:29:40 PM PST 24
Finished Feb 18 12:29:43 PM PST 24
Peak memory 205048 kb
Host smart-c9ef8e89-9632-4730-811f-4473d1c3f19a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406416120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.406416120
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2298348783
Short name T975
Test name
Test status
Simulation time 62665260 ps
CPU time 1.92 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:29:59 PM PST 24
Peak memory 213372 kb
Host smart-6fd7a6c1-140e-40fc-85d6-7140e027466e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298348783 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2298348783
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1351500520
Short name T1023
Test name
Test status
Simulation time 53105664 ps
CPU time 1.13 seconds
Started Feb 18 12:29:39 PM PST 24
Finished Feb 18 12:29:42 PM PST 24
Peak memory 205152 kb
Host smart-ed2cdfb7-5d5f-4e80-bc47-1c52431b364c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351500520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1351500520
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1743459189
Short name T967
Test name
Test status
Simulation time 37754487 ps
CPU time 0.69 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:31 PM PST 24
Peak memory 204932 kb
Host smart-96ac20ff-5ec0-4260-a45a-2cffc3a2c36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743459189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1743459189
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1555807535
Short name T1014
Test name
Test status
Simulation time 242040397 ps
CPU time 1.77 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:51 PM PST 24
Peak memory 205168 kb
Host smart-1b03082c-8832-4814-be62-c6fd2c6b5505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555807535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1555807535
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4065841800
Short name T1060
Test name
Test status
Simulation time 1017514338 ps
CPU time 4.62 seconds
Started Feb 18 12:29:27 PM PST 24
Finished Feb 18 12:29:33 PM PST 24
Peak memory 213552 kb
Host smart-39eb04e9-4f70-4806-873c-591b6874a7e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065841800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4065841800
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4129958049
Short name T941
Test name
Test status
Simulation time 40486718 ps
CPU time 2.59 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 213436 kb
Host smart-8fa52cd0-f053-43ac-b9d0-af263d130b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129958049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4129958049
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4035143120
Short name T169
Test name
Test status
Simulation time 417846620 ps
CPU time 8.84 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 208472 kb
Host smart-d580c5a6-7d38-483c-a8e8-e23c24b2e215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035143120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4035143120
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3758816487
Short name T995
Test name
Test status
Simulation time 15920117 ps
CPU time 0.73 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 204940 kb
Host smart-de001e90-4ca6-4e53-9e8c-8541ee77eb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758816487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3758816487
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.591443900
Short name T910
Test name
Test status
Simulation time 12426043 ps
CPU time 0.7 seconds
Started Feb 18 12:30:05 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 205028 kb
Host smart-d2db75d7-674a-4531-8f15-879aefb494c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591443900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.591443900
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2384092654
Short name T1028
Test name
Test status
Simulation time 21286639 ps
CPU time 0.75 seconds
Started Feb 18 12:30:06 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 205024 kb
Host smart-aec91850-2f40-4c45-963b-78c22060e2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384092654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2384092654
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3889158928
Short name T1048
Test name
Test status
Simulation time 13461896 ps
CPU time 0.75 seconds
Started Feb 18 12:30:00 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 204988 kb
Host smart-2c7e2b2b-93fc-4f46-a7ca-332b1a931b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889158928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3889158928
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2727727135
Short name T1047
Test name
Test status
Simulation time 18244561 ps
CPU time 0.86 seconds
Started Feb 18 12:30:04 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 204992 kb
Host smart-7857140c-1413-4f63-bc8d-9fbbc3e8a40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727727135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2727727135
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3633864311
Short name T947
Test name
Test status
Simulation time 8688375 ps
CPU time 0.71 seconds
Started Feb 18 12:30:02 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 204988 kb
Host smart-a4a22edb-5008-4667-b55e-1c5b1ec1c641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633864311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3633864311
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2146057289
Short name T904
Test name
Test status
Simulation time 8326983 ps
CPU time 0.68 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:19 PM PST 24
Peak memory 205028 kb
Host smart-68f33614-298f-48f1-8c81-c32f4eb806cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146057289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2146057289
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1165783385
Short name T952
Test name
Test status
Simulation time 18629180 ps
CPU time 0.71 seconds
Started Feb 18 12:30:02 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 204972 kb
Host smart-1e39224e-3d7a-4b47-8480-13740a604862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165783385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1165783385
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.249795520
Short name T1055
Test name
Test status
Simulation time 8943917 ps
CPU time 0.78 seconds
Started Feb 18 12:30:06 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 205028 kb
Host smart-256444d3-8b75-4f7a-85cb-36ee99f15de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249795520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.249795520
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.664846548
Short name T916
Test name
Test status
Simulation time 11900909 ps
CPU time 0.84 seconds
Started Feb 18 12:30:04 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 205012 kb
Host smart-18e5980d-cc1a-4a4a-a1ca-605dd756f11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664846548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.664846548
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2279364062
Short name T160
Test name
Test status
Simulation time 1216606673 ps
CPU time 4.64 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:08 PM PST 24
Peak memory 202876 kb
Host smart-d36ff3d3-47e8-40c3-b642-b425b59f6d78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279364062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
279364062
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2848815452
Short name T978
Test name
Test status
Simulation time 1673988066 ps
CPU time 9.08 seconds
Started Feb 18 12:35:19 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 205188 kb
Host smart-0e2f305e-e257-4c43-9ec5-c9ca32b979c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848815452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
848815452
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3319854896
Short name T982
Test name
Test status
Simulation time 16785901 ps
CPU time 0.9 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 205004 kb
Host smart-9a7bcfff-66ac-4d97-bf32-b55d62d2e165
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319854896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
319854896
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2146525507
Short name T1017
Test name
Test status
Simulation time 58250283 ps
CPU time 3.53 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 213548 kb
Host smart-3ed7fd4a-8827-479a-a722-8f6895313165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146525507 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2146525507
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1768752928
Short name T924
Test name
Test status
Simulation time 13279614 ps
CPU time 0.84 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 204992 kb
Host smart-7652c57c-be72-4d76-a711-3b0d35690e46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768752928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1768752928
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.857165962
Short name T943
Test name
Test status
Simulation time 47374864 ps
CPU time 0.84 seconds
Started Feb 18 12:29:45 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 205008 kb
Host smart-e561ea38-df8c-4700-afe5-8f5081b8ffe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857165962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.857165962
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3588491772
Short name T145
Test name
Test status
Simulation time 192773391 ps
CPU time 1.53 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:20 PM PST 24
Peak memory 205252 kb
Host smart-c9e1ac76-2b30-46f0-b6cf-09072eafdd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588491772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3588491772
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3360057921
Short name T1015
Test name
Test status
Simulation time 105147904 ps
CPU time 2.72 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:06 PM PST 24
Peak memory 211000 kb
Host smart-159a8a9d-3a81-4e9f-a594-02c6efc87c30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360057921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3360057921
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3798075848
Short name T1049
Test name
Test status
Simulation time 91995816 ps
CPU time 3.99 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:07 PM PST 24
Peak memory 211036 kb
Host smart-50f55cc8-6062-4e3e-9a45-3a03a8c1154a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798075848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3798075848
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1946285152
Short name T135
Test name
Test status
Simulation time 27539458 ps
CPU time 2.03 seconds
Started Feb 18 12:29:36 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 213392 kb
Host smart-1416f093-e887-4e76-8638-83923b66d436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946285152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1946285152
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.4151070078
Short name T177
Test name
Test status
Simulation time 10345635225 ps
CPU time 25.4 seconds
Started Feb 18 12:29:32 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 209036 kb
Host smart-054d0244-a1f8-4975-8751-0db56510a1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151070078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.4151070078
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3967326537
Short name T921
Test name
Test status
Simulation time 30437131 ps
CPU time 0.78 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:30:37 PM PST 24
Peak memory 204892 kb
Host smart-eab6cd32-b172-422b-bdb2-29a887f740f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967326537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3967326537
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3670454408
Short name T953
Test name
Test status
Simulation time 15086906 ps
CPU time 0.79 seconds
Started Feb 18 12:30:00 PM PST 24
Finished Feb 18 12:30:09 PM PST 24
Peak memory 205012 kb
Host smart-3b5ed742-cdb4-4938-9fe6-aa9f28f869f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670454408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3670454408
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1172328377
Short name T974
Test name
Test status
Simulation time 13296258 ps
CPU time 0.9 seconds
Started Feb 18 12:30:10 PM PST 24
Finished Feb 18 12:30:20 PM PST 24
Peak memory 205016 kb
Host smart-cd714316-3579-433c-948b-f2c03a5ceaef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172328377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1172328377
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1284573044
Short name T1052
Test name
Test status
Simulation time 35645114 ps
CPU time 0.76 seconds
Started Feb 18 12:29:53 PM PST 24
Finished Feb 18 12:29:59 PM PST 24
Peak memory 205032 kb
Host smart-81aac3b2-8802-4e44-b413-c59d62241865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284573044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1284573044
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1770277001
Short name T907
Test name
Test status
Simulation time 10270215 ps
CPU time 0.72 seconds
Started Feb 18 12:30:06 PM PST 24
Finished Feb 18 12:30:16 PM PST 24
Peak memory 204952 kb
Host smart-d9d588fa-fac1-43c5-8e96-7637aec0852f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770277001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1770277001
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1205773918
Short name T1044
Test name
Test status
Simulation time 13976277 ps
CPU time 0.67 seconds
Started Feb 18 12:30:09 PM PST 24
Finished Feb 18 12:30:19 PM PST 24
Peak memory 205008 kb
Host smart-83a664fd-4afa-417d-b490-0a43a4cad585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205773918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1205773918
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.474153170
Short name T1016
Test name
Test status
Simulation time 24919130 ps
CPU time 1.04 seconds
Started Feb 18 12:30:01 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 205060 kb
Host smart-9b675c49-5a3a-4547-9e6a-8550fd4cb36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474153170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.474153170
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2854799361
Short name T912
Test name
Test status
Simulation time 35432923 ps
CPU time 0.82 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:05 PM PST 24
Peak memory 205012 kb
Host smart-0deea2ab-a9e8-400d-837f-355c8a68fa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854799361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2854799361
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.250216107
Short name T908
Test name
Test status
Simulation time 18418746 ps
CPU time 0.72 seconds
Started Feb 18 12:29:55 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 205024 kb
Host smart-19902f83-679f-46b5-8653-43b4a1d86ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250216107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.250216107
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3925309018
Short name T1021
Test name
Test status
Simulation time 42728938 ps
CPU time 0.73 seconds
Started Feb 18 12:30:05 PM PST 24
Finished Feb 18 12:30:15 PM PST 24
Peak memory 204988 kb
Host smart-16ff8db0-279a-4757-b2e8-bc084b857b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925309018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3925309018
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1759469283
Short name T1004
Test name
Test status
Simulation time 286999056 ps
CPU time 4.05 seconds
Started Feb 18 12:29:58 PM PST 24
Finished Feb 18 12:30:12 PM PST 24
Peak memory 219200 kb
Host smart-cd3af579-b350-41d8-8edc-00b1514e18f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759469283 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1759469283
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1669431266
Short name T1000
Test name
Test status
Simulation time 91032313 ps
CPU time 1.4 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:04 PM PST 24
Peak memory 202524 kb
Host smart-0faa9c99-641a-4e2a-802c-60999d6c4266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669431266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1669431266
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2652864848
Short name T903
Test name
Test status
Simulation time 17635124 ps
CPU time 0.96 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:45 PM PST 24
Peak memory 205052 kb
Host smart-a255aede-b996-40ad-bfd7-979050374dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652864848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2652864848
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2822515909
Short name T146
Test name
Test status
Simulation time 171025150 ps
CPU time 2.22 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:32 PM PST 24
Peak memory 205256 kb
Host smart-a6c44b47-7e52-488e-ae08-dca8c5c60844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822515909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2822515909
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1828580975
Short name T119
Test name
Test status
Simulation time 85828026 ps
CPU time 2.81 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 221756 kb
Host smart-b73946b5-3b39-4d2e-bff1-73ba3df623a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828580975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1828580975
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1802784861
Short name T984
Test name
Test status
Simulation time 489094887 ps
CPU time 15.9 seconds
Started Feb 18 12:29:45 PM PST 24
Finished Feb 18 12:30:03 PM PST 24
Peak memory 213520 kb
Host smart-a5a5dfec-e297-4f56-9c71-8068839e4147
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802784861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1802784861
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.528526267
Short name T1008
Test name
Test status
Simulation time 289228305 ps
CPU time 1.79 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:31:26 PM PST 24
Peak memory 215556 kb
Host smart-6bdb97d1-11e1-4beb-ae28-36d2185eb1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528526267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.528526267
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1670660837
Short name T147
Test name
Test status
Simulation time 17442107 ps
CPU time 1.12 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 204992 kb
Host smart-56508b28-bd6b-4180-b65d-ceb61d9fcf4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670660837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1670660837
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1698749333
Short name T994
Test name
Test status
Simulation time 32025103 ps
CPU time 0.68 seconds
Started Feb 18 12:29:52 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 205024 kb
Host smart-d41814ce-6428-4780-96a2-6eb584e7e47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698749333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1698749333
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1683279057
Short name T915
Test name
Test status
Simulation time 80921904 ps
CPU time 3.63 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 205320 kb
Host smart-ca3715d3-ab86-4ba4-936e-ab11ef39c5c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683279057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1683279057
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1415393597
Short name T939
Test name
Test status
Simulation time 1665393532 ps
CPU time 17.71 seconds
Started Feb 18 12:29:42 PM PST 24
Finished Feb 18 12:30:01 PM PST 24
Peak memory 216596 kb
Host smart-eebf4ce5-4870-43a5-a94a-341349ea7899
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415393597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1415393597
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3219804570
Short name T1059
Test name
Test status
Simulation time 206772546 ps
CPU time 4.97 seconds
Started Feb 18 12:29:57 PM PST 24
Finished Feb 18 12:30:11 PM PST 24
Peak memory 219284 kb
Host smart-5f41dbc0-b119-49d1-bb02-2985db0b183b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219804570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3219804570
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2875312698
Short name T927
Test name
Test status
Simulation time 113153741 ps
CPU time 3.94 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213496 kb
Host smart-a5e49ae4-a224-4c7e-b52e-c4e984d73aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875312698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2875312698
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3807557439
Short name T181
Test name
Test status
Simulation time 235553005 ps
CPU time 8.63 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:12 PM PST 24
Peak memory 205756 kb
Host smart-e638c091-0d2f-4320-ad8c-4879ad183313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807557439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3807557439
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4036784777
Short name T966
Test name
Test status
Simulation time 646085273 ps
CPU time 3.49 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:07 PM PST 24
Peak memory 213160 kb
Host smart-77df6504-8d7f-45dd-9646-5578587bf97a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036784777 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4036784777
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3198068046
Short name T1005
Test name
Test status
Simulation time 16776380 ps
CPU time 1.19 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:30:01 PM PST 24
Peak memory 205088 kb
Host smart-107c8e59-ad21-45dc-ae3c-bda1e3b09090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198068046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3198068046
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3729191372
Short name T905
Test name
Test status
Simulation time 47012647 ps
CPU time 0.72 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:45 PM PST 24
Peak memory 204936 kb
Host smart-7350be9d-5190-4f8d-a211-5cfcfd7d82d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729191372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3729191372
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.756109166
Short name T1033
Test name
Test status
Simulation time 138740561 ps
CPU time 2.39 seconds
Started Feb 18 12:29:37 PM PST 24
Finished Feb 18 12:29:42 PM PST 24
Peak memory 205224 kb
Host smart-22c19bf5-6d40-4031-8fef-66119b8ba2c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756109166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.756109166
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.699426772
Short name T934
Test name
Test status
Simulation time 97521868 ps
CPU time 2.58 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:06 PM PST 24
Peak memory 211272 kb
Host smart-3156e22c-867d-473d-9e77-32617e017097
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699426772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.699426772
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3017335425
Short name T1020
Test name
Test status
Simulation time 787000367 ps
CPU time 4.53 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213592 kb
Host smart-198ccba5-aa28-460c-a230-9e0fe760c617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017335425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3017335425
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1832395219
Short name T189
Test name
Test status
Simulation time 127799303 ps
CPU time 2.79 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 213388 kb
Host smart-de480a42-c1d7-4a25-aab4-1892d410b9da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832395219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1832395219
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.26248129
Short name T157
Test name
Test status
Simulation time 278490435 ps
CPU time 5.27 seconds
Started Feb 18 12:29:44 PM PST 24
Finished Feb 18 12:29:52 PM PST 24
Peak memory 207944 kb
Host smart-e29be3d7-11f8-4d92-b90e-a0f343098a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26248129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.26248129
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.122774811
Short name T1057
Test name
Test status
Simulation time 415801067 ps
CPU time 2.45 seconds
Started Feb 18 12:29:36 PM PST 24
Finished Feb 18 12:29:41 PM PST 24
Peak memory 213376 kb
Host smart-edc9aaea-5714-4d09-9694-e815a133ba5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122774811 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.122774811
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2774543504
Short name T1053
Test name
Test status
Simulation time 45315165 ps
CPU time 1.19 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:29:55 PM PST 24
Peak memory 205184 kb
Host smart-e556e9a7-0dfa-4e1f-b3a1-381afbe98495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774543504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2774543504
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1404295291
Short name T931
Test name
Test status
Simulation time 12211677 ps
CPU time 0.83 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:31:28 PM PST 24
Peak memory 204920 kb
Host smart-113d74f1-ec59-45d7-9d0e-59d146856197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404295291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1404295291
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1848083492
Short name T986
Test name
Test status
Simulation time 51536706 ps
CPU time 1.54 seconds
Started Feb 18 12:29:48 PM PST 24
Finished Feb 18 12:29:51 PM PST 24
Peak memory 205084 kb
Host smart-fca7915d-408b-4ded-a993-67513d2c5608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848083492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1848083492
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.207573793
Short name T1001
Test name
Test status
Simulation time 1147605667 ps
CPU time 5.68 seconds
Started Feb 18 12:29:50 PM PST 24
Finished Feb 18 12:29:58 PM PST 24
Peak memory 213700 kb
Host smart-043b0570-659b-44cb-89d6-5cb57b1f2656
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207573793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.207573793
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3919750445
Short name T1026
Test name
Test status
Simulation time 726667669 ps
CPU time 7.37 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:29:56 PM PST 24
Peak memory 213524 kb
Host smart-7c844606-fdd5-4b25-8222-3968ba902bea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919750445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3919750445
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1533451307
Short name T911
Test name
Test status
Simulation time 205258499 ps
CPU time 1.66 seconds
Started Feb 18 12:29:35 PM PST 24
Finished Feb 18 12:29:39 PM PST 24
Peak memory 213172 kb
Host smart-4a39ab6f-61c7-4586-9256-b1591aa61d53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533451307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1533451307
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.870165233
Short name T945
Test name
Test status
Simulation time 184336049 ps
CPU time 2.91 seconds
Started Feb 18 12:29:56 PM PST 24
Finished Feb 18 12:30:09 PM PST 24
Peak memory 218752 kb
Host smart-bb961e0c-77ec-46e7-beb0-395b36ba19bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870165233 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.870165233
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1721152942
Short name T946
Test name
Test status
Simulation time 25097826 ps
CPU time 1.06 seconds
Started Feb 18 12:29:37 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 205068 kb
Host smart-50e78eb1-98ee-40b3-90b0-f821cf1d26be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721152942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1721152942
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3608422786
Short name T956
Test name
Test status
Simulation time 10017953 ps
CPU time 0.71 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:01 PM PST 24
Peak memory 205024 kb
Host smart-1a5306fb-95d3-4073-90e0-ddf66b4d2792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608422786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3608422786
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.998687902
Short name T143
Test name
Test status
Simulation time 44326779 ps
CPU time 2.11 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:02 PM PST 24
Peak memory 205256 kb
Host smart-335e4575-f64e-4b7b-93f0-ffc9c5da9769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998687902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.998687902
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.442965291
Short name T121
Test name
Test status
Simulation time 266913639 ps
CPU time 4.3 seconds
Started Feb 18 12:29:47 PM PST 24
Finished Feb 18 12:29:53 PM PST 24
Peak memory 213608 kb
Host smart-53b8a0f3-df42-444e-82ba-478539860518
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442965291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.442965291
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1703327905
Short name T112
Test name
Test status
Simulation time 333103782 ps
CPU time 12.14 seconds
Started Feb 18 12:29:51 PM PST 24
Finished Feb 18 12:30:06 PM PST 24
Peak memory 213644 kb
Host smart-07c5a4a5-3ec5-49be-a875-00cf6fd52f1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703327905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1703327905
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3130975001
Short name T1051
Test name
Test status
Simulation time 550325139 ps
CPU time 3.09 seconds
Started Feb 18 12:29:54 PM PST 24
Finished Feb 18 12:30:04 PM PST 24
Peak memory 213384 kb
Host smart-45cc6368-15ed-48df-b288-1ca191ca2810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130975001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3130975001
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3698150380
Short name T175
Test name
Test status
Simulation time 120323324 ps
CPU time 5.01 seconds
Started Feb 18 12:29:33 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 208308 kb
Host smart-f79de70e-955d-4af0-bc55-85fbaf1e7f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698150380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3698150380
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1731861669
Short name T518
Test name
Test status
Simulation time 15035490 ps
CPU time 0.93 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:30 PM PST 24
Peak memory 206192 kb
Host smart-f5ae8fdb-312b-4b07-b323-14f42114a169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731861669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1731861669
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.250582846
Short name T831
Test name
Test status
Simulation time 36361710 ps
CPU time 2.95 seconds
Started Feb 18 01:52:33 PM PST 24
Finished Feb 18 01:52:37 PM PST 24
Peak memory 214412 kb
Host smart-afb0f628-d5c3-4010-9b95-d053aa69d090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250582846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.250582846
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.57061433
Short name T535
Test name
Test status
Simulation time 147252913 ps
CPU time 4.59 seconds
Started Feb 18 01:52:21 PM PST 24
Finished Feb 18 01:52:27 PM PST 24
Peak memory 209260 kb
Host smart-8d8ce71d-5dcc-4f64-9489-93c46683a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57061433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.57061433
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3995632843
Short name T94
Test name
Test status
Simulation time 2192245821 ps
CPU time 5.41 seconds
Started Feb 18 01:52:27 PM PST 24
Finished Feb 18 01:52:34 PM PST 24
Peak memory 219488 kb
Host smart-69964411-b857-40b4-8a4f-582617458e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995632843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3995632843
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2120609682
Short name T809
Test name
Test status
Simulation time 2454439660 ps
CPU time 22.15 seconds
Started Feb 18 01:52:26 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 220840 kb
Host smart-1fa625ef-9765-4bc1-b899-82371b3c3db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120609682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2120609682
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2542597012
Short name T83
Test name
Test status
Simulation time 2648901084 ps
CPU time 12.91 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:42 PM PST 24
Peak memory 214552 kb
Host smart-05860319-0336-4406-aa6f-a754f4e60172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542597012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2542597012
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2060303598
Short name T608
Test name
Test status
Simulation time 220226109 ps
CPU time 6.74 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 207720 kb
Host smart-16b25c78-6576-4404-b04a-81bb473ce8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060303598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2060303598
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.104435969
Short name T337
Test name
Test status
Simulation time 76999873 ps
CPU time 2.95 seconds
Started Feb 18 01:52:26 PM PST 24
Finished Feb 18 01:52:30 PM PST 24
Peak memory 208688 kb
Host smart-55888bd6-cdb1-4ae7-888d-270bf06a759c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104435969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.104435969
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2889212978
Short name T563
Test name
Test status
Simulation time 51660730 ps
CPU time 2.83 seconds
Started Feb 18 01:52:24 PM PST 24
Finished Feb 18 01:52:28 PM PST 24
Peak memory 206504 kb
Host smart-f4ce7a09-926c-43d9-adbf-86caeb9bf8c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889212978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2889212978
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2341669305
Short name T887
Test name
Test status
Simulation time 37675305 ps
CPU time 2.75 seconds
Started Feb 18 01:52:23 PM PST 24
Finished Feb 18 01:52:26 PM PST 24
Peak memory 207300 kb
Host smart-9269e859-1151-461c-b0ae-b1d79369eab6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341669305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2341669305
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4269518854
Short name T641
Test name
Test status
Simulation time 163703865 ps
CPU time 2.15 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:31 PM PST 24
Peak memory 207008 kb
Host smart-0354097d-9cdc-4d7e-bb31-a982b825b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269518854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4269518854
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3513715736
Short name T662
Test name
Test status
Simulation time 1236067391 ps
CPU time 7.43 seconds
Started Feb 18 01:52:22 PM PST 24
Finished Feb 18 01:52:31 PM PST 24
Peak memory 208316 kb
Host smart-8881b4c3-e065-412f-aaa8-345b852c6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513715736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3513715736
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2746060516
Short name T507
Test name
Test status
Simulation time 716828611 ps
CPU time 5.29 seconds
Started Feb 18 01:52:22 PM PST 24
Finished Feb 18 01:52:28 PM PST 24
Peak memory 207900 kb
Host smart-62e68a84-1672-4c96-be73-c723ab6ea3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746060516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2746060516
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2069611098
Short name T204
Test name
Test status
Simulation time 80463027 ps
CPU time 4.18 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:36 PM PST 24
Peak memory 215652 kb
Host smart-64b7b6c2-4348-408c-96ca-f7cb69c24b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069611098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2069611098
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.148883263
Short name T561
Test name
Test status
Simulation time 54537051 ps
CPU time 0.79 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:37 PM PST 24
Peak memory 205912 kb
Host smart-ddc380f0-699b-4a0f-bd52-9db1dec27242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148883263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.148883263
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3816302406
Short name T671
Test name
Test status
Simulation time 783814464 ps
CPU time 7.31 seconds
Started Feb 18 01:52:28 PM PST 24
Finished Feb 18 01:52:36 PM PST 24
Peak memory 209776 kb
Host smart-41525e8b-6102-4932-933b-7ce3d4a043e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816302406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3816302406
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2839407608
Short name T745
Test name
Test status
Simulation time 56049851 ps
CPU time 2.28 seconds
Started Feb 18 01:52:27 PM PST 24
Finished Feb 18 01:52:30 PM PST 24
Peak memory 214512 kb
Host smart-db7240ab-2677-4b95-9fc7-5d53ed407f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839407608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2839407608
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.550887424
Short name T95
Test name
Test status
Simulation time 273009459 ps
CPU time 2.65 seconds
Started Feb 18 01:52:29 PM PST 24
Finished Feb 18 01:52:33 PM PST 24
Peak memory 214500 kb
Host smart-dac21448-e662-4fa4-aa93-57b73bd400d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550887424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.550887424
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3516138398
Short name T342
Test name
Test status
Simulation time 79736486 ps
CPU time 4.96 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 211644 kb
Host smart-93d1c587-e389-4851-aa43-25e8f7e14748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516138398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3516138398
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3137857234
Short name T59
Test name
Test status
Simulation time 343711712 ps
CPU time 5.25 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:37 PM PST 24
Peak memory 209136 kb
Host smart-8d69641b-50c8-4972-887e-7a44e5623bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137857234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3137857234
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.175670762
Short name T40
Test name
Test status
Simulation time 3928188506 ps
CPU time 59.72 seconds
Started Feb 18 01:52:29 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 243340 kb
Host smart-d1dd0416-d031-4a12-a67c-1996b2c57e87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175670762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.175670762
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1701609432
Short name T496
Test name
Test status
Simulation time 106612327 ps
CPU time 4.02 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:40 PM PST 24
Peak memory 206480 kb
Host smart-859a6ab0-d4b4-40db-afa6-7e04e55c09e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701609432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1701609432
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1299432591
Short name T720
Test name
Test status
Simulation time 60923348 ps
CPU time 2.3 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 206708 kb
Host smart-f3743cc8-40bb-41fb-8168-dd73ad3f9d15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299432591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1299432591
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4198219937
Short name T660
Test name
Test status
Simulation time 161896853 ps
CPU time 5.03 seconds
Started Feb 18 01:52:25 PM PST 24
Finished Feb 18 01:52:31 PM PST 24
Peak memory 207896 kb
Host smart-553ac025-df0b-42ad-ac8d-f4b3ddee64cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198219937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4198219937
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3966783699
Short name T870
Test name
Test status
Simulation time 774975708 ps
CPU time 18.83 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:52 PM PST 24
Peak memory 208784 kb
Host smart-72fb40a6-558a-442f-a047-265c276de123
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966783699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3966783699
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1787775405
Short name T361
Test name
Test status
Simulation time 3808393612 ps
CPU time 16.17 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:52:50 PM PST 24
Peak memory 209608 kb
Host smart-ba2f679f-3b51-4175-8c6b-6d790a2bd379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787775405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1787775405
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1977336814
Short name T794
Test name
Test status
Simulation time 27650658 ps
CPU time 1.95 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:34 PM PST 24
Peak memory 208368 kb
Host smart-a8dc94f8-155b-4c2f-a50a-0ca62d889092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977336814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1977336814
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2532750153
Short name T817
Test name
Test status
Simulation time 236243557 ps
CPU time 9.51 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:46 PM PST 24
Peak memory 218844 kb
Host smart-a7d8b5e4-f850-4bef-8a54-415c3e94ff6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532750153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2532750153
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1197259745
Short name T73
Test name
Test status
Simulation time 291922364 ps
CPU time 22.68 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:52:56 PM PST 24
Peak memory 222724 kb
Host smart-e7dc322e-0f5f-48d0-9770-0d20cad911e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197259745 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1197259745
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2575675683
Short name T365
Test name
Test status
Simulation time 403517564 ps
CPU time 4.52 seconds
Started Feb 18 01:52:29 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 209988 kb
Host smart-b262e727-8a3a-4c09-b323-4bf37579efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575675683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2575675683
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1373954551
Short name T736
Test name
Test status
Simulation time 118636359 ps
CPU time 1.94 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:44 PM PST 24
Peak memory 209904 kb
Host smart-1cf744df-64fc-4ef8-ab09-056f509bc073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373954551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1373954551
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3638850030
Short name T848
Test name
Test status
Simulation time 17154844 ps
CPU time 0.72 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:26 PM PST 24
Peak memory 206036 kb
Host smart-5e076737-200b-403c-a9a1-836cd43510a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638850030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3638850030
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1285964263
Short name T391
Test name
Test status
Simulation time 625120206 ps
CPU time 6.04 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 215524 kb
Host smart-f6d0bb89-a2e3-436d-a5b2-9a1f473b81a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285964263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1285964263
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.690871488
Short name T30
Test name
Test status
Simulation time 112530064 ps
CPU time 2.13 seconds
Started Feb 18 01:53:22 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 209640 kb
Host smart-bdfc2f96-5dc1-48f3-b6b6-8cb71bbb83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690871488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.690871488
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2999631777
Short name T620
Test name
Test status
Simulation time 5723635370 ps
CPU time 18.45 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:43 PM PST 24
Peak memory 214600 kb
Host smart-8dd15433-8db6-4784-9a4f-a3bcc962effa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999631777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2999631777
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1221103410
Short name T552
Test name
Test status
Simulation time 52688610 ps
CPU time 3.43 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 208592 kb
Host smart-a20c96b9-8844-4eca-b7b8-073deb73155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221103410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1221103410
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2839779146
Short name T25
Test name
Test status
Simulation time 187443931 ps
CPU time 6.2 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 211656 kb
Host smart-65b85576-826d-4a9d-8e47-d525b801a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839779146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2839779146
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3261627166
Short name T52
Test name
Test status
Simulation time 38554817 ps
CPU time 2.64 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:32 PM PST 24
Peak memory 216252 kb
Host smart-60be7ab3-037f-4238-93f4-fecfaabf8265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261627166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3261627166
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.984975278
Short name T812
Test name
Test status
Simulation time 3638399223 ps
CPU time 10.04 seconds
Started Feb 18 01:53:18 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 214540 kb
Host smart-1f81c432-e06a-4664-9a6e-4b093ef59ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984975278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.984975278
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2639946653
Short name T354
Test name
Test status
Simulation time 699280737 ps
CPU time 5.37 seconds
Started Feb 18 01:53:12 PM PST 24
Finished Feb 18 01:53:24 PM PST 24
Peak memory 206636 kb
Host smart-f1c7db05-1c1c-4bc4-91f8-69e999e1d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639946653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2639946653
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3244785331
Short name T838
Test name
Test status
Simulation time 1415103987 ps
CPU time 15.75 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:41 PM PST 24
Peak memory 208768 kb
Host smart-557355d4-4ec8-4e50-86e7-719a5aa18d4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244785331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3244785331
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.469747129
Short name T560
Test name
Test status
Simulation time 55486702 ps
CPU time 2.98 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 207024 kb
Host smart-dd449511-2b94-4870-8362-1af20d19bcce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469747129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.469747129
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1215240098
Short name T841
Test name
Test status
Simulation time 191225554 ps
CPU time 5.83 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 206756 kb
Host smart-f77105f9-2865-4b40-bc2f-d8328f0ce762
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215240098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1215240098
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3331519287
Short name T353
Test name
Test status
Simulation time 54591953 ps
CPU time 2.2 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 207716 kb
Host smart-c7d2163f-826d-485c-8c46-3232a8fc8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331519287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3331519287
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2663683919
Short name T506
Test name
Test status
Simulation time 120469349 ps
CPU time 2.21 seconds
Started Feb 18 01:53:15 PM PST 24
Finished Feb 18 01:53:25 PM PST 24
Peak memory 206640 kb
Host smart-ab7a5e92-f585-444e-9220-d6de323fe12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663683919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2663683919
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1091552462
Short name T194
Test name
Test status
Simulation time 3877561517 ps
CPU time 26.77 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 216404 kb
Host smart-5382273c-8465-429b-9df7-41d0229cd2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091552462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1091552462
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2658870963
Short name T482
Test name
Test status
Simulation time 104846501 ps
CPU time 5.42 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 210204 kb
Host smart-d30f6507-7376-4de2-865e-d0a94cdff3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658870963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2658870963
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2651579797
Short name T405
Test name
Test status
Simulation time 67612476 ps
CPU time 2.64 seconds
Started Feb 18 01:53:18 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 209800 kb
Host smart-9619bed5-4877-4a60-b366-74222ee4f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651579797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2651579797
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1885079158
Short name T513
Test name
Test status
Simulation time 37325553 ps
CPU time 0.73 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:26 PM PST 24
Peak memory 205908 kb
Host smart-3742027c-f6e3-4bc5-9ac9-c1db83aff383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885079158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1885079158
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3452479039
Short name T428
Test name
Test status
Simulation time 484985645 ps
CPU time 7.29 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 214780 kb
Host smart-fe9e5e7d-0ed2-4809-9791-c86e47fa69a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452479039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3452479039
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1936590736
Short name T27
Test name
Test status
Simulation time 4501378019 ps
CPU time 76.01 seconds
Started Feb 18 01:53:22 PM PST 24
Finished Feb 18 01:54:42 PM PST 24
Peak memory 223016 kb
Host smart-4486e478-ea76-4e30-b931-dc68739fe5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936590736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1936590736
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2463586151
Short name T340
Test name
Test status
Simulation time 70982566 ps
CPU time 2.82 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 214444 kb
Host smart-69190b9f-dc85-4606-a746-897d8f983c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463586151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2463586151
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3637550117
Short name T865
Test name
Test status
Simulation time 13764330041 ps
CPU time 62 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 219360 kb
Host smart-b17cd977-2c29-4542-95b8-d79681f8abec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637550117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3637550117
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3647627510
Short name T237
Test name
Test status
Simulation time 95564062 ps
CPU time 3.18 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 220352 kb
Host smart-29c39cef-4efc-4da7-a23d-c9e54ba2ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647627510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3647627510
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.78772594
Short name T820
Test name
Test status
Simulation time 1058945310 ps
CPU time 7.64 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 208896 kb
Host smart-671bb192-3f2b-4b79-847b-13d02c4d2a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78772594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.78772594
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4032068064
Short name T647
Test name
Test status
Simulation time 108899050 ps
CPU time 2.59 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 206616 kb
Host smart-6b82aff8-f1d6-4356-98d6-0510bf4caa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032068064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4032068064
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2867230189
Short name T503
Test name
Test status
Simulation time 57080097 ps
CPU time 2.96 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 206936 kb
Host smart-b1b528e8-8f0c-49a2-a83d-38e4e9b93d2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867230189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2867230189
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3299787446
Short name T827
Test name
Test status
Simulation time 120993654 ps
CPU time 3.12 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:29 PM PST 24
Peak memory 206744 kb
Host smart-99ad0704-71ef-41fb-bcc5-a14cb2e3a43b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299787446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3299787446
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.457420563
Short name T299
Test name
Test status
Simulation time 209350112 ps
CPU time 8.25 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 207924 kb
Host smart-8b6a610b-36ae-48aa-b754-9c16de282874
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457420563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.457420563
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1761308637
Short name T408
Test name
Test status
Simulation time 631943013 ps
CPU time 3.54 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:29 PM PST 24
Peak memory 208304 kb
Host smart-0e1c03b0-bd29-46af-9ad0-ab57e4d6d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761308637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1761308637
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3238557378
Short name T520
Test name
Test status
Simulation time 837129102 ps
CPU time 14.37 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 208492 kb
Host smart-9d6475d4-8ce3-4636-b94f-3e72bcc27e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238557378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3238557378
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1053890496
Short name T206
Test name
Test status
Simulation time 554081189 ps
CPU time 7.88 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 207676 kb
Host smart-f8f9511f-455e-4082-a8ff-ebfc3d63fb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053890496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1053890496
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1510747173
Short name T210
Test name
Test status
Simulation time 185462692 ps
CPU time 1.96 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 209764 kb
Host smart-3fa66946-9747-42b6-b254-35883c1bf1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510747173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1510747173
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.197666710
Short name T880
Test name
Test status
Simulation time 13116822 ps
CPU time 0.75 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 206116 kb
Host smart-89423fd2-dc87-4c72-9046-96df17875f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197666710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.197666710
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3945055112
Short name T31
Test name
Test status
Simulation time 76179828 ps
CPU time 3.69 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 209304 kb
Host smart-85cd1cd3-9093-42c0-a5f4-56aa7de68a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945055112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3945055112
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4020354613
Short name T314
Test name
Test status
Simulation time 429660599 ps
CPU time 11 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 214412 kb
Host smart-73ee9a19-01cd-4ad5-ac9a-32293b11148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020354613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4020354613
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.542968174
Short name T855
Test name
Test status
Simulation time 379323168 ps
CPU time 4.05 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 222648 kb
Host smart-9fa73314-f24c-43a1-b540-7507c4110f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542968174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.542968174
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.4282759154
Short name T765
Test name
Test status
Simulation time 113956734 ps
CPU time 5.46 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:36 PM PST 24
Peak memory 214432 kb
Host smart-1803d3a2-eba8-4b4d-a096-f0984cc32490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282759154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4282759154
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3574994734
Short name T207
Test name
Test status
Simulation time 43889130 ps
CPU time 2.6 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:32 PM PST 24
Peak memory 206244 kb
Host smart-c07b9a43-392d-4d46-a70b-276e180c1788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574994734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3574994734
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1972294340
Short name T643
Test name
Test status
Simulation time 635979612 ps
CPU time 6.26 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 214480 kb
Host smart-4007acf0-c019-4749-9843-71f50abc6e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972294340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1972294340
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2882306571
Short name T397
Test name
Test status
Simulation time 771827240 ps
CPU time 5.6 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 208236 kb
Host smart-db326a72-bd05-4877-afe7-2ea09689c79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882306571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2882306571
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.441547059
Short name T737
Test name
Test status
Simulation time 4845595701 ps
CPU time 18.82 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 207828 kb
Host smart-de66847b-f02a-4553-876e-6ed359e576bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441547059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.441547059
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1623950989
Short name T575
Test name
Test status
Simulation time 135640078 ps
CPU time 3.95 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 208564 kb
Host smart-036fbc8c-fa5c-4a7b-aef9-c13693466efc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623950989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1623950989
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.238608273
Short name T376
Test name
Test status
Simulation time 56159361 ps
CPU time 3.05 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 206828 kb
Host smart-56dd2662-1564-4747-bdb7-02ebedf41b9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238608273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.238608273
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4274667028
Short name T618
Test name
Test status
Simulation time 55812739 ps
CPU time 2.01 seconds
Started Feb 18 01:53:30 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 208016 kb
Host smart-b509baaa-b2ed-49e8-8709-9f5b34f5d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274667028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4274667028
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3920255599
Short name T468
Test name
Test status
Simulation time 246125394 ps
CPU time 3.13 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 206572 kb
Host smart-b713b673-4711-4f1b-914a-2dfedb6d3a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920255599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3920255599
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1522883362
Short name T74
Test name
Test status
Simulation time 3207726190 ps
CPU time 39.09 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 216236 kb
Host smart-6060f876-7771-435f-bcd9-4c9b258b9408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522883362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1522883362
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1048949617
Short name T384
Test name
Test status
Simulation time 95335841 ps
CPU time 3.23 seconds
Started Feb 18 01:53:22 PM PST 24
Finished Feb 18 01:53:29 PM PST 24
Peak memory 218376 kb
Host smart-81c620c2-945d-4f6f-a3ef-d0b2af95d1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048949617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1048949617
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2668027705
Short name T685
Test name
Test status
Simulation time 54096170 ps
CPU time 2.8 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 209896 kb
Host smart-c6875253-454e-4120-a5ca-514df9404408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668027705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2668027705
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.46785748
Short name T733
Test name
Test status
Simulation time 36180611 ps
CPU time 0.71 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 206036 kb
Host smart-a19e92aa-3492-4992-8f0f-c57226d51cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46785748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.46785748
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.181631167
Short name T868
Test name
Test status
Simulation time 2338272040 ps
CPU time 16.71 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:50 PM PST 24
Peak memory 209084 kb
Host smart-4eb2fc75-d374-4284-be6b-86c21259eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181631167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.181631167
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.200195999
Short name T538
Test name
Test status
Simulation time 928917743 ps
CPU time 2.82 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 208204 kb
Host smart-6af55ecb-1577-45c4-a1ce-19843d7c9ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200195999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.200195999
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2779281364
Short name T782
Test name
Test status
Simulation time 1450085106 ps
CPU time 13.06 seconds
Started Feb 18 01:53:22 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 214332 kb
Host smart-f72dab68-745a-41bd-af71-1a3e549f7c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779281364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2779281364
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1348672209
Short name T728
Test name
Test status
Simulation time 485773518 ps
CPU time 3.23 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:36 PM PST 24
Peak memory 209680 kb
Host smart-6c4f416b-cb3a-4d1d-8db4-e5bb25f7925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348672209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1348672209
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3979461868
Short name T758
Test name
Test status
Simulation time 864251110 ps
CPU time 9.57 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 208372 kb
Host smart-40b31a61-0397-4a6a-8143-4ee0a4565cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979461868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3979461868
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2367906877
Short name T328
Test name
Test status
Simulation time 93341278 ps
CPU time 4.08 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 208784 kb
Host smart-e0000473-d66c-4022-8820-739db1e2f1a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367906877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2367906877
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1901648728
Short name T825
Test name
Test status
Simulation time 4839561099 ps
CPU time 28.27 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 207988 kb
Host smart-d6fd8e28-5b36-4bee-b656-adf15c0ef426
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901648728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1901648728
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2389231267
Short name T756
Test name
Test status
Simulation time 25877193 ps
CPU time 1.79 seconds
Started Feb 18 01:53:30 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 208152 kb
Host smart-96b60e03-6b59-40e3-a3e8-4ceaf5c25802
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389231267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2389231267
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3629458179
Short name T803
Test name
Test status
Simulation time 197315584 ps
CPU time 2.73 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 209236 kb
Host smart-06cf9969-de5e-40e1-a672-c7fd2d41ddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629458179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3629458179
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3859675159
Short name T532
Test name
Test status
Simulation time 349475386 ps
CPU time 3.3 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 208508 kb
Host smart-dc502401-2397-403f-9504-48f6760e25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859675159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3859675159
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1069448200
Short name T264
Test name
Test status
Simulation time 1451578045 ps
CPU time 20.65 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 215800 kb
Host smart-2e5ad8ec-430c-4c66-8ca7-1aee2dd2f745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069448200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1069448200
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1806652101
Short name T125
Test name
Test status
Simulation time 137398409 ps
CPU time 9.96 seconds
Started Feb 18 01:53:21 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 222776 kb
Host smart-b108a5ab-482b-4c4a-83b3-e5946a5698e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806652101 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1806652101
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4026027123
Short name T138
Test name
Test status
Simulation time 528629707 ps
CPU time 3.18 seconds
Started Feb 18 01:53:23 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 207852 kb
Host smart-26229236-fec2-4c72-bcdc-af0444ae07b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026027123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4026027123
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1863087070
Short name T134
Test name
Test status
Simulation time 349066293 ps
CPU time 2.54 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 209948 kb
Host smart-3e04cfa9-f2ce-4881-92f5-55e8d73ab29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863087070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1863087070
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1712118313
Short name T780
Test name
Test status
Simulation time 51454130 ps
CPU time 0.79 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 205924 kb
Host smart-e765ec09-139a-4a8e-8f2c-21ce03528465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712118313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1712118313
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1066339322
Short name T767
Test name
Test status
Simulation time 71295499 ps
CPU time 3.28 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 208220 kb
Host smart-6fe17634-b846-45dd-a3f6-5238c2a2f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066339322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1066339322
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2908545379
Short name T741
Test name
Test status
Simulation time 377594230 ps
CPU time 3.18 seconds
Started Feb 18 01:53:30 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 207724 kb
Host smart-55b91a05-999b-498d-b304-d13b3db4a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908545379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2908545379
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2788264819
Short name T787
Test name
Test status
Simulation time 805904030 ps
CPU time 6.88 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 210572 kb
Host smart-b96e1220-b6a6-40a8-aab7-794718181b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788264819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2788264819
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.419948961
Short name T251
Test name
Test status
Simulation time 854444552 ps
CPU time 10.94 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:48 PM PST 24
Peak memory 209756 kb
Host smart-946e6603-25f3-4ede-90d9-8cb27c75927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419948961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.419948961
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.582208466
Short name T522
Test name
Test status
Simulation time 196708943 ps
CPU time 1.88 seconds
Started Feb 18 01:53:25 PM PST 24
Finished Feb 18 01:53:32 PM PST 24
Peak memory 207460 kb
Host smart-28c576c1-06b5-4343-9900-c80e875387b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582208466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.582208466
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2734536844
Short name T456
Test name
Test status
Simulation time 3301924738 ps
CPU time 24.94 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:54:01 PM PST 24
Peak memory 207760 kb
Host smart-da1925e9-5d34-4165-bba5-c90d46742d69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734536844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2734536844
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.868025855
Short name T804
Test name
Test status
Simulation time 62304410 ps
CPU time 3.31 seconds
Started Feb 18 01:53:24 PM PST 24
Finished Feb 18 01:53:33 PM PST 24
Peak memory 208680 kb
Host smart-383a9a6b-9c23-44a6-9d0d-b71d1adc7bb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868025855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.868025855
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2027085340
Short name T18
Test name
Test status
Simulation time 93804425 ps
CPU time 3.48 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 208748 kb
Host smart-50f8c463-3339-4538-af7f-c790bf1cd3b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027085340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2027085340
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3190593593
Short name T836
Test name
Test status
Simulation time 168590174 ps
CPU time 5.1 seconds
Started Feb 18 01:53:30 PM PST 24
Finished Feb 18 01:53:41 PM PST 24
Peak memory 214252 kb
Host smart-46c8ade6-5605-4478-8326-136abefde555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190593593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3190593593
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1380938384
Short name T667
Test name
Test status
Simulation time 2043397546 ps
CPU time 6.48 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 208492 kb
Host smart-b2006463-0ad5-4d67-b2e7-735e118d6f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380938384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1380938384
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.554107487
Short name T866
Test name
Test status
Simulation time 320514680 ps
CPU time 8.67 seconds
Started Feb 18 01:53:33 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 218412 kb
Host smart-47b4b657-b5bf-4e6c-91ba-a5fcbd72149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554107487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.554107487
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.956436964
Short name T681
Test name
Test status
Simulation time 870633689 ps
CPU time 17.2 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:51 PM PST 24
Peak memory 210768 kb
Host smart-47d731c9-27ae-4fa0-b740-0c7b33e82f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956436964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.956436964
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2375323379
Short name T466
Test name
Test status
Simulation time 11613784 ps
CPU time 0.78 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:53:32 PM PST 24
Peak memory 206016 kb
Host smart-589dd02e-baee-4944-aa24-1da23c0e21c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375323379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2375323379
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1062915162
Short name T347
Test name
Test status
Simulation time 59105905 ps
CPU time 4.12 seconds
Started Feb 18 01:53:32 PM PST 24
Finished Feb 18 01:53:43 PM PST 24
Peak memory 215568 kb
Host smart-ba9e26b9-fa8a-4f63-9aae-b4c80c6359ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062915162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1062915162
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1110532237
Short name T876
Test name
Test status
Simulation time 174696954 ps
CPU time 5.08 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 208960 kb
Host smart-1e1962bd-2972-4ff8-9d80-9316381f522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110532237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1110532237
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4007849079
Short name T884
Test name
Test status
Simulation time 388671929 ps
CPU time 2.25 seconds
Started Feb 18 01:53:30 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 209724 kb
Host smart-f33e7772-7ddb-4f91-8fdc-46612566b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007849079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4007849079
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2409897910
Short name T779
Test name
Test status
Simulation time 261165206 ps
CPU time 8.58 seconds
Started Feb 18 01:53:32 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 208936 kb
Host smart-54ccc843-2fc7-440d-b28b-bb41f7ac4c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409897910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2409897910
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1530359899
Short name T461
Test name
Test status
Simulation time 119071773 ps
CPU time 3.38 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:53:45 PM PST 24
Peak memory 214540 kb
Host smart-a4ffcb0c-93a8-47ba-95ff-ab736eae6a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530359899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1530359899
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3472517012
Short name T523
Test name
Test status
Simulation time 187665573 ps
CPU time 3.23 seconds
Started Feb 18 01:53:27 PM PST 24
Finished Feb 18 01:53:36 PM PST 24
Peak memory 210040 kb
Host smart-b29c21a2-ef22-4474-bbdd-855b25b7a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472517012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3472517012
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3177401474
Short name T545
Test name
Test status
Simulation time 429135776 ps
CPU time 3.11 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:41 PM PST 24
Peak memory 206752 kb
Host smart-001f4acc-a4a8-476d-8810-de31dfdc8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177401474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3177401474
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1566725066
Short name T878
Test name
Test status
Simulation time 957527670 ps
CPU time 4.97 seconds
Started Feb 18 01:53:32 PM PST 24
Finished Feb 18 01:53:44 PM PST 24
Peak memory 206604 kb
Host smart-5d72abc6-0486-4c8a-b70f-7b37d810f665
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566725066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1566725066
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3314230065
Short name T280
Test name
Test status
Simulation time 382204742 ps
CPU time 4.06 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 208708 kb
Host smart-aebb3a88-7286-4563-92bd-66c5785f960d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314230065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3314230065
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3647919654
Short name T614
Test name
Test status
Simulation time 43070220 ps
CPU time 2.52 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 206664 kb
Host smart-691eabb4-ada3-4946-838e-79aa74724eed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647919654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3647919654
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2001101408
Short name T486
Test name
Test status
Simulation time 57358751 ps
CPU time 1.49 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:38 PM PST 24
Peak memory 207860 kb
Host smart-bed43acb-b6ff-40b3-b07b-20b3d2af8095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001101408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2001101408
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1025393470
Short name T483
Test name
Test status
Simulation time 37202823 ps
CPU time 2.18 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 206660 kb
Host smart-23541069-3e3a-411e-8da1-9be626ac6893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025393470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1025393470
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2053205607
Short name T316
Test name
Test status
Simulation time 235188637 ps
CPU time 12.18 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 216772 kb
Host smart-d864ec7e-104c-4750-8f08-2f727775c90c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053205607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2053205607
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1758398833
Short name T703
Test name
Test status
Simulation time 493759559 ps
CPU time 9.93 seconds
Started Feb 18 01:53:28 PM PST 24
Finished Feb 18 01:53:43 PM PST 24
Peak memory 207536 kb
Host smart-167c925f-f1ff-4a1f-bfd0-a39371774250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758398833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1758398833
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1178074429
Short name T159
Test name
Test status
Simulation time 992565352 ps
CPU time 10.22 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 210684 kb
Host smart-ff76c0c6-21fa-49a5-8b44-cba10bb90828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178074429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1178074429
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3144114704
Short name T432
Test name
Test status
Simulation time 2065750124 ps
CPU time 10.13 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 215480 kb
Host smart-8d6acd8c-18f2-447a-b1eb-a678b4386bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144114704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3144114704
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3946937034
Short name T871
Test name
Test status
Simulation time 54244342 ps
CPU time 2.92 seconds
Started Feb 18 01:53:26 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 209460 kb
Host smart-941c90e3-bf9d-4d48-91a5-e4b387fb472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946937034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3946937034
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2486499439
Short name T762
Test name
Test status
Simulation time 449967806 ps
CPU time 6.32 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:53:42 PM PST 24
Peak memory 208500 kb
Host smart-93d8ac39-e092-4473-ac84-08b6eb2db22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486499439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2486499439
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2805254712
Short name T615
Test name
Test status
Simulation time 1484106458 ps
CPU time 6.04 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 210248 kb
Host smart-b4a5070a-95fa-4611-8168-c049ddc142ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805254712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2805254712
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4261270423
Short name T233
Test name
Test status
Simulation time 40594079 ps
CPU time 2.35 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:46 PM PST 24
Peak memory 216232 kb
Host smart-80d82986-d8f8-4e47-8908-db6934dbc681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261270423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4261270423
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3315583714
Short name T799
Test name
Test status
Simulation time 322751231 ps
CPU time 4.07 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:48 PM PST 24
Peak memory 214468 kb
Host smart-4c383296-22e7-4b84-8791-e3de514ecadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315583714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3315583714
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3147759411
Short name T502
Test name
Test status
Simulation time 130414364 ps
CPU time 4.69 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 208196 kb
Host smart-807da5ac-403e-449c-bf82-e7cc8a5ca237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147759411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3147759411
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.981512401
Short name T599
Test name
Test status
Simulation time 64146068 ps
CPU time 3.11 seconds
Started Feb 18 01:53:33 PM PST 24
Finished Feb 18 01:53:43 PM PST 24
Peak memory 208708 kb
Host smart-22325ec4-bc32-4eab-b565-dab29a1dc4b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981512401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.981512401
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.211692338
Short name T683
Test name
Test status
Simulation time 34622685478 ps
CPU time 57.63 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:54:40 PM PST 24
Peak memory 208520 kb
Host smart-038689f6-aca2-4761-91ac-957803488a6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211692338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.211692338
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1764365443
Short name T858
Test name
Test status
Simulation time 263007645 ps
CPU time 3.5 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:46 PM PST 24
Peak memory 208328 kb
Host smart-77a74b3c-21f3-48c7-992e-f961e7c733d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764365443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1764365443
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2338812577
Short name T708
Test name
Test status
Simulation time 744289040 ps
CPU time 23.68 seconds
Started Feb 18 01:53:32 PM PST 24
Finished Feb 18 01:54:02 PM PST 24
Peak memory 218400 kb
Host smart-9638a5c5-251b-40e1-9b49-2043ee5b33d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338812577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2338812577
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3099293740
Short name T454
Test name
Test status
Simulation time 139519297 ps
CPU time 3.2 seconds
Started Feb 18 01:53:31 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 208380 kb
Host smart-a00a21c0-44f3-4fc8-9b0c-51b9f3f62246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099293740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3099293740
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2131449666
Short name T768
Test name
Test status
Simulation time 1557930711 ps
CPU time 30.74 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:54:14 PM PST 24
Peak memory 215940 kb
Host smart-c7004611-ce03-4887-978e-f35058d23699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131449666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2131449666
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2236347611
Short name T289
Test name
Test status
Simulation time 109755867 ps
CPU time 5.37 seconds
Started Feb 18 01:53:29 PM PST 24
Finished Feb 18 01:53:40 PM PST 24
Peak memory 218400 kb
Host smart-081024a1-a261-4e39-962e-a188c862f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236347611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2236347611
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4093618751
Short name T682
Test name
Test status
Simulation time 65088594 ps
CPU time 2.66 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:45 PM PST 24
Peak memory 209796 kb
Host smart-21043957-9a4f-4c38-a7cc-73f0a61b5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093618751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4093618751
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2746268740
Short name T97
Test name
Test status
Simulation time 72747551 ps
CPU time 0.82 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 206040 kb
Host smart-285209e2-0bec-4d49-ba68-f8adc2228345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746268740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2746268740
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3491214696
Short name T333
Test name
Test status
Simulation time 160061000 ps
CPU time 4.15 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 215436 kb
Host smart-e60c2a7c-2cde-42e7-964b-995f3362e1d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491214696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3491214696
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1225635442
Short name T29
Test name
Test status
Simulation time 1129817608 ps
CPU time 6.65 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:50 PM PST 24
Peak memory 209620 kb
Host smart-59012401-0438-4564-9d75-799227bb0cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225635442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1225635442
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.56433071
Short name T68
Test name
Test status
Simulation time 7204477224 ps
CPU time 24.08 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:54:06 PM PST 24
Peak memory 214460 kb
Host smart-d1105892-c367-4341-af2c-df5678386c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56433071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.56433071
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.39797017
Short name T704
Test name
Test status
Simulation time 238555334 ps
CPU time 4.21 seconds
Started Feb 18 01:53:35 PM PST 24
Finished Feb 18 01:53:46 PM PST 24
Peak memory 214464 kb
Host smart-a789c0c6-e62c-4e3d-9f6f-ef0d5d59f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39797017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.39797017
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.319109716
Short name T582
Test name
Test status
Simulation time 310713055 ps
CPU time 7.68 seconds
Started Feb 18 01:53:44 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 214440 kb
Host smart-a010a107-fb56-4935-bd1f-a482968ee1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319109716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.319109716
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3060448263
Short name T232
Test name
Test status
Simulation time 184488889 ps
CPU time 3.25 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:46 PM PST 24
Peak memory 209948 kb
Host smart-e1b6916b-bbab-4f59-a4ac-d99eb1de94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060448263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3060448263
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2934638387
Short name T648
Test name
Test status
Simulation time 164974129 ps
CPU time 4.09 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 208920 kb
Host smart-2acd91b1-5aa1-4187-aa36-6dd7351a634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934638387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2934638387
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2383352681
Short name T722
Test name
Test status
Simulation time 234483859 ps
CPU time 3.9 seconds
Started Feb 18 01:53:37 PM PST 24
Finished Feb 18 01:53:48 PM PST 24
Peak memory 206852 kb
Host smart-8af271ec-79a8-4e89-984d-979c3e4532cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383352681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2383352681
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3238765400
Short name T749
Test name
Test status
Simulation time 279447856 ps
CPU time 3.68 seconds
Started Feb 18 01:53:40 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 208664 kb
Host smart-7a4fd392-2e76-492d-9f7a-fce024958b67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238765400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3238765400
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1453314257
Short name T818
Test name
Test status
Simulation time 51288106 ps
CPU time 2.61 seconds
Started Feb 18 01:53:38 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 206860 kb
Host smart-2ffccf6c-d4fe-4baa-8213-5dc29062b670
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453314257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1453314257
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3452057569
Short name T726
Test name
Test status
Simulation time 142807535 ps
CPU time 3.35 seconds
Started Feb 18 01:53:50 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 209076 kb
Host smart-272b92c5-8df0-4cc6-8c86-5b1da579ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452057569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3452057569
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2067410166
Short name T491
Test name
Test status
Simulation time 1985539239 ps
CPU time 43.87 seconds
Started Feb 18 01:53:36 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 208504 kb
Host smart-1105b4be-9bad-465b-b890-44259e5c8dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067410166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2067410166
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3237584836
Short name T385
Test name
Test status
Simulation time 5792150157 ps
CPU time 182.48 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:56:52 PM PST 24
Peak memory 217996 kb
Host smart-99c348bf-aea8-41ea-ad23-c9a238bd39c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237584836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3237584836
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4294552524
Short name T564
Test name
Test status
Simulation time 103329340 ps
CPU time 4.88 seconds
Started Feb 18 01:53:34 PM PST 24
Finished Feb 18 01:53:47 PM PST 24
Peak memory 208548 kb
Host smart-bb0243b9-0c1f-4de2-8632-7d70e84bba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294552524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4294552524
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1529992292
Short name T898
Test name
Test status
Simulation time 33949280 ps
CPU time 2.08 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:50 PM PST 24
Peak memory 209796 kb
Host smart-e5faef14-1c51-46f0-ac5f-5ef28b7dcb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529992292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1529992292
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2929222357
Short name T444
Test name
Test status
Simulation time 58379131 ps
CPU time 0.99 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 206180 kb
Host smart-644d29b8-0253-4b24-b1ac-0e582e73109c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929222357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2929222357
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2878457940
Short name T279
Test name
Test status
Simulation time 266934759 ps
CPU time 4.26 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:53 PM PST 24
Peak memory 210604 kb
Host smart-3a3dbb78-e1a8-4a97-82a2-15ca1af2db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878457940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2878457940
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2294259580
Short name T835
Test name
Test status
Simulation time 166717635 ps
CPU time 3.03 seconds
Started Feb 18 01:53:42 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 209104 kb
Host smart-43e34a28-e008-469a-a2d1-3334e1d64fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294259580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2294259580
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.622621225
Short name T260
Test name
Test status
Simulation time 370293770 ps
CPU time 4.24 seconds
Started Feb 18 01:53:47 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 214392 kb
Host smart-eeafad76-e4f5-47ae-bb12-ff9b05af152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622621225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.622621225
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2597476922
Short name T301
Test name
Test status
Simulation time 682599157 ps
CPU time 8.65 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 211008 kb
Host smart-3cbf7ba4-c530-4dcd-997f-17430f0f1980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597476922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2597476922
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.128008428
Short name T311
Test name
Test status
Simulation time 696767460 ps
CPU time 10.33 seconds
Started Feb 18 01:53:44 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 214340 kb
Host smart-3b2755f1-2b61-4141-9151-4a35673d8da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128008428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.128008428
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2265643018
Short name T744
Test name
Test status
Simulation time 71420963 ps
CPU time 2.7 seconds
Started Feb 18 01:53:44 PM PST 24
Finished Feb 18 01:53:49 PM PST 24
Peak memory 208452 kb
Host smart-16e5393a-cb48-4d81-bf97-40232d06c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265643018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2265643018
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1651367516
Short name T622
Test name
Test status
Simulation time 39716404 ps
CPU time 2.78 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 208628 kb
Host smart-c637d609-ae67-4bfa-bd79-edb381c62b67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651367516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1651367516
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2676591912
Short name T585
Test name
Test status
Simulation time 23286086 ps
CPU time 1.92 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 206624 kb
Host smart-a86e2852-fd88-4fdd-b2aa-018e094e6f60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676591912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2676591912
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.4213839945
Short name T879
Test name
Test status
Simulation time 224164502 ps
CPU time 2.98 seconds
Started Feb 18 01:53:48 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 208632 kb
Host smart-0b7af27b-18c9-4407-8aec-be95c5eafd51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213839945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.4213839945
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4129667931
Short name T752
Test name
Test status
Simulation time 39528732 ps
CPU time 1.96 seconds
Started Feb 18 01:53:44 PM PST 24
Finished Feb 18 01:53:48 PM PST 24
Peak memory 218068 kb
Host smart-776811d8-40be-426f-98cb-d097754edf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129667931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4129667931
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2338646074
Short name T555
Test name
Test status
Simulation time 2584664961 ps
CPU time 28.24 seconds
Started Feb 18 01:53:47 PM PST 24
Finished Feb 18 01:54:19 PM PST 24
Peak memory 208100 kb
Host smart-df7948b4-0c93-4dbe-9507-9f051e1b2768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338646074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2338646074
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3690411336
Short name T854
Test name
Test status
Simulation time 1725219335 ps
CPU time 6.59 seconds
Started Feb 18 01:53:48 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 207288 kb
Host smart-6e64057b-e5bc-44d4-974c-9861a7dc00f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690411336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3690411336
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1212872239
Short name T214
Test name
Test status
Simulation time 159293648 ps
CPU time 6.8 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 218436 kb
Host smart-3b451dba-aa43-4854-91e9-41d4966622e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212872239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1212872239
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2148407606
Short name T873
Test name
Test status
Simulation time 1513965637 ps
CPU time 12.73 seconds
Started Feb 18 01:53:44 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 211020 kb
Host smart-767e76c6-3372-4a3c-9a7f-89c24cde0dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148407606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2148407606
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1516415983
Short name T541
Test name
Test status
Simulation time 46017409 ps
CPU time 0.77 seconds
Started Feb 18 01:53:51 PM PST 24
Finished Feb 18 01:53:53 PM PST 24
Peak memory 206032 kb
Host smart-300e93cf-dbcd-462b-ae4b-219c010dd07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516415983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1516415983
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.814768771
Short name T426
Test name
Test status
Simulation time 359448102 ps
CPU time 5.34 seconds
Started Feb 18 01:53:48 PM PST 24
Finished Feb 18 01:53:56 PM PST 24
Peak memory 214484 kb
Host smart-ba4f5413-2841-4bc2-beef-17ce2e25870a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814768771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.814768771
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1081104724
Short name T65
Test name
Test status
Simulation time 550443496 ps
CPU time 2.39 seconds
Started Feb 18 01:53:47 PM PST 24
Finished Feb 18 01:53:53 PM PST 24
Peak memory 221504 kb
Host smart-d44b2733-3d9a-46ae-a4c6-3a33f78a5422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081104724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1081104724
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.602382102
Short name T853
Test name
Test status
Simulation time 96762922 ps
CPU time 4.27 seconds
Started Feb 18 01:53:47 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 214516 kb
Host smart-64aeba29-6112-4592-9ac7-4c16afe14f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602382102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.602382102
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3144279947
Short name T738
Test name
Test status
Simulation time 1058875944 ps
CPU time 4.19 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 208868 kb
Host smart-c7ce5f9b-10f4-49f0-a985-6d38225e816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144279947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3144279947
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.727316008
Short name T222
Test name
Test status
Simulation time 1728684914 ps
CPU time 13.5 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:54:11 PM PST 24
Peak memory 210672 kb
Host smart-77b36c4f-3102-4eb6-9073-587b29c4b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727316008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.727316008
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3699766013
Short name T613
Test name
Test status
Simulation time 117516744 ps
CPU time 3.25 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 207400 kb
Host smart-3f5afe59-2f36-457e-808d-f3f4d5b2d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699766013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3699766013
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2283073686
Short name T255
Test name
Test status
Simulation time 121987654 ps
CPU time 5.42 seconds
Started Feb 18 01:53:45 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 218420 kb
Host smart-b1ede362-cfbc-4d5d-8517-b92bba0c35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283073686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2283073686
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.176826439
Short name T607
Test name
Test status
Simulation time 1298140545 ps
CPU time 4.23 seconds
Started Feb 18 01:53:50 PM PST 24
Finished Feb 18 01:53:56 PM PST 24
Peak memory 208800 kb
Host smart-8af159c1-6b4c-4d71-9997-5c6e45f2a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176826439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.176826439
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3301467392
Short name T318
Test name
Test status
Simulation time 996518156 ps
CPU time 10.86 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:54:01 PM PST 24
Peak memory 208796 kb
Host smart-46433625-755a-44fb-821a-d60080e15474
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301467392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3301467392
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4140645817
Short name T137
Test name
Test status
Simulation time 357400164 ps
CPU time 4.14 seconds
Started Feb 18 01:53:42 PM PST 24
Finished Feb 18 01:53:50 PM PST 24
Peak memory 209000 kb
Host smart-b16c3a5b-b0db-4868-8504-ed2b488cb976
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140645817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4140645817
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3247174548
Short name T476
Test name
Test status
Simulation time 1633773591 ps
CPU time 32.19 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 208848 kb
Host smart-c43d2834-be66-414a-b11f-8482c9335242
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247174548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3247174548
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1735372750
Short name T826
Test name
Test status
Simulation time 90331596 ps
CPU time 1.97 seconds
Started Feb 18 01:53:51 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 207616 kb
Host smart-e47b0bd3-3d64-4cb5-9008-f60d4551a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735372750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1735372750
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1256490279
Short name T829
Test name
Test status
Simulation time 64654577 ps
CPU time 3.21 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:52 PM PST 24
Peak memory 206744 kb
Host smart-7bc41240-f739-49a8-9db5-e69070a45fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256490279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1256490279
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1668185664
Short name T123
Test name
Test status
Simulation time 152956166 ps
CPU time 9.12 seconds
Started Feb 18 01:53:47 PM PST 24
Finished Feb 18 01:54:00 PM PST 24
Peak memory 222736 kb
Host smart-7764ab4e-4410-4de1-b150-31bbeace2233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668185664 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1668185664
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4014177268
Short name T293
Test name
Test status
Simulation time 112183561 ps
CPU time 5.37 seconds
Started Feb 18 01:53:46 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 210380 kb
Host smart-6e8727be-9f00-4938-976a-2ff7dc7d1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014177268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4014177268
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2421553643
Short name T166
Test name
Test status
Simulation time 48856831 ps
CPU time 2.86 seconds
Started Feb 18 01:53:51 PM PST 24
Finished Feb 18 01:53:56 PM PST 24
Peak memory 210120 kb
Host smart-453d4853-5709-4103-9621-2d2f9bfb0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421553643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2421553643
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.521257516
Short name T791
Test name
Test status
Simulation time 13061790 ps
CPU time 0.82 seconds
Started Feb 18 01:52:33 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 206108 kb
Host smart-d8749c8c-4569-45cb-831d-0e7ce2ad3cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521257516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.521257516
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2020632355
Short name T656
Test name
Test status
Simulation time 104613490 ps
CPU time 2.1 seconds
Started Feb 18 01:52:33 PM PST 24
Finished Feb 18 01:52:36 PM PST 24
Peak memory 214464 kb
Host smart-20f57e6d-9611-44e9-b76d-d7b47d42fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020632355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2020632355
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2015624254
Short name T348
Test name
Test status
Simulation time 352039614 ps
CPU time 5.69 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 209096 kb
Host smart-49794e27-ab4d-4ed5-8631-4e96d0f555f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015624254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2015624254
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.19899879
Short name T540
Test name
Test status
Simulation time 121664885 ps
CPU time 2.35 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 206292 kb
Host smart-52df8d1f-cbdb-465e-93cf-dd0a24cee455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19899879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.19899879
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2551372151
Short name T297
Test name
Test status
Simulation time 667223866 ps
CPU time 3.99 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:46 PM PST 24
Peak memory 207956 kb
Host smart-5a526eb5-0b4b-44d6-b256-b8eda504827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551372151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2551372151
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2632448948
Short name T99
Test name
Test status
Simulation time 834724808 ps
CPU time 25.11 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:53:01 PM PST 24
Peak memory 233396 kb
Host smart-c7cf7dc2-b4b4-4f4a-9b48-783e5fc79aa0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632448948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2632448948
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3914559292
Short name T587
Test name
Test status
Simulation time 48973312 ps
CPU time 2.74 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:52:34 PM PST 24
Peak memory 207700 kb
Host smart-96083dc6-e434-411b-a10d-4c32d564f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914559292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3914559292
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2622358331
Short name T900
Test name
Test status
Simulation time 114947311 ps
CPU time 2.42 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:52:36 PM PST 24
Peak memory 206596 kb
Host smart-0648f811-d8a8-426b-b14b-7d38bc25a62e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622358331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2622358331
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2786823616
Short name T637
Test name
Test status
Simulation time 155768978 ps
CPU time 2.29 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 206768 kb
Host smart-205bf31e-f29a-4109-9dff-be733e59a3c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786823616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2786823616
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2917094722
Short name T547
Test name
Test status
Simulation time 686567038 ps
CPU time 3.55 seconds
Started Feb 18 01:52:29 PM PST 24
Finished Feb 18 01:52:33 PM PST 24
Peak memory 208876 kb
Host smart-cb399197-d1bd-465a-b2e0-f92018f2175d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917094722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2917094722
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1978360775
Short name T416
Test name
Test status
Simulation time 36304852 ps
CPU time 2.24 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:45 PM PST 24
Peak memory 207328 kb
Host smart-affe068f-4a55-428d-97fa-14e861b29a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978360775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1978360775
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3466545143
Short name T691
Test name
Test status
Simulation time 467365080 ps
CPU time 3.47 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:45 PM PST 24
Peak memory 206520 kb
Host smart-f320d773-7f62-4d41-bae7-709fcdb8310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466545143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3466545143
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.82837011
Short name T240
Test name
Test status
Simulation time 789479857 ps
CPU time 36.85 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:53:10 PM PST 24
Peak memory 216240 kb
Host smart-3c58141f-4cbb-4f87-a721-bb1ea31fd275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82837011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.82837011
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3796005849
Short name T130
Test name
Test status
Simulation time 60954597 ps
CPU time 2 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 210020 kb
Host smart-e5ee4117-4f71-4db0-85d7-071a275c3e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796005849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3796005849
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4041048030
Short name T98
Test name
Test status
Simulation time 22856931 ps
CPU time 0.75 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 206092 kb
Host smart-d9ca0226-fc44-471e-ae55-0acf26606206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041048030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4041048030
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2914318911
Short name T781
Test name
Test status
Simulation time 160684429 ps
CPU time 3.51 seconds
Started Feb 18 01:53:52 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 215260 kb
Host smart-4e8a742d-d3be-4759-9119-7da4aac64b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914318911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2914318911
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1314900208
Short name T450
Test name
Test status
Simulation time 16654931 ps
CPU time 1.43 seconds
Started Feb 18 01:53:52 PM PST 24
Finished Feb 18 01:53:57 PM PST 24
Peak memory 207440 kb
Host smart-a04c76cc-9988-4014-96ba-69b0e6b05ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314900208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1314900208
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1286651781
Short name T212
Test name
Test status
Simulation time 247948142 ps
CPU time 2.72 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:01 PM PST 24
Peak memory 220188 kb
Host smart-3aa4df9d-ec11-4ca6-a78b-aba45463f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286651781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1286651781
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.134057995
Short name T773
Test name
Test status
Simulation time 67719288 ps
CPU time 2.76 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 209832 kb
Host smart-e209ac62-d328-402f-98af-2a668860e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134057995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.134057995
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1256334230
Short name T638
Test name
Test status
Simulation time 152116011 ps
CPU time 3.29 seconds
Started Feb 18 01:53:48 PM PST 24
Finished Feb 18 01:53:54 PM PST 24
Peak memory 214396 kb
Host smart-a5f794e7-8baf-4aa4-b865-ca43685fe8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256334230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1256334230
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1716291337
Short name T567
Test name
Test status
Simulation time 48797810 ps
CPU time 2.72 seconds
Started Feb 18 01:53:52 PM PST 24
Finished Feb 18 01:53:58 PM PST 24
Peak memory 206700 kb
Host smart-afec4d91-c474-4aed-89e1-3e92c45b35ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716291337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1716291337
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2692647549
Short name T586
Test name
Test status
Simulation time 218215706 ps
CPU time 3.3 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 208304 kb
Host smart-9c84abf2-5df9-442c-a405-ac5b0e493ef3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692647549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2692647549
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1607512706
Short name T536
Test name
Test status
Simulation time 160139867 ps
CPU time 5.14 seconds
Started Feb 18 01:53:51 PM PST 24
Finished Feb 18 01:53:58 PM PST 24
Peak memory 208048 kb
Host smart-b18259fe-19af-4324-811e-80c6fda0abb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607512706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1607512706
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.362135773
Short name T686
Test name
Test status
Simulation time 95197439 ps
CPU time 4.62 seconds
Started Feb 18 01:53:49 PM PST 24
Finished Feb 18 01:53:56 PM PST 24
Peak memory 208832 kb
Host smart-ffe44a6f-0bff-4aaa-8185-2ef975be0242
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362135773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.362135773
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4156519226
Short name T388
Test name
Test status
Simulation time 37402651 ps
CPU time 2.7 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 209776 kb
Host smart-6599d6ca-c8a4-46e1-92ec-5f23b70319bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156519226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4156519226
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3401588052
Short name T443
Test name
Test status
Simulation time 2766028561 ps
CPU time 30.48 seconds
Started Feb 18 01:53:52 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 207968 kb
Host smart-754bc608-29ce-46b3-8d96-bf17333e0d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401588052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3401588052
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3263294418
Short name T239
Test name
Test status
Simulation time 945883634 ps
CPU time 8.58 seconds
Started Feb 18 01:53:55 PM PST 24
Finished Feb 18 01:54:06 PM PST 24
Peak memory 209928 kb
Host smart-82e84ec3-aefd-4929-be37-93e26c67295b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263294418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3263294418
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3473229578
Short name T367
Test name
Test status
Simulation time 725520668 ps
CPU time 19.62 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 209336 kb
Host smart-1d5e01c5-56fc-44c1-b529-48ff60fd9895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473229578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3473229578
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.825285105
Short name T504
Test name
Test status
Simulation time 7727605779 ps
CPU time 14.12 seconds
Started Feb 18 01:53:54 PM PST 24
Finished Feb 18 01:54:12 PM PST 24
Peak memory 210528 kb
Host smart-b8adfaaa-5aaa-4ac8-bca2-934052689eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825285105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.825285105
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.249220631
Short name T663
Test name
Test status
Simulation time 42887120 ps
CPU time 0.89 seconds
Started Feb 18 01:54:04 PM PST 24
Finished Feb 18 01:54:08 PM PST 24
Peak memory 206092 kb
Host smart-593b71c0-b2f5-4908-8c9d-c5d46129cee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249220631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.249220631
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2005347307
Short name T400
Test name
Test status
Simulation time 7947799022 ps
CPU time 113.73 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:55:54 PM PST 24
Peak memory 214680 kb
Host smart-5fd544b4-9ee5-4691-9723-bb3c8325b1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005347307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2005347307
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3044677627
Short name T735
Test name
Test status
Simulation time 332939467 ps
CPU time 5.72 seconds
Started Feb 18 01:53:52 PM PST 24
Finished Feb 18 01:54:01 PM PST 24
Peak memory 222476 kb
Host smart-d9aaf674-cd78-47e1-bd3b-06792a1c0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044677627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3044677627
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1619793795
Short name T653
Test name
Test status
Simulation time 32880341 ps
CPU time 1.92 seconds
Started Feb 18 01:53:54 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 209984 kb
Host smart-8224f583-f5f7-47e6-ad06-bc409a4e242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619793795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1619793795
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.404383359
Short name T87
Test name
Test status
Simulation time 259018658 ps
CPU time 7.23 seconds
Started Feb 18 01:53:55 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 208944 kb
Host smart-f815335c-2f4a-41a8-814b-c05c77e5eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404383359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.404383359
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.492356121
Short name T254
Test name
Test status
Simulation time 577165621 ps
CPU time 6.9 seconds
Started Feb 18 01:53:55 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 214476 kb
Host smart-14bdb9a7-0680-40df-a91e-e02939fac8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492356121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.492356121
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2078525012
Short name T101
Test name
Test status
Simulation time 173789525 ps
CPU time 4.59 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:04 PM PST 24
Peak memory 209980 kb
Host smart-ae11b7c3-78a9-44bc-a6a7-0b3d8f2ff826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078525012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2078525012
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.205930986
Short name T369
Test name
Test status
Simulation time 446010145 ps
CPU time 12.16 seconds
Started Feb 18 01:53:57 PM PST 24
Finished Feb 18 01:54:12 PM PST 24
Peak memory 218464 kb
Host smart-a5035b4a-26b3-4146-8cae-24f4a12c04c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205930986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.205930986
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1494499884
Short name T320
Test name
Test status
Simulation time 635785982 ps
CPU time 21.05 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:20 PM PST 24
Peak memory 208272 kb
Host smart-979a23ba-7cb7-4459-997b-419b652c56c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494499884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1494499884
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2963824954
Short name T106
Test name
Test status
Simulation time 231400919 ps
CPU time 2.91 seconds
Started Feb 18 01:53:54 PM PST 24
Finished Feb 18 01:54:00 PM PST 24
Peak memory 206704 kb
Host smart-5c03cb3d-9f5d-4f11-8635-ff6d9ea4b7e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963824954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2963824954
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3986142702
Short name T811
Test name
Test status
Simulation time 40020083 ps
CPU time 2.35 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 207120 kb
Host smart-9216e633-e4eb-4321-b360-2ed41a853982
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986142702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3986142702
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.736062684
Short name T690
Test name
Test status
Simulation time 68565769 ps
CPU time 2.22 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:01 PM PST 24
Peak memory 206792 kb
Host smart-c0f7bd2c-5b37-471b-b884-24cfb678bb64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736062684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.736062684
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3698201670
Short name T286
Test name
Test status
Simulation time 114361508 ps
CPU time 2.35 seconds
Started Feb 18 01:53:53 PM PST 24
Finished Feb 18 01:53:59 PM PST 24
Peak memory 207744 kb
Host smart-2cb4a571-e381-4d7c-bd6f-83f0202c6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698201670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3698201670
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1662453538
Short name T694
Test name
Test status
Simulation time 360938793 ps
CPU time 4.65 seconds
Started Feb 18 01:53:56 PM PST 24
Finished Feb 18 01:54:03 PM PST 24
Peak memory 208412 kb
Host smart-807d7ec1-df64-4a06-954e-a8fb743797a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662453538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1662453538
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.93627911
Short name T72
Test name
Test status
Simulation time 102214687958 ps
CPU time 141.9 seconds
Started Feb 18 01:53:57 PM PST 24
Finished Feb 18 01:56:22 PM PST 24
Peak memory 217660 kb
Host smart-3647bc55-dee6-4714-a887-3d7db0c899a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93627911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.93627911
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.906263280
Short name T512
Test name
Test status
Simulation time 276695956 ps
CPU time 4.37 seconds
Started Feb 18 01:53:58 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 209396 kb
Host smart-d3b605fa-0876-459a-ae3c-8f01d9091a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906263280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.906263280
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.552305010
Short name T184
Test name
Test status
Simulation time 299039303 ps
CPU time 1.93 seconds
Started Feb 18 01:53:54 PM PST 24
Finished Feb 18 01:54:00 PM PST 24
Peak memory 210072 kb
Host smart-271be3ad-656b-47a1-9dd6-c097f03b3876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552305010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.552305010
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.13394305
Short name T888
Test name
Test status
Simulation time 20945867 ps
CPU time 0.89 seconds
Started Feb 18 01:54:00 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 206116 kb
Host smart-faa2467f-730a-4d53-a16e-753bc9a51872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.13394305
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1066789957
Short name T313
Test name
Test status
Simulation time 155981233 ps
CPU time 8.54 seconds
Started Feb 18 01:54:01 PM PST 24
Finished Feb 18 01:54:13 PM PST 24
Peak memory 215440 kb
Host smart-8b6a0729-3d2a-4dad-97ac-dfa5dcee6110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066789957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1066789957
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2335544660
Short name T810
Test name
Test status
Simulation time 162074080 ps
CPU time 4.34 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:07 PM PST 24
Peak memory 209308 kb
Host smart-c32726c9-0921-4c7e-b646-d9c962c21121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335544660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2335544660
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3911713641
Short name T89
Test name
Test status
Simulation time 146267952 ps
CPU time 3.37 seconds
Started Feb 18 01:54:02 PM PST 24
Finished Feb 18 01:54:08 PM PST 24
Peak memory 220084 kb
Host smart-c22e35e3-4754-4c7b-8bfc-5e0835936af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911713641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3911713641
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1296206600
Short name T26
Test name
Test status
Simulation time 1101104849 ps
CPU time 8.7 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:11 PM PST 24
Peak memory 210960 kb
Host smart-14fc2615-2a16-4bbb-863f-118846bfd5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296206600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1296206600
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1904294936
Short name T43
Test name
Test status
Simulation time 99986303 ps
CPU time 4.83 seconds
Started Feb 18 01:54:01 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 209820 kb
Host smart-292ef87e-8ad7-4b7b-8d6d-01790075e6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904294936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1904294936
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.65256395
Short name T689
Test name
Test status
Simulation time 4730071234 ps
CPU time 62.07 seconds
Started Feb 18 01:53:58 PM PST 24
Finished Feb 18 01:55:03 PM PST 24
Peak memory 222728 kb
Host smart-1c0757ad-8f2a-4698-92a9-a91a52228a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65256395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.65256395
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1496726039
Short name T368
Test name
Test status
Simulation time 103751294 ps
CPU time 2.96 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:06 PM PST 24
Peak memory 206696 kb
Host smart-1839f4a5-aad4-48fc-b421-c368d89511b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496726039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1496726039
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.146302209
Short name T666
Test name
Test status
Simulation time 256312160 ps
CPU time 7.28 seconds
Started Feb 18 01:54:02 PM PST 24
Finished Feb 18 01:54:12 PM PST 24
Peak memory 207800 kb
Host smart-e99f4136-be33-4b42-b817-59975b8ba39d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146302209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.146302209
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2495463359
Short name T764
Test name
Test status
Simulation time 29192335 ps
CPU time 2.32 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 206700 kb
Host smart-20d698da-2a88-4c61-becd-743df30f1d11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495463359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2495463359
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2115191332
Short name T411
Test name
Test status
Simulation time 485045283 ps
CPU time 2.72 seconds
Started Feb 18 01:53:57 PM PST 24
Finished Feb 18 01:54:03 PM PST 24
Peak memory 207104 kb
Host smart-f2078b17-67cd-465b-8298-8d9019a1345d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115191332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2115191332
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1906939467
Short name T375
Test name
Test status
Simulation time 172291286 ps
CPU time 3.48 seconds
Started Feb 18 01:54:00 PM PST 24
Finished Feb 18 01:54:07 PM PST 24
Peak memory 210004 kb
Host smart-f8fdd15b-470e-4a29-a511-e281a5095cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906939467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1906939467
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3906604179
Short name T609
Test name
Test status
Simulation time 730178461 ps
CPU time 4.67 seconds
Started Feb 18 01:54:03 PM PST 24
Finished Feb 18 01:54:10 PM PST 24
Peak memory 207692 kb
Host smart-02b04892-6165-43fa-b8d1-f5ce6c27cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906604179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3906604179
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3049913166
Short name T315
Test name
Test status
Simulation time 3274376985 ps
CPU time 32.92 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:35 PM PST 24
Peak memory 216992 kb
Host smart-f2e5188e-c484-40db-b6e4-31d42775ed45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049913166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3049913166
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.971691464
Short name T389
Test name
Test status
Simulation time 1952056881 ps
CPU time 6.4 seconds
Started Feb 18 01:54:00 PM PST 24
Finished Feb 18 01:54:10 PM PST 24
Peak memory 214400 kb
Host smart-4ca1e8d8-ec5a-4763-aa1d-c9e05cb722c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971691464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.971691464
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2940920950
Short name T75
Test name
Test status
Simulation time 110442657 ps
CPU time 2.8 seconds
Started Feb 18 01:54:01 PM PST 24
Finished Feb 18 01:54:07 PM PST 24
Peak memory 210212 kb
Host smart-477b8fd1-3797-4756-bed1-e1d7de09df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940920950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2940920950
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3411851096
Short name T748
Test name
Test status
Simulation time 52813981 ps
CPU time 0.77 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:13 PM PST 24
Peak memory 206020 kb
Host smart-e73f00f6-89f6-4eb3-92cf-193347da3438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411851096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3411851096
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1323847274
Short name T310
Test name
Test status
Simulation time 544743006 ps
CPU time 29.49 seconds
Started Feb 18 01:54:09 PM PST 24
Finished Feb 18 01:54:43 PM PST 24
Peak memory 215648 kb
Host smart-6792fe83-f4e8-4c35-9305-4692bf91b5af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323847274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1323847274
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.373318215
Short name T21
Test name
Test status
Simulation time 106729975 ps
CPU time 4.56 seconds
Started Feb 18 01:54:08 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 207848 kb
Host smart-437f5f2c-874b-4f31-9c32-126a10de27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373318215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.373318215
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1885714738
Short name T415
Test name
Test status
Simulation time 94787687 ps
CPU time 3.47 seconds
Started Feb 18 01:54:05 PM PST 24
Finished Feb 18 01:54:13 PM PST 24
Peak memory 209384 kb
Host smart-63e454cf-d618-4c31-96e1-4571779ac3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885714738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1885714738
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2608217272
Short name T370
Test name
Test status
Simulation time 74999805 ps
CPU time 3.75 seconds
Started Feb 18 01:54:06 PM PST 24
Finished Feb 18 01:54:14 PM PST 24
Peak memory 209148 kb
Host smart-852bd9de-d9ae-46ee-8ad2-82956e93a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608217272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2608217272
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2160132892
Short name T382
Test name
Test status
Simulation time 140707238 ps
CPU time 4.84 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:20 PM PST 24
Peak memory 222620 kb
Host smart-3f78293b-1924-4882-a973-357e9d372fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160132892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2160132892
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4225483230
Short name T238
Test name
Test status
Simulation time 363808071 ps
CPU time 3.95 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 220296 kb
Host smart-3eead7b8-68ea-426d-a589-7adfcd00801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225483230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4225483230
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.51327230
Short name T757
Test name
Test status
Simulation time 591885093 ps
CPU time 5.08 seconds
Started Feb 18 01:54:05 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 210048 kb
Host smart-f130dcc3-f387-4f94-9bbf-5e926b5a4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51327230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.51327230
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3999613936
Short name T480
Test name
Test status
Simulation time 2235671623 ps
CPU time 14.63 seconds
Started Feb 18 01:54:03 PM PST 24
Finished Feb 18 01:54:20 PM PST 24
Peak memory 208060 kb
Host smart-fdc3c211-b54c-49c2-a1df-c76c00ee4816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999613936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3999613936
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.49081668
Short name T371
Test name
Test status
Simulation time 48972795 ps
CPU time 2.8 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 206788 kb
Host smart-ac73e1ad-a758-494e-9912-3ee2db954a10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49081668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.49081668
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1521722782
Short name T664
Test name
Test status
Simulation time 253647253 ps
CPU time 4.19 seconds
Started Feb 18 01:53:58 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 207216 kb
Host smart-b235ab6f-861d-46f5-a036-1e820d38ab19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521722782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1521722782
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3195471587
Short name T793
Test name
Test status
Simulation time 87624032 ps
CPU time 1.94 seconds
Started Feb 18 01:53:59 PM PST 24
Finished Feb 18 01:54:04 PM PST 24
Peak memory 206616 kb
Host smart-b1de28ed-7dad-4ba8-98e2-a9d1ededa6ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195471587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3195471587
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2479468678
Short name T325
Test name
Test status
Simulation time 81395331 ps
CPU time 1.7 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:14 PM PST 24
Peak memory 207760 kb
Host smart-7dddda9e-b940-4c61-84a4-d5a9e49bddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479468678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2479468678
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3704556871
Short name T776
Test name
Test status
Simulation time 132585577 ps
CPU time 2.64 seconds
Started Feb 18 01:54:00 PM PST 24
Finished Feb 18 01:54:06 PM PST 24
Peak memory 208372 kb
Host smart-e78a9995-52f6-43b6-b7d8-6f70390ceaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704556871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3704556871
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.167066161
Short name T893
Test name
Test status
Simulation time 148343471 ps
CPU time 4.66 seconds
Started Feb 18 01:54:06 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 208964 kb
Host smart-e9046c4f-e6d6-4941-b770-4ed27a961a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167066161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.167066161
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3608217753
Short name T60
Test name
Test status
Simulation time 5079747322 ps
CPU time 32.14 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 219996 kb
Host smart-70270adb-1041-4b02-842c-38496ca2ebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608217753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3608217753
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.632658547
Short name T797
Test name
Test status
Simulation time 21748751 ps
CPU time 0.87 seconds
Started Feb 18 01:54:09 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 206104 kb
Host smart-19b344d4-7ba7-4082-a6ff-c86a63a2a9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632658547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.632658547
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3613292861
Short name T433
Test name
Test status
Simulation time 168674404 ps
CPU time 3.42 seconds
Started Feb 18 01:54:05 PM PST 24
Finished Feb 18 01:54:13 PM PST 24
Peak memory 214468 kb
Host smart-72e64e35-934f-4022-86b0-3ac91bd4f877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613292861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3613292861
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2187737895
Short name T269
Test name
Test status
Simulation time 2798085850 ps
CPU time 4.47 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:19 PM PST 24
Peak memory 209832 kb
Host smart-3f4041d6-2e1a-4155-957a-cb6222712b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187737895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2187737895
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2545685674
Short name T84
Test name
Test status
Simulation time 401494558 ps
CPU time 3.32 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 209292 kb
Host smart-67b69c0b-eb39-4cf2-9438-6eb7c3fe2dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545685674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2545685674
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3378618387
Short name T687
Test name
Test status
Simulation time 503086701 ps
CPU time 3.66 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 210004 kb
Host smart-cef6a755-65c2-46d7-9907-654b3021a406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378618387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3378618387
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2173369887
Short name T285
Test name
Test status
Simulation time 10740715852 ps
CPU time 102.59 seconds
Started Feb 18 01:54:08 PM PST 24
Finished Feb 18 01:55:55 PM PST 24
Peak memory 222700 kb
Host smart-6fe6cb1e-95c0-487a-b473-42887a061833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173369887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2173369887
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.964166096
Short name T580
Test name
Test status
Simulation time 293897896 ps
CPU time 3.39 seconds
Started Feb 18 01:54:09 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 208580 kb
Host smart-33e98e66-b30f-47aa-a9c5-eadbc2499629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964166096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.964166096
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2094151859
Short name T847
Test name
Test status
Simulation time 45217244 ps
CPU time 2.56 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 207916 kb
Host smart-19b66e07-6e96-4c32-bcf8-714144f8857b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094151859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2094151859
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3777773312
Short name T665
Test name
Test status
Simulation time 2110327247 ps
CPU time 28.76 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:40 PM PST 24
Peak memory 208260 kb
Host smart-1b847715-7b79-433f-be68-6151c22635a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777773312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3777773312
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1068096582
Short name T751
Test name
Test status
Simulation time 6422029661 ps
CPU time 40.14 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 208540 kb
Host smart-0368f0d4-63e9-4207-897d-ddd2e7a41015
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068096582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1068096582
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3047316620
Short name T828
Test name
Test status
Simulation time 33641208 ps
CPU time 2.31 seconds
Started Feb 18 01:54:08 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 207300 kb
Host smart-35e748a8-7e8e-4837-8d7c-1257d6133643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047316620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3047316620
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3941181327
Short name T711
Test name
Test status
Simulation time 1171550841 ps
CPU time 13.66 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 208436 kb
Host smart-8afacba9-45f3-4767-a979-5494a9fc7968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941181327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3941181327
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.149819233
Short name T58
Test name
Test status
Simulation time 169507856 ps
CPU time 9.28 seconds
Started Feb 18 01:54:04 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 217104 kb
Host smart-4bb0dc5d-168b-4f80-83af-27bd37c0f24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149819233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.149819233
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2882433063
Short name T807
Test name
Test status
Simulation time 437130518 ps
CPU time 3.53 seconds
Started Feb 18 01:54:10 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 207464 kb
Host smart-ac83776b-7657-4dcf-8d58-8c34b8529b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882433063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2882433063
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.214760676
Short name T410
Test name
Test status
Simulation time 66091964 ps
CPU time 1.95 seconds
Started Feb 18 01:54:09 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 209900 kb
Host smart-6381c21b-fc48-4c5d-a53a-ec49968407e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214760676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.214760676
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3011801451
Short name T677
Test name
Test status
Simulation time 22077556 ps
CPU time 0.78 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 206008 kb
Host smart-cac1cb9d-d836-46f2-8975-44ab5e43f028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011801451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3011801451
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3320044709
Short name T407
Test name
Test status
Simulation time 58996299 ps
CPU time 4.18 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 214392 kb
Host smart-542ef695-b202-4b17-bf15-70c65dff8cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320044709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3320044709
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.945531546
Short name T743
Test name
Test status
Simulation time 2258858702 ps
CPU time 31.97 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 222992 kb
Host smart-b292b698-9ef0-4b69-96ee-8467c8a9f12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945531546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.945531546
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3491493946
Short name T830
Test name
Test status
Simulation time 122395565 ps
CPU time 3.34 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 208188 kb
Host smart-f890cbd5-d1a9-46d6-bd6f-336eea2bff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491493946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3491493946
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.476942550
Short name T774
Test name
Test status
Simulation time 7858274192 ps
CPU time 17.95 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:40 PM PST 24
Peak memory 221456 kb
Host smart-cfe11047-9042-49e9-ab87-ff284558b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476942550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.476942550
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1939202432
Short name T775
Test name
Test status
Simulation time 334977438 ps
CPU time 3.09 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:21 PM PST 24
Peak memory 214492 kb
Host smart-e60000e6-208e-4a8d-b032-61cbae7ae4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939202432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1939202432
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2049803647
Short name T392
Test name
Test status
Simulation time 652560976 ps
CPU time 4.93 seconds
Started Feb 18 01:54:08 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 207600 kb
Host smart-6e3387ba-aa99-497c-b5f5-9415daffe5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049803647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2049803647
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4232759464
Short name T717
Test name
Test status
Simulation time 1145067573 ps
CPU time 21.54 seconds
Started Feb 18 01:54:05 PM PST 24
Finished Feb 18 01:54:32 PM PST 24
Peak memory 207708 kb
Host smart-d975f6b2-ec6d-45e4-93aa-faf8dadfe048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232759464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4232759464
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2633054043
Short name T813
Test name
Test status
Simulation time 1141266119 ps
CPU time 37.77 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 208316 kb
Host smart-196280bf-a299-4907-bb85-2c73d110fcc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633054043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2633054043
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4129831015
Short name T473
Test name
Test status
Simulation time 87200637 ps
CPU time 3.08 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 206780 kb
Host smart-350c056e-d10f-4206-ab3e-0a33e7486ace
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129831015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4129831015
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1595878105
Short name T629
Test name
Test status
Simulation time 438259733 ps
CPU time 14.19 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 208228 kb
Host smart-25d3d6ab-64c4-4d4a-983f-17e0e1f0ab3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595878105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1595878105
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1435397330
Short name T639
Test name
Test status
Simulation time 671904762 ps
CPU time 16.55 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:38 PM PST 24
Peak memory 208692 kb
Host smart-9db0ecd9-2ea2-483a-8fc9-ae8a71ac36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435397330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1435397330
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.827228936
Short name T562
Test name
Test status
Simulation time 2284419345 ps
CPU time 3.6 seconds
Started Feb 18 01:54:07 PM PST 24
Finished Feb 18 01:54:15 PM PST 24
Peak memory 208440 kb
Host smart-50372065-bd58-43c2-82e6-5b932f0abced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827228936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.827228936
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1859162246
Short name T840
Test name
Test status
Simulation time 2077089259 ps
CPU time 41.44 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 214564 kb
Host smart-d95c3766-f985-46e1-b86b-f26715f570e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859162246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1859162246
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3558536010
Short name T155
Test name
Test status
Simulation time 56493371 ps
CPU time 2.17 seconds
Started Feb 18 01:54:12 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 210124 kb
Host smart-d244c86d-5988-4a4b-a402-ffd1bfd0aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558536010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3558536010
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1719861205
Short name T616
Test name
Test status
Simulation time 73966989 ps
CPU time 0.85 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 206088 kb
Host smart-eefb1b06-26a1-4b03-9140-b3391d601654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719861205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1719861205
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3351534826
Short name T750
Test name
Test status
Simulation time 33823100 ps
CPU time 2.84 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 214480 kb
Host smart-3c29f09d-626b-4d6b-9b92-3f89a8e56a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351534826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3351534826
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2181127564
Short name T534
Test name
Test status
Simulation time 762869480 ps
CPU time 5.51 seconds
Started Feb 18 01:54:15 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 218264 kb
Host smart-1d92dd97-ffc1-420c-b15b-3af64d75f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181127564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2181127564
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4166472927
Short name T889
Test name
Test status
Simulation time 35201812 ps
CPU time 2.08 seconds
Started Feb 18 01:54:15 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 209356 kb
Host smart-3c7e475d-89c4-4180-967c-2275e27b3f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166472927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4166472927
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1627223254
Short name T844
Test name
Test status
Simulation time 364467534 ps
CPU time 7.62 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 222636 kb
Host smart-e90e2282-aecd-484f-9ca9-5b17d019552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627223254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1627223254
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2053836071
Short name T495
Test name
Test status
Simulation time 57199028 ps
CPU time 3.42 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 209124 kb
Host smart-76b89e87-e399-44c5-85a7-df1f0f091325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053836071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2053836071
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3718257114
Short name T133
Test name
Test status
Simulation time 350258076 ps
CPU time 4.67 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 207968 kb
Host smart-34f05368-7527-4ed0-8f7e-980f1ffa2c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718257114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3718257114
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1853173668
Short name T881
Test name
Test status
Simulation time 1610158135 ps
CPU time 22.07 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:46 PM PST 24
Peak memory 208652 kb
Host smart-1bcde68a-d8f6-4f23-83f4-709c1b1c8df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853173668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1853173668
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3669769555
Short name T700
Test name
Test status
Simulation time 1161359261 ps
CPU time 8.37 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 208360 kb
Host smart-5d27c42c-a4fc-415b-97f9-8e1d1e827f05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669769555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3669769555
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.528323854
Short name T519
Test name
Test status
Simulation time 383017885 ps
CPU time 3.25 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 206612 kb
Host smart-8a5ea00f-136e-4921-8c4b-7fb904947c3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528323854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.528323854
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2985178620
Short name T494
Test name
Test status
Simulation time 99135333 ps
CPU time 2.97 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 208032 kb
Host smart-b068bdf8-93e3-4e98-bb32-aeb3f8cd5580
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985178620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2985178620
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2786864109
Short name T412
Test name
Test status
Simulation time 936826615 ps
CPU time 3.96 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:24 PM PST 24
Peak memory 209928 kb
Host smart-bc12375c-0ecd-4f87-a767-9cbd7e83e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786864109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2786864109
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1408205769
Short name T584
Test name
Test status
Simulation time 422152603 ps
CPU time 5.48 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:21 PM PST 24
Peak memory 206608 kb
Host smart-d30c6901-4f53-4653-8a16-7c2a922edc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408205769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1408205769
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1146658949
Short name T265
Test name
Test status
Simulation time 424046969 ps
CPU time 4.98 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 218468 kb
Host smart-11afee42-23c2-409a-bb04-eecd9fefb7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146658949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1146658949
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.4239054450
Short name T132
Test name
Test status
Simulation time 430697437 ps
CPU time 13.92 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 222796 kb
Host smart-0dc41074-1cad-4610-b477-1ec5f4471342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239054450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.4239054450
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2711941812
Short name T131
Test name
Test status
Simulation time 36440070 ps
CPU time 1.89 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:22 PM PST 24
Peak memory 209796 kb
Host smart-10c2b6f3-b923-4e5c-9778-d4776d2bf8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711941812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2711941812
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1181684386
Short name T761
Test name
Test status
Simulation time 36973469 ps
CPU time 0.82 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:21 PM PST 24
Peak memory 205796 kb
Host smart-cb329a02-d814-4015-b44a-36e4b78cbcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181684386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1181684386
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4025663183
Short name T242
Test name
Test status
Simulation time 67227210 ps
CPU time 4.08 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 214496 kb
Host smart-3148298b-e091-4a04-8ccb-34dc2ced0373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025663183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4025663183
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2072596302
Short name T211
Test name
Test status
Simulation time 102509861 ps
CPU time 1.69 seconds
Started Feb 18 01:54:12 PM PST 24
Finished Feb 18 01:54:19 PM PST 24
Peak memory 207120 kb
Host smart-8078fc2c-7dda-433e-a682-9a338989d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072596302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2072596302
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1402165818
Short name T359
Test name
Test status
Simulation time 304943155 ps
CPU time 4.94 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 222016 kb
Host smart-6df43a7c-4451-4b45-93f3-2b018769671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402165818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1402165818
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3564631172
Short name T594
Test name
Test status
Simulation time 37956381 ps
CPU time 2.16 seconds
Started Feb 18 01:54:11 PM PST 24
Finished Feb 18 01:54:18 PM PST 24
Peak memory 208452 kb
Host smart-17b25359-7563-4793-b009-4a59846aec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564631172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3564631172
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2203356028
Short name T258
Test name
Test status
Simulation time 774448234 ps
CPU time 27.28 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 209800 kb
Host smart-cf13bc02-567d-47b3-b755-24d611f2849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203356028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2203356028
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3798672663
Short name T852
Test name
Test status
Simulation time 203185818 ps
CPU time 3.48 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 208076 kb
Host smart-27788d25-ad85-4a01-993d-d8e044c0517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798672663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3798672663
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.218774421
Short name T294
Test name
Test status
Simulation time 297191424 ps
CPU time 4.42 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:24 PM PST 24
Peak memory 208700 kb
Host smart-c09c2ef0-957a-4dd5-b87a-9a6bb6fca3ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218774421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.218774421
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3135496300
Short name T372
Test name
Test status
Simulation time 107881379 ps
CPU time 3.92 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 206764 kb
Host smart-860443c7-7cc8-4320-bdac-6522ba308628
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135496300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3135496300
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2942846347
Short name T792
Test name
Test status
Simulation time 62604333 ps
CPU time 3.09 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 206860 kb
Host smart-994a0f82-f21a-4158-9d88-4ac56f3a44e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942846347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2942846347
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1468525632
Short name T699
Test name
Test status
Simulation time 80289783 ps
CPU time 1.83 seconds
Started Feb 18 01:54:13 PM PST 24
Finished Feb 18 01:54:19 PM PST 24
Peak memory 209348 kb
Host smart-efbb10ad-98f5-4de7-9675-814a47830b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468525632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1468525632
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3881689595
Short name T732
Test name
Test status
Simulation time 746833397 ps
CPU time 5.28 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 208428 kb
Host smart-b6b70004-a565-4465-9187-52d4612dc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881689595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3881689595
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.869496813
Short name T674
Test name
Test status
Simulation time 136191355 ps
CPU time 3.87 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 216128 kb
Host smart-2ad3e105-104a-4b78-b820-8dd1cb34a055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869496813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.869496813
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2846297886
Short name T478
Test name
Test status
Simulation time 258271457 ps
CPU time 4.58 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:32 PM PST 24
Peak memory 209560 kb
Host smart-947cbfb0-c29c-4417-9b8e-f41fc28b5cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846297886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2846297886
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2675730955
Short name T124
Test name
Test status
Simulation time 425870237 ps
CPU time 2.93 seconds
Started Feb 18 01:54:18 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 209924 kb
Host smart-31076746-bf8f-485b-b6f5-d7833b82a08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675730955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2675730955
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1622789799
Short name T702
Test name
Test status
Simulation time 46320478 ps
CPU time 0.74 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 206040 kb
Host smart-94b0b194-139d-4a46-aa57-fa9cae95fa71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622789799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1622789799
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1719994670
Short name T839
Test name
Test status
Simulation time 148794807 ps
CPU time 2.45 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 209976 kb
Host smart-1376497e-077c-4059-a387-57083c65a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719994670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1719994670
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1391994391
Short name T305
Test name
Test status
Simulation time 597847850 ps
CPU time 7.75 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:32 PM PST 24
Peak memory 209792 kb
Host smart-0e01e4c6-b112-4ff5-9f86-bc2158931939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391994391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1391994391
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3371955520
Short name T510
Test name
Test status
Simulation time 69736988 ps
CPU time 4.12 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:30 PM PST 24
Peak memory 208944 kb
Host smart-293084de-d0a9-48f0-9315-fe759237c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371955520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3371955520
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3347957672
Short name T217
Test name
Test status
Simulation time 2297530692 ps
CPU time 10.43 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:35 PM PST 24
Peak memory 211428 kb
Host smart-63a7a0c0-0959-42b0-b0c0-b37ffeb7c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347957672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3347957672
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2534578216
Short name T64
Test name
Test status
Simulation time 102688169 ps
CPU time 4.9 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 209504 kb
Host smart-7814f1e1-acd3-4c92-8a95-0c3d25264432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534578216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2534578216
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1873975123
Short name T589
Test name
Test status
Simulation time 47200921 ps
CPU time 3.47 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 208308 kb
Host smart-976cd99a-b182-48b1-a5a2-1c3ca273a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873975123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1873975123
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.462003923
Short name T721
Test name
Test status
Simulation time 297115453 ps
CPU time 3.13 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 206532 kb
Host smart-1c1d9040-d544-4529-8eca-d29e316887d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462003923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.462003923
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2750793128
Short name T396
Test name
Test status
Simulation time 111864986 ps
CPU time 2.6 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 206652 kb
Host smart-c5ecebfa-3362-4af2-bfe3-5dab4aad723e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750793128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2750793128
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1910313421
Short name T675
Test name
Test status
Simulation time 128255137 ps
CPU time 3.37 seconds
Started Feb 18 01:54:22 PM PST 24
Finished Feb 18 01:54:30 PM PST 24
Peak memory 208412 kb
Host smart-6f7ac09e-6f1c-4d29-bc78-5b112a1094c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910313421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1910313421
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.561323769
Short name T650
Test name
Test status
Simulation time 255231370 ps
CPU time 3.34 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 208712 kb
Host smart-8536b761-6326-45b3-bbb4-ff372ae4ce84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561323769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.561323769
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3405433772
Short name T287
Test name
Test status
Simulation time 75014063 ps
CPU time 3.65 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 209664 kb
Host smart-6a48b43a-8415-47e0-9cea-23150c7d9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405433772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3405433772
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.699921042
Short name T418
Test name
Test status
Simulation time 237153801 ps
CPU time 3.03 seconds
Started Feb 18 01:54:14 PM PST 24
Finished Feb 18 01:54:23 PM PST 24
Peak memory 208460 kb
Host smart-5ef54644-f1a8-4b0b-b339-230cb4ed3d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699921042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.699921042
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1389722491
Short name T894
Test name
Test status
Simulation time 148017342 ps
CPU time 6.82 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 218412 kb
Host smart-22a7b408-77fe-4ff0-9f68-b9d0a3ad3732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389722491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1389722491
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.35690404
Short name T111
Test name
Test status
Simulation time 108859390 ps
CPU time 3.48 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 209844 kb
Host smart-be33758e-2797-413b-91d4-67204f477e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35690404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.35690404
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3966036576
Short name T777
Test name
Test status
Simulation time 221229260 ps
CPU time 1.07 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 206204 kb
Host smart-2e779e27-e193-44a1-ae67-e3a9eaab1ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966036576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3966036576
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3675218628
Short name T249
Test name
Test status
Simulation time 285364697 ps
CPU time 10.01 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 215480 kb
Host smart-983c4594-23a6-4702-9ccf-c39b4b3f9177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675218628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3675218628
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2227309999
Short name T20
Test name
Test status
Simulation time 63829573 ps
CPU time 3.56 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 221804 kb
Host smart-b5a990e9-b230-453a-88f3-b2ef43e5bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227309999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2227309999
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3954249648
Short name T366
Test name
Test status
Simulation time 405818985 ps
CPU time 3.02 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 207452 kb
Host smart-51994065-c078-4742-be59-0edbb1a2db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954249648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3954249648
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3963366281
Short name T77
Test name
Test status
Simulation time 78792868 ps
CPU time 3.78 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:30 PM PST 24
Peak memory 208660 kb
Host smart-cdc644ff-0aa9-4cc1-b4f8-22df7856d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963366281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3963366281
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3998256264
Short name T48
Test name
Test status
Simulation time 227800149 ps
CPU time 5.98 seconds
Started Feb 18 01:54:20 PM PST 24
Finished Feb 18 01:54:31 PM PST 24
Peak memory 214424 kb
Host smart-ab4f604c-8db0-4536-948c-aeebc12fb056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998256264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3998256264
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3844201647
Short name T398
Test name
Test status
Simulation time 60167506 ps
CPU time 4.03 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 208424 kb
Host smart-a899b4a3-2295-42c3-a669-e836022a2d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844201647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3844201647
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.641417947
Short name T822
Test name
Test status
Simulation time 140305199 ps
CPU time 4.86 seconds
Started Feb 18 01:54:18 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 207508 kb
Host smart-2d273fdf-a91f-4370-9b84-73d81533e04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641417947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.641417947
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3701928283
Short name T860
Test name
Test status
Simulation time 56417065 ps
CPU time 3.18 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 208492 kb
Host smart-3a173251-a4b2-44cf-bab1-2b5bc1e45956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701928283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3701928283
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3923309343
Short name T861
Test name
Test status
Simulation time 45637167 ps
CPU time 2.78 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:30 PM PST 24
Peak memory 206772 kb
Host smart-6df787fa-858f-40c4-a0a4-3a8f2c191639
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923309343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3923309343
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1911006619
Short name T460
Test name
Test status
Simulation time 92310486 ps
CPU time 2.31 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 207832 kb
Host smart-7db94e5b-7d5f-4e6e-91f3-04ba5503c2f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911006619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1911006619
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1693632575
Short name T414
Test name
Test status
Simulation time 259881242 ps
CPU time 7.26 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:33 PM PST 24
Peak memory 208400 kb
Host smart-651d067a-c390-4c3b-8f72-165fdee01056
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693632575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1693632575
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1725550577
Short name T693
Test name
Test status
Simulation time 128093703 ps
CPU time 3.94 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 214364 kb
Host smart-9bb090f8-86fc-434f-872d-e60f57c80870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725550577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1725550577
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3933533250
Short name T446
Test name
Test status
Simulation time 64046395 ps
CPU time 3.1 seconds
Started Feb 18 01:54:17 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 208248 kb
Host smart-6ab44efb-c061-47e9-8daa-4662eb8b8650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933533250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3933533250
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3968736314
Short name T229
Test name
Test status
Simulation time 7769986413 ps
CPU time 41.65 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 217448 kb
Host smart-37e99b30-8fc9-4c83-aad1-bb724fe7a596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968736314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3968736314
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1931953651
Short name T867
Test name
Test status
Simulation time 196709054 ps
CPU time 6.43 seconds
Started Feb 18 01:54:23 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 218420 kb
Host smart-1f0a7664-fab7-4348-871e-1ac2335fc085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931953651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1931953651
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2969439008
Short name T403
Test name
Test status
Simulation time 109631480 ps
CPU time 1.84 seconds
Started Feb 18 01:54:19 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 209772 kb
Host smart-f2ffd060-85b2-4edc-afc3-93eb04f4622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969439008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2969439008
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3492371293
Short name T719
Test name
Test status
Simulation time 39078535 ps
CPU time 0.87 seconds
Started Feb 18 01:52:36 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 206108 kb
Host smart-54b53e69-5196-4fd2-8652-4ab2521309ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492371293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3492371293
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3029009389
Short name T434
Test name
Test status
Simulation time 289209907 ps
CPU time 3.69 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:40 PM PST 24
Peak memory 214532 kb
Host smart-9ceceaaa-cc2f-48e5-88bc-634212191cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029009389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3029009389
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2857277200
Short name T10
Test name
Test status
Simulation time 193763390 ps
CPU time 3.14 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:45 PM PST 24
Peak memory 214688 kb
Host smart-dc877c21-13ca-4b06-b68b-f7224df2ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857277200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2857277200
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.946580620
Short name T380
Test name
Test status
Simulation time 85603764 ps
CPU time 1.61 seconds
Started Feb 18 01:52:46 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 208044 kb
Host smart-3f429dec-0665-4f85-b571-83303183242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946580620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.946580620
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2909077251
Short name T628
Test name
Test status
Simulation time 36802682 ps
CPU time 2.72 seconds
Started Feb 18 01:52:38 PM PST 24
Finished Feb 18 01:52:41 PM PST 24
Peak memory 208972 kb
Host smart-7eb8543d-edd1-4940-b5ee-55247b445536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909077251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2909077251
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1424259274
Short name T770
Test name
Test status
Simulation time 64225264 ps
CPU time 2.72 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:52:38 PM PST 24
Peak memory 218264 kb
Host smart-34b2b0cd-f388-4939-84f0-b0c6f0190479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424259274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1424259274
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3071973812
Short name T335
Test name
Test status
Simulation time 272636129 ps
CPU time 7.9 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:52:57 PM PST 24
Peak memory 209864 kb
Host smart-14345b2e-066b-4892-975b-3e2bf29c9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071973812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3071973812
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2528275994
Short name T11
Test name
Test status
Simulation time 6512883766 ps
CPU time 32.72 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 231184 kb
Host smart-fadd1acd-27ef-4c51-9630-74af0839480e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528275994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2528275994
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3839444719
Short name T571
Test name
Test status
Simulation time 1401464673 ps
CPU time 14.25 seconds
Started Feb 18 01:52:31 PM PST 24
Finished Feb 18 01:52:47 PM PST 24
Peak memory 208240 kb
Host smart-9961128f-c43e-4a1d-a644-da0a7a84d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839444719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3839444719
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1799627601
Short name T542
Test name
Test status
Simulation time 1435340495 ps
CPU time 42.07 seconds
Started Feb 18 01:52:34 PM PST 24
Finished Feb 18 01:53:17 PM PST 24
Peak memory 208436 kb
Host smart-29fe9e6d-ef34-4b61-b9db-605113b80133
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799627601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1799627601
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3250801085
Short name T390
Test name
Test status
Simulation time 2177625033 ps
CPU time 33.9 seconds
Started Feb 18 01:52:30 PM PST 24
Finished Feb 18 01:53:06 PM PST 24
Peak memory 208592 kb
Host smart-97226d48-5af4-45b6-945e-c4d1af6e8769
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250801085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3250801085
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2857010253
Short name T710
Test name
Test status
Simulation time 21763698 ps
CPU time 1.87 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 206724 kb
Host smart-44a048bf-f3e8-4969-ac88-c77c8f182d7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857010253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2857010253
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2911159658
Short name T220
Test name
Test status
Simulation time 199378164 ps
CPU time 2.98 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:46 PM PST 24
Peak memory 209932 kb
Host smart-1a67ec89-5491-4fa2-b0a0-6b794dc05926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911159658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2911159658
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2579426949
Short name T755
Test name
Test status
Simulation time 44106586 ps
CPU time 1.86 seconds
Started Feb 18 01:52:32 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 206620 kb
Host smart-f3173b7c-dba0-42aa-ab80-c72376e7cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579426949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2579426949
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3600780854
Short name T213
Test name
Test status
Simulation time 22441700327 ps
CPU time 57.58 seconds
Started Feb 18 01:52:38 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 209072 kb
Host smart-358a5490-e4c8-4d9e-ab87-d4079cbec06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600780854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3600780854
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2199434143
Short name T49
Test name
Test status
Simulation time 37065421 ps
CPU time 1.36 seconds
Started Feb 18 01:52:37 PM PST 24
Finished Feb 18 01:52:40 PM PST 24
Peak memory 209528 kb
Host smart-d8b6ba8b-f503-4047-8fcb-38a3301df9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199434143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2199434143
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.150332423
Short name T712
Test name
Test status
Simulation time 42474505 ps
CPU time 0.72 seconds
Started Feb 18 01:54:32 PM PST 24
Finished Feb 18 01:54:35 PM PST 24
Peak memory 206092 kb
Host smart-91148fbd-2151-4a2a-809d-26f4ac55aae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150332423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.150332423
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3112155297
Short name T863
Test name
Test status
Simulation time 893296980 ps
CPU time 24.11 seconds
Started Feb 18 01:54:31 PM PST 24
Finished Feb 18 01:54:58 PM PST 24
Peak memory 209856 kb
Host smart-b99b065b-5a6a-446d-86b2-520c050e5ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112155297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3112155297
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3187481356
Short name T343
Test name
Test status
Simulation time 3907686950 ps
CPU time 37.44 seconds
Started Feb 18 01:54:29 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 222536 kb
Host smart-115c292d-7f48-4084-abbd-c1add1f3aea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187481356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3187481356
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3287474525
Short name T88
Test name
Test status
Simulation time 1013840509 ps
CPU time 6.59 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 212096 kb
Host smart-a71baebe-6f77-4b0b-a6fa-b328ef6110da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287474525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3287474525
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.17986435
Short name T228
Test name
Test status
Simulation time 51380963 ps
CPU time 2.59 seconds
Started Feb 18 01:54:26 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 215136 kb
Host smart-a7909361-9b9c-4ca3-af5d-e6221a89ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17986435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.17986435
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2110946881
Short name T800
Test name
Test status
Simulation time 71656039 ps
CPU time 3.55 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 207736 kb
Host smart-bf6cf5f3-f6d2-4516-8a59-b52a7577b44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110946881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2110946881
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.712279551
Short name T334
Test name
Test status
Simulation time 207751391 ps
CPU time 3.02 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 208276 kb
Host smart-b9537595-fb97-4980-a0a7-da42f8e810c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712279551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.712279551
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.440402255
Short name T378
Test name
Test status
Simulation time 25635570 ps
CPU time 2.05 seconds
Started Feb 18 01:54:18 PM PST 24
Finished Feb 18 01:54:26 PM PST 24
Peak memory 206884 kb
Host smart-95098c1e-c92e-41c6-9ac4-f23c28409472
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440402255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.440402255
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1254042217
Short name T252
Test name
Test status
Simulation time 135854394 ps
CPU time 3.36 seconds
Started Feb 18 01:54:21 PM PST 24
Finished Feb 18 01:54:29 PM PST 24
Peak memory 206564 kb
Host smart-88cf8e27-b59f-426a-82de-5c950d2d6883
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254042217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1254042217
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2965202784
Short name T676
Test name
Test status
Simulation time 217615723 ps
CPU time 2.98 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 206812 kb
Host smart-064e2aae-bbec-4b8a-a2e1-987b30f6f192
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965202784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2965202784
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.278178222
Short name T203
Test name
Test status
Simulation time 34117524 ps
CPU time 2.42 seconds
Started Feb 18 01:54:31 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 207068 kb
Host smart-de69c5ec-6aa7-4ee6-9ec9-84a830cfc139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278178222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.278178222
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3082316756
Short name T763
Test name
Test status
Simulation time 48222975 ps
CPU time 2.54 seconds
Started Feb 18 01:54:16 PM PST 24
Finished Feb 18 01:54:24 PM PST 24
Peak memory 206676 kb
Host smart-43d155db-f660-4b6d-b413-0780235a7a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082316756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3082316756
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3181194175
Short name T511
Test name
Test status
Simulation time 160962970 ps
CPU time 3 seconds
Started Feb 18 01:54:32 PM PST 24
Finished Feb 18 01:54:38 PM PST 24
Peak memory 207628 kb
Host smart-bfcba7fd-9ee7-4a1d-afd9-5387e268c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181194175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3181194175
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3480840123
Short name T598
Test name
Test status
Simulation time 84659010 ps
CPU time 3.47 seconds
Started Feb 18 01:54:35 PM PST 24
Finished Feb 18 01:54:41 PM PST 24
Peak memory 210044 kb
Host smart-d41164eb-9730-4b49-a03e-529086ba3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480840123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3480840123
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2851451770
Short name T805
Test name
Test status
Simulation time 13207777 ps
CPU time 0.92 seconds
Started Feb 18 01:54:32 PM PST 24
Finished Feb 18 01:54:35 PM PST 24
Peak memory 206040 kb
Host smart-a273e886-55e4-4c70-a564-baf4711d9e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851451770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2851451770
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3817719661
Short name T317
Test name
Test status
Simulation time 518705489 ps
CPU time 15.43 seconds
Started Feb 18 01:54:31 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 215348 kb
Host smart-c3523892-6ee5-4559-b36c-9ff2d1bc2ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817719661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3817719661
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2614711689
Short name T823
Test name
Test status
Simulation time 49364802 ps
CPU time 2.43 seconds
Started Feb 18 01:54:26 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 219512 kb
Host smart-fe3d7608-0138-4361-b718-debb8a07005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614711689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2614711689
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2650651052
Short name T886
Test name
Test status
Simulation time 3869379178 ps
CPU time 13.72 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:54:50 PM PST 24
Peak memory 208952 kb
Host smart-e9b0edb2-c518-419b-aba6-5d55e5d4e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650651052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2650651052
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2900333049
Short name T91
Test name
Test status
Simulation time 397678578 ps
CPU time 4.27 seconds
Started Feb 18 01:54:38 PM PST 24
Finished Feb 18 01:54:44 PM PST 24
Peak memory 209112 kb
Host smart-01ef6b6b-1a5d-4d70-8ffa-d17053fc5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900333049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2900333049
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.341549782
Short name T627
Test name
Test status
Simulation time 119479298 ps
CPU time 5.18 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:54:41 PM PST 24
Peak memory 211612 kb
Host smart-cf066ea2-70fc-4af7-ba19-422e75bdeab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341549782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.341549782
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.258040508
Short name T651
Test name
Test status
Simulation time 36928975 ps
CPU time 2.4 seconds
Started Feb 18 01:54:31 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 214412 kb
Host smart-f671373f-963f-4a0a-b71b-5b8fd6b445ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258040508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.258040508
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.30865404
Short name T394
Test name
Test status
Simulation time 168205374 ps
CPU time 5.7 seconds
Started Feb 18 01:54:34 PM PST 24
Finished Feb 18 01:54:43 PM PST 24
Peak memory 207988 kb
Host smart-ac00ef22-73d3-4755-a20d-67cea70526d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30865404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.30865404
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.995752207
Short name T291
Test name
Test status
Simulation time 72148054 ps
CPU time 2.81 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:48 PM PST 24
Peak memory 206540 kb
Host smart-f8f62f70-0e36-4cab-bb75-e823a6183662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995752207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.995752207
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4158933050
Short name T533
Test name
Test status
Simulation time 3966762709 ps
CPU time 79.96 seconds
Started Feb 18 01:54:38 PM PST 24
Finished Feb 18 01:55:59 PM PST 24
Peak memory 208264 kb
Host smart-e74e3da8-7f5f-449e-9b25-d8b4e39959fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158933050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4158933050
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3956515468
Short name T344
Test name
Test status
Simulation time 52123121 ps
CPU time 3.11 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:54:39 PM PST 24
Peak memory 207952 kb
Host smart-c3267197-19a7-4365-87eb-54fd716434de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956515468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3956515468
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2003417497
Short name T80
Test name
Test status
Simulation time 484296748 ps
CPU time 6.06 seconds
Started Feb 18 01:54:34 PM PST 24
Finished Feb 18 01:54:43 PM PST 24
Peak memory 207812 kb
Host smart-1a20b7a3-a6f2-407d-b712-062cda7aba11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003417497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2003417497
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3184679886
Short name T833
Test name
Test status
Simulation time 271029509 ps
CPU time 2.16 seconds
Started Feb 18 01:54:26 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 209828 kb
Host smart-6659629a-35bd-4e11-afd6-d40eb4ae453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184679886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3184679886
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.461681735
Short name T631
Test name
Test status
Simulation time 25117964 ps
CPU time 1.7 seconds
Started Feb 18 01:54:35 PM PST 24
Finished Feb 18 01:54:39 PM PST 24
Peak memory 206556 kb
Host smart-6a201d6b-2c0a-4c13-9e21-d200220536a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461681735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.461681735
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.644476788
Short name T326
Test name
Test status
Simulation time 784480890 ps
CPU time 6.24 seconds
Started Feb 18 01:54:32 PM PST 24
Finished Feb 18 01:54:41 PM PST 24
Peak memory 210008 kb
Host smart-5c6e84a3-83d6-4109-9244-f520681c3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644476788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.644476788
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3150770869
Short name T122
Test name
Test status
Simulation time 620810436 ps
CPU time 2.74 seconds
Started Feb 18 01:54:36 PM PST 24
Finished Feb 18 01:54:41 PM PST 24
Peak memory 210288 kb
Host smart-05d1c732-0b53-42d6-a7ff-814ad5429ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150770869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3150770869
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2248632048
Short name T447
Test name
Test status
Simulation time 150141905 ps
CPU time 0.92 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 206128 kb
Host smart-0201513a-72b5-47b2-84a2-52aa7d185179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248632048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2248632048
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1200758593
Short name T872
Test name
Test status
Simulation time 73517896 ps
CPU time 1.95 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 210044 kb
Host smart-56aa2bd5-b2b3-4c02-9978-18de01b8e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200758593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1200758593
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2488448454
Short name T658
Test name
Test status
Simulation time 466642005 ps
CPU time 2.98 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 209516 kb
Host smart-e90e3010-e47a-4550-ba33-7bfbaac966b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488448454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2488448454
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1380092693
Short name T321
Test name
Test status
Simulation time 60280013 ps
CPU time 3.48 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:54:46 PM PST 24
Peak memory 219660 kb
Host smart-c983232e-fd29-4d0e-9acd-fd27ced2b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380092693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1380092693
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.782111833
Short name T459
Test name
Test status
Simulation time 149554336 ps
CPU time 3.67 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 209904 kb
Host smart-24e22364-3da4-4575-a0c0-be3cd7e07f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782111833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.782111833
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.428228706
Short name T771
Test name
Test status
Simulation time 179354196 ps
CPU time 5.29 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 214452 kb
Host smart-13362423-037d-4388-86f3-d2509a643dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428228706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.428228706
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3030926957
Short name T668
Test name
Test status
Simulation time 31144506 ps
CPU time 2.22 seconds
Started Feb 18 01:54:28 PM PST 24
Finished Feb 18 01:54:34 PM PST 24
Peak memory 208348 kb
Host smart-540a5902-5389-43d8-b5f6-352e37b317e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030926957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3030926957
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1308589617
Short name T623
Test name
Test status
Simulation time 108968551 ps
CPU time 3.25 seconds
Started Feb 18 01:54:38 PM PST 24
Finished Feb 18 01:54:42 PM PST 24
Peak memory 208460 kb
Host smart-908ba74d-8172-4615-8fc0-74dd59ff9394
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308589617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1308589617
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.128106135
Short name T515
Test name
Test status
Simulation time 3045531173 ps
CPU time 16.4 seconds
Started Feb 18 01:54:33 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 207884 kb
Host smart-7d53733b-54ba-48d8-b986-d19697be0550
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128106135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.128106135
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1613301307
Short name T678
Test name
Test status
Simulation time 211021424 ps
CPU time 3.11 seconds
Started Feb 18 01:54:25 PM PST 24
Finished Feb 18 01:54:33 PM PST 24
Peak memory 208480 kb
Host smart-1e04acbd-abb0-46c5-a91a-0df2000bc455
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613301307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1613301307
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2181381825
Short name T309
Test name
Test status
Simulation time 2633086578 ps
CPU time 12.24 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 208940 kb
Host smart-95e2defa-576a-4773-a293-f973b0281b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181381825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2181381825
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.434355610
Short name T464
Test name
Test status
Simulation time 88606765 ps
CPU time 3.64 seconds
Started Feb 18 01:54:28 PM PST 24
Finished Feb 18 01:54:36 PM PST 24
Peak memory 206504 kb
Host smart-384ab5f6-b170-4cbd-9a17-d05f540727fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434355610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.434355610
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.324403531
Short name T419
Test name
Test status
Simulation time 415798293 ps
CPU time 5.1 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 209208 kb
Host smart-4820ec79-318d-4684-948a-1e40f13f8dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324403531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.324403531
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.154975888
Short name T201
Test name
Test status
Simulation time 418114868 ps
CPU time 3.41 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:45 PM PST 24
Peak memory 210488 kb
Host smart-73b7d54a-bd09-4c2e-a5e7-e248745ebc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154975888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.154975888
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4026284851
Short name T669
Test name
Test status
Simulation time 31588066 ps
CPU time 0.79 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 206112 kb
Host smart-273ca7da-03cc-4823-b85a-1c11859aad51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026284851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4026284851
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1942632925
Short name T441
Test name
Test status
Simulation time 806273243 ps
CPU time 6.5 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:48 PM PST 24
Peak memory 215636 kb
Host smart-945efedb-b4bd-4921-a958-3b6430170ebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942632925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1942632925
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1330755488
Short name T501
Test name
Test status
Simulation time 1211364940 ps
CPU time 23.65 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 222940 kb
Host smart-dd54e340-e2a4-411f-906a-4b5d8bdd02da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330755488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1330755488
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.430330262
Short name T697
Test name
Test status
Simulation time 240794840 ps
CPU time 3.23 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:46 PM PST 24
Peak memory 209728 kb
Host smart-43656939-ac5d-440e-b40b-998401c97bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430330262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.430330262
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1012418409
Short name T601
Test name
Test status
Simulation time 260800874 ps
CPU time 8.32 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 214480 kb
Host smart-78000af4-24f6-429e-b38d-6a5c4b9af524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012418409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1012418409
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.554106865
Short name T302
Test name
Test status
Simulation time 1950637552 ps
CPU time 16.95 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 214408 kb
Host smart-ef8717d2-abdf-4af6-9148-52d869446b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554106865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.554106865
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3658249328
Short name T877
Test name
Test status
Simulation time 114884569 ps
CPU time 3.83 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 218712 kb
Host smart-3d5b0220-ef1d-4d54-a90f-b3b7e57ca62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658249328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3658249328
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.202173077
Short name T537
Test name
Test status
Simulation time 128161234 ps
CPU time 6.06 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:48 PM PST 24
Peak memory 208056 kb
Host smart-20186785-b9f2-4a1a-ac66-042231069d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202173077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.202173077
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2542780897
Short name T591
Test name
Test status
Simulation time 706680867 ps
CPU time 5.67 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 208636 kb
Host smart-779120ad-0567-42d0-bc0f-68defc28c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542780897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2542780897
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.245827344
Short name T612
Test name
Test status
Simulation time 442149149 ps
CPU time 3.88 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 208748 kb
Host smart-fd9d7f5b-aeb7-4f05-a5d8-b8acff69085c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245827344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.245827344
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1549499520
Short name T644
Test name
Test status
Simulation time 7989171522 ps
CPU time 38.68 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 208356 kb
Host smart-77e615d2-be20-4954-a76c-31078bad75de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549499520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1549499520
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2275414649
Short name T15
Test name
Test status
Simulation time 205888704 ps
CPU time 3.65 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 208636 kb
Host smart-52420039-c10d-4567-85eb-21ce1f4b4714
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275414649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2275414649
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3624707242
Short name T331
Test name
Test status
Simulation time 46620574 ps
CPU time 2.53 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 207728 kb
Host smart-7a4fc9a4-7993-4d04-ad9d-abc3dbedcbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624707242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3624707242
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1140399500
Short name T442
Test name
Test status
Simulation time 109360872 ps
CPU time 2.76 seconds
Started Feb 18 01:54:43 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 208368 kb
Host smart-191b2255-5ab4-4d15-b249-04ce242420c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140399500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1140399500
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.261901440
Short name T324
Test name
Test status
Simulation time 1447381824 ps
CPU time 34.67 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 215124 kb
Host smart-53a6df6e-5f98-4e59-b98e-0caa1c1cafba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261901440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.261901440
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.87185238
Short name T374
Test name
Test status
Simulation time 170979295 ps
CPU time 5.63 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 208536 kb
Host smart-524242cc-92a7-4029-b5e7-c95355bfec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87185238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.87185238
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3046652456
Short name T832
Test name
Test status
Simulation time 63119775 ps
CPU time 2.74 seconds
Started Feb 18 01:54:35 PM PST 24
Finished Feb 18 01:54:40 PM PST 24
Peak memory 209948 kb
Host smart-a0ef054d-4ce4-4e90-b585-74d8ec98f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046652456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3046652456
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1142272877
Short name T725
Test name
Test status
Simulation time 17108100 ps
CPU time 0.78 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 206020 kb
Host smart-a19c9126-4afa-4364-8890-e9396b448fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142272877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1142272877
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1517600934
Short name T724
Test name
Test status
Simulation time 108009351 ps
CPU time 3.76 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 216648 kb
Host smart-0fd0755a-cab0-407e-b6f0-29111da96fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517600934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1517600934
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2372976694
Short name T104
Test name
Test status
Simulation time 29064788 ps
CPU time 2.02 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 207804 kb
Host smart-b61ead8a-1dd3-4c9f-8055-c94c0f97cd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372976694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2372976694
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1050336504
Short name T788
Test name
Test status
Simulation time 674862886 ps
CPU time 8.52 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:59 PM PST 24
Peak memory 221896 kb
Host smart-989ccea6-29d6-4213-b9b9-a616588da286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050336504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1050336504
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.679078400
Short name T360
Test name
Test status
Simulation time 379790089 ps
CPU time 5.12 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 214044 kb
Host smart-e18a756c-3bb7-446d-a746-ad1c68e5ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679078400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.679078400
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1223657150
Short name T739
Test name
Test status
Simulation time 124690459 ps
CPU time 3.19 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 206632 kb
Host smart-1469fd93-f9e8-45d1-90e4-53c97aa22a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223657150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1223657150
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.419909859
Short name T742
Test name
Test status
Simulation time 65612719 ps
CPU time 4 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:46 PM PST 24
Peak memory 210196 kb
Host smart-21e61148-704a-4931-825e-a32c1c215da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419909859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.419909859
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4187464873
Short name T588
Test name
Test status
Simulation time 145231178 ps
CPU time 2.59 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 208556 kb
Host smart-45ba6eae-7822-4414-90df-c08d85a82582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187464873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4187464873
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4159511138
Short name T219
Test name
Test status
Simulation time 2626664939 ps
CPU time 36.19 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 208192 kb
Host smart-b3404d07-9f5f-44b2-9ab1-d84b6130c8bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159511138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4159511138
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.966279308
Short name T349
Test name
Test status
Simulation time 606487860 ps
CPU time 5.38 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 206800 kb
Host smart-e9b82967-36fd-4dce-acdc-341c226a34e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966279308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.966279308
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3590661866
Short name T695
Test name
Test status
Simulation time 172583881 ps
CPU time 5.11 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 208256 kb
Host smart-d67b2870-fc8a-48e8-bf60-931b4014d0ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590661866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3590661866
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.655106423
Short name T714
Test name
Test status
Simulation time 29333664 ps
CPU time 2.26 seconds
Started Feb 18 01:54:39 PM PST 24
Finished Feb 18 01:54:43 PM PST 24
Peak memory 209112 kb
Host smart-48c70050-2b43-4ac4-8325-91160eef23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655106423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.655106423
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1619736945
Short name T529
Test name
Test status
Simulation time 49380101 ps
CPU time 2.68 seconds
Started Feb 18 01:54:40 PM PST 24
Finished Feb 18 01:54:44 PM PST 24
Peak memory 206672 kb
Host smart-dac5412e-ad70-41b5-88ad-a22e2e461056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619736945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1619736945
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1051183498
Short name T679
Test name
Test status
Simulation time 388845702 ps
CPU time 13.42 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 219548 kb
Host smart-a7cbde05-421d-4092-969b-e76fee3e4def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051183498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1051183498
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2303094564
Short name T300
Test name
Test status
Simulation time 1449983207 ps
CPU time 36.54 seconds
Started Feb 18 01:54:51 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 208740 kb
Host smart-98b38302-b86c-4649-be8d-75de5e23b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303094564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2303094564
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3417857842
Short name T802
Test name
Test status
Simulation time 13314443 ps
CPU time 0.89 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:54:57 PM PST 24
Peak memory 206148 kb
Host smart-f05ca4d7-60e4-40a0-b167-dc9842a5ca1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417857842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3417857842
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4011860554
Short name T116
Test name
Test status
Simulation time 38210065 ps
CPU time 3.06 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 214456 kb
Host smart-55bf27d0-bc00-454f-94dd-db637ef02e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011860554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4011860554
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3101088819
Short name T9
Test name
Test status
Simulation time 1311471270 ps
CPU time 38.05 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 222576 kb
Host smart-23058282-687c-4026-9b46-e2e0d2e2285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101088819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3101088819
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2499814805
Short name T670
Test name
Test status
Simulation time 94334939 ps
CPU time 2.12 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:49 PM PST 24
Peak memory 207452 kb
Host smart-201d529d-02b5-46d5-b79a-2af2a33cb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499814805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2499814805
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.923053921
Short name T401
Test name
Test status
Simulation time 1537097303 ps
CPU time 27.76 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 214456 kb
Host smart-7b4d49be-424e-49af-a693-1eeb2441805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923053921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.923053921
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1566728528
Short name T149
Test name
Test status
Simulation time 34518850 ps
CPU time 2.1 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:54:59 PM PST 24
Peak memory 214688 kb
Host smart-e9a6b37b-a0f1-4662-b443-5ebe91f470f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566728528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1566728528
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1428903212
Short name T600
Test name
Test status
Simulation time 470354980 ps
CPU time 5.02 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 209128 kb
Host smart-e90686c6-7ec5-4e97-bdef-d94a851c6089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428903212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1428903212
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1468170502
Short name T684
Test name
Test status
Simulation time 187621859 ps
CPU time 4.83 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:50 PM PST 24
Peak memory 208376 kb
Host smart-6999e5a5-2a13-46d7-aab4-f85f931e1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468170502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1468170502
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3582750438
Short name T373
Test name
Test status
Simulation time 1362461898 ps
CPU time 37.8 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 207768 kb
Host smart-4250c55e-5eb4-4233-87ab-ed1f35b73eb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582750438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3582750438
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3476440288
Short name T673
Test name
Test status
Simulation time 98881019 ps
CPU time 4.15 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:54:56 PM PST 24
Peak memory 208644 kb
Host smart-c7e100c6-f934-4220-8ecf-c664b2188713
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476440288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3476440288
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1246600848
Short name T521
Test name
Test status
Simulation time 34039000 ps
CPU time 2.38 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:54:58 PM PST 24
Peak memory 206736 kb
Host smart-2b540cbe-46f6-4b77-a6b3-d4ba1892dc4f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246600848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1246600848
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.146512380
Short name T798
Test name
Test status
Simulation time 72224597 ps
CPU time 3.38 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 209972 kb
Host smart-cfed2952-8952-4634-a06a-e7e0b898e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146512380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.146512380
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1851025882
Short name T574
Test name
Test status
Simulation time 321928333 ps
CPU time 8.31 seconds
Started Feb 18 01:54:41 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 207624 kb
Host smart-565da25d-8c5e-496a-bc84-5c97805ca5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851025882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1851025882
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1701570078
Short name T846
Test name
Test status
Simulation time 210549021 ps
CPU time 4.7 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 208656 kb
Host smart-7723b6e7-3179-433b-bfce-1f26b10e09eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701570078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1701570078
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2684042230
Short name T19
Test name
Test status
Simulation time 147919281 ps
CPU time 4.41 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 210912 kb
Host smart-7ec822b8-b404-4b6f-9684-7653d1687bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684042230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2684042230
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3852347839
Short name T548
Test name
Test status
Simulation time 38409685 ps
CPU time 0.92 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 206028 kb
Host smart-f513e2e0-ccdc-4fef-bf41-ca4c3537209b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852347839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3852347839
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.747247796
Short name T37
Test name
Test status
Simulation time 54339695 ps
CPU time 2.87 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 208180 kb
Host smart-67bd37fa-7f98-4dad-9c08-9381807121f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747247796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.747247796
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.896757958
Short name T70
Test name
Test status
Simulation time 528340349 ps
CPU time 3.09 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 210288 kb
Host smart-b5a7510c-a55f-4c8f-bdd9-035b2926b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896757958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.896757958
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3762069900
Short name T261
Test name
Test status
Simulation time 63117681 ps
CPU time 2.51 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 209428 kb
Host smart-7d07bd2c-92b6-4818-96e6-bff292d65587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762069900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3762069900
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2198136502
Short name T569
Test name
Test status
Simulation time 110221021 ps
CPU time 2.97 seconds
Started Feb 18 01:54:42 PM PST 24
Finished Feb 18 01:54:47 PM PST 24
Peak memory 219752 kb
Host smart-db65263a-758d-4332-896e-4998f28023f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198136502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2198136502
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1259186914
Short name T576
Test name
Test status
Simulation time 52065451 ps
CPU time 3.42 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 207612 kb
Host smart-9e4dd660-0741-4d91-9e42-e6e8df3944d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259186914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1259186914
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2136471809
Short name T327
Test name
Test status
Simulation time 64461941 ps
CPU time 2.24 seconds
Started Feb 18 01:54:48 PM PST 24
Finished Feb 18 01:54:54 PM PST 24
Peak memory 207428 kb
Host smart-2f269b56-62cc-4ff0-81bb-3c50c3b61b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136471809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2136471809
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2928061800
Short name T899
Test name
Test status
Simulation time 2043919826 ps
CPU time 16.44 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 207308 kb
Host smart-4e54cd9a-371b-42c7-8a72-7ed8a000dd71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928061800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2928061800
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3088109675
Short name T413
Test name
Test status
Simulation time 722286529 ps
CPU time 6.04 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 208568 kb
Host smart-fa4feb36-09ec-4111-b028-511a7cdef6e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088109675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3088109675
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3784395480
Short name T322
Test name
Test status
Simulation time 279394425 ps
CPU time 7.69 seconds
Started Feb 18 01:54:44 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 208508 kb
Host smart-7850c96a-0b39-4bfd-9c29-e3418534347d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784395480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3784395480
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3694867644
Short name T451
Test name
Test status
Simulation time 459950746 ps
CPU time 3.72 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:54:59 PM PST 24
Peak memory 215532 kb
Host smart-8810402d-8787-4f00-b769-3db6805b35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694867644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3694867644
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1171267093
Short name T783
Test name
Test status
Simulation time 34615331 ps
CPU time 2.55 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 208452 kb
Host smart-039e9b7c-d338-47ec-a75a-89e7d75d0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171267093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1171267093
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2844677862
Short name T500
Test name
Test status
Simulation time 54829832 ps
CPU time 2.36 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 209856 kb
Host smart-a5a284c3-a4aa-4371-8026-65135631d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844677862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2844677862
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2446396379
Short name T806
Test name
Test status
Simulation time 45272850 ps
CPU time 0.77 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:54:58 PM PST 24
Peak memory 205948 kb
Host smart-54fa1f90-532f-4d83-8413-cf77b01f02a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446396379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2446396379
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4095833132
Short name T718
Test name
Test status
Simulation time 180700800 ps
CPU time 2.32 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 209328 kb
Host smart-25afe59c-d574-4644-a521-19ccbbfd162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095833132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4095833132
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.972082103
Short name T50
Test name
Test status
Simulation time 102600049 ps
CPU time 2.97 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 209892 kb
Host smart-b5995492-923c-405c-8259-da8936d9e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972082103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.972082103
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.383496411
Short name T808
Test name
Test status
Simulation time 136334807 ps
CPU time 2.81 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 214444 kb
Host smart-02282f81-1307-4829-b148-7872b8481755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383496411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.383496411
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2620518542
Short name T272
Test name
Test status
Simulation time 487562888 ps
CPU time 5.21 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:56 PM PST 24
Peak memory 209020 kb
Host smart-7790b764-8c86-43be-9ac6-e2ddd97c139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620518542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2620518542
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2292309134
Short name T759
Test name
Test status
Simulation time 541597061 ps
CPU time 7.13 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 220296 kb
Host smart-31e9a3f1-c0ef-47a4-9843-48c8e4f3e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292309134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2292309134
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2096755056
Short name T845
Test name
Test status
Simulation time 801609986 ps
CPU time 9.43 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 222592 kb
Host smart-2c954dc6-f78e-4639-abf1-aa341f8df28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096755056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2096755056
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4069137548
Short name T672
Test name
Test status
Simulation time 195586752 ps
CPU time 5.82 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:04 PM PST 24
Peak memory 208248 kb
Host smart-3bc499d5-5e5a-4176-8c4d-edb0d5292fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069137548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4069137548
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3670626537
Short name T457
Test name
Test status
Simulation time 32616427 ps
CPU time 1.97 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:51 PM PST 24
Peak memory 206704 kb
Host smart-1bd54dd0-1035-4631-b49f-326eedf71dce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670626537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3670626537
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2031610020
Short name T595
Test name
Test status
Simulation time 213340289 ps
CPU time 3.55 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 206776 kb
Host smart-c7b8d982-d50b-46c5-ad0a-79d32633ef54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031610020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2031610020
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3483116936
Short name T356
Test name
Test status
Simulation time 411927714 ps
CPU time 8.48 seconds
Started Feb 18 01:54:50 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 208688 kb
Host smart-413e61c5-36eb-46e8-95e7-665fc27454eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483116936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3483116936
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1118720463
Short name T199
Test name
Test status
Simulation time 2786173436 ps
CPU time 3.96 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 214500 kb
Host smart-884b23ce-278f-452c-b77f-9aa2734c3071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118720463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1118720463
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3409637079
Short name T508
Test name
Test status
Simulation time 57243838 ps
CPU time 1.89 seconds
Started Feb 18 01:54:46 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 207008 kb
Host smart-4078e500-5635-46c2-9839-213ddc4d0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409637079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3409637079
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1916401274
Short name T339
Test name
Test status
Simulation time 3682243408 ps
CPU time 38.6 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 214472 kb
Host smart-a1de1160-c166-4ab9-91d5-b20e15b86b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916401274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1916401274
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.768283086
Short name T180
Test name
Test status
Simulation time 141491441 ps
CPU time 3.19 seconds
Started Feb 18 01:54:47 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 209724 kb
Host smart-78b0bdae-282a-4a9a-a740-4f0024426b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768283086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.768283086
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2799049842
Short name T197
Test name
Test status
Simulation time 23093006 ps
CPU time 0.74 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 206108 kb
Host smart-7cc508ba-00c0-4456-a9c4-efabbaa3f348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799049842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2799049842
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3177171012
Short name T352
Test name
Test status
Simulation time 61506591 ps
CPU time 3.94 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:08 PM PST 24
Peak memory 215276 kb
Host smart-10268c6c-84d5-49c7-8671-a0858c0b9d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177171012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3177171012
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3114064419
Short name T208
Test name
Test status
Simulation time 134309072 ps
CPU time 3.79 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 216412 kb
Host smart-4e5054dd-5545-407b-b45d-9db6fba3d16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114064419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3114064419
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2530109526
Short name T778
Test name
Test status
Simulation time 196628650 ps
CPU time 3.23 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 209728 kb
Host smart-609335c0-82e3-4ab8-baab-f8d4fd1cd6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530109526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2530109526
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.145172757
Short name T727
Test name
Test status
Simulation time 390341309 ps
CPU time 10.56 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:13 PM PST 24
Peak memory 214480 kb
Host smart-84f4432e-8d9c-4f09-a953-6ffaf90269c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145172757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.145172757
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1084228694
Short name T283
Test name
Test status
Simulation time 105020584 ps
CPU time 2.85 seconds
Started Feb 18 01:54:57 PM PST 24
Finished Feb 18 01:55:03 PM PST 24
Peak memory 210852 kb
Host smart-e3212c9d-209e-40b0-a097-d7bbd6907e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084228694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1084228694
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.173575637
Short name T849
Test name
Test status
Simulation time 210424895 ps
CPU time 3.38 seconds
Started Feb 18 01:54:51 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 208984 kb
Host smart-886fe278-d2a8-4ab1-9a1c-fc683d9b8e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173575637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.173575637
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.955761317
Short name T247
Test name
Test status
Simulation time 1056588366 ps
CPU time 26.1 seconds
Started Feb 18 01:54:54 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 208368 kb
Host smart-7abbd547-9219-4957-9b0d-983d23c4e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955761317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.955761317
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1909730563
Short name T399
Test name
Test status
Simulation time 174200151 ps
CPU time 2.68 seconds
Started Feb 18 01:54:55 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 206548 kb
Host smart-b9838442-3852-4038-9067-dba530b5464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909730563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1909730563
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4172236812
Short name T395
Test name
Test status
Simulation time 358111038 ps
CPU time 3.54 seconds
Started Feb 18 01:54:51 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 207216 kb
Host smart-f527fdd4-43d6-46ef-b1cd-f9f82cf745bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172236812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4172236812
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3614852223
Short name T661
Test name
Test status
Simulation time 300959633 ps
CPU time 3.66 seconds
Started Feb 18 01:54:57 PM PST 24
Finished Feb 18 01:55:04 PM PST 24
Peak memory 208528 kb
Host smart-8d87e9a8-0253-4912-b2ba-1b544dbfa188
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614852223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3614852223
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2825676426
Short name T570
Test name
Test status
Simulation time 944792206 ps
CPU time 10.1 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 207732 kb
Host smart-e10210af-814c-4ed1-a764-3bd1a8bf95e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825676426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2825676426
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1128322214
Short name T472
Test name
Test status
Simulation time 716752715 ps
CPU time 12.23 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 214324 kb
Host smart-b4c2d40c-f230-4836-b6d0-cbffeead31ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128322214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1128322214
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3623234400
Short name T215
Test name
Test status
Simulation time 60648157 ps
CPU time 3.08 seconds
Started Feb 18 01:54:45 PM PST 24
Finished Feb 18 01:54:50 PM PST 24
Peak memory 208404 kb
Host smart-b33b33c4-d7e8-4cdc-9a67-77db826ca73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623234400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3623234400
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2656777632
Short name T602
Test name
Test status
Simulation time 593609401 ps
CPU time 5.9 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 210268 kb
Host smart-10239031-f009-4025-9d8c-232ad849c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656777632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2656777632
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.772654739
Short name T158
Test name
Test status
Simulation time 1972418491 ps
CPU time 4.34 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:04 PM PST 24
Peak memory 209812 kb
Host smart-7b89b5d0-0b6c-49a3-a339-cec99b2f83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772654739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.772654739
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2597791004
Short name T76
Test name
Test status
Simulation time 39454268 ps
CPU time 0.9 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 205988 kb
Host smart-216590f0-e683-4bb1-8813-b9728e3778ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597791004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2597791004
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1644160362
Short name T244
Test name
Test status
Simulation time 33500513 ps
CPU time 2.96 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 214536 kb
Host smart-46c7ca02-91ef-4eff-ba24-3e227565c0b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644160362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1644160362
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3759339577
Short name T544
Test name
Test status
Simulation time 1022365593 ps
CPU time 12.08 seconds
Started Feb 18 01:54:49 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 210216 kb
Host smart-1530941d-066a-45f7-b288-951b370e1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759339577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3759339577
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4188711668
Short name T734
Test name
Test status
Simulation time 1092112409 ps
CPU time 19.81 seconds
Started Feb 18 01:54:55 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 218680 kb
Host smart-7912bba9-5586-4971-b15d-4f0f466e9f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188711668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4188711668
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1884707408
Short name T603
Test name
Test status
Simulation time 162885492 ps
CPU time 6.55 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:04 PM PST 24
Peak memory 214384 kb
Host smart-b5338709-a5e8-455e-a73c-64c7c1cf86b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884707408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1884707408
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.501392688
Short name T103
Test name
Test status
Simulation time 661472003 ps
CPU time 8.18 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:08 PM PST 24
Peak memory 214420 kb
Host smart-d0198620-7305-4312-a323-49af23062ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501392688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.501392688
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_random.3675185028
Short name T351
Test name
Test status
Simulation time 275222956 ps
CPU time 9.22 seconds
Started Feb 18 01:54:57 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 208356 kb
Host smart-918c7969-3e38-4e2c-9cd2-21d1bdcf44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675185028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3675185028
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.782349852
Short name T218
Test name
Test status
Simulation time 415900962 ps
CPU time 4.59 seconds
Started Feb 18 01:54:55 PM PST 24
Finished Feb 18 01:55:04 PM PST 24
Peak memory 208824 kb
Host smart-f5ffe1b7-c0a2-4f4c-8103-f96db211d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782349852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.782349852
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4284753586
Short name T789
Test name
Test status
Simulation time 40228407 ps
CPU time 1.79 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:54:59 PM PST 24
Peak memory 206536 kb
Host smart-ff19310a-f330-4789-a5b8-06c0abbd3186
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284753586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4284753586
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.187829263
Short name T626
Test name
Test status
Simulation time 22994526 ps
CPU time 1.88 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 206612 kb
Host smart-27255b93-e601-4cba-8437-320007c1deff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187829263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.187829263
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1119521657
Short name T688
Test name
Test status
Simulation time 474689418 ps
CPU time 6.8 seconds
Started Feb 18 01:54:53 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 208184 kb
Host smart-24529a5b-4a44-4271-a54e-9d9a501ae62e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119521657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1119521657
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.839631346
Short name T245
Test name
Test status
Simulation time 220028778 ps
CPU time 2.64 seconds
Started Feb 18 01:54:52 PM PST 24
Finished Feb 18 01:55:00 PM PST 24
Peak memory 209312 kb
Host smart-1efd2681-2af6-465a-8d86-2900f334d99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839631346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.839631346
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1183604010
Short name T715
Test name
Test status
Simulation time 548094997 ps
CPU time 3.93 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 206508 kb
Host smart-b12565d9-6f14-451d-bda5-a9b24c7acaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183604010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1183604010
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2001488642
Short name T236
Test name
Test status
Simulation time 27808285787 ps
CPU time 62.03 seconds
Started Feb 18 01:54:54 PM PST 24
Finished Feb 18 01:56:01 PM PST 24
Peak memory 216632 kb
Host smart-411a0057-9274-4575-a9c5-eba8ed03c413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001488642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2001488642
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1832149417
Short name T590
Test name
Test status
Simulation time 59843270 ps
CPU time 3.68 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:03 PM PST 24
Peak memory 214516 kb
Host smart-17627545-de15-4065-8740-9aaef8d6e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832149417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1832149417
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2422651211
Short name T108
Test name
Test status
Simulation time 154018777 ps
CPU time 2.09 seconds
Started Feb 18 01:54:54 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 209764 kb
Host smart-f25fd7c2-70c1-4bf3-aced-bfed1bb63bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422651211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2422651211
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2069687624
Short name T625
Test name
Test status
Simulation time 18144431 ps
CPU time 0.86 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:42 PM PST 24
Peak memory 206096 kb
Host smart-99bebb20-5df8-47ac-8688-bcb268ed7fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069687624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2069687624
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3059445296
Short name T857
Test name
Test status
Simulation time 229385714 ps
CPU time 4.15 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:52:53 PM PST 24
Peak memory 215352 kb
Host smart-a79891e6-12b7-4dbb-b0d3-cae57029650d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059445296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3059445296
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1337729615
Short name T225
Test name
Test status
Simulation time 303120835 ps
CPU time 3.31 seconds
Started Feb 18 01:52:43 PM PST 24
Finished Feb 18 01:52:47 PM PST 24
Peak memory 214520 kb
Host smart-efdf65da-a30e-4466-bd9e-d73cef8295fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337729615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1337729615
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2114013878
Short name T766
Test name
Test status
Simulation time 18728957 ps
CPU time 1.46 seconds
Started Feb 18 01:52:42 PM PST 24
Finished Feb 18 01:52:44 PM PST 24
Peak memory 207452 kb
Host smart-e04b908f-fbd4-4094-b466-0652a548ac1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114013878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2114013878
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2413372030
Short name T578
Test name
Test status
Simulation time 17580598967 ps
CPU time 38.73 seconds
Started Feb 18 01:52:45 PM PST 24
Finished Feb 18 01:53:24 PM PST 24
Peak memory 222688 kb
Host smart-13a5678b-e0ad-40f0-9fd8-eb9f677518be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413372030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2413372030
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3631106157
Short name T62
Test name
Test status
Simulation time 130710038 ps
CPU time 5.5 seconds
Started Feb 18 01:52:42 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 222504 kb
Host smart-af70ffed-91c0-4d9c-9315-3d5a2c11cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631106157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3631106157
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1843600846
Short name T556
Test name
Test status
Simulation time 122892407 ps
CPU time 4.52 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:47 PM PST 24
Peak memory 207180 kb
Host smart-600c25ab-fd51-4216-a718-91f30643c89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843600846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1843600846
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1560565572
Short name T12
Test name
Test status
Simulation time 1799238399 ps
CPU time 16.02 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:58 PM PST 24
Peak memory 230840 kb
Host smart-db134e69-9a57-404a-8072-c20146386f89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560565572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1560565572
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.68954135
Short name T579
Test name
Test status
Simulation time 88389985 ps
CPU time 3.94 seconds
Started Feb 18 01:52:37 PM PST 24
Finished Feb 18 01:52:43 PM PST 24
Peak memory 208756 kb
Host smart-caf33b93-4a3e-4c9f-a71b-4cc5cf0a19de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68954135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.68954135
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1179106832
Short name T581
Test name
Test status
Simulation time 123047534 ps
CPU time 3.13 seconds
Started Feb 18 01:52:39 PM PST 24
Finished Feb 18 01:52:43 PM PST 24
Peak memory 208528 kb
Host smart-f5402758-dc94-4b1e-9793-b7a68915bd63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179106832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1179106832
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3303479499
Short name T632
Test name
Test status
Simulation time 975967372 ps
CPU time 7.26 seconds
Started Feb 18 01:52:42 PM PST 24
Finished Feb 18 01:52:50 PM PST 24
Peak memory 207844 kb
Host smart-82644742-c7ca-4566-85dc-049badee4593
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303479499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3303479499
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1031904922
Short name T345
Test name
Test status
Simulation time 1111560684 ps
CPU time 28.99 seconds
Started Feb 18 01:52:38 PM PST 24
Finished Feb 18 01:53:08 PM PST 24
Peak memory 208452 kb
Host smart-014e8629-0f92-45e1-9654-d0b9ad211a45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031904922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1031904922
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2494117297
Short name T706
Test name
Test status
Simulation time 374261932 ps
CPU time 3.67 seconds
Started Feb 18 01:52:41 PM PST 24
Finished Feb 18 01:52:45 PM PST 24
Peak memory 209760 kb
Host smart-86632eae-36e1-42c6-9c8c-5a0ae8d3349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494117297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2494117297
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.945313243
Short name T593
Test name
Test status
Simulation time 1040796704 ps
CPU time 30.39 seconds
Started Feb 18 01:52:47 PM PST 24
Finished Feb 18 01:53:19 PM PST 24
Peak memory 208072 kb
Host smart-aa5e3105-8983-4271-89cb-45160dc980ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945313243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.945313243
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1915218547
Short name T156
Test name
Test status
Simulation time 771115378 ps
CPU time 24.13 seconds
Started Feb 18 01:52:40 PM PST 24
Finished Feb 18 01:53:05 PM PST 24
Peak memory 217408 kb
Host smart-2316bb54-71e6-4761-bd2d-bd78b72df7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915218547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1915218547
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1019462236
Short name T546
Test name
Test status
Simulation time 119336019 ps
CPU time 3.91 seconds
Started Feb 18 01:52:46 PM PST 24
Finished Feb 18 01:52:50 PM PST 24
Peak memory 210196 kb
Host smart-4113e84c-5997-4a07-8e0c-2c64c8ff1f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019462236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1019462236
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1386265178
Short name T171
Test name
Test status
Simulation time 108735876 ps
CPU time 2.6 seconds
Started Feb 18 01:52:43 PM PST 24
Finished Feb 18 01:52:46 PM PST 24
Peak memory 211028 kb
Host smart-7ea91792-08d1-4041-80d6-bab82c44b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386265178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1386265178
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1776155289
Short name T549
Test name
Test status
Simulation time 25333057 ps
CPU time 0.74 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 206084 kb
Host smart-973cb2f7-a6b6-45ce-a97a-86b4ae6f2047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776155289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1776155289
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.407032341
Short name T243
Test name
Test status
Simulation time 603472201 ps
CPU time 8.71 seconds
Started Feb 18 01:55:03 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 222588 kb
Host smart-92cd1bec-d8df-4e34-9929-26170c230f4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407032341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.407032341
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1616368137
Short name T753
Test name
Test status
Simulation time 551669588 ps
CPU time 2.26 seconds
Started Feb 18 01:55:25 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 209028 kb
Host smart-d1b536a3-0f4e-46db-902b-37734af352d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616368137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1616368137
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1759436341
Short name T281
Test name
Test status
Simulation time 10927641625 ps
CPU time 19.65 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 214520 kb
Host smart-dd075515-5fde-43ff-a1ec-43ebd1a91a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759436341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1759436341
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.80758914
Short name T216
Test name
Test status
Simulation time 216371488 ps
CPU time 7.37 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:11 PM PST 24
Peak memory 210176 kb
Host smart-153c15bc-4d15-4a89-a546-0deee6d5aff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80758914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.80758914
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_random.3415115597
Short name T484
Test name
Test status
Simulation time 1567484633 ps
CPU time 9.18 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:16 PM PST 24
Peak memory 218128 kb
Host smart-bc157a53-42da-47ed-98fd-5655487a3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415115597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3415115597
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2135123416
Short name T895
Test name
Test status
Simulation time 913743378 ps
CPU time 5.96 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:06 PM PST 24
Peak memory 208376 kb
Host smart-17a971e4-c7a3-430e-b26c-090a8a8e11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135123416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2135123416
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2334081022
Short name T458
Test name
Test status
Simulation time 1979239798 ps
CPU time 25.53 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:29 PM PST 24
Peak memory 208220 kb
Host smart-57e8a38e-7d2e-4c13-9616-e03b1b7f6f09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334081022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2334081022
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1136222588
Short name T730
Test name
Test status
Simulation time 1578064030 ps
CPU time 5.63 seconds
Started Feb 18 01:54:54 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 207932 kb
Host smart-b8464454-016a-4e0d-9d2b-88b64f007fb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136222588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1136222588
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1242314308
Short name T543
Test name
Test status
Simulation time 3459103432 ps
CPU time 8.14 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 208780 kb
Host smart-09ae20d1-71c4-4d42-88de-08b47fbdc337
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242314308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1242314308
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4271831589
Short name T263
Test name
Test status
Simulation time 216763060 ps
CPU time 1.78 seconds
Started Feb 18 01:55:02 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 209948 kb
Host smart-2c98a458-6a93-4386-9ad6-55493731ed4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271831589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4271831589
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.412247961
Short name T417
Test name
Test status
Simulation time 91301594 ps
CPU time 2.43 seconds
Started Feb 18 01:54:56 PM PST 24
Finished Feb 18 01:55:02 PM PST 24
Peak memory 206764 kb
Host smart-b94d1ade-3540-4c5c-b4e8-b10fa04f0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412247961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.412247961
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.4255406450
Short name T205
Test name
Test status
Simulation time 4934111302 ps
CPU time 57.05 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:56:00 PM PST 24
Peak memory 215644 kb
Host smart-80b10adf-f17b-4ad1-8757-643eab8360cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255406450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4255406450
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4245294477
Short name T897
Test name
Test status
Simulation time 2146211001 ps
CPU time 57.37 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:56:03 PM PST 24
Peak memory 210128 kb
Host smart-2f0273db-6b26-4c53-910d-8d89bb5c2427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245294477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4245294477
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.610020981
Short name T178
Test name
Test status
Simulation time 58683888 ps
CPU time 2.01 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 209744 kb
Host smart-bab066e8-19e8-4ee8-afaa-d5aec50f7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610020981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.610020981
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.547527714
Short name T862
Test name
Test status
Simulation time 138219403 ps
CPU time 0.95 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:08 PM PST 24
Peak memory 206104 kb
Host smart-f331392a-0046-48b3-9e49-7531de52af13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547527714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.547527714
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3699388833
Short name T869
Test name
Test status
Simulation time 129738044 ps
CPU time 3.54 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 208980 kb
Host smart-8708bc01-a064-4404-8021-567f229ab2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699388833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3699388833
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3672224585
Short name T284
Test name
Test status
Simulation time 292269493 ps
CPU time 5.85 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:55:11 PM PST 24
Peak memory 214388 kb
Host smart-7baf1c15-8d32-4cd5-bf62-08878a349fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672224585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3672224585
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1008305404
Short name T423
Test name
Test status
Simulation time 2479164808 ps
CPU time 25.81 seconds
Started Feb 18 01:55:02 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 216084 kb
Host smart-611ad8b9-ffab-460a-b46a-3f0d30a09c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008305404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1008305404
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.129083271
Short name T698
Test name
Test status
Simulation time 225261949 ps
CPU time 3.05 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 214468 kb
Host smart-e077cab3-1797-4bb8-b2e3-db2ecd4d8b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129083271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.129083271
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2249136749
Short name T290
Test name
Test status
Simulation time 33888561 ps
CPU time 2.42 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 209160 kb
Host smart-48b2304d-048d-4d05-a9d7-266bdafab409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249136749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2249136749
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.280053266
Short name T617
Test name
Test status
Simulation time 36264699 ps
CPU time 2.29 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:05 PM PST 24
Peak memory 206728 kb
Host smart-a509dd5b-2a45-4e6d-92fc-c480cb6d0d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280053266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.280053266
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.963613106
Short name T659
Test name
Test status
Simulation time 63504392 ps
CPU time 2.29 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 207104 kb
Host smart-2c7aec7c-8c02-499b-be41-6fd679215d98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963613106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.963613106
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2106988839
Short name T198
Test name
Test status
Simulation time 39609559 ps
CPU time 2.56 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 206860 kb
Host smart-fad20659-4ced-4c78-8fa1-356eddef96e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106988839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2106988839
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2996318683
Short name T497
Test name
Test status
Simulation time 753285670 ps
CPU time 22.75 seconds
Started Feb 18 01:55:04 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 208144 kb
Host smart-df02eb6d-40b0-4f53-8613-3be4d5cb742a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996318683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2996318683
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.258240903
Short name T453
Test name
Test status
Simulation time 204477527 ps
CPU time 3.23 seconds
Started Feb 18 01:55:03 PM PST 24
Finished Feb 18 01:55:12 PM PST 24
Peak memory 207916 kb
Host smart-29a9ceb5-7dd5-4292-85d2-ac793397c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258240903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.258240903
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3482889790
Short name T716
Test name
Test status
Simulation time 138143122 ps
CPU time 4.1 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 207308 kb
Host smart-a021cf95-cd6f-4b34-a680-03e75733d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482889790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3482889790
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3060929956
Short name T785
Test name
Test status
Simulation time 360570984 ps
CPU time 4.18 seconds
Started Feb 18 01:55:00 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 209352 kb
Host smart-3dc4be20-7a78-4fcb-88ed-25a6b6443abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060929956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3060929956
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3179795708
Short name T193
Test name
Test status
Simulation time 164823921 ps
CPU time 2.49 seconds
Started Feb 18 01:55:01 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 210244 kb
Host smart-f22b8dd2-e4f4-4813-86ff-bc8708211490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179795708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3179795708
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1460044801
Short name T107
Test name
Test status
Simulation time 52475192 ps
CPU time 0.77 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 206108 kb
Host smart-f3a09789-375b-4da1-99da-c6af00efb2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460044801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1460044801
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2370392797
Short name T784
Test name
Test status
Simulation time 229239451 ps
CPU time 4.79 seconds
Started Feb 18 01:54:58 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 215080 kb
Host smart-7ff55f64-ba2f-4580-9cbd-0b9d4b3bad41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370392797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2370392797
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2868815927
Short name T55
Test name
Test status
Simulation time 319323790 ps
CPU time 2.94 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 207572 kb
Host smart-52d677a5-fb4c-4a5a-9ca8-72ca07537cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868815927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2868815927
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3418405746
Short name T363
Test name
Test status
Simulation time 45152544 ps
CPU time 2.91 seconds
Started Feb 18 01:55:04 PM PST 24
Finished Feb 18 01:55:12 PM PST 24
Peak memory 208396 kb
Host smart-297e54fd-0097-4351-b3a7-62790e38e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418405746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3418405746
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1699091997
Short name T224
Test name
Test status
Simulation time 108689447 ps
CPU time 4.96 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 209780 kb
Host smart-c34e3a2e-bc54-4017-bc62-66c8ebde7dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699091997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1699091997
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3190101487
Short name T14
Test name
Test status
Simulation time 2603370075 ps
CPU time 82.25 seconds
Started Feb 18 01:55:03 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 209580 kb
Host smart-b86b1f28-096e-4420-b7db-b4a83a50313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190101487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3190101487
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.526498636
Short name T81
Test name
Test status
Simulation time 15362139100 ps
CPU time 56.59 seconds
Started Feb 18 01:55:02 PM PST 24
Finished Feb 18 01:56:04 PM PST 24
Peak memory 208380 kb
Host smart-c8013c61-754f-495a-9f4f-75f968ff49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526498636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.526498636
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.505857592
Short name T475
Test name
Test status
Simulation time 659886468 ps
CPU time 5.9 seconds
Started Feb 18 01:55:02 PM PST 24
Finished Feb 18 01:55:13 PM PST 24
Peak memory 207888 kb
Host smart-fadf34e2-a0f1-450c-9877-2d86af5395b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505857592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.505857592
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.961354747
Short name T604
Test name
Test status
Simulation time 33165841 ps
CPU time 2.39 seconds
Started Feb 18 01:55:02 PM PST 24
Finished Feb 18 01:55:10 PM PST 24
Peak memory 206744 kb
Host smart-7bf887ef-fd05-4cb6-b6a4-28865d6f4b1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961354747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.961354747
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.735173654
Short name T308
Test name
Test status
Simulation time 791411808 ps
CPU time 3.23 seconds
Started Feb 18 01:55:04 PM PST 24
Finished Feb 18 01:55:13 PM PST 24
Peak memory 209708 kb
Host smart-be9e0733-35f9-4363-b6c7-cec2399eba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735173654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.735173654
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1169876493
Short name T796
Test name
Test status
Simulation time 257706959 ps
CPU time 4.3 seconds
Started Feb 18 01:55:03 PM PST 24
Finished Feb 18 01:55:14 PM PST 24
Peak memory 208216 kb
Host smart-66a27e25-e1ed-46b8-98f3-54111cef54e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169876493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1169876493
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3404942383
Short name T357
Test name
Test status
Simulation time 1432509305 ps
CPU time 34.67 seconds
Started Feb 18 01:55:25 PM PST 24
Finished Feb 18 01:56:03 PM PST 24
Peak memory 216076 kb
Host smart-08ba7762-7e61-40f5-baa0-5707f15b634b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404942383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3404942383
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.4153056525
Short name T760
Test name
Test status
Simulation time 230953389 ps
CPU time 3.34 seconds
Started Feb 18 01:55:04 PM PST 24
Finished Feb 18 01:55:13 PM PST 24
Peak memory 208992 kb
Host smart-2f5ac205-344d-4ee8-bb40-41781cb8998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153056525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.4153056525
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.128615235
Short name T842
Test name
Test status
Simulation time 175456586 ps
CPU time 2.98 seconds
Started Feb 18 01:54:59 PM PST 24
Finished Feb 18 01:55:07 PM PST 24
Peak memory 210836 kb
Host smart-d7639533-3d0c-4f7f-a83c-4024aa0f1e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128615235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.128615235
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2855213001
Short name T448
Test name
Test status
Simulation time 12323739 ps
CPU time 0.78 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:13 PM PST 24
Peak memory 206004 kb
Host smart-abe5eb66-1a42-4555-8387-8142fffca5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855213001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2855213001
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.575371279
Short name T33
Test name
Test status
Simulation time 140416586 ps
CPU time 4.45 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 210180 kb
Host smart-e72e9b18-a14c-4369-8894-49bdfee76637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575371279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.575371279
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.99454520
Short name T592
Test name
Test status
Simulation time 339125646 ps
CPU time 10.65 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:23 PM PST 24
Peak memory 215304 kb
Host smart-f463e130-1c85-4813-a3d0-4dc758c557e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99454520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.99454520
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3481498150
Short name T78
Test name
Test status
Simulation time 147540397 ps
CPU time 5.75 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 221316 kb
Host smart-38de26bb-3092-46a3-9eab-d636c325802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481498150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3481498150
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3436021568
Short name T524
Test name
Test status
Simulation time 527068873 ps
CPU time 6.23 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 214344 kb
Host smart-d3821ea2-732f-452c-8fe7-eb7d3078fe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436021568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3436021568
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4278202860
Short name T298
Test name
Test status
Simulation time 140612975 ps
CPU time 3.88 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:16 PM PST 24
Peak memory 208420 kb
Host smart-1a344f9d-9270-453d-b705-1a1f5cd5f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278202860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4278202860
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1583409092
Short name T514
Test name
Test status
Simulation time 105516670 ps
CPU time 4.86 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 208852 kb
Host smart-6b27929f-5cd2-419b-837f-4d5c4cf56054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583409092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1583409092
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1007164846
Short name T705
Test name
Test status
Simulation time 621558823 ps
CPU time 6.84 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 208408 kb
Host smart-b20a35cd-174e-4a5a-83b9-7cccce0a4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007164846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1007164846
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4099674022
Short name T655
Test name
Test status
Simulation time 221831639 ps
CPU time 3.04 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 207132 kb
Host smart-76b4bbe6-f409-4573-b6a1-7103feb4a5ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099674022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4099674022
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2832112682
Short name T597
Test name
Test status
Simulation time 75176445 ps
CPU time 3.4 seconds
Started Feb 18 01:55:10 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 208784 kb
Host smart-c8a16d34-24cb-44ca-bdef-3eed2cc89b0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832112682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2832112682
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.420649599
Short name T527
Test name
Test status
Simulation time 797168905 ps
CPU time 20.58 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:49 PM PST 24
Peak memory 208004 kb
Host smart-1d764b13-637d-45c9-ab07-cb5324a8be82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420649599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.420649599
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1702169710
Short name T526
Test name
Test status
Simulation time 39801366 ps
CPU time 2.34 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 207524 kb
Host smart-0e525144-1eef-4631-95f2-7d7fee9158b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702169710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1702169710
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3050026755
Short name T462
Test name
Test status
Simulation time 585258902 ps
CPU time 4 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:15 PM PST 24
Peak memory 206616 kb
Host smart-46de4fd9-fd5b-4af0-b6d5-a97270282507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050026755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3050026755
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1350375468
Short name T883
Test name
Test status
Simulation time 2666995435 ps
CPU time 66.48 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:56:21 PM PST 24
Peak memory 218892 kb
Host smart-fb3337ff-6e5e-472f-b93f-048c5b4d2b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350375468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1350375468
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2501601148
Short name T646
Test name
Test status
Simulation time 182928306 ps
CPU time 7.41 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 208944 kb
Host smart-575f0e91-71ed-4db7-82ed-8fb02fbf3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501601148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2501601148
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2573906868
Short name T126
Test name
Test status
Simulation time 62469301 ps
CPU time 2.64 seconds
Started Feb 18 01:55:11 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 209904 kb
Host smart-18fd0fa8-bb0e-4c28-a979-4d7c742d5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573906868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2573906868
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2291644664
Short name T469
Test name
Test status
Simulation time 21480082 ps
CPU time 0.76 seconds
Started Feb 18 01:55:05 PM PST 24
Finished Feb 18 01:55:11 PM PST 24
Peak memory 206016 kb
Host smart-8c71bfef-4cd1-41c6-a736-c2b416e56280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291644664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2291644664
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4029842735
Short name T406
Test name
Test status
Simulation time 55820307 ps
CPU time 3.98 seconds
Started Feb 18 01:55:11 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 214468 kb
Host smart-69ec59d3-d48c-4150-b063-79b0acd87484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029842735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4029842735
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.106989065
Short name T636
Test name
Test status
Simulation time 427306617 ps
CPU time 11.5 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:29 PM PST 24
Peak memory 209016 kb
Host smart-f134524b-a18c-4c3d-afe7-2b7a658a266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106989065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.106989065
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1315583004
Short name T723
Test name
Test status
Simulation time 351486247 ps
CPU time 9.36 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 214332 kb
Host smart-041f946e-a6b6-4f70-a434-e2e9b9f96ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315583004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1315583004
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3605419380
Short name T885
Test name
Test status
Simulation time 84713442 ps
CPU time 3.68 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:15 PM PST 24
Peak memory 210112 kb
Host smart-05a10767-ad12-4f79-a26d-d781295568d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605419380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3605419380
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2798183416
Short name T843
Test name
Test status
Simulation time 154185957 ps
CPU time 6.07 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 218472 kb
Host smart-971f42f6-a212-4d5d-aeab-06b0578ae6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798183416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2798183416
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2975518761
Short name T624
Test name
Test status
Simulation time 84607242 ps
CPU time 3.62 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:15 PM PST 24
Peak memory 208104 kb
Host smart-1e9a97e2-8d3c-488c-9d65-b1f939127b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975518761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2975518761
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2523887662
Short name T701
Test name
Test status
Simulation time 47864318 ps
CPU time 2.72 seconds
Started Feb 18 01:55:10 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 207932 kb
Host smart-4b82276a-f576-4b68-b816-66d5e8d5b9af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523887662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2523887662
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3830163387
Short name T288
Test name
Test status
Simulation time 880542133 ps
CPU time 6.56 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 208760 kb
Host smart-3ff20e55-daa2-40ea-a7f5-b0c7dbd5a1bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830163387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3830163387
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1633268706
Short name T467
Test name
Test status
Simulation time 573169200 ps
CPU time 3.42 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 206732 kb
Host smart-d0740f0a-3f41-407e-ae0e-3c671d61b7f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633268706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1633268706
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3265290376
Short name T772
Test name
Test status
Simulation time 388632151 ps
CPU time 4.71 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 208444 kb
Host smart-1e6720fe-5294-4e96-9358-d23e8b0eb773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265290376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3265290376
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.786027328
Short name T452
Test name
Test status
Simulation time 8569469070 ps
CPU time 25.68 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 207892 kb
Host smart-daea3111-a7a9-489d-8f86-ff13b60a278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786027328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.786027328
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.632832896
Short name T100
Test name
Test status
Simulation time 71733069 ps
CPU time 2.82 seconds
Started Feb 18 01:55:09 PM PST 24
Finished Feb 18 01:55:17 PM PST 24
Peak memory 208188 kb
Host smart-a2c8590d-1b6b-4517-8317-31983a7159ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632832896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.632832896
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1885415934
Short name T185
Test name
Test status
Simulation time 151262620 ps
CPU time 3.16 seconds
Started Feb 18 01:55:09 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 210048 kb
Host smart-c485c271-1f9c-47b6-8af4-498536aff480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885415934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1885415934
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1181990356
Short name T565
Test name
Test status
Simulation time 32753649 ps
CPU time 0.83 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 206020 kb
Host smart-d151e209-367b-41ae-b293-39447fef9d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181990356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1181990356
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.74482830
Short name T267
Test name
Test status
Simulation time 137211318 ps
CPU time 7.14 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 215120 kb
Host smart-197916ab-875a-49b4-a0cc-a9a996e5e13e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74482830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.74482830
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3242377133
Short name T859
Test name
Test status
Simulation time 410728148 ps
CPU time 3.08 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 208216 kb
Host smart-fe18faab-4f22-4076-8959-8ac375081c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242377133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3242377133
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.256835496
Short name T306
Test name
Test status
Simulation time 292793534 ps
CPU time 5.46 seconds
Started Feb 18 01:55:05 PM PST 24
Finished Feb 18 01:55:16 PM PST 24
Peak memory 214444 kb
Host smart-8169f4f8-ea35-4bfd-8bd3-5907676ec2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256835496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.256835496
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.4170013573
Short name T277
Test name
Test status
Simulation time 282465551 ps
CPU time 5.71 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 210864 kb
Host smart-e127cfff-9e2f-4393-83f7-6451b00a7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170013573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4170013573
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.7999957
Short name T47
Test name
Test status
Simulation time 133571773 ps
CPU time 3.14 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 214488 kb
Host smart-7cf7e938-740e-42ec-b841-3f335d48a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7999957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.7999957
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.717372827
Short name T649
Test name
Test status
Simulation time 411946469 ps
CPU time 6.7 seconds
Started Feb 18 01:55:25 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 215144 kb
Host smart-038d865e-a8d5-4118-abc9-ce81c95068c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717372827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.717372827
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3947066883
Short name T477
Test name
Test status
Simulation time 59536443 ps
CPU time 2.91 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:14 PM PST 24
Peak memory 206540 kb
Host smart-32c7b27f-d9a0-4cb8-808a-3a636374c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947066883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3947066883
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3003562252
Short name T740
Test name
Test status
Simulation time 339885503 ps
CPU time 3.17 seconds
Started Feb 18 01:55:06 PM PST 24
Finished Feb 18 01:55:14 PM PST 24
Peak memory 208420 kb
Host smart-afbec2d9-f9d6-4d77-867c-b376bbbe3f6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003562252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3003562252
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3042645597
Short name T528
Test name
Test status
Simulation time 537279725 ps
CPU time 15.36 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 207780 kb
Host smart-490047f9-2837-4166-8e1e-ffad7f19d724
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042645597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3042645597
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2031274244
Short name T611
Test name
Test status
Simulation time 3739413858 ps
CPU time 6.81 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 207820 kb
Host smart-436b1a38-89e7-4a0c-8759-9291f5cc292d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031274244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2031274244
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2116688836
Short name T834
Test name
Test status
Simulation time 132890886 ps
CPU time 4.26 seconds
Started Feb 18 01:55:08 PM PST 24
Finished Feb 18 01:55:19 PM PST 24
Peak memory 218280 kb
Host smart-449f05a6-291d-4e90-87db-2d127c297048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116688836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2116688836
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3393688023
Short name T769
Test name
Test status
Simulation time 453431960 ps
CPU time 3.86 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 208516 kb
Host smart-22a79c74-ccc2-40bb-9209-5922a4a94c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393688023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3393688023
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2256957889
Short name T680
Test name
Test status
Simulation time 151063917 ps
CPU time 3.94 seconds
Started Feb 18 01:55:16 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 208464 kb
Host smart-f2d751f5-6b16-4ba5-b77e-e429419653df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256957889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2256957889
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.754941005
Short name T250
Test name
Test status
Simulation time 230889073 ps
CPU time 5.54 seconds
Started Feb 18 01:55:07 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 218304 kb
Host smart-78661e09-d587-42b2-a973-7f91e89dfb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754941005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.754941005
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1703026577
Short name T707
Test name
Test status
Simulation time 2141287283 ps
CPU time 17.14 seconds
Started Feb 18 01:55:12 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 210408 kb
Host smart-c3ac57a7-204c-4332-a5ff-c1e1994f562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703026577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1703026577
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1104109577
Short name T449
Test name
Test status
Simulation time 11728267 ps
CPU time 0.85 seconds
Started Feb 18 01:55:17 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 206116 kb
Host smart-5d037708-d58f-44de-8433-09ed5ee824aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104109577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1104109577
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2365462260
Short name T436
Test name
Test status
Simulation time 47078374 ps
CPU time 2.85 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 214464 kb
Host smart-4b6e9519-f1db-42b1-8398-54cd5aa5119d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365462260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2365462260
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.891611262
Short name T487
Test name
Test status
Simulation time 18765623 ps
CPU time 1.55 seconds
Started Feb 18 01:55:16 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 209928 kb
Host smart-7dc6de32-38f6-4918-ad4e-318eefaa62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891611262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.891611262
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1680106807
Short name T481
Test name
Test status
Simulation time 249201027 ps
CPU time 5.43 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 214428 kb
Host smart-b8c3a841-16d2-4dfb-af27-f416f7905ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680106807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1680106807
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1366832726
Short name T381
Test name
Test status
Simulation time 476048339 ps
CPU time 5.99 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 209880 kb
Host smart-f5e3fdaf-bbda-4449-978e-2e84265cf04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366832726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1366832726
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4250938022
Short name T474
Test name
Test status
Simulation time 372952423 ps
CPU time 4.46 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 209380 kb
Host smart-07455cfb-a4b8-4320-b5fd-d814635f1ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250938022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4250938022
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3617279831
Short name T566
Test name
Test status
Simulation time 2012896855 ps
CPU time 9.49 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 209364 kb
Host smart-170c84a5-85b2-4c10-8985-35820a7c0c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617279831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3617279831
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.415703270
Short name T209
Test name
Test status
Simulation time 66639305 ps
CPU time 3.31 seconds
Started Feb 18 01:55:17 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 206552 kb
Host smart-334d932a-b82a-488a-b26e-14f0b8e82be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415703270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.415703270
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.697420769
Short name T516
Test name
Test status
Simulation time 434732939 ps
CPU time 3.63 seconds
Started Feb 18 01:55:12 PM PST 24
Finished Feb 18 01:55:20 PM PST 24
Peak memory 208752 kb
Host smart-38aee215-3f7e-4815-bf35-17d66271933f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697420769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.697420769
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1752370762
Short name T731
Test name
Test status
Simulation time 508608384 ps
CPU time 15.42 seconds
Started Feb 18 01:55:13 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 207988 kb
Host smart-da74ec75-ef16-4d09-85c0-30f9899da571
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752370762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1752370762
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.211322621
Short name T557
Test name
Test status
Simulation time 253574072 ps
CPU time 6.01 seconds
Started Feb 18 01:55:16 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 208568 kb
Host smart-4ba26b5c-4f08-44e8-911c-0006b31b2dd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211322621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.211322621
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2584920478
Short name T696
Test name
Test status
Simulation time 146420160 ps
CPU time 1.95 seconds
Started Feb 18 01:55:22 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 207372 kb
Host smart-6973f543-2eb8-434b-a3ac-fe32b6fadeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584920478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2584920478
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2726558220
Short name T896
Test name
Test status
Simulation time 189664430 ps
CPU time 2.25 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 206604 kb
Host smart-da251cda-6e8d-49be-a7cd-4eda5ca2bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726558220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2726558220
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3689542887
Short name T499
Test name
Test status
Simulation time 44162952 ps
CPU time 3.02 seconds
Started Feb 18 01:55:16 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 207388 kb
Host smart-0934fcf1-7dba-4470-8e55-ba308fad90b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689542887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3689542887
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.318639780
Short name T2
Test name
Test status
Simulation time 50077434 ps
CPU time 1.07 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 206300 kb
Host smart-29709abe-0e66-48fe-a1c1-45c1cb0ec4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318639780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.318639780
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3419932812
Short name T22
Test name
Test status
Simulation time 149514241 ps
CPU time 2.64 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:21 PM PST 24
Peak memory 215784 kb
Host smart-80e2f85a-0157-40c4-bcc1-211ac13a31de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419932812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3419932812
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3799533597
Short name T713
Test name
Test status
Simulation time 798237821 ps
CPU time 4.02 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:23 PM PST 24
Peak memory 210212 kb
Host smart-e3d96531-da0a-4419-8f9f-165b86840fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799533597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3799533597
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.316801774
Short name T652
Test name
Test status
Simulation time 1655922636 ps
CPU time 24.84 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:48 PM PST 24
Peak memory 214420 kb
Host smart-1323ac3d-378b-4651-abca-e3498376c05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316801774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.316801774
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.203003278
Short name T815
Test name
Test status
Simulation time 111080781 ps
CPU time 5.79 seconds
Started Feb 18 01:55:14 PM PST 24
Finished Feb 18 01:55:24 PM PST 24
Peak memory 210944 kb
Host smart-54821d76-6197-4372-bba1-84581c0d0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203003278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.203003278
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.258080257
Short name T425
Test name
Test status
Simulation time 84537734 ps
CPU time 3.58 seconds
Started Feb 18 01:55:18 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 215780 kb
Host smart-dc047628-6455-49ad-b7e6-a741dab1f82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258080257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.258080257
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.969956769
Short name T292
Test name
Test status
Simulation time 121332758 ps
CPU time 3.92 seconds
Started Feb 18 01:55:24 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 218424 kb
Host smart-c503fbd5-f096-4266-a9d5-5474c070383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969956769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.969956769
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.765091958
Short name T492
Test name
Test status
Simulation time 3328791871 ps
CPU time 29.84 seconds
Started Feb 18 01:55:17 PM PST 24
Finished Feb 18 01:55:50 PM PST 24
Peak memory 208364 kb
Host smart-ba2aa8a9-6268-4706-80f1-60b0fbf48175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765091958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.765091958
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4161479555
Short name T630
Test name
Test status
Simulation time 27678308 ps
CPU time 2.29 seconds
Started Feb 18 01:55:16 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 208392 kb
Host smart-5e103d1b-efbe-41c4-81e4-9b9983ecbafd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161479555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4161479555
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2595241376
Short name T795
Test name
Test status
Simulation time 182357030 ps
CPU time 2.74 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:27 PM PST 24
Peak memory 206692 kb
Host smart-6436eea6-4441-42c5-baaf-bc99347561f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595241376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2595241376
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1481193170
Short name T336
Test name
Test status
Simulation time 407776853 ps
CPU time 3.67 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 206676 kb
Host smart-81127aa5-a6da-4fa2-9e33-9928057ad2ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481193170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1481193170
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1303605579
Short name T583
Test name
Test status
Simulation time 539712241 ps
CPU time 4.12 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 214420 kb
Host smart-17f666df-04d2-428d-8859-b14026fec08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303605579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1303605579
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3033163893
Short name T129
Test name
Test status
Simulation time 75470764 ps
CPU time 1.74 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 206212 kb
Host smart-b3ec369c-b465-431c-8e3b-715689795615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033163893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3033163893
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1785542920
Short name T479
Test name
Test status
Simulation time 139557481 ps
CPU time 3.13 seconds
Started Feb 18 01:55:18 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 208064 kb
Host smart-7b265720-adb5-4213-bf3f-d772cb259a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785542920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1785542920
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.742797133
Short name T105
Test name
Test status
Simulation time 237960471 ps
CPU time 6.24 seconds
Started Feb 18 01:55:15 PM PST 24
Finished Feb 18 01:55:25 PM PST 24
Peak memory 214468 kb
Host smart-bce9f7a2-f166-408a-a0cb-c2cca0dbb476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742797133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.742797133
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3951385544
Short name T409
Test name
Test status
Simulation time 290516237 ps
CPU time 2.47 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 209932 kb
Host smart-db2837da-507d-4616-92e7-f4ac8d96a87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951385544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3951385544
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1096575600
Short name T657
Test name
Test status
Simulation time 44433599 ps
CPU time 0.77 seconds
Started Feb 18 01:55:21 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 206024 kb
Host smart-c1544d1e-fc38-4358-aae4-467284d0af62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096575600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1096575600
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4216075466
Short name T355
Test name
Test status
Simulation time 217133416 ps
CPU time 4.29 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:27 PM PST 24
Peak memory 217632 kb
Host smart-4adadf24-870f-41f8-8f1b-83241d30e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216075466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4216075466
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3164661976
Short name T790
Test name
Test status
Simulation time 103503982 ps
CPU time 2.96 seconds
Started Feb 18 01:55:21 PM PST 24
Finished Feb 18 01:55:29 PM PST 24
Peak memory 207252 kb
Host smart-cb4cc805-299b-4e94-81f3-63384a14eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164661976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3164661976
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2609237409
Short name T874
Test name
Test status
Simulation time 277708231 ps
CPU time 6.54 seconds
Started Feb 18 01:55:24 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 214372 kb
Host smart-9c73e470-2d0b-4e36-9043-fadd017b9707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609237409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2609237409
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1938839411
Short name T274
Test name
Test status
Simulation time 683262815 ps
CPU time 4.5 seconds
Started Feb 18 01:55:29 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 222564 kb
Host smart-9fc4cd28-fa40-41f1-9a25-6f34d62ad08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938839411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1938839411
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2273878213
Short name T850
Test name
Test status
Simulation time 43698072 ps
CPU time 3.1 seconds
Started Feb 18 01:55:29 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 218116 kb
Host smart-3f413772-6db7-4a0b-801b-fadff29a0bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273878213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2273878213
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2525604611
Short name T266
Test name
Test status
Simulation time 423617334 ps
CPU time 6.64 seconds
Started Feb 18 01:55:22 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 208636 kb
Host smart-50f37da0-d214-4262-9039-62026f78edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525604611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2525604611
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3937894338
Short name T221
Test name
Test status
Simulation time 261268929 ps
CPU time 7.69 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 208620 kb
Host smart-2ab6ec76-ddda-4068-b309-ab0ba6be8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937894338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3937894338
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.620815695
Short name T746
Test name
Test status
Simulation time 266247716 ps
CPU time 7.47 seconds
Started Feb 18 01:55:24 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 207808 kb
Host smart-db0cc27f-4d09-467d-9f6e-c827e4ec1ad0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620815695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.620815695
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.658956385
Short name T531
Test name
Test status
Simulation time 116694226 ps
CPU time 3.25 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:27 PM PST 24
Peak memory 208444 kb
Host smart-5560ca29-0635-45d9-997c-deda69217d15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658956385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.658956385
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1583437973
Short name T729
Test name
Test status
Simulation time 349365184 ps
CPU time 3.38 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 208464 kb
Host smart-28d97390-3411-4968-a8ff-d08c24457c0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583437973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1583437973
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1981992926
Short name T332
Test name
Test status
Simulation time 95510653 ps
CPU time 4.32 seconds
Started Feb 18 01:55:23 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 214336 kb
Host smart-e2b3b53c-0c84-49e7-bda5-09c6e7bfec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981992926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1981992926
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3264241239
Short name T554
Test name
Test status
Simulation time 93648593 ps
CPU time 3.53 seconds
Started Feb 18 01:55:19 PM PST 24
Finished Feb 18 01:55:27 PM PST 24
Peak memory 207452 kb
Host smart-6ccc6e96-9da9-47fe-b503-9c3ccfa03e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264241239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3264241239
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2927436430
Short name T577
Test name
Test status
Simulation time 31704793 ps
CPU time 0.77 seconds
Started Feb 18 01:55:20 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 206016 kb
Host smart-edaf3dd4-6fbf-4c16-ae24-4f0559981732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927436430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2927436430
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.678022367
Short name T307
Test name
Test status
Simulation time 429818997 ps
CPU time 5.01 seconds
Started Feb 18 01:55:29 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 209712 kb
Host smart-e7fb47e9-6dd3-48d1-af68-9d40c9fe3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678022367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.678022367
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1567204424
Short name T173
Test name
Test status
Simulation time 157109389 ps
CPU time 3.09 seconds
Started Feb 18 01:55:21 PM PST 24
Finished Feb 18 01:55:28 PM PST 24
Peak memory 210356 kb
Host smart-e488ea92-8890-4787-b60b-e6589eb16711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567204424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1567204424
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3793003790
Short name T551
Test name
Test status
Simulation time 14579397 ps
CPU time 0.79 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:36 PM PST 24
Peak memory 206108 kb
Host smart-7d1d2d1e-399e-4bd7-8c42-32a178ef99a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793003790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3793003790
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3373381864
Short name T437
Test name
Test status
Simulation time 38978779 ps
CPU time 3.11 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 215408 kb
Host smart-1150f370-a7ea-4dea-8389-73747b79cb69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373381864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3373381864
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.418691817
Short name T230
Test name
Test status
Simulation time 202289216 ps
CPU time 5.27 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 210248 kb
Host smart-2488a64b-7271-451c-a589-f92ed9c348b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418691817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.418691817
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2396516191
Short name T44
Test name
Test status
Simulation time 86481087 ps
CPU time 2.14 seconds
Started Feb 18 01:55:27 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 208692 kb
Host smart-77ffd3f7-8679-458e-bd43-65b38b45e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396516191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2396516191
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2888099918
Short name T402
Test name
Test status
Simulation time 280802383 ps
CPU time 2.96 seconds
Started Feb 18 01:55:25 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 214480 kb
Host smart-0e33a51a-f824-45c0-914f-f15f0d7042b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888099918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2888099918
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1049714961
Short name T86
Test name
Test status
Simulation time 188056348 ps
CPU time 4.2 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 222568 kb
Host smart-c826c526-0988-4227-9a8f-7dc1313e0c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049714961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1049714961
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2772768824
Short name T57
Test name
Test status
Simulation time 686978433 ps
CPU time 6.41 seconds
Started Feb 18 01:55:28 PM PST 24
Finished Feb 18 01:55:36 PM PST 24
Peak memory 222672 kb
Host smart-6ea95f4a-085d-495d-981b-17e1aaf11174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772768824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2772768824
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2543014774
Short name T329
Test name
Test status
Simulation time 5284701875 ps
CPU time 35.59 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:56:14 PM PST 24
Peak memory 208392 kb
Host smart-ee07b0b4-073b-4b59-9acc-6f8c6ff1cdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543014774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2543014774
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3580828443
Short name T379
Test name
Test status
Simulation time 3875726319 ps
CPU time 34 seconds
Started Feb 18 01:55:27 PM PST 24
Finished Feb 18 01:56:03 PM PST 24
Peak memory 208360 kb
Host smart-db71beca-3329-4903-b500-8a15fefc9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580828443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3580828443
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.42842188
Short name T875
Test name
Test status
Simulation time 95508970 ps
CPU time 2.75 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 206720 kb
Host smart-5f02686a-eff3-4cc6-b9dd-d5886af93b90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.42842188
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1146818252
Short name T568
Test name
Test status
Simulation time 44476357 ps
CPU time 2.96 seconds
Started Feb 18 01:55:30 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 208628 kb
Host smart-7b9db266-0f31-44c2-821d-821788f7ca6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146818252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1146818252
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1487934195
Short name T505
Test name
Test status
Simulation time 241915374 ps
CPU time 4.29 seconds
Started Feb 18 01:55:28 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 208516 kb
Host smart-d58b58ad-40a1-4b92-b22f-4bd19ee01057
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487934195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1487934195
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2159948281
Short name T816
Test name
Test status
Simulation time 186348231 ps
CPU time 3.88 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 207432 kb
Host smart-c9668210-49f2-4095-beb9-9f53ba20c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159948281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2159948281
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1284599554
Short name T463
Test name
Test status
Simulation time 340182698 ps
CPU time 3.23 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 206624 kb
Host smart-62efbbbf-8ac5-4486-beab-bc3bb23a9b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284599554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1284599554
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.108185365
Short name T257
Test name
Test status
Simulation time 1743762359 ps
CPU time 19.45 seconds
Started Feb 18 01:55:25 PM PST 24
Finished Feb 18 01:55:48 PM PST 24
Peak memory 214552 kb
Host smart-b316d6c4-ac2c-43df-8d51-4ad0ba391f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108185365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.108185365
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3550560785
Short name T819
Test name
Test status
Simulation time 90645737 ps
CPU time 4.88 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 207452 kb
Host smart-84b3b080-e385-47ee-b704-5c2f24dfd022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550560785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3550560785
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.143674783
Short name T56
Test name
Test status
Simulation time 1473729241 ps
CPU time 6.55 seconds
Started Feb 18 01:55:28 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 210864 kb
Host smart-3a755df4-2c45-4a62-85f2-d6d1c92503eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143674783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.143674783
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.762312817
Short name T498
Test name
Test status
Simulation time 10480338 ps
CPU time 0.83 seconds
Started Feb 18 01:52:51 PM PST 24
Finished Feb 18 01:52:53 PM PST 24
Peak memory 206016 kb
Host smart-30af95f7-af4e-4661-ad1f-b7e05cfd174e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762312817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.762312817
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1938006165
Short name T246
Test name
Test status
Simulation time 278098796 ps
CPU time 2.92 seconds
Started Feb 18 01:52:43 PM PST 24
Finished Feb 18 01:52:47 PM PST 24
Peak memory 214480 kb
Host smart-a6f55930-33b1-4aad-ab63-137b29a9a141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938006165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1938006165
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2345738167
Short name T36
Test name
Test status
Simulation time 421901954 ps
CPU time 2.05 seconds
Started Feb 18 01:52:46 PM PST 24
Finished Feb 18 01:52:50 PM PST 24
Peak memory 209608 kb
Host smart-81dfbf92-7009-40d9-9926-6da16079ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345738167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2345738167
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1327974471
Short name T66
Test name
Test status
Simulation time 52596823 ps
CPU time 2.26 seconds
Started Feb 18 01:52:45 PM PST 24
Finished Feb 18 01:52:48 PM PST 24
Peak memory 209888 kb
Host smart-c7ba070d-61c3-42b7-8b5a-2014b09edbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327974471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1327974471
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3144930188
Short name T386
Test name
Test status
Simulation time 719274841 ps
CPU time 8.23 seconds
Started Feb 18 01:52:49 PM PST 24
Finished Feb 18 01:52:58 PM PST 24
Peak memory 214504 kb
Host smart-59f5110e-eeea-4cb2-b783-0ad981ac4a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144930188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3144930188
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2203760288
Short name T41
Test name
Test status
Simulation time 152315290 ps
CPU time 3.51 seconds
Started Feb 18 01:52:50 PM PST 24
Finished Feb 18 01:52:54 PM PST 24
Peak memory 216656 kb
Host smart-e2788d47-c299-4a43-9c24-5f44b94222bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203760288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2203760288
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1556531463
Short name T420
Test name
Test status
Simulation time 162567278 ps
CPU time 3.33 seconds
Started Feb 18 01:52:44 PM PST 24
Finished Feb 18 01:52:48 PM PST 24
Peak memory 206936 kb
Host smart-8bdcc767-ec30-4595-a2ad-b5c0df650b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556531463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1556531463
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1578435417
Short name T634
Test name
Test status
Simulation time 46381749 ps
CPU time 2.67 seconds
Started Feb 18 01:52:46 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 207748 kb
Host smart-3e0f7819-f9bd-4cdc-829c-1626249b706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578435417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1578435417
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2334257571
Short name T550
Test name
Test status
Simulation time 56628480 ps
CPU time 2.99 seconds
Started Feb 18 01:52:45 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 206824 kb
Host smart-21708fee-eb4a-4654-bb5f-3214acc81a7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334257571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2334257571
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.75674486
Short name T856
Test name
Test status
Simulation time 158604629 ps
CPU time 6.46 seconds
Started Feb 18 01:52:43 PM PST 24
Finished Feb 18 01:52:50 PM PST 24
Peak memory 208212 kb
Host smart-74420b39-880b-47f9-9d62-5ce35d688ee1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75674486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.75674486
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.253291472
Short name T128
Test name
Test status
Simulation time 133271641 ps
CPU time 5.55 seconds
Started Feb 18 01:52:42 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 208980 kb
Host smart-d25cca8c-7532-47a9-9edb-2b8f8eaba1ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253291472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.253291472
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2632576309
Short name T439
Test name
Test status
Simulation time 1189772374 ps
CPU time 8.54 seconds
Started Feb 18 01:52:47 PM PST 24
Finished Feb 18 01:52:57 PM PST 24
Peak memory 208220 kb
Host smart-a81e3149-eeef-4746-9664-222c94329f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632576309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2632576309
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1186772968
Short name T471
Test name
Test status
Simulation time 243440883 ps
CPU time 2.83 seconds
Started Feb 18 01:52:45 PM PST 24
Finished Feb 18 01:52:49 PM PST 24
Peak memory 207232 kb
Host smart-6737fa7c-a49f-413e-8126-cdc3800dcfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186772968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1186772968
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1844150665
Short name T191
Test name
Test status
Simulation time 137645062 ps
CPU time 5.39 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:52:55 PM PST 24
Peak memory 207252 kb
Host smart-604f45c3-1927-4c41-ae9d-891d72e081cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844150665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1844150665
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1891827581
Short name T393
Test name
Test status
Simulation time 188807862 ps
CPU time 4.39 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:52:54 PM PST 24
Peak memory 206540 kb
Host smart-33e39d52-26a3-4725-b95f-3f1980bc9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891827581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1891827581
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3355997870
Short name T596
Test name
Test status
Simulation time 71166220 ps
CPU time 3.02 seconds
Started Feb 18 01:52:51 PM PST 24
Finished Feb 18 01:52:55 PM PST 24
Peak memory 209968 kb
Host smart-6df1b0d5-768e-49ec-b063-04dfe28cad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355997870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3355997870
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1481360198
Short name T445
Test name
Test status
Simulation time 73735249 ps
CPU time 0.83 seconds
Started Feb 18 01:53:02 PM PST 24
Finished Feb 18 01:53:04 PM PST 24
Peak memory 206108 kb
Host smart-ef7884d3-936c-4567-bf3c-3f983f168dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481360198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1481360198
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2121718025
Short name T431
Test name
Test status
Simulation time 48222067 ps
CPU time 3.7 seconds
Started Feb 18 01:52:57 PM PST 24
Finished Feb 18 01:53:02 PM PST 24
Peak memory 215584 kb
Host smart-e660281c-2f81-4474-a0d2-75a24df8d695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121718025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2121718025
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2741902541
Short name T786
Test name
Test status
Simulation time 311796620 ps
CPU time 2.72 seconds
Started Feb 18 01:52:56 PM PST 24
Finished Feb 18 01:53:00 PM PST 24
Peak memory 210120 kb
Host smart-66fb204e-6357-4373-8729-e903d3ba4809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741902541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2741902541
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3995989013
Short name T851
Test name
Test status
Simulation time 38745092 ps
CPU time 2.72 seconds
Started Feb 18 01:52:57 PM PST 24
Finished Feb 18 01:53:01 PM PST 24
Peak memory 209520 kb
Host smart-4c3db81f-b56f-40f4-80f0-288902b62868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995989013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3995989013
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.344944552
Short name T383
Test name
Test status
Simulation time 47830025 ps
CPU time 3.18 seconds
Started Feb 18 01:52:53 PM PST 24
Finished Feb 18 01:52:58 PM PST 24
Peak memory 211620 kb
Host smart-86ab9575-cbe3-48c3-b989-1b9397ab81a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344944552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.344944552
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3850680528
Short name T46
Test name
Test status
Simulation time 120948617 ps
CPU time 3.2 seconds
Started Feb 18 01:52:57 PM PST 24
Finished Feb 18 01:53:02 PM PST 24
Peak memory 214548 kb
Host smart-9623f783-9a4e-41d7-825c-31ffa7da31d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850680528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3850680528
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3638828949
Short name T493
Test name
Test status
Simulation time 30360196 ps
CPU time 2.32 seconds
Started Feb 18 01:52:55 PM PST 24
Finished Feb 18 01:52:58 PM PST 24
Peak memory 214456 kb
Host smart-3bd2b390-c485-4ffd-b9e4-f00ae0bc8966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638828949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3638828949
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2153073198
Short name T642
Test name
Test status
Simulation time 216511254 ps
CPU time 3 seconds
Started Feb 18 01:52:49 PM PST 24
Finished Feb 18 01:52:53 PM PST 24
Peak memory 206764 kb
Host smart-cf546089-3200-4c7c-bfd6-23a0ecbab3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153073198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2153073198
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4136433451
Short name T709
Test name
Test status
Simulation time 5669901652 ps
CPU time 15.19 seconds
Started Feb 18 01:52:54 PM PST 24
Finished Feb 18 01:53:10 PM PST 24
Peak memory 208204 kb
Host smart-2fff48d1-400f-4608-9471-2b83096eecbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136433451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4136433451
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3142823100
Short name T558
Test name
Test status
Simulation time 138399722 ps
CPU time 3.33 seconds
Started Feb 18 01:52:48 PM PST 24
Finished Feb 18 01:52:53 PM PST 24
Peak memory 206768 kb
Host smart-b31a41ce-80c4-4202-b225-e807933401b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142823100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3142823100
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3573358732
Short name T606
Test name
Test status
Simulation time 204896759 ps
CPU time 6.07 seconds
Started Feb 18 01:52:58 PM PST 24
Finished Feb 18 01:53:06 PM PST 24
Peak memory 207812 kb
Host smart-10007610-17fc-49ac-a1ce-1ebda451876f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573358732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3573358732
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1318308755
Short name T892
Test name
Test status
Simulation time 154881698 ps
CPU time 1.53 seconds
Started Feb 18 01:52:59 PM PST 24
Finished Feb 18 01:53:01 PM PST 24
Peak memory 207796 kb
Host smart-c5b1eb6e-ae7a-45a8-8fb6-122bdabda47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318308755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1318308755
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2358624322
Short name T421
Test name
Test status
Simulation time 125808176 ps
CPU time 2.47 seconds
Started Feb 18 01:52:47 PM PST 24
Finished Feb 18 01:52:51 PM PST 24
Peak memory 206644 kb
Host smart-6d3e7ca1-a5e4-44cb-983f-db93c81b91d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358624322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2358624322
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.586080756
Short name T34
Test name
Test status
Simulation time 4134906138 ps
CPU time 29.08 seconds
Started Feb 18 01:52:54 PM PST 24
Finished Feb 18 01:53:24 PM PST 24
Peak memory 216304 kb
Host smart-33a3cb89-cc29-49bd-84e7-2038cd09e220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586080756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.586080756
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3906420217
Short name T127
Test name
Test status
Simulation time 62862001 ps
CPU time 4.22 seconds
Started Feb 18 01:52:52 PM PST 24
Finished Feb 18 01:52:58 PM PST 24
Peak memory 207604 kb
Host smart-abfab14d-505f-4b6e-99b7-c9b53ee3a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906420217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3906420217
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4206122420
Short name T525
Test name
Test status
Simulation time 110420038 ps
CPU time 1.9 seconds
Started Feb 18 01:52:57 PM PST 24
Finished Feb 18 01:53:00 PM PST 24
Peak memory 210036 kb
Host smart-413a14ba-34c0-402e-9049-3e8318c01b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206122420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4206122420
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1626412180
Short name T640
Test name
Test status
Simulation time 53541060 ps
CPU time 0.76 seconds
Started Feb 18 01:53:12 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 206032 kb
Host smart-4d3b6bbc-1445-4fbc-bca9-80f7ba82e6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626412180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1626412180
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.896212871
Short name T559
Test name
Test status
Simulation time 140815522 ps
CPU time 4.98 seconds
Started Feb 18 01:53:02 PM PST 24
Finished Feb 18 01:53:08 PM PST 24
Peak memory 209472 kb
Host smart-a0e7d78c-abf7-4e22-a4a4-03ecebd24a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896212871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.896212871
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2991712130
Short name T202
Test name
Test status
Simulation time 55164918 ps
CPU time 1.68 seconds
Started Feb 18 01:53:08 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 208360 kb
Host smart-4bcd2bb3-0d19-43fe-a2fa-3765f110b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991712130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2991712130
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2469573982
Short name T754
Test name
Test status
Simulation time 127074729 ps
CPU time 5.84 seconds
Started Feb 18 01:53:05 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 209240 kb
Host smart-9839f48c-b8ea-43ce-9196-0ff487c39a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469573982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2469573982
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2303917417
Short name T275
Test name
Test status
Simulation time 298000906 ps
CPU time 10.14 seconds
Started Feb 18 01:53:04 PM PST 24
Finished Feb 18 01:53:14 PM PST 24
Peak memory 211256 kb
Host smart-2c9f4f1b-a0a4-45ce-a0c9-e471cfb3776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303917417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2303917417
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3590083500
Short name T619
Test name
Test status
Simulation time 417390620 ps
CPU time 5.94 seconds
Started Feb 18 01:53:04 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 214476 kb
Host smart-f20ea2af-4718-4e07-91b4-693dedb77f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590083500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3590083500
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3715767303
Short name T654
Test name
Test status
Simulation time 69507986 ps
CPU time 2.69 seconds
Started Feb 18 01:53:07 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 208004 kb
Host smart-bee05e68-d243-495f-8d32-1e16c34079ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715767303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3715767303
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.605302351
Short name T747
Test name
Test status
Simulation time 231901958 ps
CPU time 2.4 seconds
Started Feb 18 01:53:04 PM PST 24
Finished Feb 18 01:53:08 PM PST 24
Peak memory 206672 kb
Host smart-4b225f39-51e8-45c5-9f36-696e7eb48e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605302351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.605302351
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1253897133
Short name T864
Test name
Test status
Simulation time 38804852 ps
CPU time 2.46 seconds
Started Feb 18 01:53:03 PM PST 24
Finished Feb 18 01:53:06 PM PST 24
Peak memory 207516 kb
Host smart-a4d1f794-af05-4a9c-9eb3-4afea9aa155b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253897133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1253897133
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3767082901
Short name T102
Test name
Test status
Simulation time 473139572 ps
CPU time 4.54 seconds
Started Feb 18 01:53:05 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 208992 kb
Host smart-6c0b2e45-9bc4-4258-8c6f-0c6e6d66e0f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767082901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3767082901
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2590523310
Short name T377
Test name
Test status
Simulation time 359878734 ps
CPU time 3.42 seconds
Started Feb 18 01:53:05 PM PST 24
Finished Feb 18 01:53:10 PM PST 24
Peak memory 208564 kb
Host smart-fe2901aa-cb36-4f81-b50d-ee34ead8e4a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590523310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2590523310
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1854319001
Short name T422
Test name
Test status
Simulation time 44884155 ps
CPU time 2.15 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 206772 kb
Host smart-07236149-f730-48f4-90f1-472b8af8548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854319001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1854319001
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2437559158
Short name T424
Test name
Test status
Simulation time 1715291802 ps
CPU time 29.7 seconds
Started Feb 18 01:53:04 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 208468 kb
Host smart-83827800-07f4-4b0a-bd59-ba8eed4b0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437559158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2437559158
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4156913548
Short name T295
Test name
Test status
Simulation time 293145355 ps
CPU time 4.94 seconds
Started Feb 18 01:53:08 PM PST 24
Finished Feb 18 01:53:14 PM PST 24
Peak memory 216068 kb
Host smart-8c4289aa-65d6-408a-b4e0-e24bc584e245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156913548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4156913548
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1848572705
Short name T488
Test name
Test status
Simulation time 169501048 ps
CPU time 5.64 seconds
Started Feb 18 01:53:04 PM PST 24
Finished Feb 18 01:53:11 PM PST 24
Peak memory 214380 kb
Host smart-82e78ae2-78be-48cc-96c7-8067e6282299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848572705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1848572705
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4186438872
Short name T39
Test name
Test status
Simulation time 115886548 ps
CPU time 1.85 seconds
Started Feb 18 01:53:09 PM PST 24
Finished Feb 18 01:53:13 PM PST 24
Peak memory 209876 kb
Host smart-aebbac98-87f2-4c9a-8299-96d1341187d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186438872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4186438872
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4087189043
Short name T621
Test name
Test status
Simulation time 15026563 ps
CPU time 0.91 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:15 PM PST 24
Peak memory 206228 kb
Host smart-3ddb928f-8ab3-45c5-a3b4-5709818f3f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087189043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4087189043
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3729551666
Short name T489
Test name
Test status
Simulation time 79253014 ps
CPU time 4.35 seconds
Started Feb 18 01:53:08 PM PST 24
Finished Feb 18 01:53:14 PM PST 24
Peak memory 210152 kb
Host smart-13ab2446-61f9-4e5d-b4e5-059fd2608836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729551666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3729551666
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3474605257
Short name T633
Test name
Test status
Simulation time 102364188 ps
CPU time 2.96 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:20 PM PST 24
Peak memory 207040 kb
Host smart-242e9288-118d-4c2b-916e-44433017706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474605257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3474605257
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2887786839
Short name T82
Test name
Test status
Simulation time 90037218 ps
CPU time 4.1 seconds
Started Feb 18 01:53:08 PM PST 24
Finished Feb 18 01:53:14 PM PST 24
Peak memory 209096 kb
Host smart-6e7e9eaf-f85a-4506-a98e-a6e0459a4fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887786839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2887786839
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2719042133
Short name T303
Test name
Test status
Simulation time 178438168 ps
CPU time 8.48 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:23 PM PST 24
Peak memory 211924 kb
Host smart-109c35c5-3149-470e-a25a-625121d757fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719042133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2719042133
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1953564307
Short name T63
Test name
Test status
Simulation time 45243980 ps
CPU time 3.04 seconds
Started Feb 18 01:53:12 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 220016 kb
Host smart-3d6b4b00-8a5a-49d5-81b2-1bd5a2060539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953564307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1953564307
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3782321537
Short name T573
Test name
Test status
Simulation time 424506016 ps
CPU time 2.35 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:19 PM PST 24
Peak memory 208680 kb
Host smart-c95f726f-4b9b-4865-a8fa-5209e192a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782321537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3782321537
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4267729432
Short name T605
Test name
Test status
Simulation time 214616082 ps
CPU time 7.22 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:24 PM PST 24
Peak memory 206672 kb
Host smart-b47f0a49-deeb-4ff1-ac1c-01227cb9bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267729432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4267729432
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1356631055
Short name T530
Test name
Test status
Simulation time 121961514 ps
CPU time 4 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:18 PM PST 24
Peak memory 206584 kb
Host smart-025080da-dd6d-4c75-bad0-06199dc459e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356631055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1356631055
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1462527525
Short name T470
Test name
Test status
Simulation time 42337052 ps
CPU time 2.63 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:19 PM PST 24
Peak memory 206644 kb
Host smart-5a1f7e8b-5231-4056-86f2-f0b17877b4f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462527525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1462527525
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1136545919
Short name T891
Test name
Test status
Simulation time 4384111052 ps
CPU time 45.87 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:54:02 PM PST 24
Peak memory 208616 kb
Host smart-54ebb77c-f9b2-4095-91c2-402984a6c79f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136545919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1136545919
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4273929504
Short name T465
Test name
Test status
Simulation time 142694556 ps
CPU time 2.66 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:17 PM PST 24
Peak memory 208148 kb
Host smart-6a1e35ba-8f47-42e1-8270-09e740b39b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273929504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4273929504
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.303467736
Short name T572
Test name
Test status
Simulation time 176733367 ps
CPU time 2.69 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:18 PM PST 24
Peak memory 206636 kb
Host smart-f21edb34-04e2-4f80-9ecc-3841fde445dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303467736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.303467736
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1020031775
Short name T821
Test name
Test status
Simulation time 278738558 ps
CPU time 11.21 seconds
Started Feb 18 01:53:09 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 221400 kb
Host smart-4d3a1142-513d-475a-847c-d7c0b36eec22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020031775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1020031775
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2121349397
Short name T485
Test name
Test status
Simulation time 274495899 ps
CPU time 7.59 seconds
Started Feb 18 01:53:08 PM PST 24
Finished Feb 18 01:53:17 PM PST 24
Peak memory 208676 kb
Host smart-872ee896-6a51-4d45-9089-5014db9b66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121349397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2121349397
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3005241889
Short name T635
Test name
Test status
Simulation time 157671577 ps
CPU time 1.54 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:15 PM PST 24
Peak memory 209520 kb
Host smart-c1230564-54e5-4319-9115-2652ba4327cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005241889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3005241889
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1662201522
Short name T539
Test name
Test status
Simulation time 29009994 ps
CPU time 0.88 seconds
Started Feb 18 01:53:12 PM PST 24
Finished Feb 18 01:53:20 PM PST 24
Peak memory 205528 kb
Host smart-277c74fb-7a0b-46af-b103-0e3aab85a6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662201522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1662201522
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1495020185
Short name T438
Test name
Test status
Simulation time 80519096 ps
CPU time 3.19 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:21 PM PST 24
Peak memory 214412 kb
Host smart-aea1bfbd-8cf2-441b-9cef-361c2711547c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495020185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1495020185
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2606484660
Short name T814
Test name
Test status
Simulation time 132586065 ps
CPU time 4.19 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:21 PM PST 24
Peak memory 221576 kb
Host smart-1a4ee125-8b49-4888-82d7-78cdf7f92484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606484660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2606484660
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3297114976
Short name T490
Test name
Test status
Simulation time 122345610 ps
CPU time 2.36 seconds
Started Feb 18 01:53:14 PM PST 24
Finished Feb 18 01:53:25 PM PST 24
Peak memory 210112 kb
Host smart-c2081096-2bbf-42a6-8596-044c6ab4764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297114976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3297114976
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2233819098
Short name T93
Test name
Test status
Simulation time 708584543 ps
CPU time 12.31 seconds
Started Feb 18 01:53:11 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 214476 kb
Host smart-058da5cc-f20d-4195-9f75-21e88f1066d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233819098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2233819098
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3333338912
Short name T53
Test name
Test status
Simulation time 231700656 ps
CPU time 3.72 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:19 PM PST 24
Peak memory 220352 kb
Host smart-371ffc1a-c2ce-49f1-a1ce-666c87179a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333338912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3333338912
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_sideload.921284913
Short name T882
Test name
Test status
Simulation time 705404011 ps
CPU time 20.76 seconds
Started Feb 18 01:53:10 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 208176 kb
Host smart-0cd1199b-492b-41ff-abf0-678e8179b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921284913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.921284913
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3160021581
Short name T692
Test name
Test status
Simulation time 70813153 ps
CPU time 3.33 seconds
Started Feb 18 01:53:18 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 208504 kb
Host smart-a430ca5e-e0a5-4dd6-a529-09d345c83806
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160021581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3160021581
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2912657575
Short name T517
Test name
Test status
Simulation time 310707697 ps
CPU time 4.03 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:29 PM PST 24
Peak memory 208608 kb
Host smart-9f49917e-42db-4b0d-8349-3ffc98f00c43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912657575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2912657575
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.815670784
Short name T553
Test name
Test status
Simulation time 480740463 ps
CPU time 6.15 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:31 PM PST 24
Peak memory 207864 kb
Host smart-7a8acc23-0fa7-4fb5-89d7-b863786c4a48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815670784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.815670784
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1426186282
Short name T837
Test name
Test status
Simulation time 309239817 ps
CPU time 2.26 seconds
Started Feb 18 01:53:15 PM PST 24
Finished Feb 18 01:53:25 PM PST 24
Peak memory 207780 kb
Host smart-1d304494-2cf3-4df2-afc4-028938648756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426186282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1426186282
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2952151945
Short name T645
Test name
Test status
Simulation time 93917513 ps
CPU time 3.13 seconds
Started Feb 18 01:53:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 208208 kb
Host smart-a6510035-c64e-4d1b-b633-7cb670bfd087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952151945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2952151945
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2107707297
Short name T890
Test name
Test status
Simulation time 397925838 ps
CPU time 5.22 seconds
Started Feb 18 01:53:18 PM PST 24
Finished Feb 18 01:53:30 PM PST 24
Peak memory 208900 kb
Host smart-8ca7965f-cf31-406d-9ae7-2d520959535d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107707297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2107707297
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.471995022
Short name T109
Test name
Test status
Simulation time 142640539 ps
CPU time 10.89 seconds
Started Feb 18 01:53:20 PM PST 24
Finished Feb 18 01:53:36 PM PST 24
Peak memory 222552 kb
Host smart-be17cda9-6259-4099-96f2-bf9e4c3e7b11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471995022 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.471995022
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.446600929
Short name T509
Test name
Test status
Simulation time 4404480415 ps
CPU time 45.87 seconds
Started Feb 18 01:53:15 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 214504 kb
Host smart-e4d7d4bd-9c1c-4799-ac6e-5055ba34a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446600929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.446600929
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.251915687
Short name T167
Test name
Test status
Simulation time 147618350 ps
CPU time 3.02 seconds
Started Feb 18 01:53:12 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 209588 kb
Host smart-180fb02f-7c29-4460-8024-7efa537abda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251915687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.251915687
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%