Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	44	1			T38	2		T39	1		T28	1
auto[OpGenId]	12	1			T9	1		T25	1		T38	1
auto[OpGenSwOut]	20	1			T49	2		T39	1		T54	1
auto[OpGenHwOut]	13	1			T8	1		T41	1		T210	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1694	1			T44	3		T45	2		T51	2
auto[StInit]	74	1			T7	1		T46	1		T44	1
auto[StCreatorRootKey]	58	1			T29	1		T8	1		T139	1
auto[StOwnerIntKey]	41	1			T30	1		T23	1		T53	1
auto[StOwnerKey]	28	1			T22	1		T36	1		T57	1
auto[StDisabled]	435	1			T3	1		T12	3		T44	6
auto[StInvalid]	42	1			T31	1		T32	1		T48	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3350

1

T1

1

T2

1

T3

2

auto[1]

89

1

T8

1

T9

1

T25

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1687	1			T44	3		T45	2		T51	2
auto[StReset]	auto[1]	7	1			T38	1		T62	1		T47	1
auto[StInit]	auto[0]	41	1			T7	1		T46	1		T44	1
auto[StInit]	auto[1]	33	1			T9	1		T25	1		T38	1
auto[StCreatorRootKey]	auto[0]	42	1			T29	1		T139	1		T21	1
auto[StCreatorRootKey]	auto[1]	16	1			T8	1		T38	1		T39	1
auto[StOwnerIntKey]	auto[0]	27	1			T30	1		T23	1		T53	1
auto[StOwnerIntKey]	auto[1]	14	1			T39	1		T28	1		T54	1
auto[StOwnerKey]	auto[0]	19	1			T22	1		T36	1		T57	1
auto[StOwnerKey]	auto[1]	9	1			T58	1		T43	1		T67	1
auto[StDisabled]	auto[0]	425	1			T3	1		T12	3		T44	6
auto[StDisabled]	auto[1]	10	1			T211	1		T212	1		T41	1
auto[StInvalid]	auto[0]	42	1			T31	1		T32	1		T48	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T38	1		T47	1		T137	1
auto[StReset]	auto[OpGenId]	1	1			T62	1		-	-		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T213	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	14	1			T40	1		T214	1		T133	1
auto[StInit]	auto[OpGenId]	7	1			T9	1		T25	1		T38	1
auto[StInit]	auto[OpGenSwOut]	7	1			T49	2		T215	1		T188	1
auto[StInit]	auto[OpGenHwOut]	5	1			T41	1		T210	1		T42	1
auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T38	1		T216	1		T217	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T212	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T39	1		T218	1		T47	2
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T8	1		T188	1		T219	1
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T39	1		T28	1		T55	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T54	1		T220	1		T221	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T43	1		T47	1		T222	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T58	1		T43	1		T67	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T69	1		T188	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T223	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T224	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T41	1		T43	1		T65	1
auto[StDisabled]	auto[OpGenId]	1	1			T211	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T212	1		T224	1		-	-