Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.53	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	78	252	76.36

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	59	221	78.93	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4735

1

T1

6

T2

4

T3

8

auto[1]

563

1

T1

3

T3

2

T12

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4735

1

T1

6

T2

4

T3

8

auto[1]

563

1

T1

3

T3

2

T12

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4754

1

T1

9

T2

4

T3

8

auto[1]

544

1

T3

2

T13

4

T44

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4754

1

T1

9

T2

4

T3

8

auto[1]

544

1

T3

2

T13

4

T44

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	425	1			T3	1		T10	2		T130	1
auto[OpGenId]	1159	1			T1	3		T3	8		T10	2
auto[OpGenSwOut]	1129	1			T1	3		T2	3		T12	4
auto[OpGenHwOut]	2512	1			T1	3		T2	1		T3	1
auto[OpDisable]	73	1			T44	1		T51	1		T52	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	425	1			T3	1		T10	2		T130	1
auto[OpGenId]	1159	1			T1	3		T3	8		T10	2
auto[OpGenSwOut]	1129	1			T1	3		T2	3		T12	4
auto[OpGenHwOut]	2512	1			T1	3		T2	1		T3	1
auto[OpDisable]	73	1			T44	1		T51	1		T52	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4740

1

T1

9

T2

1

T3

9

auto[1]

558

1

T2

3

T3

1

T12

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4740

1

T1

9

T2

1

T3

9

auto[1]

558

1

T2

3

T3

1

T12

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4993

1

T1

9

T2

4

T3

10

auto[1]

305

1

T104

3

T116

4

T132

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1799	1			T1	3		T2	2		T3	2
auto[1]	695	1			T3	2		T12	2		T13	1
auto[2]	673	1			T1	2		T2	1		T3	1
auto[3]	692	1			T1	2		T3	3		T10	2
auto[4]	323	1			T10	1		T13	1		T75	1
auto[5]	396	1			T1	1		T2	1		T12	1
auto[6]	382	1			T1	1		T3	1		T12	1
auto[7]	338	1			T3	1		T13	2		T129	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1439	1			T1	2		T2	1		T3	2
clear_one[1]	695	1			T3	2		T12	2		T13	1
clear_one[2]	673	1			T1	2		T2	1		T3	1
clear_one[3]	692	1			T1	2		T3	3		T10	2
clear_none	1799	1			T1	3		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	929	1			T1	2		T3	2		T12	1
auto[StInit]	744	1			T1	1		T3	1		T10	6
auto[StCreatorRootKey]	587	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	516	1			T1	1		T3	2		T12	2
auto[StOwnerKey]	465	1			T1	1		T3	1		T12	1
auto[StDisabled]	1895	1			T1	3		T2	3		T3	3
auto[StInvalid]	162	1			T31	5		T32	6		T48	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	929	1			T1	2		T3	2		T12	1
auto[StInit]	744	1			T1	1		T3	1		T10	6
auto[StCreatorRootKey]	587	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	516	1			T1	1		T3	2		T12	2
auto[StOwnerKey]	465	1			T1	1		T3	1		T12	1
auto[StDisabled]	1895	1			T1	3		T2	3		T3	3
auto[StInvalid]	162	1			T31	5		T32	6		T48	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	59	221	78.93	59

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[4] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[5]]	[auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[5]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	--	--	2
[auto[4] - auto[5]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[5]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T225	1		T226	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	144	1			T3	2		T14	1		T192	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	155	1			T1	1		T129	1		T44	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	242	1			T12	1		T201	1		T31	1
auto[0]	auto[StInit]	auto[OpAdvance]	39	1			T10	1		T44	1		T104	1
auto[0]	auto[StInit]	auto[OpGenId]	96	1			T10	1		T227	1		T117	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	106	1			T71	1		T22	1		T20	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	192	1			T10	1		T13	1		T75	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	37	1			T38	1		T23	1		T78	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	56	1			T51	1		T38	2		T194	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	43	1			T38	1		T118	1		T228	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	77	1			T2	1		T44	1		T38	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	18	1			T130	1		T118	1		T96	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T59	1		T96	1		T16	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T12	1		T15	1		T104	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T1	1		T13	1		T72	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T116	1		T96	1		T205	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	33	1			T70	1		T38	1		T116	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T104	1		T49	1		T229	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T186	1		T72	1		T104	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	21	1			T230	1		T64	1		T231	1
auto[0]	auto[StDisabled]	auto[OpGenId]	74	1			T44	1		T59	1		T227	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T1	1		T2	1		T186	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T12	1		T13	1		T77	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T44	1		T232	1		T233	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	6	1			T193	1		T234	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenId]	11	1			T193	1		T83	1		T236	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T82	1		T237	1		T238	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T48	1		T239	1		T240	1
auto[1]	auto[StReset]	auto[OpGenId]	11	1			T181	1		T39	1		T110	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T16	1		T241	1		T242	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T44	1		T209	1		T243	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T208	1		T211	1		T43	1
auto[1]	auto[StInit]	auto[OpGenId]	19	1			T3	1		T85	1		T205	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T16	1		T244	1		T245	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	31	1			T191	1		T170	1		T85	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T22	1		T57	1		T27	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T119	1		T244	1		T110	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T38	1		T43	1		T187	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T201	1		T45	1		T246	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T55	1		T247	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T75	1		T249	1		T43	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T250	1		T241	1		T43	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T201	1		T206	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T38	1		T117	1		T252	2
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T253	1		T254	1		T241	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T49	1		T255	1		T65	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T12	1		T201	1		T206	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T70	1		T78	1		T178	1
auto[1]	auto[StDisabled]	auto[OpGenId]	54	1			T3	1		T12	1		T200	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T38	2		T253	1		T96	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T13	1		T201	1		T209	1
auto[1]	auto[StDisabled]	auto[OpDisable]	5	1			T49	1		T256	1		T257	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T82	1		T258	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T32	1		T48	1		T193	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T48	2		T193	1		T195	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T195	1		T260	1		T261	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T1	1		T44	1		T19	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T204	1		T230	1		T119	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	45	1			T201	2		T31	1		T38	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T20	1		T262	1		T47	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T44	1		T81	1		T263	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T14	1		T192	1		T170	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T1	1		T19	1		T243	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T212	1		T264	1		T265	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T204	1		T52	1		T266	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T49	1		T229	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T268	1		T182	1		T269	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T71	1		T270	1		T271	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T38	2		T211	1		T65	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T38	1		T56	1		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T51	1		T246	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T59	1		T211	1		T231	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T19	1		T273	1		T64	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T211	1		T241	1		T42	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T77	1		T246	1		T268	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T230	1		T120	1		T181	1
auto[2]	auto[StDisabled]	auto[OpGenId]	62	1			T3	1		T44	1		T70	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T2	1		T12	2		T38	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T12	1		T77	1		T44	1
auto[2]	auto[StDisabled]	auto[OpDisable]	16	1			T52	1		T56	1		T64	1
auto[2]	auto[StInvalid]	auto[OpGenId]	5	1			T83	1		T236	1		T274	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T275	1		T239	1		T276	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T31	2		T195	1		T275	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T44	1		T241	1		T258	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T208	1		T207	1		T49	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	29	1			T206	1		T230	1		T203	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T10	1		T32	1		T81	1
auto[3]	auto[StInit]	auto[OpGenId]	18	1			T10	1		T84	1		T120	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	15	1			T277	1		T110	1		T64	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	25	1			T12	1		T201	1		T268	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T132	1		T33	1		T65	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	20	1			T277	1		T181	1		T39	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T278	1		T233	1		T279	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	31	1			T3	1		T77	1		T280	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T44	1		T110	1		T241	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T3	1		T129	1		T227	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T192	1		T198	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T12	1		T95	1		T178	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T212	1		T224	1		T248	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	10	1			T1	1		T282	1		T283	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T38	1		T199	1		T110	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T13	1		T203	1		T284	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	36	1			T132	2		T92	1		T120	1
auto[3]	auto[StDisabled]	auto[OpGenId]	59	1			T1	1		T3	1		T70	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T15	1		T44	1		T104	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	169	1			T201	1		T44	1		T72	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T51	1		T39	1		T285	2
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T48	1		T195	1		T261	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T31	1		T32	1		T83	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T31	1		T260	1		T276	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T285	1		T286	1		T43	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T26	1		T110	2		T287	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T203	2		T268	1		T280	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T79	1		T58	1		T288	1
auto[4]	auto[StInit]	auto[OpGenId]	11	1			T207	1		T112	2		T289	2
auto[4]	auto[StInit]	auto[OpGenSwOut]	2	1			T290	1		T291	1		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T10	1		T39	1		T292	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T16	1		T270	1		T241	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T293	1		T66	1		T67	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T13	1		T72	1		T206	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T294	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T44	1		T90	1		T241	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T295	1		T285	1		T41	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T77	1		T243	1		T296	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T49	1		T297	1		T298	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	1	1			T175	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T44	1		T211	1		T289	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T202	1		T97	1		T182	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T132	1		T119	2		T64	1
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T75	1		T38	1		T96	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T204	1		T208	1		T281	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T72	1		T209	1		T246	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T211	1		T299	1		T300	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T193	1		T275	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T82	1		T196	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T82	1		T258	1		T261	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T301	1		T302	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T19	1		T38	1		T43	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	15	1			T82	1		T247	1		T303	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T52	1		T304	1		T286	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T134	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	12	1			T19	1		T85	1		T229	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	2	1			T39	1		T79	1		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T72	1		T84	1		T206	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T44	1		T208	1		T117	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T117	2		T65	1		T305	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	31	1			T1	1		T209	1		T272	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T132	2		T64	1		T306	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T132	1		T64	1		T307	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T211	1		T225	1		T308	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T230	1		T203	1		T110	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T306	1		T225	1		T65	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T38	1		T132	1		T228	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T75	1		T225	1		T43	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T93	1		T309	1		T310	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T78	1		T49	1		T295	1
auto[5]	auto[StDisabled]	auto[OpGenId]	33	1			T311	1		T281	1		T90	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T2	1		T75	1		T192	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T12	1		T201	1		T186	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T90	1		T179	1		T65	2
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T32	1		T275	1		T312	1
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T31	1		T235	1		T313	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T234	1		T260	1		T314	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T236	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T90	1		T41	1		T286	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T230	1		T315	1		T33	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T243	1		T95	1		T181	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T316	1		T317	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T81	1		T279	1		T318	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T170	1		T319	1		T320	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	17	1			T84	1		T203	1		T110	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T321	1		T322	1		T323	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T324	1		T211	1		T111	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T12	1		T178	1		T325	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T130	1		T95	1		T326	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T321	1		T211	1		T327	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T24	1		T267	1		T47	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T204	1		T119	1		T323	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T209	1		T202	1		T90	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T64	1		T265	1		T328	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T3	1		T64	1		T285	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T44	1		T90	1		T329	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T330	3		T331	1		T332	3
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T116	1		T306	2		T322	3
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T45	1		T38	1		T49	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T1	1		T192	1		T59	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T77	2		T246	1		T116	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T40	1		T279	1		T41	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T333	1		T334	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T83	1		T335	1		T336	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T337	1		T338	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T193	1		T83	1		T302	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T31	1		T110	1		T241	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	4	1			T250	1		T47	1		T302	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	18	1			T32	1		T202	1		T339	1
auto[7]	auto[StInit]	auto[OpAdvance]	7	1			T340	1		T288	1		T320	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T212	1		T247	1		T341	2
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T80	1		T342	1		T343	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T209	1		T93	1		T280	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T344	1		T345	1		T346	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T347	1		T64	1		T211	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T286	1		T348	2		T43	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T243	1		T349	1		T350	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T3	1		T117	2		T49	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T69	1		T351	1		T248	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T184	1		T43	1		T352	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T353	1		T254	1		T332	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T49	1		T354	1		T315	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T129	1		T117	1		T277	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T355	1		T114	1		T356	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T194	1		T357	1		T358	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T118	1		T49	1		T354	1
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T38	1		T116	1		T208	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T38	1		T354	3		T285	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T13	2		T72	1		T194	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T64	1		T211	1		T285	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T258	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T32	1		T48	1		T236	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T32	2		T236	1		T240	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T238	1		T258	1		T274	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1439

1

T1

2

T2

1

T3

2

clear_one[1]

auto[0]

auto[0]

auto[0]

421

1

T3

1

T12

1

T75

1

clear_one[1]

auto[0]

auto[0]

auto[1]

110

1

T12

1

T209

1

T246

2

clear_one[1]

auto[0]

auto[1]

auto[0]

113

1

T3

1

T13

1

T70

1

clear_one[1]

auto[0]

auto[1]

auto[1]

51

1

T19

1

T200

2

T38

2

clear_one[2]

auto[0]

auto[0]

auto[0]

387

1

T1

2

T12

2

T14

1

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T2

1

T3

1

T44

1

clear_one[2]

auto[1]

auto[0]

auto[0]

126

1

T77

2

T206

2

T119

1

clear_one[2]

auto[1]

auto[0]

auto[1]

41

1

T12

1

T59

1

T38

1

clear_one[3]

auto[0]

auto[0]

auto[0]

403

1

T1

1

T10

2

T12

2

clear_one[3]

auto[0]

auto[1]

auto[0]

115

1

T3

1

T13

1

T38

1

clear_one[3]

auto[1]

auto[0]

auto[0]

129

1

T1

1

T3

2

T77

1

clear_one[3]

auto[1]

auto[1]

auto[0]

45

1

T70

1

T104

2

T38

2

clear_none

auto[0]

auto[0]

auto[0]

1296

1

T1

1

T3

2

T10

3

clear_none

auto[0]

auto[0]

auto[1]

125

1

T2

2

T12

1

T186

2

clear_none

auto[0]

auto[1]

auto[0]

121

1

T13

2

T44

2

T38

3

clear_none

auto[0]

auto[1]

auto[1]

35

1

T38

1

T194

1

T24

1

clear_none

auto[1]

auto[0]

auto[0]

117

1

T1

2

T77

1

T201

1

clear_none

auto[1]

auto[0]

auto[1]

41

1

T12

1

T44

3

T104

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T38

1

T116

2

T208

1

clear_none

auto[1]

auto[1]

auto[1]

36

1

T200

1

T49

1

T39

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1344	1			T1	2		T2	1		T3	2
clear_all	auto[1]	95	1			T116	2		T132	3		T117	4
clear_one[1]	auto[0]	650	1			T3	2		T12	2		T13	1
clear_one[1]	auto[1]	45	1			T117	3		T330	1		T315	1
clear_one[2]	auto[0]	647	1			T1	2		T2	1		T3	1
clear_one[2]	auto[1]	26	1			T315	7		T359	2		T360	5
clear_one[3]	auto[0]	666	1			T1	2		T3	3		T10	2
clear_one[3]	auto[1]	26	1			T104	1		T132	1		T296	2
clear_none	auto[0]	1686	1			T1	3		T2	2		T3	2
clear_none	auto[1]	113	1			T104	2		T116	2		T132	2