Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10989

1

T1

12

T2

6

T3

28

auto[Attestation]

8237

1

T1

2

T2

2

T3

22

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2821	1			T1	3		T2	1		T3	5
auto[Aes]	3407	1			T1	2		T2	3		T3	11
auto[Kmac]	3513	1			T1	2		T2	2		T3	9
auto[Otbn]	3486	1			T1	1		T2	1		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7954	1			T1	8		T2	8		T3	16
auto[OpGenId]	5999	1			T1	6		T2	1		T3	17
auto[OpGenSwOut]	6106	1			T1	5		T2	5		T3	16
auto[OpGenHwOut]	7121	1			T1	3		T2	2		T3	17
auto[OpDisable]	133	1			T14	1		T44	2		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10190

1

T1

8

T2

8

T3

20

auto[OpDoneFail]

17123

1

T1

14

T2

8

T3

46

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5898	1			T1	7		T2	1		T3	12
auto[StInit]	4463	1			T1	2		T2	2		T3	6
auto[StCreatorRootKey]	3006	1			T1	2		T2	2		T3	5
auto[StOwnerIntKey]	2669	1			T1	2		T2	2		T3	4
auto[StOwnerKey]	2391	1			T1	2		T2	2		T3	10
auto[StDisabled]	7854	1			T1	7		T2	7		T3	29
auto[StInvalid]	1032	1			T31	31		T32	24		T48	33

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T1	1		T11	4		T12	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T76	1		T129	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T131	1		T44	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T15	1		T73	1		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	44	1			T15	1		T44	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	214	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T31	1		T32	2		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	278	1			T1	1		T3	1		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T51	1		T38	3		T132	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	62	1			T11	1		T131	1		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T12	1		T192	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T3	1		T75	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	209	1			T2	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T32	1		T48	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	303	1			T1	1		T11	1		T12	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T15	1		T70	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T104	1		T194	1		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T191	1		T116	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T15	1		T104	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	233	1			T2	1		T3	2		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	29	1			T83	2		T195	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	281	1			T3	1		T12	2		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T10	1		T70	1		T73	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T15	1		T131	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T75	1		T181	1		T49	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T36	1		T191	2		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	215	1			T1	1		T12	2		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T32	1		T48	2		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	86	1			T31	2		T44	3		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	152	1			T12	1		T30	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T12	1		T44	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	83	1			T15	1		T30	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T11	1		T15	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T3	1		T12	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	31	1			T31	2		T48	2		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	101	1			T44	1		T32	1		T38	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T3	1		T12	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	77	1			T185	1		T139	1		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T2	1		T11	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T12	1		T15	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	236	1			T2	1		T3	3		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T31	1		T48	1		T193	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	94	1			T44	2		T51	2		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	139	1			T12	1		T71	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	75	1			T75	1		T38	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T44	2		T22	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	47	1			T3	1		T44	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	189	1			T3	1		T12	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T32	1		T48	1		T82	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T44	1		T32	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T192	1		T44	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T3	1		T30	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T75	1		T70	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T75	1		T130	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	205	1			T3	1		T12	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T32	2		T48	2		T193	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	236	1			T12	1		T129	2		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	126	1			T75	1		T30	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T130	1		T44	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T44	1		T78	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T3	1		T36	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T3	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	25	1			T31	1		T32	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	383	1			T3	2		T12	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T3	1		T10	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	99	1			T3	1		T77	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T1	1		T45	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	77	1			T129	1		T130	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	278	1			T12	2		T15	2		T201	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T31	1		T48	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	452	1			T3	2		T75	1		T129	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	124	1			T2	1		T29	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T15	1		T202	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T44	1		T191	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T3	1		T129	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	293	1			T13	2		T14	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T31	1		T48	1		T195	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	398	1			T3	2		T129	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	135	1			T10	1		T70	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T2	1		T12	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T186	1		T44	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T3	1		T12	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	277	1			T12	1		T75	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T31	2		T32	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T44	1		T49	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T1	1		T10	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T3	1		T129	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	53	1			T204	1		T110	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T12	1		T129	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	195	1			T15	1		T192	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T31	1		T32	1		T48	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T44	3		T51	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	141	1			T201	1		T44	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T206	1		T207	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	100	1			T75	1		T77	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	92	1			T77	1		T201	1		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	279	1			T14	1		T77	4		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T31	2		T82	1		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T44	3		T32	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T12	1		T13	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	120	1			T1	1		T13	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T13	1		T38	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	97	1			T13	1		T75	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	287	1			T3	2		T13	2		T70	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	46	1			T193	1		T82	1		T195	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T44	2		T32	2		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	148	1			T10	1		T75	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T131	1		T36	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T12	1		T72	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	94	1			T3	2		T130	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	266	1			T12	1		T75	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T31	1		T32	1		T48	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	164	1			T15	2		T131	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	653	1			T1	2		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T3	1		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	637	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T104	2		T191	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	710	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	213	1			T15	1		T131	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	673	1			T1	1		T3	1		T10	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T11	1		T12	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	503	1			T3	1		T12	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	186	1			T2	1		T11	1		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	502	1			T2	1		T3	4		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	166	1			T75	1		T44	3		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	470	1			T3	2		T12	2		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T3	1		T75	2		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	442	1			T3	1		T12	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T3	1		T130	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	573	1			T3	1		T12	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T1	1		T3	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	844	1			T3	3		T10	1		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	235	1			T3	1		T129	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	915	1			T2	1		T3	2		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T2	1		T12	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	862	1			T3	3		T10	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	158	1			T12	1		T129	2		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	413	1			T1	1		T3	1		T10	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T75	1		T77	2		T201	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	518	1			T14	1		T77	4		T201	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T1	1		T13	3		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	551	1			T3	2		T12	1		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T3	2		T12	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	523	1			T10	1		T12	1		T75	2