Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31325

1

T1

30

T2

21

T3

76

auto[1]

296

1

T104

2

T116

1

T132

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31340	1			T1	30		T2	21		T3	76
auto[134217728:268435455]	10	1			T118	1		T281	1		T354	2
auto[268435456:402653183]	6	1			T96	1		T226	1		T388	1
auto[402653184:536870911]	7	1			T330	1		T354	1		T252	1
auto[536870912:671088639]	12	1			T96	2		T354	1		T296	1
auto[671088640:805306367]	7	1			T132	1		T117	1		T354	1
auto[805306368:939524095]	7	1			T117	1		T332	1		T359	1
auto[939524096:1073741823]	11	1			T321	1		T225	1		T355	1
auto[1073741824:1207959551]	9	1			T118	1		T330	1		T315	1
auto[1207959552:1342177279]	18	1			T104	1		T118	1		T96	1
auto[1342177280:1476395007]	5	1			T104	1		T354	1		T389	1
auto[1476395008:1610612735]	7	1			T96	1		T296	1		T226	1
auto[1610612736:1744830463]	9	1			T390	2		T252	1		T306	1
auto[1744830464:1879048191]	11	1			T252	1		T306	1		T225	1
auto[1879048192:2013265919]	4	1			T306	1		T391	1		T392	1
auto[2013265920:2147483647]	7	1			T315	1		T308	1		T393	1
auto[2147483648:2281701375]	5	1			T252	1		T306	1		T225	1
auto[2281701376:2415919103]	12	1			T96	1		T330	1		T354	1
auto[2415919104:2550136831]	8	1			T96	1		T390	1		T360	1
auto[2550136832:2684354559]	12	1			T118	1		T252	1		T394	1
auto[2684354560:2818572287]	6	1			T96	1		T296	1		T321	1
auto[2818572288:2952790015]	15	1			T132	1		T117	1		T96	2
auto[2952790016:3087007743]	7	1			T132	1		T117	1		T296	1
auto[3087007744:3221225471]	17	1			T116	1		T354	2		T306	1
auto[3221225472:3355443199]	7	1			T354	1		T296	1		T252	1
auto[3355443200:3489660927]	4	1			T330	1		T360	1		T395	1
auto[3489660928:3623878655]	8	1			T117	1		T330	1		T354	3
auto[3623878656:3758096383]	17	1			T117	3		T315	2		T296	1
auto[3758096384:3892314111]	8	1			T330	1		T315	1		T390	1
auto[3892314112:4026531839]	5	1			T132	1		T330	1		T348	1
auto[4026531840:4160749567]	9	1			T315	1		T390	1		T348	2
auto[4160749568:4294967295]	11	1			T117	1		T96	1		T315	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31325	1			T1	30		T2	21		T3	76
auto[0:134217727]	auto[1]	15	1			T132	1		T354	1		T296	1
auto[134217728:268435455]	auto[1]	10	1			T118	1		T281	1		T354	2
auto[268435456:402653183]	auto[1]	6	1			T96	1		T226	1		T388	1
auto[402653184:536870911]	auto[1]	7	1			T330	1		T354	1		T252	1
auto[536870912:671088639]	auto[1]	12	1			T96	2		T354	1		T296	1
auto[671088640:805306367]	auto[1]	7	1			T132	1		T117	1		T354	1
auto[805306368:939524095]	auto[1]	7	1			T117	1		T332	1		T359	1
auto[939524096:1073741823]	auto[1]	11	1			T321	1		T225	1		T355	1
auto[1073741824:1207959551]	auto[1]	9	1			T118	1		T330	1		T315	1
auto[1207959552:1342177279]	auto[1]	18	1			T104	1		T118	1		T96	1
auto[1342177280:1476395007]	auto[1]	5	1			T104	1		T354	1		T389	1
auto[1476395008:1610612735]	auto[1]	7	1			T96	1		T296	1		T226	1
auto[1610612736:1744830463]	auto[1]	9	1			T390	2		T252	1		T306	1
auto[1744830464:1879048191]	auto[1]	11	1			T252	1		T306	1		T225	1
auto[1879048192:2013265919]	auto[1]	4	1			T306	1		T391	1		T392	1
auto[2013265920:2147483647]	auto[1]	7	1			T315	1		T308	1		T393	1
auto[2147483648:2281701375]	auto[1]	5	1			T252	1		T306	1		T225	1
auto[2281701376:2415919103]	auto[1]	12	1			T96	1		T330	1		T354	1
auto[2415919104:2550136831]	auto[1]	8	1			T96	1		T390	1		T360	1
auto[2550136832:2684354559]	auto[1]	12	1			T118	1		T252	1		T394	1
auto[2684354560:2818572287]	auto[1]	6	1			T96	1		T296	1		T321	1
auto[2818572288:2952790015]	auto[1]	15	1			T132	1		T117	1		T96	2
auto[2952790016:3087007743]	auto[1]	7	1			T132	1		T117	1		T296	1
auto[3087007744:3221225471]	auto[1]	17	1			T116	1		T354	2		T306	1
auto[3221225472:3355443199]	auto[1]	7	1			T354	1		T296	1		T252	1
auto[3355443200:3489660927]	auto[1]	4	1			T330	1		T360	1		T395	1
auto[3489660928:3623878655]	auto[1]	8	1			T117	1		T330	1		T354	3
auto[3623878656:3758096383]	auto[1]	17	1			T117	3		T315	2		T296	1
auto[3758096384:3892314111]	auto[1]	8	1			T330	1		T315	1		T390	1
auto[3892314112:4026531839]	auto[1]	5	1			T132	1		T330	1		T348	1
auto[4026531840:4160749567]	auto[1]	9	1			T315	1		T390	1		T348	2
auto[4160749568:4294967295]	auto[1]	11	1			T117	1		T96	1		T315	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1469

1

T3

4

T15

1

T7

1

auto[1]

1740

1

T3

6

T10

2

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T25	1		T38	1		T90	1
auto[134217728:268435455]	79	1			T44	1		T59	1		T38	3
auto[268435456:402653183]	102	1			T281	1		T96	1		T232	1
auto[402653184:536870911]	118	1			T44	1		T32	1		T48	1
auto[536870912:671088639]	77	1			T71	1		T32	1		T104	1
auto[671088640:805306367]	93	1			T75	1		T31	1		T44	1
auto[805306368:939524095]	120	1			T3	2		T75	1		T46	1
auto[939524096:1073741823]	109	1			T104	1		T59	1		T20	1
auto[1073741824:1207959551]	88	1			T10	1		T44	1		T198	1
auto[1207959552:1342177279]	111	1			T75	1		T44	1		T70	1
auto[1342177280:1476395007]	91	1			T70	1		T32	1		T19	1
auto[1476395008:1610612735]	109	1			T32	2		T48	2		T204	1
auto[1610612736:1744830463]	94	1			T131	1		T44	1		T71	1
auto[1744830464:1879048191]	111	1			T15	1		T75	1		T70	1
auto[1879048192:2013265919]	98	1			T3	2		T204	1		T200	1
auto[2013265920:2147483647]	101	1			T44	1		T48	1		T200	1
auto[2147483648:2281701375]	111	1			T15	1		T129	1		T71	1
auto[2281701376:2415919103]	104	1			T10	1		T131	1		T19	1
auto[2415919104:2550136831]	104	1			T51	1		T38	3		T52	1
auto[2550136832:2684354559]	109	1			T75	1		T45	1		T198	1
auto[2684354560:2818572287]	89	1			T3	1		T46	2		T130	1
auto[2818572288:2952790015]	89	1			T3	1		T14	1		T7	1
auto[2952790016:3087007743]	101	1			T3	1		T75	1		T44	1
auto[3087007744:3221225471]	109	1			T31	2		T38	1		T84	1
auto[3221225472:3355443199]	93	1			T75	1		T38	1		T52	1
auto[3355443200:3489660927]	102	1			T44	1		T19	1		T38	1
auto[3489660928:3623878655]	97	1			T22	1		T32	1		T48	1
auto[3623878656:3758096383]	87	1			T15	2		T130	1		T191	1
auto[3758096384:3892314111]	103	1			T3	1		T46	2		T44	1
auto[3892314112:4026531839]	105	1			T3	1		T129	1		T198	1
auto[4026531840:4160749567]	102	1			T31	1		T44	1		T32	1
auto[4160749568:4294967295]	97	1			T3	1		T44	1		T104	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T25	1		T90	1		T179	1
auto[0:134217727]	auto[1]	51	1			T38	1		T49	2		T61	1
auto[134217728:268435455]	auto[0]	35	1			T38	2		T319	1		T49	1
auto[134217728:268435455]	auto[1]	44	1			T44	1		T59	1		T38	1
auto[268435456:402653183]	auto[0]	52	1			T281	1		T96	1		T49	1
auto[268435456:402653183]	auto[1]	50	1			T232	1		T57	1		T396	1
auto[402653184:536870911]	auto[0]	47	1			T32	1		T48	1		T38	2
auto[402653184:536870911]	auto[1]	71	1			T44	1		T51	1		T38	1
auto[536870912:671088639]	auto[0]	36	1			T32	1		T198	1		T38	1
auto[536870912:671088639]	auto[1]	41	1			T71	1		T104	1		T198	1
auto[671088640:805306367]	auto[0]	30	1			T200	1		T180	1		T83	1
auto[671088640:805306367]	auto[1]	63	1			T75	1		T31	1		T44	1
auto[805306368:939524095]	auto[0]	54	1			T3	1		T32	1		T181	1
auto[805306368:939524095]	auto[1]	66	1			T3	1		T75	1		T46	1
auto[939524096:1073741823]	auto[0]	54	1			T59	1		T20	1		T281	1
auto[939524096:1073741823]	auto[1]	55	1			T104	1		T38	2		T117	1
auto[1073741824:1207959551]	auto[0]	47	1			T38	1		T230	1		T170	1
auto[1073741824:1207959551]	auto[1]	41	1			T10	1		T44	1		T198	1
auto[1207959552:1342177279]	auto[0]	49	1			T75	1		T191	1		T59	1
auto[1207959552:1342177279]	auto[1]	62	1			T44	1		T70	1		T45	2
auto[1342177280:1476395007]	auto[0]	37	1			T24	1		T90	1		T57	1
auto[1342177280:1476395007]	auto[1]	54	1			T70	1		T32	1		T19	1
auto[1476395008:1610612735]	auto[0]	48	1			T32	1		T48	1		T38	1
auto[1476395008:1610612735]	auto[1]	61	1			T32	1		T48	1		T204	1
auto[1610612736:1744830463]	auto[0]	41	1			T38	1		T52	1		T311	1
auto[1610612736:1744830463]	auto[1]	53	1			T131	1		T44	1		T71	1
auto[1744830464:1879048191]	auto[0]	54	1			T75	1		T45	1		T208	1
auto[1744830464:1879048191]	auto[1]	57	1			T15	1		T70	1		T52	1
auto[1879048192:2013265919]	auto[0]	49	1			T3	1		T200	1		T51	1
auto[1879048192:2013265919]	auto[1]	49	1			T3	1		T204	1		T117	1
auto[2013265920:2147483647]	auto[0]	46	1			T48	1		T374	1		T39	1
auto[2013265920:2147483647]	auto[1]	55	1			T44	1		T200	1		T50	1
auto[2147483648:2281701375]	auto[0]	45	1			T48	1		T38	1		T230	1
auto[2147483648:2281701375]	auto[1]	66	1			T15	1		T129	1		T71	1
auto[2281701376:2415919103]	auto[0]	49	1			T59	1		T20	1		T230	1
auto[2281701376:2415919103]	auto[1]	55	1			T10	1		T131	1		T19	1
auto[2415919104:2550136831]	auto[0]	45	1			T52	1		T118	1		T108	1
auto[2415919104:2550136831]	auto[1]	59	1			T51	1		T38	3		T108	1
auto[2550136832:2684354559]	auto[0]	59	1			T45	1		T198	1		T25	1
auto[2550136832:2684354559]	auto[1]	50	1			T75	1		T116	1		T311	1
auto[2684354560:2818572287]	auto[0]	44	1			T3	1		T46	2		T130	1
auto[2684354560:2818572287]	auto[1]	45	1			T45	1		T19	1		T38	1
auto[2818572288:2952790015]	auto[0]	36	1			T7	1		T90	1		T181	1
auto[2818572288:2952790015]	auto[1]	53	1			T3	1		T14	1		T31	1
auto[2952790016:3087007743]	auto[0]	47	1			T75	1		T32	1		T48	1
auto[2952790016:3087007743]	auto[1]	54	1			T3	1		T44	1		T38	1
auto[3087007744:3221225471]	auto[0]	48	1			T38	1		T266	1		T180	1
auto[3087007744:3221225471]	auto[1]	61	1			T31	2		T84	1		T92	1
auto[3221225472:3355443199]	auto[0]	35	1			T52	1		T90	1		T39	1
auto[3221225472:3355443199]	auto[1]	58	1			T75	1		T38	1		T311	1
auto[3355443200:3489660927]	auto[0]	48	1			T44	1		T19	1		T92	1
auto[3355443200:3489660927]	auto[1]	54	1			T38	1		T116	1		T117	1
auto[3489660928:3623878655]	auto[0]	48	1			T32	1		T191	1		T20	1
auto[3489660928:3623878655]	auto[1]	49	1			T22	1		T48	1		T104	1
auto[3623878656:3758096383]	auto[0]	37	1			T15	1		T130	1		T191	1
auto[3623878656:3758096383]	auto[1]	50	1			T15	1		T45	1		T200	1
auto[3758096384:3892314111]	auto[0]	54	1			T46	2		T44	1		T22	1
auto[3758096384:3892314111]	auto[1]	49	1			T3	1		T193	1		T82	1
auto[3892314112:4026531839]	auto[0]	43	1			T38	2		T170	1		T228	1
auto[3892314112:4026531839]	auto[1]	62	1			T3	1		T129	1		T198	1
auto[4026531840:4160749567]	auto[0]	51	1			T44	1		T32	1		T204	1
auto[4026531840:4160749567]	auto[1]	51	1			T31	1		T25	1		T38	1
auto[4160749568:4294967295]	auto[0]	46	1			T3	1		T44	1		T38	1
auto[4160749568:4294967295]	auto[1]	51	1			T104	1		T200	1		T51	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1466

1

T3

3

T10

1

T15

1

auto[1]

1740

1

T3

7

T10

1

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T7	1		T22	1		T116	1
auto[134217728:268435455]	112	1			T71	1		T45	1		T19	1
auto[268435456:402653183]	87	1			T75	1		T8	1		T194	1
auto[402653184:536870911]	107	1			T3	2		T44	1		T71	1
auto[536870912:671088639]	94	1			T3	1		T44	1		T38	1
auto[671088640:805306367]	84	1			T14	1		T75	1		T44	1
auto[805306368:939524095]	109	1			T31	1		T70	1		T104	1
auto[939524096:1073741823]	98	1			T3	1		T75	1		T85	1
auto[1073741824:1207959551]	92	1			T31	2		T44	1		T32	1
auto[1207959552:1342177279]	86	1			T131	1		T32	1		T48	1
auto[1342177280:1476395007]	100	1			T75	1		T129	1		T38	4
auto[1476395008:1610612735]	114	1			T15	1		T191	1		T51	1
auto[1610612736:1744830463]	92	1			T3	1		T15	1		T44	1
auto[1744830464:1879048191]	109	1			T32	1		T204	1		T198	1
auto[1879048192:2013265919]	109	1			T15	1		T46	1		T104	1
auto[2013265920:2147483647]	87	1			T44	1		T191	1		T45	1
auto[2147483648:2281701375]	103	1			T200	1		T59	1		T198	1
auto[2281701376:2415919103]	100	1			T130	1		T22	1		T48	1
auto[2415919104:2550136831]	88	1			T46	1		T38	3		T132	1
auto[2550136832:2684354559]	112	1			T71	1		T48	1		T45	1
auto[2684354560:2818572287]	95	1			T3	1		T75	1		T130	1
auto[2818572288:2952790015]	100	1			T31	1		T70	1		T32	1
auto[2952790016:3087007743]	101	1			T10	1		T32	1		T45	2
auto[3087007744:3221225471]	103	1			T3	1		T75	1		T46	1
auto[3221225472:3355443199]	104	1			T44	1		T70	1		T38	1
auto[3355443200:3489660927]	107	1			T3	1		T44	1		T19	1
auto[3489660928:3623878655]	103	1			T200	1		T59	1		T198	1
auto[3623878656:3758096383]	91	1			T3	1		T15	1		T75	1
auto[3758096384:3892314111]	94	1			T3	1		T129	1		T44	1
auto[3892314112:4026531839]	113	1			T10	1		T46	1		T44	1
auto[4026531840:4160749567]	127	1			T46	1		T32	2		T38	1
auto[4160749568:4294967295]	85	1			T131	1		T31	1		T200	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T132	1		T230	1		T311	1
auto[0:134217727]	auto[1]	58	1			T7	1		T22	1		T116	1
auto[134217728:268435455]	auto[0]	39	1			T25	1		T319	1		T26	1
auto[134217728:268435455]	auto[1]	73	1			T71	1		T45	1		T19	1
auto[268435456:402653183]	auto[0]	43	1			T8	1		T108	1		T83	1
auto[268435456:402653183]	auto[1]	44	1			T75	1		T194	1		T116	1
auto[402653184:536870911]	auto[0]	52	1			T3	1		T45	1		T51	1
auto[402653184:536870911]	auto[1]	55	1			T3	1		T44	1		T71	1
auto[536870912:671088639]	auto[0]	40	1			T3	1		T90	1		T26	1
auto[536870912:671088639]	auto[1]	54	1			T44	1		T38	1		T50	1
auto[671088640:805306367]	auto[0]	35	1			T75	1		T20	1		T117	1
auto[671088640:805306367]	auto[1]	49	1			T14	1		T44	1		T194	1
auto[805306368:939524095]	auto[0]	41	1			T45	1		T281	1		T49	1
auto[805306368:939524095]	auto[1]	68	1			T31	1		T70	1		T104	1
auto[939524096:1073741823]	auto[0]	50	1			T85	1		T178	1		T180	1
auto[939524096:1073741823]	auto[1]	48	1			T3	1		T75	1		T49	1
auto[1073741824:1207959551]	auto[0]	35	1			T32	1		T19	1		T51	1
auto[1073741824:1207959551]	auto[1]	57	1			T31	2		T44	1		T48	1
auto[1207959552:1342177279]	auto[0]	42	1			T32	1		T48	1		T191	1
auto[1207959552:1342177279]	auto[1]	44	1			T131	1		T38	1		T193	1
auto[1342177280:1476395007]	auto[0]	54	1			T75	1		T38	3		T230	1
auto[1342177280:1476395007]	auto[1]	46	1			T129	1		T38	1		T319	1
auto[1476395008:1610612735]	auto[0]	46	1			T191	1		T39	1		T315	1
auto[1476395008:1610612735]	auto[1]	68	1			T15	1		T51	1		T59	1
auto[1610612736:1744830463]	auto[0]	37	1			T44	1		T20	1		T266	1
auto[1610612736:1744830463]	auto[1]	55	1			T3	1		T15	1		T25	1
auto[1744830464:1879048191]	auto[0]	50	1			T32	1		T198	1		T25	1
auto[1744830464:1879048191]	auto[1]	59	1			T204	1		T38	1		T39	1
auto[1879048192:2013265919]	auto[0]	49	1			T46	1		T51	1		T59	1
auto[1879048192:2013265919]	auto[1]	60	1			T15	1		T104	1		T38	1
auto[2013265920:2147483647]	auto[0]	46	1			T191	1		T45	1		T38	2
auto[2013265920:2147483647]	auto[1]	41	1			T44	1		T198	1		T38	1
auto[2147483648:2281701375]	auto[0]	53	1			T200	1		T59	1		T198	1
auto[2147483648:2281701375]	auto[1]	50	1			T38	2		T84	1		T50	2
auto[2281701376:2415919103]	auto[0]	45	1			T130	1		T22	1		T48	1
auto[2281701376:2415919103]	auto[1]	55	1			T49	1		T39	1		T40	1
auto[2415919104:2550136831]	auto[0]	39	1			T46	1		T38	1		T132	1
auto[2415919104:2550136831]	auto[1]	49	1			T38	2		T311	1		T92	1
auto[2550136832:2684354559]	auto[0]	60	1			T48	1		T59	1		T198	1
auto[2550136832:2684354559]	auto[1]	52	1			T71	1		T45	1		T38	1
auto[2684354560:2818572287]	auto[0]	46	1			T75	1		T130	1		T38	1
auto[2684354560:2818572287]	auto[1]	49	1			T3	1		T48	1		T38	1
auto[2818572288:2952790015]	auto[0]	42	1			T70	1		T38	2		T266	1
auto[2818572288:2952790015]	auto[1]	58	1			T31	1		T32	1		T200	1
auto[2952790016:3087007743]	auto[0]	46	1			T10	1		T32	1		T38	1
auto[2952790016:3087007743]	auto[1]	55	1			T45	2		T200	1		T51	1
auto[3087007744:3221225471]	auto[0]	57	1			T46	1		T44	1		T32	1
auto[3087007744:3221225471]	auto[1]	46	1			T3	1		T75	1		T31	1
auto[3221225472:3355443199]	auto[0]	45	1			T44	1		T181	1		T325	1
auto[3221225472:3355443199]	auto[1]	59	1			T70	1		T38	1		T90	2
auto[3355443200:3489660927]	auto[0]	42	1			T38	1		T118	1		T28	1
auto[3355443200:3489660927]	auto[1]	65	1			T3	1		T44	1		T19	1
auto[3489660928:3623878655]	auto[0]	57	1			T59	1		T38	2		T170	1
auto[3489660928:3623878655]	auto[1]	46	1			T200	1		T198	1		T92	1
auto[3623878656:3758096383]	auto[0]	42	1			T15	1		T311	1		T181	1
auto[3623878656:3758096383]	auto[1]	49	1			T3	1		T75	1		T104	1
auto[3758096384:3892314111]	auto[0]	47	1			T3	1		T32	1		T311	1
auto[3758096384:3892314111]	auto[1]	47	1			T129	1		T44	1		T104	1
auto[3892314112:4026531839]	auto[0]	53	1			T46	1		T44	1		T48	3
auto[3892314112:4026531839]	auto[1]	60	1			T10	1		T116	1		T117	1
auto[4026531840:4160749567]	auto[0]	60	1			T46	1		T32	2		T81	1
auto[4026531840:4160749567]	auto[1]	67	1			T38	1		T208	1		T117	2
auto[4160749568:4294967295]	auto[0]	31	1			T38	1		T52	1		T39	1
auto[4160749568:4294967295]	auto[1]	54	1			T131	1		T31	1		T200	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1449

1

T3

5

T10

1

T15

1

auto[1]

1757

1

T3

5

T10

1

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T75	1		T45	1		T19	1
auto[134217728:268435455]	119	1			T3	1		T129	1		T131	1
auto[268435456:402653183]	107	1			T3	1		T8	1		T59	1
auto[402653184:536870911]	99	1			T31	1		T32	1		T48	1
auto[536870912:671088639]	86	1			T3	1		T31	1		T45	1
auto[671088640:805306367]	107	1			T75	2		T44	1		T70	1
auto[805306368:939524095]	104	1			T129	1		T32	1		T204	1
auto[939524096:1073741823]	99	1			T44	1		T45	1		T51	1
auto[1073741824:1207959551]	101	1			T15	1		T31	1		T44	1
auto[1207959552:1342177279]	88	1			T46	1		T31	1		T44	1
auto[1342177280:1476395007]	102	1			T75	1		T204	1		T38	3
auto[1476395008:1610612735]	90	1			T3	1		T15	1		T31	1
auto[1610612736:1744830463]	99	1			T3	1		T191	1		T38	1
auto[1744830464:1879048191]	98	1			T75	1		T46	1		T44	1
auto[1879048192:2013265919]	87	1			T131	1		T19	1		T92	1
auto[2013265920:2147483647]	105	1			T75	1		T45	1		T200	1
auto[2147483648:2281701375]	100	1			T70	1		T71	1		T104	1
auto[2281701376:2415919103]	104	1			T7	1		T22	1		T45	1
auto[2415919104:2550136831]	95	1			T191	1		T200	1		T198	1
auto[2550136832:2684354559]	93	1			T46	1		T32	1		T48	1
auto[2684354560:2818572287]	95	1			T32	1		T200	2		T59	1
auto[2818572288:2952790015]	109	1			T46	1		T44	1		T32	1
auto[2952790016:3087007743]	89	1			T3	2		T46	1		T130	1
auto[3087007744:3221225471]	111	1			T44	1		T104	1		T20	1
auto[3221225472:3355443199]	96	1			T130	1		T32	1		T48	1
auto[3355443200:3489660927]	103	1			T44	1		T104	1		T38	1
auto[3489660928:3623878655]	82	1			T3	1		T10	1		T45	1
auto[3623878656:3758096383]	119	1			T3	1		T10	1		T31	1
auto[3758096384:3892314111]	115	1			T71	1		T22	1		T51	1
auto[3892314112:4026531839]	112	1			T3	1		T15	1		T45	1
auto[4026531840:4160749567]	107	1			T15	1		T75	1		T44	1
auto[4160749568:4294967295]	89	1			T14	1		T44	1		T59	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T75	1		T90	1		T179	1
auto[0:134217727]	auto[1]	49	1			T45	1		T19	1		T38	1
auto[134217728:268435455]	auto[0]	52	1			T48	2		T19	1		T198	1
auto[134217728:268435455]	auto[1]	67	1			T3	1		T129	1		T131	1
auto[268435456:402653183]	auto[0]	49	1			T3	1		T59	1		T38	1
auto[268435456:402653183]	auto[1]	58	1			T8	1		T39	1		T229	1
auto[402653184:536870911]	auto[0]	49	1			T32	1		T48	1		T38	1
auto[402653184:536870911]	auto[1]	50	1			T31	1		T24	1		T90	1
auto[536870912:671088639]	auto[0]	43	1			T45	1		T38	1		T52	1
auto[536870912:671088639]	auto[1]	43	1			T3	1		T31	1		T311	1
auto[671088640:805306367]	auto[0]	45	1			T75	1		T44	1		T38	1
auto[671088640:805306367]	auto[1]	62	1			T75	1		T70	1		T38	1
auto[805306368:939524095]	auto[0]	36	1			T311	1		T49	1		T57	1
auto[805306368:939524095]	auto[1]	68	1			T129	1		T32	1		T204	1
auto[939524096:1073741823]	auto[0]	50	1			T44	1		T51	1		T198	1
auto[939524096:1073741823]	auto[1]	49	1			T45	1		T84	1		T311	1
auto[1073741824:1207959551]	auto[0]	43	1			T44	1		T32	1		T59	1
auto[1073741824:1207959551]	auto[1]	58	1			T15	1		T31	1		T71	1
auto[1207959552:1342177279]	auto[0]	43	1			T19	1		T38	1		T108	1
auto[1207959552:1342177279]	auto[1]	45	1			T46	1		T31	1		T44	1
auto[1342177280:1476395007]	auto[0]	49	1			T75	1		T38	1		T397	1
auto[1342177280:1476395007]	auto[1]	53	1			T204	1		T38	2		T132	1
auto[1476395008:1610612735]	auto[0]	38	1			T3	1		T31	1		T59	1
auto[1476395008:1610612735]	auto[1]	52	1			T15	1		T38	1		T116	1
auto[1610612736:1744830463]	auto[0]	48	1			T3	1		T191	1		T52	1
auto[1610612736:1744830463]	auto[1]	51	1			T38	1		T90	1		T266	1
auto[1744830464:1879048191]	auto[0]	45	1			T75	1		T46	1		T25	1
auto[1744830464:1879048191]	auto[1]	53	1			T44	1		T311	1		T118	1
auto[1879048192:2013265919]	auto[0]	37	1			T26	1		T39	2		T61	1
auto[1879048192:2013265919]	auto[1]	50	1			T131	1		T19	1		T92	1
auto[2013265920:2147483647]	auto[0]	42	1			T75	1		T38	1		T311	1
auto[2013265920:2147483647]	auto[1]	63	1			T45	1		T200	1		T38	1
auto[2147483648:2281701375]	auto[0]	41	1			T38	2		T39	1		T57	1
auto[2147483648:2281701375]	auto[1]	59	1			T70	1		T71	1		T104	1
auto[2281701376:2415919103]	auto[0]	48	1			T22	1		T45	1		T25	1
auto[2281701376:2415919103]	auto[1]	56	1			T7	1		T19	1		T51	1
auto[2415919104:2550136831]	auto[0]	41	1			T198	1		T38	1		T118	1
auto[2415919104:2550136831]	auto[1]	54	1			T191	1		T200	1		T23	1
auto[2550136832:2684354559]	auto[0]	41	1			T46	1		T32	1		T48	1
auto[2550136832:2684354559]	auto[1]	52	1			T38	2		T194	1		T230	1
auto[2684354560:2818572287]	auto[0]	47	1			T32	1		T200	1		T59	1
auto[2684354560:2818572287]	auto[1]	48	1			T200	1		T193	1		T178	1
auto[2818572288:2952790015]	auto[0]	45	1			T46	1		T44	1		T32	1
auto[2818572288:2952790015]	auto[1]	64	1			T48	1		T45	1		T59	1
auto[2952790016:3087007743]	auto[0]	44	1			T3	2		T46	1		T130	1
auto[2952790016:3087007743]	auto[1]	45	1			T44	1		T116	1		T230	1
auto[3087007744:3221225471]	auto[0]	50	1			T20	1		T208	1		T311	1
auto[3087007744:3221225471]	auto[1]	61	1			T44	1		T104	1		T117	1
auto[3221225472:3355443199]	auto[0]	53	1			T130	1		T32	1		T52	1
auto[3221225472:3355443199]	auto[1]	43	1			T48	1		T198	1		T38	1
auto[3355443200:3489660927]	auto[0]	39	1			T181	1		T228	1		T54	1
auto[3355443200:3489660927]	auto[1]	64	1			T44	1		T104	1		T38	1
auto[3489660928:3623878655]	auto[0]	36	1			T10	1		T194	1		T85	1
auto[3489660928:3623878655]	auto[1]	46	1			T3	1		T45	1		T200	1
auto[3623878656:3758096383]	auto[0]	51	1			T32	2		T38	1		T319	1
auto[3623878656:3758096383]	auto[1]	68	1			T3	1		T10	1		T31	1
auto[3758096384:3892314111]	auto[0]	50	1			T20	1		T38	1		T266	1
auto[3758096384:3892314111]	auto[1]	65	1			T71	1		T22	1		T51	1
auto[3892314112:4026531839]	auto[0]	51	1			T38	1		T52	1		T49	2
auto[3892314112:4026531839]	auto[1]	61	1			T3	1		T15	1		T45	1
auto[4026531840:4160749567]	auto[0]	52	1			T15	1		T44	1		T48	1
auto[4026531840:4160749567]	auto[1]	55	1			T75	1		T204	1		T19	1
auto[4160749568:4294967295]	auto[0]	44	1			T59	1		T25	1		T24	1
auto[4160749568:4294967295]	auto[1]	45	1			T14	1		T44	1		T38	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1469

1

T3

3

T15

1

T7

1

auto[1]

1737

1

T3

7

T10

2

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	77	1			T51	1		T20	2		T38	1
auto[134217728:268435455]	124	1			T3	1		T200	1		T116	1
auto[268435456:402653183]	118	1			T3	1		T46	1		T129	1
auto[402653184:536870911]	86	1			T75	1		T22	1		T45	1
auto[536870912:671088639]	102	1			T46	1		T104	1		T200	2
auto[671088640:805306367]	104	1			T71	1		T45	3		T20	1
auto[805306368:939524095]	97	1			T75	1		T46	1		T51	1
auto[939524096:1073741823]	119	1			T44	1		T32	2		T200	1
auto[1073741824:1207959551]	83	1			T3	1		T191	1		T19	1
auto[1207959552:1342177279]	109	1			T3	1		T44	2		T200	1
auto[1342177280:1476395007]	96	1			T46	1		T31	1		T19	1
auto[1476395008:1610612735]	108	1			T31	1		T48	2		T45	1
auto[1610612736:1744830463]	100	1			T15	1		T32	1		T51	1
auto[1744830464:1879048191]	101	1			T3	1		T44	1		T191	1
auto[1879048192:2013265919]	81	1			T3	1		T71	1		T117	1
auto[2013265920:2147483647]	107	1			T3	1		T200	1		T38	2
auto[2147483648:2281701375]	110	1			T15	1		T75	2		T31	1
auto[2281701376:2415919103]	89	1			T75	2		T46	1		T48	1
auto[2415919104:2550136831]	80	1			T191	1		T38	1		T84	1
auto[2550136832:2684354559]	114	1			T70	1		T71	1		T45	1
auto[2684354560:2818572287]	102	1			T129	1		T31	1		T8	1
auto[2818572288:2952790015]	100	1			T3	1		T44	1		T32	1
auto[2952790016:3087007743]	90	1			T10	1		T131	1		T51	1
auto[3087007744:3221225471]	103	1			T3	1		T14	1		T32	1
auto[3221225472:3355443199]	109	1			T44	2		T104	1		T19	1
auto[3355443200:3489660927]	125	1			T7	1		T75	1		T44	1
auto[3489660928:3623878655]	99	1			T3	1		T44	1		T48	1
auto[3623878656:3758096383]	99	1			T44	1		T32	1		T204	2
auto[3758096384:3892314111]	100	1			T70	1		T38	3		T118	1
auto[3892314112:4026531839]	100	1			T15	1		T130	1		T70	1
auto[4026531840:4160749567]	96	1			T130	1		T131	1		T31	1
auto[4160749568:4294967295]	78	1			T10	1		T15	1		T38	4