Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2826

1

T3

10

T10

2

T14

1

auto[1]

273

1

T104

8

T116

4

T132

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T15	1		T71	1		T22	1
auto[134217728:268435455]	93	1			T45	1		T116	2		T118	1
auto[268435456:402653183]	81	1			T44	1		T70	1		T191	1
auto[402653184:536870911]	93	1			T3	1		T70	1		T71	1
auto[536870912:671088639]	92	1			T3	1		T75	1		T46	1
auto[671088640:805306367]	79	1			T198	1		T38	1		T194	1
auto[805306368:939524095]	101	1			T3	1		T15	1		T75	1
auto[939524096:1073741823]	93	1			T75	1		T48	1		T25	1
auto[1073741824:1207959551]	103	1			T3	2		T14	1		T104	1
auto[1207959552:1342177279]	88	1			T15	1		T44	2		T19	1
auto[1342177280:1476395007]	91	1			T200	1		T59	1		T198	1
auto[1476395008:1610612735]	81	1			T22	1		T20	1		T38	1
auto[1610612736:1744830463]	102	1			T38	3		T96	1		T90	1
auto[1744830464:1879048191]	96	1			T31	2		T44	1		T104	1
auto[1879048192:2013265919]	97	1			T200	1		T198	1		T20	1
auto[2013265920:2147483647]	102	1			T3	1		T70	1		T104	1
auto[2147483648:2281701375]	100	1			T10	1		T48	1		T45	1
auto[2281701376:2415919103]	106	1			T31	1		T71	1		T32	1
auto[2415919104:2550136831]	111	1			T104	1		T200	2		T198	1
auto[2550136832:2684354559]	104	1			T44	2		T104	1		T45	1
auto[2684354560:2818572287]	99	1			T45	1		T200	1		T59	1
auto[2818572288:2952790015]	101	1			T3	1		T32	1		T48	2
auto[2952790016:3087007743]	103	1			T10	1		T75	2		T44	2
auto[3087007744:3221225471]	98	1			T15	1		T31	1		T48	1
auto[3221225472:3355443199]	95	1			T45	1		T204	1		T19	2
auto[3355443200:3489660927]	94	1			T129	1		T44	2		T104	1
auto[3489660928:3623878655]	102	1			T3	1		T131	1		T31	1
auto[3623878656:3758096383]	84	1			T45	1		T200	1		T132	1
auto[3758096384:3892314111]	91	1			T3	1		T129	1		T44	1
auto[3892314112:4026531839]	83	1			T75	1		T32	2		T8	1
auto[4026531840:4160749567]	125	1			T3	1		T75	1		T44	1
auto[4160749568:4294967295]	97	1			T130	1		T131	1		T32	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	102	1			T15	1		T71	1		T22	1
auto[0:134217727]	auto[1]	12	1			T96	1		T354	2		T315	1
auto[134217728:268435455]	auto[0]	81	1			T45	1		T116	2		T24	1
auto[134217728:268435455]	auto[1]	12	1			T118	1		T315	1		T321	1
auto[268435456:402653183]	auto[0]	76	1			T44	1		T70	1		T191	1
auto[268435456:402653183]	auto[1]	5	1			T118	1		T315	1		T252	1
auto[402653184:536870911]	auto[0]	88	1			T3	1		T70	1		T71	1
auto[402653184:536870911]	auto[1]	5	1			T332	1		T322	1		T391	1
auto[536870912:671088639]	auto[0]	90	1			T3	1		T75	1		T46	1
auto[536870912:671088639]	auto[1]	2	1			T96	1		T119	1		-	-
auto[671088640:805306367]	auto[0]	78	1			T198	1		T38	1		T194	1
auto[671088640:805306367]	auto[1]	1	1			T308	1		-	-		-	-
auto[805306368:939524095]	auto[0]	90	1			T3	1		T15	1		T75	1
auto[805306368:939524095]	auto[1]	11	1			T104	1		T96	1		T330	1
auto[939524096:1073741823]	auto[0]	84	1			T75	1		T48	1		T25	1
auto[939524096:1073741823]	auto[1]	9	1			T296	1		T348	2		T355	1
auto[1073741824:1207959551]	auto[0]	96	1			T3	2		T14	1		T104	1
auto[1073741824:1207959551]	auto[1]	7	1			T120	1		T296	1		T388	2
auto[1207959552:1342177279]	auto[0]	80	1			T15	1		T44	2		T19	1
auto[1207959552:1342177279]	auto[1]	8	1			T116	1		T315	2		T394	1
auto[1342177280:1476395007]	auto[0]	83	1			T200	1		T59	1		T198	1
auto[1342177280:1476395007]	auto[1]	8	1			T252	1		T226	1		T359	1
auto[1476395008:1610612735]	auto[0]	72	1			T22	1		T20	1		T38	1
auto[1476395008:1610612735]	auto[1]	9	1			T315	1		T306	1		T308	2
auto[1610612736:1744830463]	auto[0]	96	1			T38	3		T96	1		T90	1
auto[1610612736:1744830463]	auto[1]	6	1			T296	1		T389	1		T294	1
auto[1744830464:1879048191]	auto[0]	86	1			T31	2		T44	1		T104	1
auto[1744830464:1879048191]	auto[1]	10	1			T118	1		T96	1		T330	1
auto[1879048192:2013265919]	auto[0]	87	1			T200	1		T198	1		T20	1
auto[1879048192:2013265919]	auto[1]	10	1			T132	1		T118	1		T354	1
auto[2013265920:2147483647]	auto[0]	89	1			T3	1		T70	1		T51	1
auto[2013265920:2147483647]	auto[1]	13	1			T104	1		T116	1		T321	1
auto[2147483648:2281701375]	auto[0]	90	1			T10	1		T48	1		T45	1
auto[2147483648:2281701375]	auto[1]	10	1			T330	1		T332	1		T226	1
auto[2281701376:2415919103]	auto[0]	97	1			T31	1		T71	1		T32	1
auto[2281701376:2415919103]	auto[1]	9	1			T306	1		T332	1		T355	1
auto[2415919104:2550136831]	auto[0]	99	1			T104	1		T200	2		T198	1
auto[2415919104:2550136831]	auto[1]	12	1			T330	1		T315	1		T225	1
auto[2550136832:2684354559]	auto[0]	95	1			T44	2		T45	1		T25	1
auto[2550136832:2684354559]	auto[1]	9	1			T104	1		T117	1		T315	1
auto[2684354560:2818572287]	auto[0]	83	1			T45	1		T200	1		T59	1
auto[2684354560:2818572287]	auto[1]	16	1			T116	1		T132	1		T117	1
auto[2818572288:2952790015]	auto[0]	92	1			T3	1		T32	1		T48	2
auto[2818572288:2952790015]	auto[1]	9	1			T117	2		T96	1		T330	1
auto[2952790016:3087007743]	auto[0]	94	1			T10	1		T75	2		T44	2
auto[2952790016:3087007743]	auto[1]	9	1			T104	1		T354	1		T315	1
auto[3087007744:3221225471]	auto[0]	90	1			T15	1		T31	1		T48	1
auto[3087007744:3221225471]	auto[1]	8	1			T104	1		T330	1		T296	1
auto[3221225472:3355443199]	auto[0]	86	1			T45	1		T204	1		T19	2
auto[3221225472:3355443199]	auto[1]	9	1			T116	1		T96	1		T330	2
auto[3355443200:3489660927]	auto[0]	87	1			T129	1		T44	2		T20	1
auto[3355443200:3489660927]	auto[1]	7	1			T104	1		T355	1		T404	2
auto[3489660928:3623878655]	auto[0]	97	1			T3	1		T131	1		T31	1
auto[3489660928:3623878655]	auto[1]	5	1			T118	1		T252	1		T388	1
auto[3623878656:3758096383]	auto[0]	80	1			T45	1		T200	1		T132	1
auto[3623878656:3758096383]	auto[1]	4	1			T330	1		T321	1		T360	1
auto[3758096384:3892314111]	auto[0]	84	1			T3	1		T129	1		T44	1
auto[3758096384:3892314111]	auto[1]	7	1			T104	1		T118	1		T296	1
auto[3892314112:4026531839]	auto[0]	78	1			T75	1		T32	2		T8	1
auto[3892314112:4026531839]	auto[1]	5	1			T390	1		T391	1		T407	1
auto[4026531840:4160749567]	auto[0]	108	1			T3	1		T75	1		T44	1
auto[4026531840:4160749567]	auto[1]	17	1			T104	1		T117	1		T118	1
auto[4160749568:4294967295]	auto[0]	88	1			T130	1		T131	1		T32	1
auto[4160749568:4294967295]	auto[1]	9	1			T120	1		T315	1		T390	1