Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1464

1

T3

3

T10

1

T15

1

auto[1]

1742

1

T3

7

T10

1

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T3	1		T70	1		T32	1
auto[134217728:268435455]	101	1			T46	2		T44	1		T71	1
auto[268435456:402653183]	100	1			T14	1		T32	1		T59	1
auto[402653184:536870911]	90	1			T129	1		T48	1		T117	1
auto[536870912:671088639]	92	1			T44	1		T45	1		T198	1
auto[671088640:805306367]	89	1			T38	1		T116	2		T230	1
auto[805306368:939524095]	100	1			T3	1		T15	2		T44	1
auto[939524096:1073741823]	100	1			T75	1		T31	1		T191	1
auto[1073741824:1207959551]	95	1			T3	1		T31	1		T48	1
auto[1207959552:1342177279]	106	1			T3	1		T19	1		T198	1
auto[1342177280:1476395007]	104	1			T3	1		T75	1		T31	1
auto[1476395008:1610612735]	103	1			T44	2		T71	1		T51	1
auto[1610612736:1744830463]	101	1			T15	1		T44	1		T198	1
auto[1744830464:1879048191]	90	1			T3	1		T45	1		T204	1
auto[1879048192:2013265919]	118	1			T75	1		T104	1		T19	1
auto[2013265920:2147483647]	96	1			T15	1		T31	1		T44	2
auto[2147483648:2281701375]	104	1			T3	1		T7	1		T46	1
auto[2281701376:2415919103]	99	1			T130	1		T104	1		T204	1
auto[2415919104:2550136831]	95	1			T3	1		T75	1		T200	1
auto[2550136832:2684354559]	104	1			T3	1		T75	1		T204	1
auto[2684354560:2818572287]	94	1			T45	1		T38	1		T84	1
auto[2818572288:2952790015]	93	1			T10	1		T32	1		T45	1
auto[2952790016:3087007743]	111	1			T3	1		T46	1		T131	1
auto[3087007744:3221225471]	120	1			T10	1		T75	1		T129	1
auto[3221225472:3355443199]	104	1			T130	1		T22	1		T48	1
auto[3355443200:3489660927]	95	1			T131	1		T44	1		T8	1
auto[3489660928:3623878655]	92	1			T32	1		T45	1		T200	1
auto[3623878656:3758096383]	91	1			T75	1		T70	1		T104	1
auto[3758096384:3892314111]	115	1			T70	1		T104	1		T19	1
auto[3892314112:4026531839]	91	1			T44	1		T20	1		T38	2
auto[4026531840:4160749567]	107	1			T31	1		T44	1		T48	2
auto[4160749568:4294967295]	102	1			T46	1		T59	1		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T3	1		T38	1		T90	1
auto[0:134217727]	auto[1]	58	1			T70	1		T32	1		T38	1
auto[134217728:268435455]	auto[0]	44	1			T46	2		T44	1		T20	1
auto[134217728:268435455]	auto[1]	57	1			T71	1		T19	1		T59	1
auto[268435456:402653183]	auto[0]	51	1			T32	1		T59	1		T25	1
auto[268435456:402653183]	auto[1]	49	1			T14	1		T38	2		T39	1
auto[402653184:536870911]	auto[0]	46	1			T129	1		T230	1		T178	1
auto[402653184:536870911]	auto[1]	44	1			T48	1		T117	1		T193	1
auto[536870912:671088639]	auto[0]	38	1			T45	1		T198	1		T38	1
auto[536870912:671088639]	auto[1]	54	1			T44	1		T116	1		T120	1
auto[671088640:805306367]	auto[0]	45	1			T230	1		T311	1		T96	1
auto[671088640:805306367]	auto[1]	44	1			T38	1		T116	2		T110	1
auto[805306368:939524095]	auto[0]	41	1			T3	1		T44	1		T198	1
auto[805306368:939524095]	auto[1]	59	1			T15	2		T38	2		T315	1
auto[939524096:1073741823]	auto[0]	39	1			T191	1		T38	2		T230	1
auto[939524096:1073741823]	auto[1]	61	1			T75	1		T31	1		T132	1
auto[1073741824:1207959551]	auto[0]	41	1			T48	1		T38	1		T52	1
auto[1073741824:1207959551]	auto[1]	54	1			T3	1		T31	1		T19	1
auto[1207959552:1342177279]	auto[0]	41	1			T52	1		T108	1		T180	1
auto[1207959552:1342177279]	auto[1]	65	1			T3	1		T19	1		T198	1
auto[1342177280:1476395007]	auto[0]	51	1			T22	1		T32	1		T48	1
auto[1342177280:1476395007]	auto[1]	53	1			T3	1		T75	1		T31	1
auto[1476395008:1610612735]	auto[0]	46	1			T44	1		T51	1		T20	1
auto[1476395008:1610612735]	auto[1]	57	1			T44	1		T71	1		T38	2
auto[1610612736:1744830463]	auto[0]	52	1			T44	1		T52	1		T24	1
auto[1610612736:1744830463]	auto[1]	49	1			T15	1		T198	1		T194	1
auto[1744830464:1879048191]	auto[0]	38	1			T19	1		T230	1		T170	1
auto[1744830464:1879048191]	auto[1]	52	1			T3	1		T45	1		T204	1
auto[1879048192:2013265919]	auto[0]	44	1			T75	1		T20	1		T178	1
auto[1879048192:2013265919]	auto[1]	74	1			T104	1		T19	1		T38	2
auto[2013265920:2147483647]	auto[0]	45	1			T15	1		T31	1		T44	1
auto[2013265920:2147483647]	auto[1]	51	1			T44	1		T191	1		T200	2
auto[2147483648:2281701375]	auto[0]	44	1			T46	1		T48	1		T45	1
auto[2147483648:2281701375]	auto[1]	60	1			T3	1		T7	1		T48	1
auto[2281701376:2415919103]	auto[0]	47	1			T51	1		T132	1		T57	1
auto[2281701376:2415919103]	auto[1]	52	1			T130	1		T104	1		T204	1
auto[2415919104:2550136831]	auto[0]	35	1			T3	1		T26	1		T39	1
auto[2415919104:2550136831]	auto[1]	60	1			T75	1		T200	1		T38	1
auto[2550136832:2684354559]	auto[0]	54	1			T75	1		T204	1		T51	1
auto[2550136832:2684354559]	auto[1]	50	1			T3	1		T38	1		T194	1
auto[2684354560:2818572287]	auto[0]	41	1			T266	1		T39	2		T40	1
auto[2684354560:2818572287]	auto[1]	53	1			T45	1		T38	1		T84	1
auto[2818572288:2952790015]	auto[0]	44	1			T32	1		T59	1		T38	1
auto[2818572288:2952790015]	auto[1]	49	1			T10	1		T45	1		T38	1
auto[2952790016:3087007743]	auto[0]	47	1			T46	1		T131	1		T32	2
auto[2952790016:3087007743]	auto[1]	64	1			T3	1		T38	2		T82	1
auto[3087007744:3221225471]	auto[0]	58	1			T10	1		T75	1		T200	1
auto[3087007744:3221225471]	auto[1]	62	1			T129	1		T31	1		T44	1
auto[3221225472:3355443199]	auto[0]	57	1			T130	1		T48	1		T45	1
auto[3221225472:3355443199]	auto[1]	47	1			T22	1		T191	1		T38	1
auto[3355443200:3489660927]	auto[0]	49	1			T8	1		T25	1		T38	1
auto[3355443200:3489660927]	auto[1]	46	1			T131	1		T44	1		T96	1
auto[3489660928:3623878655]	auto[0]	46	1			T32	1		T200	1		T38	1
auto[3489660928:3623878655]	auto[1]	46	1			T45	1		T59	1		T39	2
auto[3623878656:3758096383]	auto[0]	44	1			T75	1		T38	1		T181	1
auto[3623878656:3758096383]	auto[1]	47	1			T70	1		T104	1		T59	1
auto[3758096384:3892314111]	auto[0]	46	1			T38	1		T311	1		T170	1
auto[3758096384:3892314111]	auto[1]	69	1			T70	1		T104	1		T19	1
auto[3892314112:4026531839]	auto[0]	45	1			T20	1		T38	1		T208	1
auto[3892314112:4026531839]	auto[1]	46	1			T44	1		T38	1		T16	1
auto[4026531840:4160749567]	auto[0]	55	1			T44	1		T48	2		T45	1
auto[4026531840:4160749567]	auto[1]	52	1			T31	1		T200	2		T38	1
auto[4160749568:4294967295]	auto[0]	44	1			T46	1		T59	1		T38	1
auto[4160749568:4294967295]	auto[1]	58	1			T50	1		T26	1		T399	1