dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6677 1 T3 31 T10 5 T14 2
auto[1] 292 1 T104 2 T116 6 T132 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2826 1 T3 13 T10 2 T14 1
auto[134217728:268435455] 165 1 T75 1 T129 1 T31 1
auto[268435456:402653183] 175 1 T75 2 T204 1 T19 1
auto[402653184:536870911] 147 1 T44 1 T45 1 T19 2
auto[536870912:671088639] 162 1 T15 1 T75 1 T48 1
auto[671088640:805306367] 114 1 T3 1 T129 1 T31 2
auto[805306368:939524095] 155 1 T3 1 T70 1 T45 2
auto[939524096:1073741823] 132 1 T10 1 T75 1 T44 1
auto[1073741824:1207959551] 152 1 T3 2 T15 1 T48 1
auto[1207959552:1342177279] 123 1 T3 1 T10 1 T130 1
auto[1342177280:1476395007] 139 1 T3 1 T15 1 T75 1
auto[1476395008:1610612735] 139 1 T75 1 T131 1 T32 1
auto[1610612736:1744830463] 139 1 T15 1 T44 1 T45 2
auto[1744830464:1879048191] 126 1 T31 1 T44 2 T70 1
auto[1879048192:2013265919] 132 1 T71 1 T48 2 T45 1
auto[2013265920:2147483647] 109 1 T3 2 T129 1 T32 1
auto[2147483648:2281701375] 119 1 T15 2 T75 1 T131 1
auto[2281701376:2415919103] 144 1 T3 2 T75 1 T46 1
auto[2415919104:2550136831] 134 1 T3 1 T75 1 T31 1
auto[2550136832:2684354559] 128 1 T3 1 T14 1 T130 1
auto[2684354560:2818572287] 108 1 T3 1 T44 1 T70 1
auto[2818572288:2952790015] 124 1 T75 1 T44 1 T70 1
auto[2952790016:3087007743] 99 1 T48 1 T204 1 T51 1
auto[3087007744:3221225471] 122 1 T3 1 T10 1 T204 1
auto[3221225472:3355443199] 135 1 T48 1 T104 1 T45 1
auto[3355443200:3489660927] 114 1 T15 1 T44 1 T19 2
auto[3489660928:3623878655] 132 1 T75 2 T19 1 T51 1
auto[3623878656:3758096383] 120 1 T3 2 T44 1 T32 1
auto[3758096384:3892314111] 152 1 T75 1 T70 1 T22 1
auto[3892314112:4026531839] 115 1 T75 1 T129 1 T22 1
auto[4026531840:4160749567] 129 1 T3 1 T31 1 T200 2
auto[4160749568:4294967295] 159 1 T3 1 T15 1 T70 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2818 1 T3 13 T10 2 T14 1
auto[0:134217727] auto[1] 8 1 T116 1 T315 1 T252 2
auto[134217728:268435455] auto[0] 155 1 T75 1 T129 1 T31 1
auto[134217728:268435455] auto[1] 10 1 T117 1 T315 1 T332 1
auto[268435456:402653183] auto[0] 168 1 T75 2 T204 1 T19 1
auto[268435456:402653183] auto[1] 7 1 T96 1 T368 1 T389 2
auto[402653184:536870911] auto[0] 139 1 T44 1 T45 1 T19 2
auto[402653184:536870911] auto[1] 8 1 T252 1 T394 1 T322 1
auto[536870912:671088639] auto[0] 155 1 T15 1 T75 1 T48 1
auto[536870912:671088639] auto[1] 7 1 T118 1 T354 1 T390 1
auto[671088640:805306367] auto[0] 109 1 T3 1 T129 1 T31 2
auto[671088640:805306367] auto[1] 5 1 T281 1 T330 1 T296 1
auto[805306368:939524095] auto[0] 144 1 T3 1 T70 1 T45 2
auto[805306368:939524095] auto[1] 11 1 T96 1 T119 1 T296 1
auto[939524096:1073741823] auto[0] 125 1 T10 1 T75 1 T44 1
auto[939524096:1073741823] auto[1] 7 1 T354 1 T315 1 T265 1
auto[1073741824:1207959551] auto[0] 137 1 T3 2 T15 1 T48 1
auto[1073741824:1207959551] auto[1] 15 1 T116 1 T281 1 T321 1
auto[1207959552:1342177279] auto[0] 112 1 T3 1 T10 1 T130 1
auto[1207959552:1342177279] auto[1] 11 1 T117 1 T281 1 T96 1
auto[1342177280:1476395007] auto[0] 126 1 T3 1 T15 1 T75 1
auto[1342177280:1476395007] auto[1] 13 1 T104 1 T117 1 T96 1
auto[1476395008:1610612735] auto[0] 131 1 T75 1 T131 1 T32 1
auto[1476395008:1610612735] auto[1] 8 1 T120 1 T252 1 T306 1
auto[1610612736:1744830463] auto[0] 132 1 T15 1 T44 1 T45 2
auto[1610612736:1744830463] auto[1] 7 1 T96 1 T120 1 T330 1
auto[1744830464:1879048191] auto[0] 119 1 T31 1 T44 2 T70 1
auto[1744830464:1879048191] auto[1] 7 1 T104 1 T120 1 T306 1
auto[1879048192:2013265919] auto[0] 122 1 T71 1 T48 2 T45 1
auto[1879048192:2013265919] auto[1] 10 1 T118 1 T120 1 T296 2
auto[2013265920:2147483647] auto[0] 103 1 T3 2 T129 1 T32 1
auto[2013265920:2147483647] auto[1] 6 1 T118 1 T392 1 T400 1
auto[2147483648:2281701375] auto[0] 110 1 T15 2 T75 1 T131 1
auto[2147483648:2281701375] auto[1] 9 1 T117 1 T96 3 T330 1
auto[2281701376:2415919103] auto[0] 135 1 T3 2 T75 1 T46 1
auto[2281701376:2415919103] auto[1] 9 1 T116 1 T354 1 T296 1
auto[2415919104:2550136831] auto[0] 120 1 T3 1 T75 1 T31 1
auto[2415919104:2550136831] auto[1] 14 1 T116 1 T132 1 T354 1
auto[2550136832:2684354559] auto[0] 120 1 T3 1 T14 1 T130 1
auto[2550136832:2684354559] auto[1] 8 1 T390 1 T394 1 T355 1
auto[2684354560:2818572287] auto[0] 100 1 T3 1 T44 1 T70 1
auto[2684354560:2818572287] auto[1] 8 1 T96 1 T354 1 T360 1
auto[2818572288:2952790015] auto[0] 114 1 T75 1 T44 1 T70 1
auto[2818572288:2952790015] auto[1] 10 1 T118 2 T330 1 T348 1
auto[2952790016:3087007743] auto[0] 89 1 T48 1 T204 1 T51 1
auto[2952790016:3087007743] auto[1] 10 1 T118 1 T330 1 T296 2
auto[3087007744:3221225471] auto[0] 111 1 T3 1 T10 1 T204 1
auto[3087007744:3221225471] auto[1] 11 1 T321 1 T252 1 T306 2
auto[3221225472:3355443199] auto[0] 126 1 T48 1 T104 1 T45 1
auto[3221225472:3355443199] auto[1] 9 1 T116 1 T354 1 T306 1
auto[3355443200:3489660927] auto[0] 105 1 T15 1 T44 1 T19 2
auto[3355443200:3489660927] auto[1] 9 1 T315 1 T348 1 T226 1
auto[3489660928:3623878655] auto[0] 123 1 T75 2 T19 1 T51 1
auto[3489660928:3623878655] auto[1] 9 1 T118 1 T120 1 T330 1
auto[3623878656:3758096383] auto[0] 114 1 T3 2 T44 1 T32 1
auto[3623878656:3758096383] auto[1] 6 1 T321 1 T355 2 T389 1
auto[3758096384:3892314111] auto[0] 141 1 T75 1 T70 1 T22 1
auto[3758096384:3892314111] auto[1] 11 1 T330 1 T354 1 T315 1
auto[3892314112:4026531839] auto[0] 106 1 T75 1 T129 1 T22 1
auto[3892314112:4026531839] auto[1] 9 1 T330 1 T315 1 T296 2
auto[4026531840:4160749567] auto[0] 122 1 T3 1 T31 1 T200 2
auto[4026531840:4160749567] auto[1] 7 1 T116 1 T315 1 T296 1
auto[4160749568:4294967295] auto[0] 146 1 T3 1 T15 1 T70 1
auto[4160749568:4294967295] auto[1] 13 1 T118 1 T354 1 T315 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%