Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 98.14 98.24 100.00 99.11 98.41 91.56


Total test records in report: 1067
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T1009 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1126423590 Feb 21 02:59:15 PM PST 24 Feb 21 02:59:17 PM PST 24 216552993 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3522443385 Feb 21 02:59:01 PM PST 24 Feb 21 02:59:11 PM PST 24 1723353410 ps
T1011 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2746903538 Feb 21 02:59:29 PM PST 24 Feb 21 02:59:30 PM PST 24 19780325 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3297731849 Feb 21 02:59:03 PM PST 24 Feb 21 02:59:29 PM PST 24 863343015 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3282268145 Feb 21 02:59:32 PM PST 24 Feb 21 02:59:34 PM PST 24 190037056 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1062792310 Feb 21 02:58:47 PM PST 24 Feb 21 02:58:50 PM PST 24 267708202 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3962396482 Feb 21 02:59:15 PM PST 24 Feb 21 02:59:17 PM PST 24 24710593 ps
T1016 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2479214867 Feb 21 02:59:10 PM PST 24 Feb 21 02:59:13 PM PST 24 976777027 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.786299054 Feb 21 02:59:03 PM PST 24 Feb 21 02:59:06 PM PST 24 98917952 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4243276597 Feb 21 02:59:24 PM PST 24 Feb 21 02:59:32 PM PST 24 375011552 ps
T1019 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.969261998 Feb 21 02:59:40 PM PST 24 Feb 21 02:59:41 PM PST 24 9757567 ps
T1020 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.112014971 Feb 21 02:59:01 PM PST 24 Feb 21 02:59:05 PM PST 24 91942262 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1602402315 Feb 21 02:58:57 PM PST 24 Feb 21 02:58:59 PM PST 24 12130751 ps
T1022 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1433376201 Feb 21 02:59:36 PM PST 24 Feb 21 02:59:45 PM PST 24 1393336204 ps
T140 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.558517744 Feb 21 02:58:57 PM PST 24 Feb 21 02:59:09 PM PST 24 1397596763 ps
T1023 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1114846277 Feb 21 02:59:34 PM PST 24 Feb 21 02:59:36 PM PST 24 40283266 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3465965029 Feb 21 02:59:30 PM PST 24 Feb 21 02:59:35 PM PST 24 178509153 ps
T164 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1426982359 Feb 21 02:58:59 PM PST 24 Feb 21 02:59:09 PM PST 24 347310191 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.887471771 Feb 21 02:58:53 PM PST 24 Feb 21 02:58:55 PM PST 24 28842320 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3205115999 Feb 21 02:58:51 PM PST 24 Feb 21 02:58:55 PM PST 24 73560224 ps
T1027 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.737004264 Feb 21 02:59:33 PM PST 24 Feb 21 02:59:34 PM PST 24 72457443 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.188127138 Feb 21 02:59:24 PM PST 24 Feb 21 02:59:26 PM PST 24 170658926 ps
T157 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4126092486 Feb 21 02:59:32 PM PST 24 Feb 21 02:59:38 PM PST 24 147362553 ps
T156 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2211980176 Feb 21 02:58:56 PM PST 24 Feb 21 02:59:06 PM PST 24 436163998 ps
T1029 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4143012943 Feb 21 02:59:29 PM PST 24 Feb 21 02:59:30 PM PST 24 37044465 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1240766659 Feb 21 02:58:55 PM PST 24 Feb 21 02:59:13 PM PST 24 1337541020 ps
T1031 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3273336143 Feb 21 02:58:58 PM PST 24 Feb 21 02:59:01 PM PST 24 381317591 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.441319938 Feb 21 02:58:59 PM PST 24 Feb 21 02:59:03 PM PST 24 84834314 ps
T1033 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2015304340 Feb 21 02:59:24 PM PST 24 Feb 21 02:59:26 PM PST 24 15412216 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3469420973 Feb 21 02:58:56 PM PST 24 Feb 21 02:59:13 PM PST 24 785964049 ps
T1035 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1541319323 Feb 21 02:59:05 PM PST 24 Feb 21 02:59:10 PM PST 24 77612550 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3832421152 Feb 21 02:59:22 PM PST 24 Feb 21 02:59:23 PM PST 24 17080166 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.730611140 Feb 21 02:59:30 PM PST 24 Feb 21 02:59:31 PM PST 24 45044939 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3832347167 Feb 21 02:58:46 PM PST 24 Feb 21 02:58:53 PM PST 24 3128715562 ps
T1039 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.919330596 Feb 21 02:59:18 PM PST 24 Feb 21 02:59:19 PM PST 24 17313866 ps
T1040 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1113052280 Feb 21 02:59:22 PM PST 24 Feb 21 02:59:33 PM PST 24 2011863365 ps
T151 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3021425710 Feb 21 02:59:16 PM PST 24 Feb 21 02:59:24 PM PST 24 770906214 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2178595522 Feb 21 02:58:53 PM PST 24 Feb 21 02:58:55 PM PST 24 70886617 ps
T1042 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.257769323 Feb 21 02:59:30 PM PST 24 Feb 21 02:59:32 PM PST 24 30267631 ps
T1043 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2725164120 Feb 21 02:59:30 PM PST 24 Feb 21 02:59:31 PM PST 24 43082100 ps
T1044 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3758623799 Feb 21 02:59:31 PM PST 24 Feb 21 02:59:32 PM PST 24 36358336 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1470223452 Feb 21 02:59:24 PM PST 24 Feb 21 02:59:26 PM PST 24 203987473 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2153475577 Feb 21 02:59:16 PM PST 24 Feb 21 02:59:18 PM PST 24 52578223 ps
T1047 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4200997651 Feb 21 02:59:32 PM PST 24 Feb 21 02:59:33 PM PST 24 25253734 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2880035392 Feb 21 02:59:00 PM PST 24 Feb 21 02:59:02 PM PST 24 157708801 ps
T363 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3608788259 Feb 21 02:59:06 PM PST 24 Feb 21 02:59:43 PM PST 24 1263549525 ps
T1049 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.115553317 Feb 21 02:59:19 PM PST 24 Feb 21 02:59:22 PM PST 24 177416883 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4157797053 Feb 21 02:59:35 PM PST 24 Feb 21 02:59:36 PM PST 24 27916305 ps
T1051 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1044045993 Feb 21 02:59:23 PM PST 24 Feb 21 02:59:24 PM PST 24 60831951 ps
T1052 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1255096769 Feb 21 02:58:54 PM PST 24 Feb 21 02:58:56 PM PST 24 48403679 ps
T1053 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3229264826 Feb 21 02:59:04 PM PST 24 Feb 21 02:59:06 PM PST 24 39264835 ps
T1054 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4101581551 Feb 21 02:58:57 PM PST 24 Feb 21 02:59:06 PM PST 24 585262798 ps
T1055 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1704606639 Feb 21 02:58:53 PM PST 24 Feb 21 02:58:55 PM PST 24 384484568 ps
T141 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4194462376 Feb 21 02:58:47 PM PST 24 Feb 21 02:58:57 PM PST 24 215326168 ps
T1056 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1420215160 Feb 21 02:58:54 PM PST 24 Feb 21 02:58:56 PM PST 24 102008108 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1068793195 Feb 21 02:58:59 PM PST 24 Feb 21 02:59:06 PM PST 24 825417301 ps
T1058 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.198157667 Feb 21 02:59:26 PM PST 24 Feb 21 02:59:27 PM PST 24 14462692 ps
T1059 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2413905930 Feb 21 02:59:40 PM PST 24 Feb 21 02:59:41 PM PST 24 30259419 ps
T1060 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4017257468 Feb 21 02:59:07 PM PST 24 Feb 21 02:59:09 PM PST 24 97248109 ps
T158 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3931843917 Feb 21 02:59:22 PM PST 24 Feb 21 02:59:31 PM PST 24 842052595 ps
T1061 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3765117296 Feb 21 02:58:59 PM PST 24 Feb 21 02:59:01 PM PST 24 36562270 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3611552965 Feb 21 02:59:03 PM PST 24 Feb 21 02:59:12 PM PST 24 1159217520 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.357821647 Feb 21 02:58:51 PM PST 24 Feb 21 02:58:54 PM PST 24 27247276 ps
T1064 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3651199950 Feb 21 02:59:12 PM PST 24 Feb 21 02:59:14 PM PST 24 14719641 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2522244253 Feb 21 02:58:53 PM PST 24 Feb 21 02:59:02 PM PST 24 336976976 ps
T1066 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1868803399 Feb 21 02:59:26 PM PST 24 Feb 21 02:59:36 PM PST 24 682913600 ps
T1067 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4151372726 Feb 21 02:59:31 PM PST 24 Feb 21 02:59:32 PM PST 24 69627353 ps

Test location /workspace/coverage/default/7.keymgr_stress_all.1806286915
Short name T3
Test name
Test status
Simulation time 387355677 ps
CPU time 6.76 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:38 PM PST 24
Peak memory 220988 kb
Host smart-0efd5312-e5c3-4ded-ab63-2393e0d6cd3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806286915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1806286915
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4160528895
Short name T38
Test name
Test status
Simulation time 9696406382 ps
CPU time 89.2 seconds
Started Feb 21 02:56:53 PM PST 24
Finished Feb 21 02:58:22 PM PST 24
Peak memory 222372 kb
Host smart-d3cbe5c5-c746-4c5b-8c80-6eb2c9376392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160528895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4160528895
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.698148317
Short name T44
Test name
Test status
Simulation time 1988352338 ps
CPU time 25.09 seconds
Started Feb 21 02:56:41 PM PST 24
Finished Feb 21 02:57:07 PM PST 24
Peak memory 222460 kb
Host smart-b84af45c-a559-4617-9747-8b62e85505f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698148317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.698148317
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1709863793
Short name T5
Test name
Test status
Simulation time 338342660 ps
CPU time 11.08 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:25 PM PST 24
Peak memory 231136 kb
Host smart-b189726a-736f-44e8-b49f-0eadab0ae7a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709863793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1709863793
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1889227948
Short name T22
Test name
Test status
Simulation time 246309987 ps
CPU time 7.57 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 208696 kb
Host smart-77f3f232-cc41-4175-90f7-408bd3c3df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889227948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1889227948
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4279846423
Short name T39
Test name
Test status
Simulation time 1514819963 ps
CPU time 30.8 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:57:05 PM PST 24
Peak memory 217116 kb
Host smart-285e43d9-76e3-4c25-86e1-28d0ab29d636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279846423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4279846423
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3798960090
Short name T103
Test name
Test status
Simulation time 477767406 ps
CPU time 9.41 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 213772 kb
Host smart-f3968dc2-8554-4b37-80b1-22aff1fd22c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798960090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3798960090
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.12045927
Short name T28
Test name
Test status
Simulation time 50242606 ps
CPU time 3.27 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 210048 kb
Host smart-d5414200-c409-465e-bf78-32c58641a3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12045927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.12045927
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2081252142
Short name T96
Test name
Test status
Simulation time 9213607340 ps
CPU time 121.86 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:59:22 PM PST 24
Peak memory 222400 kb
Host smart-d91ff315-d4dc-4cf7-a2fe-0b80407aa9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081252142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2081252142
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3627629078
Short name T49
Test name
Test status
Simulation time 18365921645 ps
CPU time 216.33 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 03:01:06 PM PST 24
Peak memory 222388 kb
Host smart-565146dc-da1f-48ef-b2ad-f6487fee3179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627629078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3627629078
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3100892309
Short name T31
Test name
Test status
Simulation time 86819948 ps
CPU time 3.58 seconds
Started Feb 21 02:58:00 PM PST 24
Finished Feb 21 02:58:04 PM PST 24
Peak memory 214224 kb
Host smart-44a148ba-642f-4b62-9360-c99af10441c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100892309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3100892309
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3011957698
Short name T99
Test name
Test status
Simulation time 286930923 ps
CPU time 3.73 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 219668 kb
Host smart-6ab438bb-0064-43c6-b83f-5415dcade750
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011957698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3011957698
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2029326167
Short name T391
Test name
Test status
Simulation time 294043180 ps
CPU time 8.7 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 222464 kb
Host smart-83db7a18-9089-4578-a8a6-a49265c0e871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029326167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2029326167
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1263915252
Short name T10
Test name
Test status
Simulation time 132376891 ps
CPU time 4.57 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 209540 kb
Host smart-9c51c54d-54fb-4ec2-8712-990ac89db876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263915252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1263915252
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.593155027
Short name T315
Test name
Test status
Simulation time 467543180 ps
CPU time 12.94 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:30 PM PST 24
Peak memory 215604 kb
Host smart-4c3d9623-3ba2-4684-ba5a-e528596b4844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593155027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.593155027
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4219897601
Short name T211
Test name
Test status
Simulation time 12995861540 ps
CPU time 421.76 seconds
Started Feb 21 02:58:41 PM PST 24
Finished Feb 21 03:05:44 PM PST 24
Peak memory 222444 kb
Host smart-a6f1046d-b62f-4517-ba7e-1e50221eae3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219897601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4219897601
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2017307630
Short name T330
Test name
Test status
Simulation time 114610481 ps
CPU time 6.51 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 214984 kb
Host smart-adb748f4-9c9e-4818-bcaa-09257aa88571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017307630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2017307630
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.302052951
Short name T404
Test name
Test status
Simulation time 168469337 ps
CPU time 9.24 seconds
Started Feb 21 02:57:59 PM PST 24
Finished Feb 21 02:58:09 PM PST 24
Peak memory 214208 kb
Host smart-18c388ca-8529-4fb0-a451-73e4b8156510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302052951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.302052951
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1430961696
Short name T32
Test name
Test status
Simulation time 400352839 ps
CPU time 5.49 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 222268 kb
Host smart-5852851b-d861-4d54-9959-09eb49fee0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430961696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1430961696
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.932188788
Short name T43
Test name
Test status
Simulation time 22327822878 ps
CPU time 62.56 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:59:55 PM PST 24
Peak memory 222512 kb
Host smart-1310f5e2-d68e-4198-a13c-58de69b48346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932188788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.932188788
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.501427545
Short name T110
Test name
Test status
Simulation time 282680667 ps
CPU time 18.76 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 222612 kb
Host smart-1b2eafbb-23f5-4018-ab84-47c2cfe8842b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501427545 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.501427545
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.438787538
Short name T354
Test name
Test status
Simulation time 790474712 ps
CPU time 10.89 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 214152 kb
Host smart-968337bb-6eac-4ef0-ae1b-f8149d781a99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438787538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.438787538
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.523136119
Short name T341
Test name
Test status
Simulation time 3503984095 ps
CPU time 31.43 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 222492 kb
Host smart-80aaff0a-f03d-4dd4-be38-2a427e5d5340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523136119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.523136119
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3981535746
Short name T33
Test name
Test status
Simulation time 363881613 ps
CPU time 3.67 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 218460 kb
Host smart-6d5a7c62-358c-4095-9de5-6b863b0c6b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981535746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3981535746
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2006862310
Short name T64
Test name
Test status
Simulation time 1559901219 ps
CPU time 22.21 seconds
Started Feb 21 02:56:18 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 215776 kb
Host smart-760a0d3d-c08a-4713-83d5-3d7ec992c61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006862310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2006862310
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2353880760
Short name T134
Test name
Test status
Simulation time 629775324 ps
CPU time 7.04 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 222604 kb
Host smart-ca4fb506-6173-4de4-ada8-ba4c474741b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353880760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2353880760
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.429708059
Short name T30
Test name
Test status
Simulation time 231508830 ps
CPU time 3.01 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:53 PM PST 24
Peak memory 209548 kb
Host smart-2e3a6c30-8769-4778-ba64-c444e5781559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429708059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.429708059
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2598304205
Short name T355
Test name
Test status
Simulation time 350857424 ps
CPU time 18.39 seconds
Started Feb 21 02:57:04 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 215452 kb
Host smart-7e61c622-f6ff-4b19-b966-a05ba7b6a398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598304205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2598304205
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1071492958
Short name T117
Test name
Test status
Simulation time 64790443 ps
CPU time 4.55 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 214212 kb
Host smart-53a29eb9-8dc5-442e-9e43-bf5b06dc5365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071492958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1071492958
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1643713523
Short name T87
Test name
Test status
Simulation time 288232419 ps
CPU time 8.27 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:25 PM PST 24
Peak memory 209348 kb
Host smart-090555c6-b720-468e-b842-047aa012c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643713523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1643713523
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2418073058
Short name T17
Test name
Test status
Simulation time 318597773 ps
CPU time 2.19 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 209604 kb
Host smart-2532a815-f741-4d52-8e9b-e24400a715e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418073058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2418073058
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4089551671
Short name T803
Test name
Test status
Simulation time 210410012 ps
CPU time 12.16 seconds
Started Feb 21 02:58:34 PM PST 24
Finished Feb 21 02:58:46 PM PST 24
Peak memory 214796 kb
Host smart-62e912f3-daa5-49c7-bd1f-3416ce19c2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089551671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4089551671
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2350653220
Short name T410
Test name
Test status
Simulation time 17804953 ps
CPU time 0.8 seconds
Started Feb 21 02:56:59 PM PST 24
Finished Feb 21 02:57:01 PM PST 24
Peak memory 205812 kb
Host smart-195fa396-3f48-4922-a62c-06e9b8f63902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350653220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2350653220
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1151521997
Short name T155
Test name
Test status
Simulation time 381305411 ps
CPU time 8.96 seconds
Started Feb 21 02:59:16 PM PST 24
Finished Feb 21 02:59:25 PM PST 24
Peak memory 208652 kb
Host smart-0c9cc3b1-3027-4aca-a33d-bad50702d5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151521997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1151521997
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3123150966
Short name T191
Test name
Test status
Simulation time 547739148 ps
CPU time 3.9 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 209380 kb
Host smart-095ae7f4-c849-4b39-ae27-dbb983c0961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123150966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3123150966
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2856294997
Short name T16
Test name
Test status
Simulation time 237516327 ps
CPU time 2.51 seconds
Started Feb 21 02:58:09 PM PST 24
Finished Feb 21 02:58:12 PM PST 24
Peak memory 221808 kb
Host smart-1447dadb-6bb6-43a5-b93a-d01f9c3dadc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856294997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2856294997
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2048350377
Short name T258
Test name
Test status
Simulation time 117009774 ps
CPU time 5.52 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 222332 kb
Host smart-72f19470-9267-420a-85ee-871d6924fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048350377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2048350377
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3697827941
Short name T306
Test name
Test status
Simulation time 719101421 ps
CPU time 6.85 seconds
Started Feb 21 02:57:07 PM PST 24
Finished Feb 21 02:57:14 PM PST 24
Peak memory 214408 kb
Host smart-c4f92cf5-e139-4ed6-b68b-ad202ba0ecf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697827941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3697827941
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2243144003
Short name T241
Test name
Test status
Simulation time 3597710251 ps
CPU time 33.14 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:59:14 PM PST 24
Peak memory 215360 kb
Host smart-bbe88a53-b81e-4ae8-b7f2-dcd1a5a01222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243144003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2243144003
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.558517744
Short name T140
Test name
Test status
Simulation time 1397596763 ps
CPU time 10.82 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 213656 kb
Host smart-a6a60632-99eb-4c09-82ec-1b1a72e45b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558517744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
558517744
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3925471525
Short name T133
Test name
Test status
Simulation time 2390098971 ps
CPU time 5.01 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:55 PM PST 24
Peak memory 217584 kb
Host smart-9742cc6d-31d0-4139-811c-fa80988c958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925471525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3925471525
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1756742394
Short name T248
Test name
Test status
Simulation time 32016395042 ps
CPU time 216.8 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 222424 kb
Host smart-62303d13-0cd3-4c75-b773-94dd992ee1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756742394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1756742394
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.38094889
Short name T282
Test name
Test status
Simulation time 1195825103 ps
CPU time 16.06 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 221780 kb
Host smart-104b9e79-0f9b-4a0e-8b52-e0f142565ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38094889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.38094889
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2314410982
Short name T167
Test name
Test status
Simulation time 474872136 ps
CPU time 10.9 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:40 PM PST 24
Peak memory 209084 kb
Host smart-e680ff22-f1d9-4108-be09-8b9a2a4e706a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314410982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2314410982
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1754683834
Short name T98
Test name
Test status
Simulation time 152160899 ps
CPU time 8.36 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 213832 kb
Host smart-175552bb-ec3b-4890-917c-02a0cb3056ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754683834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1754683834
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.668090845
Short name T193
Test name
Test status
Simulation time 53176421 ps
CPU time 3.45 seconds
Started Feb 21 02:57:13 PM PST 24
Finished Feb 21 02:57:17 PM PST 24
Peak memory 209792 kb
Host smart-b18f2cc1-c7cf-4ca5-9894-bf5c587326ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668090845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.668090845
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.43384305
Short name T294
Test name
Test status
Simulation time 311335946 ps
CPU time 17 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:57:04 PM PST 24
Peak memory 214232 kb
Host smart-a8ebed9b-5de4-4f39-9ad5-9b99d99ed331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43384305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.43384305
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3273491746
Short name T132
Test name
Test status
Simulation time 48289406 ps
CPU time 3.57 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:25 PM PST 24
Peak memory 214204 kb
Host smart-40e1885a-7815-4696-82a9-9ea92a806bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273491746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3273491746
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3021425710
Short name T151
Test name
Test status
Simulation time 770906214 ps
CPU time 7.16 seconds
Started Feb 21 02:59:16 PM PST 24
Finished Feb 21 02:59:24 PM PST 24
Peak memory 208844 kb
Host smart-235c966c-5515-486a-b21f-73ae71036a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021425710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3021425710
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1048289504
Short name T224
Test name
Test status
Simulation time 991259977 ps
CPU time 26.64 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:57 PM PST 24
Peak memory 216404 kb
Host smart-1037eabc-c730-4a2a-a563-ab0a0a02a494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048289504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1048289504
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4126092486
Short name T157
Test name
Test status
Simulation time 147362553 ps
CPU time 6.02 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:38 PM PST 24
Peak memory 208836 kb
Host smart-bc4e5cc4-2c0d-4780-8c31-c1cd5192768f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126092486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4126092486
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.305445217
Short name T289
Test name
Test status
Simulation time 1338474721 ps
CPU time 26.85 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 220620 kb
Host smart-0b426925-8d3c-41b5-baa4-5e363536ebaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305445217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.305445217
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1841509690
Short name T80
Test name
Test status
Simulation time 1489637115 ps
CPU time 9.57 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 214228 kb
Host smart-d8cd2f4c-feae-4748-86b2-36259a16c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841509690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1841509690
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2821273803
Short name T302
Test name
Test status
Simulation time 1940541962 ps
CPU time 15.36 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:26 PM PST 24
Peak memory 222220 kb
Host smart-3b33c711-10bf-4ad6-a81d-b1a2e1bd455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821273803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2821273803
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4180553640
Short name T246
Test name
Test status
Simulation time 220580287 ps
CPU time 3.24 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 207728 kb
Host smart-42db3fa2-4873-4e4a-8835-96eb847fb650
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180553640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4180553640
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3208771734
Short name T334
Test name
Test status
Simulation time 330261591 ps
CPU time 4.05 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:08 PM PST 24
Peak memory 209048 kb
Host smart-479d01e6-4699-4b3b-9fed-87e828848195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208771734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3208771734
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3931843917
Short name T158
Test name
Test status
Simulation time 842052595 ps
CPU time 8.84 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 208696 kb
Host smart-b20c5f47-6a20-47d5-8b11-bed3df44b955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931843917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3931843917
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.878926020
Short name T162
Test name
Test status
Simulation time 100932434 ps
CPU time 2.13 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:19 PM PST 24
Peak memory 208896 kb
Host smart-7a4ba991-768c-4cce-9a87-3b64e280a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878926020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.878926020
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_random.2070527393
Short name T278
Test name
Test status
Simulation time 234574134 ps
CPU time 5.41 seconds
Started Feb 21 02:56:56 PM PST 24
Finished Feb 21 02:57:03 PM PST 24
Peak memory 209664 kb
Host smart-06b38211-0439-4eb9-a8e2-cd79a499e24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070527393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2070527393
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2491786354
Short name T316
Test name
Test status
Simulation time 316657764 ps
CPU time 3.87 seconds
Started Feb 21 02:56:45 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 214204 kb
Host smart-12cd37a4-aae2-456e-94f2-151a75301b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491786354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2491786354
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2364817929
Short name T296
Test name
Test status
Simulation time 111744413 ps
CPU time 5.95 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 215404 kb
Host smart-a32d4a72-e05d-409d-906b-9e4ec4ef3b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364817929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2364817929
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4072437910
Short name T308
Test name
Test status
Simulation time 4835391072 ps
CPU time 137.23 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:59:42 PM PST 24
Peak memory 215420 kb
Host smart-d9ca3f2c-9d84-41eb-9621-f37eb1e19ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072437910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4072437910
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3402653609
Short name T336
Test name
Test status
Simulation time 210501067 ps
CPU time 4.9 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 222360 kb
Host smart-629dfe65-7453-46a9-a382-0291caf2d361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402653609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3402653609
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2657347635
Short name T457
Test name
Test status
Simulation time 368697310 ps
CPU time 2.33 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:15 PM PST 24
Peak memory 209708 kb
Host smart-5e0465bf-40b6-4c87-8479-e146939a36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657347635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2657347635
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1832644998
Short name T654
Test name
Test status
Simulation time 3053503430 ps
CPU time 30.76 seconds
Started Feb 21 02:57:42 PM PST 24
Finished Feb 21 02:58:13 PM PST 24
Peak memory 214832 kb
Host smart-5b56fe2f-f28f-47f9-93d6-fb4ea3ce1fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832644998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1832644998
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1564678352
Short name T314
Test name
Test status
Simulation time 314633878 ps
CPU time 9.66 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:26 PM PST 24
Peak memory 215260 kb
Host smart-c139bf19-8acd-44ce-99a7-369b226fe464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564678352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1564678352
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1055474803
Short name T356
Test name
Test status
Simulation time 887332330 ps
CPU time 12.91 seconds
Started Feb 21 02:58:02 PM PST 24
Finished Feb 21 02:58:16 PM PST 24
Peak memory 214804 kb
Host smart-d94dadfa-c456-46b5-a433-8101605d824b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055474803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1055474803
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1593214318
Short name T337
Test name
Test status
Simulation time 771441030 ps
CPU time 6.33 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:43 PM PST 24
Peak memory 209716 kb
Host smart-13ff3135-eb2c-452d-a9e7-684e9b9d89d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593214318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1593214318
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.182226291
Short name T188
Test name
Test status
Simulation time 17225352800 ps
CPU time 64.96 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:59:40 PM PST 24
Peak memory 216588 kb
Host smart-1c61efe3-a11f-4240-b3e5-3a040ab0d01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182226291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.182226291
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2493365522
Short name T144
Test name
Test status
Simulation time 2190676032 ps
CPU time 13.28 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:16 PM PST 24
Peak memory 209144 kb
Host smart-366b8cd8-2b1d-43e9-8c01-ff7950074967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493365522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2493365522
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1191192742
Short name T147
Test name
Test status
Simulation time 426789186 ps
CPU time 5.61 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 208404 kb
Host smart-440fd265-dab7-49a1-9ac2-3ad61711c79c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191192742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1191192742
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3520066752
Short name T165
Test name
Test status
Simulation time 46530711 ps
CPU time 1.69 seconds
Started Feb 21 02:56:53 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 209284 kb
Host smart-3bac5c63-191c-4cda-b2ec-cde98a14a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520066752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3520066752
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4161714996
Short name T137
Test name
Test status
Simulation time 324080737 ps
CPU time 2.79 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 215744 kb
Host smart-3c49549b-96f6-421d-8bcf-723191701b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161714996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4161714996
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.62688933
Short name T136
Test name
Test status
Simulation time 202434854 ps
CPU time 2.95 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 217236 kb
Host smart-63a43471-ba5e-4fdf-ae17-da5fff78fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62688933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.62688933
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3975726646
Short name T175
Test name
Test status
Simulation time 226382356 ps
CPU time 7.96 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 220040 kb
Host smart-ea9d17b6-c147-4ec0-8f68-6ff05c418eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975726646 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3975726646
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.829154593
Short name T226
Test name
Test status
Simulation time 1429444749 ps
CPU time 38.47 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 214412 kb
Host smart-e0fbff12-b5f2-463a-9bef-25f7db6db938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829154593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.829154593
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.938477934
Short name T213
Test name
Test status
Simulation time 227831088 ps
CPU time 8.92 seconds
Started Feb 21 02:57:01 PM PST 24
Finished Feb 21 02:57:10 PM PST 24
Peak memory 219612 kb
Host smart-dbe63159-47a7-4f2c-9502-3a9bf434dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938477934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.938477934
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3358188117
Short name T65
Test name
Test status
Simulation time 1437228909 ps
CPU time 51.74 seconds
Started Feb 21 02:57:09 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 217508 kb
Host smart-8e7f575a-61c4-4f69-9249-ec400aabdda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358188117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3358188117
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2939835959
Short name T345
Test name
Test status
Simulation time 4993252994 ps
CPU time 51.83 seconds
Started Feb 21 02:56:52 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 215904 kb
Host smart-6d2be168-e271-4d44-a78a-3777122592c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939835959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2939835959
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2026511421
Short name T650
Test name
Test status
Simulation time 1034164997 ps
CPU time 3.42 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:56:50 PM PST 24
Peak memory 214228 kb
Host smart-9a96383e-c6e6-4803-ae57-02e57ae0cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026511421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2026511421
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2686615871
Short name T221
Test name
Test status
Simulation time 55069299 ps
CPU time 3.13 seconds
Started Feb 21 02:57:05 PM PST 24
Finished Feb 21 02:57:09 PM PST 24
Peak memory 214300 kb
Host smart-248a6f93-6aac-4795-afa3-e24fb5fa3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686615871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2686615871
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.320354018
Short name T79
Test name
Test status
Simulation time 161688301 ps
CPU time 3.87 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 213968 kb
Host smart-ffbea60a-18bf-4483-a3ff-7526477cd03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320354018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.320354018
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1769138533
Short name T322
Test name
Test status
Simulation time 206936778 ps
CPU time 3.93 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 214936 kb
Host smart-ea383eef-b039-483e-b1b0-86876c7e34af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769138533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1769138533
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1876074640
Short name T291
Test name
Test status
Simulation time 1280180803 ps
CPU time 13.27 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:46 PM PST 24
Peak memory 214216 kb
Host smart-9f1b8c94-12e6-4966-b743-38d5bda7b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876074640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1876074640
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2555028617
Short name T854
Test name
Test status
Simulation time 357929325 ps
CPU time 8.84 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208944 kb
Host smart-f6e30a3b-3f04-45e8-9e19-544d2bbb870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555028617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2555028617
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3393789145
Short name T82
Test name
Test status
Simulation time 666457300 ps
CPU time 5.85 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 210804 kb
Host smart-2a4c7705-c920-4189-ab60-922f8348b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393789145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3393789145
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1107665188
Short name T223
Test name
Test status
Simulation time 107649942 ps
CPU time 4.65 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 209400 kb
Host smart-f5fab443-cfcc-46dd-8e57-b95b8ca2c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107665188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1107665188
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3410468058
Short name T212
Test name
Test status
Simulation time 6426237161 ps
CPU time 42.56 seconds
Started Feb 21 02:57:54 PM PST 24
Finished Feb 21 02:58:36 PM PST 24
Peak memory 220708 kb
Host smart-c5bb89ea-26bc-4f80-a126-10bd32186137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410468058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3410468058
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3561066964
Short name T62
Test name
Test status
Simulation time 652744327 ps
CPU time 3.87 seconds
Started Feb 21 02:58:02 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 214556 kb
Host smart-9c64f67a-6809-46db-87cb-f791c4c38ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561066964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3561066964
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.844747544
Short name T236
Test name
Test status
Simulation time 60105213 ps
CPU time 2.43 seconds
Started Feb 21 02:58:14 PM PST 24
Finished Feb 21 02:58:17 PM PST 24
Peak memory 208504 kb
Host smart-43e54b17-95f8-4d54-8f3d-c7582ed2009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844747544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.844747544
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2713593901
Short name T118
Test name
Test status
Simulation time 236716561 ps
CPU time 12.47 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:46 PM PST 24
Peak memory 214208 kb
Host smart-c5f45108-354c-4dfa-b6ee-3071211a9ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713593901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2713593901
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2120621503
Short name T135
Test name
Test status
Simulation time 1400625160 ps
CPU time 5.46 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 217420 kb
Host smart-e3bec391-cbd0-4113-ab5b-31003cb1d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120621503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2120621503
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1788254426
Short name T939
Test name
Test status
Simulation time 491435492 ps
CPU time 17.24 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:22 PM PST 24
Peak memory 205328 kb
Host smart-ec5847dd-23d1-4274-8a28-616eda827619
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788254426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
788254426
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2924059068
Short name T177
Test name
Test status
Simulation time 1334334531 ps
CPU time 18.1 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:15 PM PST 24
Peak memory 205360 kb
Host smart-45f5f8e5-5ec5-4e7c-9cd5-33953610b516
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924059068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
924059068
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.418258641
Short name T972
Test name
Test status
Simulation time 106353995 ps
CPU time 1.41 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 205368 kb
Host smart-4a3b5d8f-8516-4667-82cc-935979bfff0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418258641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.418258641
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2484841810
Short name T966
Test name
Test status
Simulation time 30243496 ps
CPU time 1.11 seconds
Started Feb 21 02:58:55 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 205300 kb
Host smart-0dc4d197-fabd-44d7-a945-64ac341e278a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484841810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2484841810
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3603242874
Short name T126
Test name
Test status
Simulation time 291833087 ps
CPU time 1.23 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 205344 kb
Host smart-ce101f6e-4083-4b64-892f-38579838c702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603242874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3603242874
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.455912942
Short name T945
Test name
Test status
Simulation time 28973668 ps
CPU time 0.7 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 205208 kb
Host smart-2fc16d59-0379-4ec0-852e-206b8fecd71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455912942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.455912942
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.511612244
Short name T1002
Test name
Test status
Simulation time 69946717 ps
CPU time 1.78 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 205400 kb
Host smart-c824e7fd-f9fe-4fbb-bdb9-63b18df029d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511612244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.511612244
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3469420973
Short name T1034
Test name
Test status
Simulation time 785964049 ps
CPU time 15.62 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:13 PM PST 24
Peak memory 215668 kb
Host smart-75990642-a4c7-41d4-8e31-75f561dad1f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469420973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3469420973
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4101581551
Short name T1054
Test name
Test status
Simulation time 585262798 ps
CPU time 8.19 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 213776 kb
Host smart-9d681d99-48ca-486b-8cc1-d3a07653b5ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101581551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4101581551
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3412735007
Short name T927
Test name
Test status
Simulation time 22827200 ps
CPU time 1.8 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 213680 kb
Host smart-56f989a5-a29e-4628-a593-aa75d4c15bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412735007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3412735007
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1426982359
Short name T164
Test name
Test status
Simulation time 347310191 ps
CPU time 10.37 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 208932 kb
Host smart-2f3fbf52-6144-4c5c-8c94-84d275609c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426982359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1426982359
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3994971658
Short name T952
Test name
Test status
Simulation time 371569016 ps
CPU time 8.84 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:12 PM PST 24
Peak memory 205408 kb
Host smart-13d099fc-7235-4eb8-bae3-38d1d2347082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994971658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
994971658
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1240766659
Short name T1030
Test name
Test status
Simulation time 1337541020 ps
CPU time 17.45 seconds
Started Feb 21 02:58:55 PM PST 24
Finished Feb 21 02:59:13 PM PST 24
Peak memory 205096 kb
Host smart-813b3022-dfc4-485c-8795-75b07447b304
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240766659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
240766659
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3282790990
Short name T922
Test name
Test status
Simulation time 15223951 ps
CPU time 0.88 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 205268 kb
Host smart-e527f05f-7203-4d91-bf66-9d5e927a94cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282790990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
282790990
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.357821647
Short name T1063
Test name
Test status
Simulation time 27247276 ps
CPU time 1.95 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 213736 kb
Host smart-8163b896-3d00-4198-b718-6d76cb1dfc90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357821647 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.357821647
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1602402315
Short name T1021
Test name
Test status
Simulation time 12130751 ps
CPU time 1.1 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 205372 kb
Host smart-a193a20e-cfa6-4a94-8522-63a14e61af5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602402315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1602402315
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1457001563
Short name T964
Test name
Test status
Simulation time 11147645 ps
CPU time 0.82 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 205132 kb
Host smart-2f273d7f-2d95-487b-b031-7da307c68d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457001563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1457001563
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2700503974
Short name T953
Test name
Test status
Simulation time 526667242 ps
CPU time 2.65 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:52 PM PST 24
Peak memory 205624 kb
Host smart-01852f96-8a57-485e-ad46-0ca9ad2be581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700503974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2700503974
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4004425869
Short name T909
Test name
Test status
Simulation time 120017417 ps
CPU time 1.68 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 213840 kb
Host smart-b7cbb667-9d1a-42bc-9bd1-296a5fcb0042
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004425869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4004425869
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1156139118
Short name T986
Test name
Test status
Simulation time 93341318 ps
CPU time 4.14 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 213800 kb
Host smart-42769ba9-95d1-4c67-8b6d-bbcd62c96f7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156139118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1156139118
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3205115999
Short name T1026
Test name
Test status
Simulation time 73560224 ps
CPU time 3.02 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 213636 kb
Host smart-d2d45b11-da9d-45da-8b8d-bee9ece4756f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205115999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3205115999
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.405182002
Short name T365
Test name
Test status
Simulation time 269719406 ps
CPU time 6.41 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 208632 kb
Host smart-fc6caa8c-4db4-477e-91db-256b7273069a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405182002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
405182002
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.625305365
Short name T940
Test name
Test status
Simulation time 68208788 ps
CPU time 2.92 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 213592 kb
Host smart-ac8dad2e-434f-48b1-a55f-5fc8475078ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625305365 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.625305365
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3453742110
Short name T967
Test name
Test status
Simulation time 72333459 ps
CPU time 1.17 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 205312 kb
Host smart-7b39f9c4-2eed-44f9-8874-aeb524a90973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453742110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3453742110
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2202914111
Short name T993
Test name
Test status
Simulation time 8791135 ps
CPU time 0.75 seconds
Started Feb 21 02:59:05 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 205216 kb
Host smart-03470b58-a058-4343-a2cd-a621b7ecf4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202914111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2202914111
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1036183403
Short name T959
Test name
Test status
Simulation time 201270880 ps
CPU time 2.56 seconds
Started Feb 21 02:59:13 PM PST 24
Finished Feb 21 02:59:17 PM PST 24
Peak memory 213668 kb
Host smart-2f9d3f0c-4947-440f-9706-024b6666c4f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036183403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1036183403
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1113052280
Short name T1040
Test name
Test status
Simulation time 2011863365 ps
CPU time 10.84 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 213804 kb
Host smart-0a9759df-e6f1-4960-95fb-11852bd0e481
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113052280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1113052280
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3522443385
Short name T1010
Test name
Test status
Simulation time 1723353410 ps
CPU time 9.95 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:11 PM PST 24
Peak memory 219484 kb
Host smart-ef044984-3456-4e53-9dd5-c5a5480505b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522443385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3522443385
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4112880693
Short name T937
Test name
Test status
Simulation time 268676592 ps
CPU time 3.46 seconds
Started Feb 21 02:59:15 PM PST 24
Finished Feb 21 02:59:19 PM PST 24
Peak memory 214636 kb
Host smart-d67bd97c-123a-41bf-89e4-6ef80f318db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112880693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4112880693
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2238009785
Short name T1001
Test name
Test status
Simulation time 53890612 ps
CPU time 1.66 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 213580 kb
Host smart-335acbaf-a139-43d4-a107-ab0572d2a1e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238009785 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2238009785
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2153475577
Short name T1046
Test name
Test status
Simulation time 52578223 ps
CPU time 1.09 seconds
Started Feb 21 02:59:16 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 205360 kb
Host smart-058b0d04-fdd2-44b8-ab9c-0fc8de153157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153475577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2153475577
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3829663331
Short name T950
Test name
Test status
Simulation time 12530425 ps
CPU time 0.86 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:23 PM PST 24
Peak memory 205204 kb
Host smart-5369ed28-da05-4ecc-8630-952f90dc1237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829663331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3829663331
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.786299054
Short name T1017
Test name
Test status
Simulation time 98917952 ps
CPU time 1.8 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 205344 kb
Host smart-4e1989db-a8bf-4f34-bce8-6ac618b74282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786299054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.786299054
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3893916494
Short name T931
Test name
Test status
Simulation time 545513536 ps
CPU time 3.45 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:26 PM PST 24
Peak memory 213908 kb
Host smart-07a1bb28-c050-44fc-91db-695604474333
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893916494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3893916494
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.112014971
Short name T1020
Test name
Test status
Simulation time 91942262 ps
CPU time 3.61 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 213572 kb
Host smart-4c659f16-6487-445f-b33c-96a328579a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112014971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.112014971
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1971414965
Short name T145
Test name
Test status
Simulation time 87999098 ps
CPU time 2.12 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 213748 kb
Host smart-b80ab8a5-269d-4a4d-a32e-1aba14290b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971414965 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1971414965
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2086345875
Short name T969
Test name
Test status
Simulation time 21102132 ps
CPU time 0.98 seconds
Started Feb 21 02:59:19 PM PST 24
Finished Feb 21 02:59:20 PM PST 24
Peak memory 205180 kb
Host smart-237acfd1-b086-463c-878a-39eb8eaa2abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086345875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2086345875
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1580490256
Short name T996
Test name
Test status
Simulation time 17108041 ps
CPU time 0.71 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 205220 kb
Host smart-15562444-bc96-41c4-841b-d62bc8d9c81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580490256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1580490256
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2465483063
Short name T930
Test name
Test status
Simulation time 329927715 ps
CPU time 2.7 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 205392 kb
Host smart-457ff0f0-3bd6-4094-ba38-1870654646ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465483063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2465483063
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3084699408
Short name T924
Test name
Test status
Simulation time 1403155812 ps
CPU time 9.8 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 220148 kb
Host smart-7d3bef9f-2c37-49f6-87f5-0edf59cff2d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084699408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3084699408
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1228326816
Short name T956
Test name
Test status
Simulation time 215920739 ps
CPU time 3.15 seconds
Started Feb 21 02:59:08 PM PST 24
Finished Feb 21 02:59:12 PM PST 24
Peak memory 216048 kb
Host smart-b81ec3d3-ba70-47f0-a877-52b6481a87e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228326816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1228326816
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1470223452
Short name T1045
Test name
Test status
Simulation time 203987473 ps
CPU time 1.46 seconds
Started Feb 21 02:59:24 PM PST 24
Finished Feb 21 02:59:26 PM PST 24
Peak memory 213668 kb
Host smart-7fb1d759-91f2-4ed9-abcc-c0dc4ad497fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470223452 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1470223452
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1282467539
Short name T990
Test name
Test status
Simulation time 132695308 ps
CPU time 1.3 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 205356 kb
Host smart-8cc9a353-dad6-4d06-a0e5-edd8df3ee446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282467539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1282467539
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3832421152
Short name T1036
Test name
Test status
Simulation time 17080166 ps
CPU time 0.71 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:23 PM PST 24
Peak memory 205208 kb
Host smart-ec404d79-1693-4a61-948e-59a3bd755419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832421152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3832421152
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2222128621
Short name T124
Test name
Test status
Simulation time 231001228 ps
CPU time 2.6 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:25 PM PST 24
Peak memory 205312 kb
Host smart-02f74036-c9a4-45e1-8425-2574f9f8614f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222128621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2222128621
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.482849230
Short name T962
Test name
Test status
Simulation time 2348810984 ps
CPU time 3.87 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 213872 kb
Host smart-788d2856-2681-4069-93f4-ba9efa94242e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482849230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.482849230
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2825288851
Short name T971
Test name
Test status
Simulation time 1905408372 ps
CPU time 8.53 seconds
Started Feb 21 02:59:13 PM PST 24
Finished Feb 21 02:59:22 PM PST 24
Peak memory 219596 kb
Host smart-c384f479-b7bb-42eb-bc18-4869d4f0a21b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825288851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2825288851
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1645969247
Short name T907
Test name
Test status
Simulation time 77321016 ps
CPU time 2.41 seconds
Started Feb 21 02:59:04 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 213556 kb
Host smart-75827fb0-197b-4c51-9249-e934b1fd6857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645969247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1645969247
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2294493752
Short name T153
Test name
Test status
Simulation time 1621740555 ps
CPU time 28.48 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 208648 kb
Host smart-c9894006-93d7-4c8c-b3ce-12d949139445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294493752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2294493752
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.381003614
Short name T915
Test name
Test status
Simulation time 61437736 ps
CPU time 1.44 seconds
Started Feb 21 02:59:12 PM PST 24
Finished Feb 21 02:59:15 PM PST 24
Peak memory 213596 kb
Host smart-854d2099-b970-43a1-8fe2-9d710ede6bd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381003614 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.381003614
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.336740273
Short name T926
Test name
Test status
Simulation time 169919012 ps
CPU time 1.23 seconds
Started Feb 21 02:59:20 PM PST 24
Finished Feb 21 02:59:22 PM PST 24
Peak memory 205384 kb
Host smart-3b4cbc85-d006-458e-8db4-c598031d3a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336740273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.336740273
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3651199950
Short name T1064
Test name
Test status
Simulation time 14719641 ps
CPU time 0.69 seconds
Started Feb 21 02:59:12 PM PST 24
Finished Feb 21 02:59:14 PM PST 24
Peak memory 205112 kb
Host smart-83a9872f-4a4b-4ed0-b934-752b313c79ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651199950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3651199950
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3007073024
Short name T998
Test name
Test status
Simulation time 52616422 ps
CPU time 2.51 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 205364 kb
Host smart-6494fe37-4495-4027-9923-2ce4e317b731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007073024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3007073024
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1886202611
Short name T983
Test name
Test status
Simulation time 315309900 ps
CPU time 7.04 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 213864 kb
Host smart-6a127cbb-1096-4e11-a670-4b08ee94f340
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886202611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1886202611
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4243276597
Short name T1018
Test name
Test status
Simulation time 375011552 ps
CPU time 7.62 seconds
Started Feb 21 02:59:24 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 214020 kb
Host smart-bff8d3e8-16c6-4611-962d-050168aeb89e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243276597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4243276597
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2869066629
Short name T934
Test name
Test status
Simulation time 185885285 ps
CPU time 5.89 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 214880 kb
Host smart-609cb665-4bd4-451d-9c71-497cabacdbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869066629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2869066629
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.356531154
Short name T146
Test name
Test status
Simulation time 148459743 ps
CPU time 6.01 seconds
Started Feb 21 02:59:22 PM PST 24
Finished Feb 21 02:59:28 PM PST 24
Peak memory 213544 kb
Host smart-bdb785b2-8a15-4cbc-8d0f-e3a2e957daa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356531154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.356531154
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.730611140
Short name T1037
Test name
Test status
Simulation time 45044939 ps
CPU time 1.13 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205460 kb
Host smart-bbab06ee-b95d-4b2a-b080-b3b2348a29fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730611140 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.730611140
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3962396482
Short name T1015
Test name
Test status
Simulation time 24710593 ps
CPU time 1.11 seconds
Started Feb 21 02:59:15 PM PST 24
Finished Feb 21 02:59:17 PM PST 24
Peak memory 205356 kb
Host smart-a2f8b6bc-a7c9-4f9e-9b54-8713b651bed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962396482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3962396482
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.919330596
Short name T1039
Test name
Test status
Simulation time 17313866 ps
CPU time 0.83 seconds
Started Feb 21 02:59:18 PM PST 24
Finished Feb 21 02:59:19 PM PST 24
Peak memory 205164 kb
Host smart-8c3f4ca0-2732-4b0e-9d9d-fa3ce3884a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919330596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.919330596
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.115553317
Short name T1049
Test name
Test status
Simulation time 177416883 ps
CPU time 2.77 seconds
Started Feb 21 02:59:19 PM PST 24
Finished Feb 21 02:59:22 PM PST 24
Peak memory 205484 kb
Host smart-b729ad1b-3cd4-4f42-b503-107ba0b9ca60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115553317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.115553317
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2479214867
Short name T1016
Test name
Test status
Simulation time 976777027 ps
CPU time 2.33 seconds
Started Feb 21 02:59:10 PM PST 24
Finished Feb 21 02:59:13 PM PST 24
Peak memory 213848 kb
Host smart-495ed439-6552-4f46-90ee-3364b866050b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479214867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2479214867
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1247752732
Short name T106
Test name
Test status
Simulation time 602012664 ps
CPU time 7.77 seconds
Started Feb 21 02:59:10 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 213736 kb
Host smart-e02ec0f8-53a4-4b03-aed9-c8460564daa0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247752732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1247752732
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3250313710
Short name T176
Test name
Test status
Simulation time 61494087 ps
CPU time 1.75 seconds
Started Feb 21 02:59:13 PM PST 24
Finished Feb 21 02:59:16 PM PST 24
Peak memory 213584 kb
Host smart-51fe5922-e883-4cb9-b2f3-c65e4334af03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250313710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3250313710
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2379233394
Short name T979
Test name
Test status
Simulation time 204078079 ps
CPU time 5.27 seconds
Started Feb 21 02:59:11 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 208836 kb
Host smart-7a419eb9-b22d-49d0-99b3-862c4108a8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379233394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2379233394
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2681139198
Short name T904
Test name
Test status
Simulation time 21612202 ps
CPU time 1.4 seconds
Started Feb 21 02:59:28 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 213644 kb
Host smart-15631013-e9fc-47e5-9f4f-04907c726e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681139198 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2681139198
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4157797053
Short name T1050
Test name
Test status
Simulation time 27916305 ps
CPU time 1.14 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 205212 kb
Host smart-b2608095-dd68-4cda-9ae3-ea2c2222e64d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157797053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4157797053
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3808270730
Short name T984
Test name
Test status
Simulation time 22057830 ps
CPU time 0.74 seconds
Started Feb 21 02:59:28 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 205204 kb
Host smart-ea6fb4c5-557a-463b-82b5-63fe4653a10c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808270730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3808270730
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2957688361
Short name T920
Test name
Test status
Simulation time 221181134 ps
CPU time 2.17 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 205372 kb
Host smart-77ed3d2e-6e82-40fe-b9c0-37026cef20a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957688361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2957688361
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3969165430
Short name T941
Test name
Test status
Simulation time 190988900 ps
CPU time 3.69 seconds
Started Feb 21 02:59:15 PM PST 24
Finished Feb 21 02:59:20 PM PST 24
Peak memory 213852 kb
Host smart-81b2cef0-ec7a-4dd2-b01d-c06684c5b25b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969165430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3969165430
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3465965029
Short name T1024
Test name
Test status
Simulation time 178509153 ps
CPU time 4.79 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:35 PM PST 24
Peak memory 219768 kb
Host smart-5d374fa1-5b74-4aff-90b3-ffe3f5275b99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465965029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3465965029
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.257769323
Short name T1042
Test name
Test status
Simulation time 30267631 ps
CPU time 1.77 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 213632 kb
Host smart-1675298f-4c97-4464-a32a-a511506a795e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257769323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.257769323
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4200997651
Short name T1047
Test name
Test status
Simulation time 25253734 ps
CPU time 1.05 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 205372 kb
Host smart-5f6d521d-a696-4358-b242-6ffe04aa3d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200997651 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4200997651
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2015304340
Short name T1033
Test name
Test status
Simulation time 15412216 ps
CPU time 0.91 seconds
Started Feb 21 02:59:24 PM PST 24
Finished Feb 21 02:59:26 PM PST 24
Peak memory 205172 kb
Host smart-cec94f8e-319a-4e2c-8a77-9503f34241f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015304340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2015304340
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4006581264
Short name T933
Test name
Test status
Simulation time 17555857 ps
CPU time 0.8 seconds
Started Feb 21 02:59:24 PM PST 24
Finished Feb 21 02:59:25 PM PST 24
Peak memory 205208 kb
Host smart-b9e668e8-9f9f-4200-9574-689c396b1e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006581264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4006581264
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1333552791
Short name T992
Test name
Test status
Simulation time 164984731 ps
CPU time 3.31 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:35 PM PST 24
Peak memory 205372 kb
Host smart-138068f9-89ad-41eb-891b-e5e231d7af3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333552791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1333552791
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2137491258
Short name T944
Test name
Test status
Simulation time 531356935 ps
CPU time 3.5 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 213820 kb
Host smart-5bdeca85-a3f4-4da3-961d-97e74e1ebed0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137491258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2137491258
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1433376201
Short name T1022
Test name
Test status
Simulation time 1393336204 ps
CPU time 8.64 seconds
Started Feb 21 02:59:36 PM PST 24
Finished Feb 21 02:59:45 PM PST 24
Peak memory 213844 kb
Host smart-17c47900-429b-4816-a45d-1490cd5ddf42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433376201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1433376201
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1307016690
Short name T1006
Test name
Test status
Simulation time 117282154 ps
CPU time 2.21 seconds
Started Feb 21 02:59:37 PM PST 24
Finished Feb 21 02:59:40 PM PST 24
Peak memory 213728 kb
Host smart-0cbacafc-04e4-4d3d-8e30-a41be8f5bb18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307016690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1307016690
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2666827153
Short name T985
Test name
Test status
Simulation time 36032304 ps
CPU time 1.67 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 213640 kb
Host smart-524244a6-fe4c-4905-9049-bfcfa5d4d39b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666827153 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2666827153
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1216433088
Short name T943
Test name
Test status
Simulation time 48740920 ps
CPU time 1.11 seconds
Started Feb 21 02:59:34 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 205316 kb
Host smart-a524eda6-cb0d-49af-aeb7-aa2ebb3b023f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216433088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1216433088
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4143012943
Short name T1029
Test name
Test status
Simulation time 37044465 ps
CPU time 0.85 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205208 kb
Host smart-90d06453-3d6b-4b68-926f-049943eba331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143012943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4143012943
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1484787734
Short name T936
Test name
Test status
Simulation time 136482831 ps
CPU time 2.44 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 205408 kb
Host smart-48a16537-5443-4104-9558-fb04d803ae6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484787734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1484787734
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3574253465
Short name T963
Test name
Test status
Simulation time 618375881 ps
CPU time 3.96 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 221944 kb
Host smart-42cbe523-380a-4149-bbb1-6be6577fde83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574253465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3574253465
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2125497828
Short name T127
Test name
Test status
Simulation time 497095420 ps
CPU time 10 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:46 PM PST 24
Peak memory 213848 kb
Host smart-7b2c9dd5-4873-4b55-aaa8-9d038e56df8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125497828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2125497828
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3282268145
Short name T1013
Test name
Test status
Simulation time 190037056 ps
CPU time 1.58 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 213636 kb
Host smart-4da0a38c-65ed-490f-8e58-a9176cddabb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282268145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3282268145
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1790183957
Short name T946
Test name
Test status
Simulation time 90462587 ps
CPU time 1.53 seconds
Started Feb 21 02:59:27 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 213568 kb
Host smart-9adb4d6c-cecb-460f-95a1-9a18c4a2a1c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790183957 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1790183957
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3455930611
Short name T981
Test name
Test status
Simulation time 23211904 ps
CPU time 1.13 seconds
Started Feb 21 02:59:28 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205264 kb
Host smart-e3b92c09-decd-4293-9cc6-b2d4044258e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455930611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3455930611
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2531165769
Short name T928
Test name
Test status
Simulation time 23272973 ps
CPU time 0.76 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205128 kb
Host smart-6bd6406c-315c-4837-b8f8-443b4f8d03c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531165769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2531165769
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.265288538
Short name T121
Test name
Test status
Simulation time 22452117 ps
CPU time 1.67 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 205468 kb
Host smart-83833377-8d1d-4a28-a696-a308cb8749d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265288538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.265288538
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2706002580
Short name T918
Test name
Test status
Simulation time 146473154 ps
CPU time 2.75 seconds
Started Feb 21 02:59:23 PM PST 24
Finished Feb 21 02:59:26 PM PST 24
Peak memory 221940 kb
Host smart-c18fb19e-1408-4d92-96aa-0f7db01c75dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706002580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2706002580
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1868803399
Short name T1066
Test name
Test status
Simulation time 682913600 ps
CPU time 9.85 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 222020 kb
Host smart-a3393dab-de16-425a-8453-0a5e69c86b68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868803399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1868803399
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.794805372
Short name T942
Test name
Test status
Simulation time 144717345 ps
CPU time 4.78 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 213608 kb
Host smart-91bfd75f-680f-4020-bee5-6eaa153e9d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794805372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.794805372
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1645418398
Short name T166
Test name
Test status
Simulation time 846287410 ps
CPU time 8.92 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 208924 kb
Host smart-c0b9d6b6-dc5a-4fd8-b9eb-de0a14df42e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645418398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1645418398
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2596271661
Short name T949
Test name
Test status
Simulation time 525819807 ps
CPU time 8.81 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:12 PM PST 24
Peak memory 205292 kb
Host smart-4333c4ce-dc57-46c3-8542-5a3b5ac349fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596271661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
596271661
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2354358629
Short name T960
Test name
Test status
Simulation time 1745595948 ps
CPU time 18.05 seconds
Started Feb 21 02:59:05 PM PST 24
Finished Feb 21 02:59:24 PM PST 24
Peak memory 205280 kb
Host smart-933b5029-3fca-4b59-82eb-27db32e3f11d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354358629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
354358629
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.824546660
Short name T923
Test name
Test status
Simulation time 94006323 ps
CPU time 1.42 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 205340 kb
Host smart-60be3596-7e6a-4f6c-8b16-c13d32f2661d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824546660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.824546660
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1331681630
Short name T914
Test name
Test status
Simulation time 22475893 ps
CPU time 1.52 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 215820 kb
Host smart-fec3fa62-49ee-43a8-a73f-d55b32a44d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331681630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1331681630
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.241430922
Short name T125
Test name
Test status
Simulation time 67974049 ps
CPU time 1.56 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 205216 kb
Host smart-48a06455-0656-4f50-a718-0504af184a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241430922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.241430922
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1513147967
Short name T973
Test name
Test status
Simulation time 38410609 ps
CPU time 0.87 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 205248 kb
Host smart-26739616-9919-4945-9fe9-9971466652f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513147967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1513147967
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1704606639
Short name T1055
Test name
Test status
Simulation time 384484568 ps
CPU time 1.35 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 205428 kb
Host smart-184aa6c4-f9cd-4722-8eec-3555d2f729c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704606639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1704606639
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1893691150
Short name T925
Test name
Test status
Simulation time 107248882 ps
CPU time 2.26 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 213796 kb
Host smart-7dcc527a-c56d-4648-9d4c-ec08f48cb1c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893691150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1893691150
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1941598204
Short name T107
Test name
Test status
Simulation time 1502544713 ps
CPU time 9.2 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:11 PM PST 24
Peak memory 213844 kb
Host smart-c4eca8e0-67a2-428e-a6cf-4f2b94a83e57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941598204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1941598204
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1774356279
Short name T919
Test name
Test status
Simulation time 281290564 ps
CPU time 4.06 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 215596 kb
Host smart-6f6969eb-2386-498d-9108-ffc22ed69165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774356279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1774356279
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1132189706
Short name T159
Test name
Test status
Simulation time 12502430135 ps
CPU time 25.91 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:19 PM PST 24
Peak memory 208548 kb
Host smart-a47bad22-a550-4361-a799-5a9ec1a3ba19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132189706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1132189706
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.189669837
Short name T913
Test name
Test status
Simulation time 37292713 ps
CPU time 0.71 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205144 kb
Host smart-37d644e9-1cef-4d53-9f69-0126646d2c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189669837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.189669837
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2390019042
Short name T976
Test name
Test status
Simulation time 131262192 ps
CPU time 0.86 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205180 kb
Host smart-42ae3ec9-6f32-4399-8312-868b14e92479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390019042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2390019042
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3261595212
Short name T977
Test name
Test status
Simulation time 158551915 ps
CPU time 0.87 seconds
Started Feb 21 02:59:34 PM PST 24
Finished Feb 21 02:59:35 PM PST 24
Peak memory 205184 kb
Host smart-f5bda868-4856-4d5a-a3d9-1505d6b69cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261595212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3261595212
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1044045993
Short name T1051
Test name
Test status
Simulation time 60831951 ps
CPU time 0.86 seconds
Started Feb 21 02:59:23 PM PST 24
Finished Feb 21 02:59:24 PM PST 24
Peak memory 205196 kb
Host smart-1c5c6db2-31f6-4fea-8c3e-0a6b4dff5ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044045993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1044045993
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1114846277
Short name T1023
Test name
Test status
Simulation time 40283266 ps
CPU time 0.91 seconds
Started Feb 21 02:59:34 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 205180 kb
Host smart-0ad5f099-e850-42aa-be47-e0f20fa2e284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114846277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1114846277
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2597272925
Short name T917
Test name
Test status
Simulation time 47640574 ps
CPU time 0.89 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205224 kb
Host smart-4645309a-eab0-4d58-9e59-6fb000ee91b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597272925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2597272925
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1952366419
Short name T965
Test name
Test status
Simulation time 10254954 ps
CPU time 0.72 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 205144 kb
Host smart-7e67dfe5-7c29-4b7f-b9ae-8aacb1cea295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952366419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1952366419
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3230648977
Short name T988
Test name
Test status
Simulation time 17277271 ps
CPU time 0.77 seconds
Started Feb 21 02:59:33 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 205212 kb
Host smart-88c5ca7a-8257-444e-8e13-021bfec954a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230648977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3230648977
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2796326974
Short name T912
Test name
Test status
Simulation time 32797589 ps
CPU time 0.82 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205176 kb
Host smart-5886fd4a-19c3-4fb3-afb3-6a3a4bf408c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796326974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2796326974
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.969261998
Short name T1019
Test name
Test status
Simulation time 9757567 ps
CPU time 0.83 seconds
Started Feb 21 02:59:40 PM PST 24
Finished Feb 21 02:59:41 PM PST 24
Peak memory 205212 kb
Host smart-41886d48-6540-458e-a63a-5bb7c4b43fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969261998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.969261998
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3963674705
Short name T128
Test name
Test status
Simulation time 431469777 ps
CPU time 13.61 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:21 PM PST 24
Peak memory 205260 kb
Host smart-8490bff3-8362-4205-9c67-13e23c340532
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963674705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
963674705
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3611552965
Short name T1062
Test name
Test status
Simulation time 1159217520 ps
CPU time 8.53 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:12 PM PST 24
Peak memory 205352 kb
Host smart-5642a51b-c3c3-42eb-aae4-d1cbba5d5dd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611552965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
611552965
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3006216308
Short name T908
Test name
Test status
Simulation time 322751231 ps
CPU time 1.23 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 205348 kb
Host smart-6911ca6a-fa5e-4f9c-bf1c-985adcb59d0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006216308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
006216308
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2178595522
Short name T1041
Test name
Test status
Simulation time 70886617 ps
CPU time 1.43 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 205504 kb
Host smart-dd80758d-1a6e-4355-840b-29eea1306b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178595522 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2178595522
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.887471771
Short name T1025
Test name
Test status
Simulation time 28842320 ps
CPU time 1.08 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 205376 kb
Host smart-113a1dda-2877-4c1a-b730-6022f900c7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887471771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.887471771
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3853221282
Short name T902
Test name
Test status
Simulation time 17426775 ps
CPU time 0.72 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 205220 kb
Host smart-4cccf5a5-e454-4cb7-80fa-31da9afb76b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853221282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3853221282
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.506423756
Short name T957
Test name
Test status
Simulation time 70492849 ps
CPU time 1.7 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:52 PM PST 24
Peak memory 205348 kb
Host smart-5de7a266-1c45-4b7d-8783-48b99219ded2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506423756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.506423756
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3913521102
Short name T948
Test name
Test status
Simulation time 1016052478 ps
CPU time 4.54 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:11 PM PST 24
Peak memory 213800 kb
Host smart-2326d046-5e24-46a5-9123-e4c718e84a89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913521102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3913521102
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3832347167
Short name T1038
Test name
Test status
Simulation time 3128715562 ps
CPU time 6.02 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 213804 kb
Host smart-0646ea3b-446d-4196-a9a2-31f92962787f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832347167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3832347167
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1062792310
Short name T1014
Test name
Test status
Simulation time 267708202 ps
CPU time 2.38 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 213500 kb
Host smart-b722d325-d155-4bc8-809e-285cb34cc96c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062792310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1062792310
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4194462376
Short name T141
Test name
Test status
Simulation time 215326168 ps
CPU time 9.03 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 213484 kb
Host smart-13b89302-e7de-45fe-9a45-e6814b63e251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194462376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4194462376
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1483072486
Short name T987
Test name
Test status
Simulation time 26770174 ps
CPU time 0.71 seconds
Started Feb 21 02:59:33 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 205216 kb
Host smart-4352176e-0a80-4117-a693-8c221e5341f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483072486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1483072486
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3758623799
Short name T1044
Test name
Test status
Simulation time 36358336 ps
CPU time 0.74 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 205184 kb
Host smart-a8c6ca5f-68b9-4358-8e55-6e7cabfd320b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758623799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3758623799
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4252480524
Short name T1000
Test name
Test status
Simulation time 17370480 ps
CPU time 0.71 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205208 kb
Host smart-fd26edce-9101-4c82-aab1-72c8abae1682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252480524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4252480524
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1984449324
Short name T1004
Test name
Test status
Simulation time 12688008 ps
CPU time 0.79 seconds
Started Feb 21 02:59:39 PM PST 24
Finished Feb 21 02:59:40 PM PST 24
Peak memory 205216 kb
Host smart-d3bfbf48-84fe-446c-bd2e-d14e16670660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984449324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1984449324
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.985862888
Short name T968
Test name
Test status
Simulation time 12115341 ps
CPU time 0.77 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205200 kb
Host smart-2eff5f22-5898-4271-bcd2-c5ba7e910af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985862888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.985862888
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2746903538
Short name T1011
Test name
Test status
Simulation time 19780325 ps
CPU time 0.78 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205208 kb
Host smart-c08964c8-5974-473e-a82a-8a1694b79645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746903538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2746903538
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4151372726
Short name T1067
Test name
Test status
Simulation time 69627353 ps
CPU time 0.73 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 205208 kb
Host smart-810fadda-046f-423d-abc6-28c4111e8037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151372726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4151372726
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2413905930
Short name T1059
Test name
Test status
Simulation time 30259419 ps
CPU time 0.79 seconds
Started Feb 21 02:59:40 PM PST 24
Finished Feb 21 02:59:41 PM PST 24
Peak memory 205216 kb
Host smart-8000ceb8-451d-438c-a16f-8ba881c305c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413905930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2413905930
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4152083414
Short name T999
Test name
Test status
Simulation time 77111050 ps
CPU time 0.87 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:37 PM PST 24
Peak memory 205200 kb
Host smart-02756c94-a4bf-4164-a34e-adabdb72e37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152083414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4152083414
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.198157667
Short name T1058
Test name
Test status
Simulation time 14462692 ps
CPU time 0.68 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:27 PM PST 24
Peak memory 205188 kb
Host smart-365fe0c0-1c08-4e7e-80e5-97c11e7ed942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198157667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.198157667
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3559804666
Short name T1005
Test name
Test status
Simulation time 1373752329 ps
CPU time 9.33 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 205432 kb
Host smart-44aca4d4-e631-441d-8033-395f47978f08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559804666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
559804666
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3297731849
Short name T1012
Test name
Test status
Simulation time 863343015 ps
CPU time 25.19 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 205444 kb
Host smart-c9873da4-4fc4-41a2-be03-6a215d16ade3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297731849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
297731849
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.702011672
Short name T906
Test name
Test status
Simulation time 32140260 ps
CPU time 1.2 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 205320 kb
Host smart-59e30fad-95ac-42f2-8efd-f4f610c81091
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702011672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.702011672
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2880035392
Short name T1048
Test name
Test status
Simulation time 157708801 ps
CPU time 2.17 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 213684 kb
Host smart-af5585df-dc56-4406-bd86-0e4d9e6d4a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880035392 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2880035392
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3765117296
Short name T1061
Test name
Test status
Simulation time 36562270 ps
CPU time 1.21 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 205340 kb
Host smart-d0596800-4128-41bb-b638-a163f96897a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765117296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3765117296
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3907044868
Short name T961
Test name
Test status
Simulation time 23255985 ps
CPU time 1 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 205284 kb
Host smart-4569fbc6-0e3b-4831-8b64-0fdb5bb55f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907044868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3907044868
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.423663002
Short name T974
Test name
Test status
Simulation time 129512440 ps
CPU time 2.53 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 205408 kb
Host smart-42d8cb91-e662-4d7a-af8b-79ca3c79b8a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423663002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.423663002
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2659452177
Short name T958
Test name
Test status
Simulation time 219835498 ps
CPU time 6.17 seconds
Started Feb 21 02:59:05 PM PST 24
Finished Feb 21 02:59:13 PM PST 24
Peak memory 213728 kb
Host smart-7734827b-a9de-43b4-a1c7-5df05d733332
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659452177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2659452177
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2522244253
Short name T1065
Test name
Test status
Simulation time 336976976 ps
CPU time 8.28 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 213856 kb
Host smart-0a5bf6af-92c4-4200-a2fc-e25879034bfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522244253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2522244253
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.771264639
Short name T989
Test name
Test status
Simulation time 103496620 ps
CPU time 3.18 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 215652 kb
Host smart-c6e62424-fbfc-4562-ad19-7539bb3237df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771264639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.771264639
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3162642589
Short name T168
Test name
Test status
Simulation time 1178294763 ps
CPU time 9.47 seconds
Started Feb 21 02:58:55 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 208292 kb
Host smart-d63f63f0-1f7f-46a9-af17-ad2e2f94a30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162642589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3162642589
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4006606435
Short name T982
Test name
Test status
Simulation time 39509519 ps
CPU time 0.85 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:37 PM PST 24
Peak memory 205132 kb
Host smart-b2e07d1e-8006-4cd6-9259-26a719812f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006606435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4006606435
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3267824131
Short name T910
Test name
Test status
Simulation time 21234750 ps
CPU time 0.71 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:33 PM PST 24
Peak memory 205196 kb
Host smart-db5a2169-55e9-4f67-9991-6674be538a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267824131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3267824131
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.379472973
Short name T929
Test name
Test status
Simulation time 13842521 ps
CPU time 0.75 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 205192 kb
Host smart-c97a314c-15b0-429d-9b3f-5b29f0d745a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379472973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.379472973
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.785223189
Short name T991
Test name
Test status
Simulation time 20778732 ps
CPU time 0.85 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205104 kb
Host smart-52fbdaf2-2abe-49dc-aad2-9a4e6c6783b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785223189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.785223189
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3422789164
Short name T1008
Test name
Test status
Simulation time 11083353 ps
CPU time 0.79 seconds
Started Feb 21 02:59:29 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 205164 kb
Host smart-34ffdfe3-ecfa-4df7-bbb8-6937ab649255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422789164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3422789164
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3182018544
Short name T980
Test name
Test status
Simulation time 18404324 ps
CPU time 0.81 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 205192 kb
Host smart-60251ed4-bff3-42a7-83c5-a624388ff9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182018544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3182018544
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2725164120
Short name T1043
Test name
Test status
Simulation time 43082100 ps
CPU time 0.75 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 02:59:31 PM PST 24
Peak memory 205228 kb
Host smart-a1176e91-3766-4522-bd4e-b8f8d7f76115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725164120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2725164120
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2755987823
Short name T995
Test name
Test status
Simulation time 13653434 ps
CPU time 0.78 seconds
Started Feb 21 02:59:33 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 205180 kb
Host smart-bd4dccd1-06ff-4378-b156-8f0afb71ca51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755987823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2755987823
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.737004264
Short name T1027
Test name
Test status
Simulation time 72457443 ps
CPU time 0.72 seconds
Started Feb 21 02:59:33 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 205188 kb
Host smart-d278df0f-50c8-422a-a548-775db68d9700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737004264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.737004264
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3295552115
Short name T1007
Test name
Test status
Simulation time 38774848 ps
CPU time 0.9 seconds
Started Feb 21 02:59:27 PM PST 24
Finished Feb 21 02:59:28 PM PST 24
Peak memory 205204 kb
Host smart-c1ac26ed-adfa-4ab0-85aa-562b01b1e3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295552115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3295552115
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3226405215
Short name T955
Test name
Test status
Simulation time 22661003 ps
CPU time 1.11 seconds
Started Feb 21 02:58:54 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 205400 kb
Host smart-22b29661-1fdc-4169-8895-04fbf3f6dabe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226405215 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3226405215
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.486457362
Short name T911
Test name
Test status
Simulation time 25131249 ps
CPU time 1.46 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 205276 kb
Host smart-bfd94659-80a8-44d9-907d-76b0b068e977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486457362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.486457362
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2204147201
Short name T978
Test name
Test status
Simulation time 34912798 ps
CPU time 0.71 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 205136 kb
Host smart-b23a626e-ea56-4b64-a2f8-907409f22d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204147201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2204147201
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3135913906
Short name T970
Test name
Test status
Simulation time 99419899 ps
CPU time 2.77 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 205412 kb
Host smart-f67f07cb-1fc2-40e3-8045-7151c690b343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135913906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3135913906
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1068793195
Short name T1057
Test name
Test status
Simulation time 825417301 ps
CPU time 7.09 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 213764 kb
Host smart-3ed21b09-6fa5-4039-867a-23cd812b305b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068793195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1068793195
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.297919409
Short name T932
Test name
Test status
Simulation time 217222761 ps
CPU time 8.64 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 219788 kb
Host smart-6d02f625-f076-4ba9-bdf8-13a13331dcf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297919409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.297919409
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.441319938
Short name T1032
Test name
Test status
Simulation time 84834314 ps
CPU time 3.21 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 213584 kb
Host smart-1511303a-ac54-4bb5-9cf4-c36dd32e3d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441319938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.441319938
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1415983220
Short name T163
Test name
Test status
Simulation time 1702583194 ps
CPU time 11.58 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:10 PM PST 24
Peak memory 208612 kb
Host smart-73297ead-2405-436e-8679-063bcf6534fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415983220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1415983220
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3593171735
Short name T954
Test name
Test status
Simulation time 79853406 ps
CPU time 1.46 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 213708 kb
Host smart-94a9fa50-10e2-4b3b-8a60-3f46ae87662b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593171735 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3593171735
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2177736953
Short name T138
Test name
Test status
Simulation time 11234869 ps
CPU time 0.97 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 205336 kb
Host smart-c2eb19d9-b8c9-4d85-840b-bfb8ef067cae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177736953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2177736953
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2821809164
Short name T903
Test name
Test status
Simulation time 14880314 ps
CPU time 0.75 seconds
Started Feb 21 02:58:54 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 205156 kb
Host smart-5e79653d-fdf2-4d82-99d8-56a7bb813f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821809164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2821809164
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1420215160
Short name T1056
Test name
Test status
Simulation time 102008108 ps
CPU time 2.08 seconds
Started Feb 21 02:58:54 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 205436 kb
Host smart-5f892033-1c60-4075-987e-84a1317eb738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420215160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1420215160
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1086584384
Short name T100
Test name
Test status
Simulation time 541373657 ps
CPU time 4.18 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 213916 kb
Host smart-0286824b-4ad1-42e6-82d3-5452cec2cf8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086584384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1086584384
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.938639612
Short name T935
Test name
Test status
Simulation time 186236281 ps
CPU time 8.88 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:10 PM PST 24
Peak memory 213864 kb
Host smart-0329739f-6a5d-475c-b18f-99e8dfe614a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938639612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.938639612
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.593184744
Short name T905
Test name
Test status
Simulation time 69611861 ps
CPU time 2.17 seconds
Started Feb 21 02:58:55 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 216696 kb
Host smart-fa21e462-2fb9-4112-b860-bc37464ce1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593184744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.593184744
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2211980176
Short name T156
Test name
Test status
Simulation time 436163998 ps
CPU time 9.17 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 209000 kb
Host smart-b67d0e8b-7965-4f2e-9d6d-164aa1f1bc25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211980176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2211980176
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2379517337
Short name T916
Test name
Test status
Simulation time 51770562 ps
CPU time 2.14 seconds
Started Feb 21 02:59:04 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 213492 kb
Host smart-602db4b7-2eeb-4d43-b23c-8dd388a573c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379517337 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2379517337
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1255096769
Short name T1052
Test name
Test status
Simulation time 48403679 ps
CPU time 1.22 seconds
Started Feb 21 02:58:54 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 205520 kb
Host smart-e1cddcc9-71b6-452e-99b5-44c059b75122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255096769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1255096769
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1884932617
Short name T951
Test name
Test status
Simulation time 14115903 ps
CPU time 0.78 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 205208 kb
Host smart-ddab6668-85d3-4904-b108-ce8f1b83b0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884932617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1884932617
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2389890399
Short name T938
Test name
Test status
Simulation time 326727239 ps
CPU time 2.47 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 205432 kb
Host smart-2c357d78-6b1b-4e5c-aad6-a9d53caa39ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389890399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2389890399
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3273336143
Short name T1031
Test name
Test status
Simulation time 381317591 ps
CPU time 3.3 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 213800 kb
Host smart-69f06e90-0cb3-45c9-afb0-2d119ce58b27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273336143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3273336143
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1541319323
Short name T1035
Test name
Test status
Simulation time 77612550 ps
CPU time 3.53 seconds
Started Feb 21 02:59:05 PM PST 24
Finished Feb 21 02:59:10 PM PST 24
Peak memory 213836 kb
Host smart-fbe4016d-85f3-4bac-88b9-7a8ba3d85742
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541319323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1541319323
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4017257468
Short name T1060
Test name
Test status
Simulation time 97248109 ps
CPU time 1.8 seconds
Started Feb 21 02:59:07 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 213540 kb
Host smart-f65b2d88-bbfd-4351-9ff8-e90b362177fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017257468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4017257468
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1518683324
Short name T921
Test name
Test status
Simulation time 104306089 ps
CPU time 2.06 seconds
Started Feb 21 02:59:14 PM PST 24
Finished Feb 21 02:59:17 PM PST 24
Peak memory 213728 kb
Host smart-d64e4beb-a67c-439d-bbbe-2ba8040d4571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518683324 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1518683324
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.98064452
Short name T1003
Test name
Test status
Simulation time 95368154 ps
CPU time 1.08 seconds
Started Feb 21 02:59:05 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 205356 kb
Host smart-0b0a9882-6020-4c19-8a1f-0c5875c39143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98064452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.98064452
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3569564414
Short name T994
Test name
Test status
Simulation time 23293486 ps
CPU time 0.77 seconds
Started Feb 21 02:59:13 PM PST 24
Finished Feb 21 02:59:15 PM PST 24
Peak memory 205188 kb
Host smart-2c2607e2-a370-4cbe-9a9d-8dd4e7a08815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569564414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3569564414
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1885125120
Short name T997
Test name
Test status
Simulation time 89846615 ps
CPU time 3.58 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 205400 kb
Host smart-0d132599-a4ec-45f1-b7ef-56dd0aa5c763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885125120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1885125120
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4237060730
Short name T102
Test name
Test status
Simulation time 224439726 ps
CPU time 6.18 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 221916 kb
Host smart-9c66ec8f-6268-4347-8f10-cdf846b986cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237060730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4237060730
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2650718401
Short name T975
Test name
Test status
Simulation time 82446034 ps
CPU time 1.89 seconds
Started Feb 21 02:59:15 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 213632 kb
Host smart-cfa062e1-3940-417e-b11a-36caa87cd658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650718401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2650718401
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1126423590
Short name T1009
Test name
Test status
Simulation time 216552993 ps
CPU time 1.57 seconds
Started Feb 21 02:59:15 PM PST 24
Finished Feb 21 02:59:17 PM PST 24
Peak memory 213560 kb
Host smart-0ec64533-acf6-4867-9095-08fab384d2d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126423590 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1126423590
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.25393003
Short name T122
Test name
Test status
Simulation time 53197355 ps
CPU time 1.18 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 205380 kb
Host smart-0dbadceb-30ef-4f7b-a23e-4931a46a99ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25393003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.25393003
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3229264826
Short name T1053
Test name
Test status
Simulation time 39264835 ps
CPU time 0.75 seconds
Started Feb 21 02:59:04 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 205404 kb
Host smart-080f113d-bb19-4a47-84c6-3534815813a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229264826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3229264826
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2411831868
Short name T123
Test name
Test status
Simulation time 361089230 ps
CPU time 3.07 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 205376 kb
Host smart-2f11b1cd-96c3-4ca0-9de7-100b258261c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411831868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2411831868
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3058295830
Short name T105
Test name
Test status
Simulation time 323616679 ps
CPU time 3.65 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 213836 kb
Host smart-1c19511f-a1d1-459b-9157-2e6ab5571c56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058295830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3058295830
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1481301910
Short name T947
Test name
Test status
Simulation time 1614775165 ps
CPU time 10.08 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:14 PM PST 24
Peak memory 213916 kb
Host smart-051fe1a4-448f-4c94-927e-5d0efdfdb858
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481301910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1481301910
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.188127138
Short name T1028
Test name
Test status
Simulation time 170658926 ps
CPU time 1.96 seconds
Started Feb 21 02:59:24 PM PST 24
Finished Feb 21 02:59:26 PM PST 24
Peak memory 214924 kb
Host smart-fd6f8ade-fe93-4fec-92c7-1579e46a9f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188127138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.188127138
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3608788259
Short name T363
Test name
Test status
Simulation time 1263549525 ps
CPU time 36.17 seconds
Started Feb 21 02:59:06 PM PST 24
Finished Feb 21 02:59:43 PM PST 24
Peak memory 208708 kb
Host smart-9c517b4e-dd25-4307-bd12-1822cdc3654f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608788259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3608788259
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.958834881
Short name T445
Test name
Test status
Simulation time 62754832 ps
CPU time 0.82 seconds
Started Feb 21 02:56:12 PM PST 24
Finished Feb 21 02:56:14 PM PST 24
Peak memory 205868 kb
Host smart-bc475432-32c2-4718-a088-10778f94c225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958834881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.958834881
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2867696793
Short name T348
Test name
Test status
Simulation time 94070298 ps
CPU time 3.7 seconds
Started Feb 21 02:56:02 PM PST 24
Finished Feb 21 02:56:06 PM PST 24
Peak memory 214308 kb
Host smart-cc4a6894-7a8d-4436-956f-fd9343286ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867696793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2867696793
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3707153953
Short name T771
Test name
Test status
Simulation time 696110384 ps
CPU time 8.93 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 222684 kb
Host smart-4aa5e106-3b20-413e-9973-466e0a786a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707153953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3707153953
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1241187451
Short name T515
Test name
Test status
Simulation time 1038563473 ps
CPU time 28.89 seconds
Started Feb 21 02:56:02 PM PST 24
Finished Feb 21 02:56:32 PM PST 24
Peak memory 208396 kb
Host smart-28307b49-4e8c-4e44-8030-ed417db63b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241187451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1241187451
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1676819051
Short name T590
Test name
Test status
Simulation time 971022704 ps
CPU time 7.04 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:24 PM PST 24
Peak memory 208004 kb
Host smart-981baaaa-d9e4-4589-9247-eebcfc6d34d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676819051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1676819051
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2594508708
Short name T665
Test name
Test status
Simulation time 127909867 ps
CPU time 5.36 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 214192 kb
Host smart-468c2386-7acc-4fa4-a886-a5f990bfa526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594508708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2594508708
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3163221629
Short name T398
Test name
Test status
Simulation time 59918540 ps
CPU time 3.63 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:14 PM PST 24
Peak memory 209668 kb
Host smart-91ac0277-3399-4a2d-a42e-91766162c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163221629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3163221629
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2984366007
Short name T328
Test name
Test status
Simulation time 2642717556 ps
CPU time 32.01 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:50 PM PST 24
Peak memory 207824 kb
Host smart-f0cec553-20d5-4b1d-bc78-85ccdbc5fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984366007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2984366007
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1366845201
Short name T6
Test name
Test status
Simulation time 590907701 ps
CPU time 10.34 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:22 PM PST 24
Peak memory 231160 kb
Host smart-4a7f894a-ffc3-4c6c-88af-1d9ee1aa6180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366845201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1366845201
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2685902658
Short name T1
Test name
Test status
Simulation time 915178435 ps
CPU time 7.74 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:25 PM PST 24
Peak memory 208412 kb
Host smart-5d965772-18d9-411a-98dc-a29b268d17f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685902658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2685902658
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1756978652
Short name T487
Test name
Test status
Simulation time 243561600 ps
CPU time 6.46 seconds
Started Feb 21 02:56:12 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 208104 kb
Host smart-ae0bae75-ecc6-47a3-a825-f82a216a2304
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756978652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1756978652
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3587184101
Short name T685
Test name
Test status
Simulation time 309025127 ps
CPU time 3.87 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 208452 kb
Host smart-1a0f037a-377a-436b-82fb-3a36aaa02e2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587184101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3587184101
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.496195529
Short name T458
Test name
Test status
Simulation time 53340175 ps
CPU time 2.91 seconds
Started Feb 21 02:56:01 PM PST 24
Finished Feb 21 02:56:05 PM PST 24
Peak memory 206656 kb
Host smart-5bc750e7-f535-4581-b21e-dc0e981a413b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496195529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.496195529
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3632453163
Short name T129
Test name
Test status
Simulation time 3835249491 ps
CPU time 35.57 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:50 PM PST 24
Peak memory 218620 kb
Host smart-2d07d4d1-3b5c-4c5b-954f-8d85fa38c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632453163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3632453163
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3417314797
Short name T694
Test name
Test status
Simulation time 72067524 ps
CPU time 3.15 seconds
Started Feb 21 02:56:03 PM PST 24
Finished Feb 21 02:56:07 PM PST 24
Peak memory 208248 kb
Host smart-7645184c-a48d-4112-ab84-4f2b0e843801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417314797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3417314797
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3875975493
Short name T862
Test name
Test status
Simulation time 702322587 ps
CPU time 5.7 seconds
Started Feb 21 02:56:02 PM PST 24
Finished Feb 21 02:56:09 PM PST 24
Peak memory 218108 kb
Host smart-eae2b9cd-c5ab-4dab-814b-4a6662c5c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875975493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3875975493
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4103314802
Short name T101
Test name
Test status
Simulation time 562478737 ps
CPU time 2.24 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 209920 kb
Host smart-ed0712a2-918f-4fc4-b875-7a5c1778e1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103314802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4103314802
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1319479642
Short name T425
Test name
Test status
Simulation time 19588158 ps
CPU time 0.76 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:11 PM PST 24
Peak memory 205856 kb
Host smart-144b2a9e-9f1d-45f6-8d0e-f7db125ef9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319479642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1319479642
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3514865420
Short name T35
Test name
Test status
Simulation time 1028248734 ps
CPU time 6.24 seconds
Started Feb 21 02:56:18 PM PST 24
Finished Feb 21 02:56:25 PM PST 24
Peak memory 209876 kb
Host smart-e0698da6-4c53-402f-91ca-af44f946ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514865420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3514865420
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2894445002
Short name T56
Test name
Test status
Simulation time 35882374 ps
CPU time 2.44 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:16 PM PST 24
Peak memory 209672 kb
Host smart-50b86e4b-eec0-448f-a718-01258f452108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894445002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2894445002
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2499146811
Short name T645
Test name
Test status
Simulation time 325985483 ps
CPU time 5.3 seconds
Started Feb 21 02:56:12 PM PST 24
Finished Feb 21 02:56:18 PM PST 24
Peak memory 220800 kb
Host smart-de085b77-f879-41cc-94db-5ae44fdc8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499146811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2499146811
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3661756576
Short name T195
Test name
Test status
Simulation time 142313376 ps
CPU time 6.1 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:23 PM PST 24
Peak memory 214156 kb
Host smart-79637ede-9d75-44c7-aacc-9f4cb040219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661756576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3661756576
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1161627507
Short name T563
Test name
Test status
Simulation time 78086245 ps
CPU time 2.72 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:14 PM PST 24
Peak memory 214984 kb
Host smart-d07fcbb6-3392-4bc6-865a-5c1271bf4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161627507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1161627507
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2825700254
Short name T700
Test name
Test status
Simulation time 54263543 ps
CPU time 3.25 seconds
Started Feb 21 02:56:03 PM PST 24
Finished Feb 21 02:56:08 PM PST 24
Peak memory 209548 kb
Host smart-7099155f-57fe-4a42-a2b7-d9ccf831eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825700254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2825700254
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3108936290
Short name T91
Test name
Test status
Simulation time 694066242 ps
CPU time 10.6 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:28 PM PST 24
Peak memory 231300 kb
Host smart-f119036e-44ab-4ed3-98cd-273eff99b4eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108936290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3108936290
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1619128553
Short name T722
Test name
Test status
Simulation time 38940773 ps
CPU time 2.41 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 207580 kb
Host smart-4a452dda-8b5c-46ba-bd78-42055b5e93d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619128553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1619128553
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1293056506
Short name T326
Test name
Test status
Simulation time 257986987 ps
CPU time 3.38 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 206584 kb
Host smart-9e5755bc-87b3-4114-ae38-90090a22eede
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293056506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1293056506
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2274507429
Short name T418
Test name
Test status
Simulation time 248566994 ps
CPU time 3.69 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 206612 kb
Host smart-42a6c74c-333c-4cd0-a026-ec26c41eeed0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274507429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2274507429
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3793347779
Short name T687
Test name
Test status
Simulation time 791911675 ps
CPU time 6.6 seconds
Started Feb 21 02:56:12 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 208248 kb
Host smart-cb8088b4-e8a7-4ff8-8eae-45887c185861
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793347779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3793347779
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3344475965
Short name T519
Test name
Test status
Simulation time 205845464 ps
CPU time 4.33 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:22 PM PST 24
Peak memory 215616 kb
Host smart-05284bd7-72de-4cdd-af5c-79ecf575be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344475965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3344475965
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1652021172
Short name T505
Test name
Test status
Simulation time 100426281 ps
CPU time 2.45 seconds
Started Feb 21 02:56:03 PM PST 24
Finished Feb 21 02:56:07 PM PST 24
Peak memory 206340 kb
Host smart-c68860de-0bec-4029-aead-e306f2f1421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652021172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1652021172
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.433299509
Short name T247
Test name
Test status
Simulation time 3822015437 ps
CPU time 40.32 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:56 PM PST 24
Peak memory 215280 kb
Host smart-b0473a9b-fa9b-477e-ae43-3d27abfd4e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433299509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.433299509
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3972826406
Short name T530
Test name
Test status
Simulation time 6143076847 ps
CPU time 23.99 seconds
Started Feb 21 02:56:12 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 209036 kb
Host smart-5c632d53-f0f0-47db-a7c9-85a78da235fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972826406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3972826406
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.104915555
Short name T377
Test name
Test status
Simulation time 79458199 ps
CPU time 1.8 seconds
Started Feb 21 02:56:04 PM PST 24
Finished Feb 21 02:56:06 PM PST 24
Peak memory 209904 kb
Host smart-916b0b25-ca9e-4aff-a241-8cc87f34e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104915555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.104915555
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.956035062
Short name T608
Test name
Test status
Simulation time 16691581 ps
CPU time 0.99 seconds
Started Feb 21 02:57:07 PM PST 24
Finished Feb 21 02:57:08 PM PST 24
Peak memory 206216 kb
Host smart-8da4ef37-bc60-441a-ab74-b82c08096b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956035062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.956035062
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3514007502
Short name T642
Test name
Test status
Simulation time 117839692 ps
CPU time 3.32 seconds
Started Feb 21 02:57:06 PM PST 24
Finished Feb 21 02:57:09 PM PST 24
Peak memory 208324 kb
Host smart-4e3d510b-4d12-452d-9c2d-d7b360325a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514007502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3514007502
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3447920339
Short name T889
Test name
Test status
Simulation time 13868448382 ps
CPU time 63.87 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 209624 kb
Host smart-1e712769-1512-46bb-adb9-2eaddf5d71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447920339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3447920339
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1069490493
Short name T801
Test name
Test status
Simulation time 110897738 ps
CPU time 4.8 seconds
Started Feb 21 02:57:13 PM PST 24
Finished Feb 21 02:57:18 PM PST 24
Peak memory 209528 kb
Host smart-9b020845-14bb-4a73-864e-4303dd37fca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069490493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1069490493
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3423841662
Short name T692
Test name
Test status
Simulation time 82843803 ps
CPU time 3.08 seconds
Started Feb 21 02:56:43 PM PST 24
Finished Feb 21 02:56:47 PM PST 24
Peak memory 209828 kb
Host smart-adb3299c-d4ab-4373-bbe8-0a551cfdefb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423841662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3423841662
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.4181469480
Short name T706
Test name
Test status
Simulation time 642007884 ps
CPU time 16.14 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 208308 kb
Host smart-1743c045-6a89-4297-97f7-a655687fa714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181469480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4181469480
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4138142424
Short name T850
Test name
Test status
Simulation time 131065775 ps
CPU time 4.49 seconds
Started Feb 21 02:56:42 PM PST 24
Finished Feb 21 02:56:47 PM PST 24
Peak memory 208544 kb
Host smart-682ca1b3-d78f-4de6-819d-29297d816177
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138142424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4138142424
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1977277005
Short name T704
Test name
Test status
Simulation time 258004234 ps
CPU time 6.39 seconds
Started Feb 21 02:56:39 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 207584 kb
Host smart-748d5aed-d736-465b-8aa5-926d2cf52274
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977277005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1977277005
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1364422603
Short name T858
Test name
Test status
Simulation time 319014993 ps
CPU time 3.69 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:25 PM PST 24
Peak memory 208608 kb
Host smart-ceabfb97-270a-4d50-b91a-aa94c9e9f9ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364422603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1364422603
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.9127549
Short name T635
Test name
Test status
Simulation time 122814683 ps
CPU time 1.75 seconds
Started Feb 21 02:56:43 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 208796 kb
Host smart-88615a9c-d759-486f-8724-4975eb3b7449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9127549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.9127549
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2013867735
Short name T471
Test name
Test status
Simulation time 82951482 ps
CPU time 3.53 seconds
Started Feb 21 02:56:42 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 208248 kb
Host smart-4d24ac7e-60c8-456b-a40d-b680c1516653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013867735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2013867735
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3712573705
Short name T849
Test name
Test status
Simulation time 185150190 ps
CPU time 8.19 seconds
Started Feb 21 02:56:52 PM PST 24
Finished Feb 21 02:57:00 PM PST 24
Peak memory 222532 kb
Host smart-b849766b-fce0-4bda-b1ec-69448e997026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712573705 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3712573705
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2998915781
Short name T205
Test name
Test status
Simulation time 150356424 ps
CPU time 5.77 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 209656 kb
Host smart-02649d5b-5369-4fec-b765-5719f72c4bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998915781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2998915781
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3813046914
Short name T776
Test name
Test status
Simulation time 231760245 ps
CPU time 3.01 seconds
Started Feb 21 02:56:59 PM PST 24
Finished Feb 21 02:57:03 PM PST 24
Peak memory 210396 kb
Host smart-bc09b161-69a2-42d2-b9f2-671df3b1dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813046914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3813046914
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.110843293
Short name T443
Test name
Test status
Simulation time 11387207 ps
CPU time 0.88 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 205860 kb
Host smart-56329e0b-97d2-44ed-ae6d-05cd9878eb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110843293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.110843293
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1588141434
Short name T120
Test name
Test status
Simulation time 291125461 ps
CPU time 3.13 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 215116 kb
Host smart-41d93795-d4a2-4db5-b7b2-d9628f3fcf9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588141434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1588141434
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1343968805
Short name T897
Test name
Test status
Simulation time 203427043 ps
CPU time 5.87 seconds
Started Feb 21 02:56:49 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 218168 kb
Host smart-93a363d8-d8dd-484e-9320-a44b82436b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343968805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1343968805
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3857319191
Short name T499
Test name
Test status
Simulation time 84390794 ps
CPU time 3.93 seconds
Started Feb 21 02:56:54 PM PST 24
Finished Feb 21 02:56:58 PM PST 24
Peak memory 208076 kb
Host smart-cee262c5-4493-4c88-a4eb-32a6448ccaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857319191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3857319191
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.182710915
Short name T611
Test name
Test status
Simulation time 149315990 ps
CPU time 2.74 seconds
Started Feb 21 02:57:09 PM PST 24
Finished Feb 21 02:57:13 PM PST 24
Peak memory 220492 kb
Host smart-e5a8683e-f198-44b3-bbc2-00af5d80e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182710915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.182710915
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2097194307
Short name T842
Test name
Test status
Simulation time 2148252922 ps
CPU time 5.47 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:53 PM PST 24
Peak memory 209024 kb
Host smart-c966fccf-f087-43b2-8287-753d0f06a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097194307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2097194307
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.140032768
Short name T2
Test name
Test status
Simulation time 41796546 ps
CPU time 1.79 seconds
Started Feb 21 02:57:12 PM PST 24
Finished Feb 21 02:57:15 PM PST 24
Peak memory 206524 kb
Host smart-25aaccaa-3039-49fb-828f-255809a35689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140032768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.140032768
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1939340872
Short name T622
Test name
Test status
Simulation time 468830572 ps
CPU time 9.86 seconds
Started Feb 21 02:57:11 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 207900 kb
Host smart-d278289a-d422-443f-a110-a18fb9cddff4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939340872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1939340872
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3266846408
Short name T660
Test name
Test status
Simulation time 245682168 ps
CPU time 6.77 seconds
Started Feb 21 02:56:52 PM PST 24
Finished Feb 21 02:56:59 PM PST 24
Peak memory 207604 kb
Host smart-95ebc0d3-e236-4e53-9db3-b45f76328604
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266846408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3266846408
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3141879523
Short name T453
Test name
Test status
Simulation time 199643212 ps
CPU time 6.02 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:56:54 PM PST 24
Peak memory 207768 kb
Host smart-48cf15e4-8823-48d1-a8ae-a0a172b3ea82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141879523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3141879523
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1308447875
Short name T684
Test name
Test status
Simulation time 329676981 ps
CPU time 2.31 seconds
Started Feb 21 02:56:55 PM PST 24
Finished Feb 21 02:56:58 PM PST 24
Peak memory 206416 kb
Host smart-5b210ddb-6802-47da-85dd-b62edd3a8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308447875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1308447875
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3505174528
Short name T777
Test name
Test status
Simulation time 89244842 ps
CPU time 2.43 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 207660 kb
Host smart-97f81c7c-2204-4ad2-9d36-f7aafa66cbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505174528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3505174528
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2732247348
Short name T286
Test name
Test status
Simulation time 1919552956 ps
CPU time 11.65 seconds
Started Feb 21 02:56:49 PM PST 24
Finished Feb 21 02:57:01 PM PST 24
Peak memory 214440 kb
Host smart-2ab67a70-8cc7-4c01-a9af-85a726088978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732247348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2732247348
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1791760471
Short name T430
Test name
Test status
Simulation time 765211203 ps
CPU time 14.52 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:57:01 PM PST 24
Peak memory 210780 kb
Host smart-9701e31b-5a4e-4904-b65d-53f67b86bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791760471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1791760471
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3263327014
Short name T708
Test name
Test status
Simulation time 51593194 ps
CPU time 3.38 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:50 PM PST 24
Peak memory 208928 kb
Host smart-40afc628-e9d2-4253-be98-e368d50766fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263327014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3263327014
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2145830962
Short name T788
Test name
Test status
Simulation time 163547290 ps
CPU time 2.67 seconds
Started Feb 21 02:57:06 PM PST 24
Finished Feb 21 02:57:09 PM PST 24
Peak memory 208584 kb
Host smart-502b691f-4726-45fe-aeae-ae0cfd5fa42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145830962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2145830962
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2616696598
Short name T340
Test name
Test status
Simulation time 60604556 ps
CPU time 3.74 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:51 PM PST 24
Peak memory 214260 kb
Host smart-9356c478-4c06-4712-a6ed-04ea4855b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616696598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2616696598
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1188217556
Short name T451
Test name
Test status
Simulation time 186315117 ps
CPU time 4.67 seconds
Started Feb 21 02:56:50 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 210216 kb
Host smart-8f31a04a-be2d-42ad-a48d-eebd59b95645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188217556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1188217556
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2065667370
Short name T668
Test name
Test status
Simulation time 1384936644 ps
CPU time 6.94 seconds
Started Feb 21 02:56:59 PM PST 24
Finished Feb 21 02:57:07 PM PST 24
Peak memory 218276 kb
Host smart-93c271aa-5aa9-4ad6-ac5b-259d090dedd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065667370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2065667370
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.547773557
Short name T253
Test name
Test status
Simulation time 116495066 ps
CPU time 4.19 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 207896 kb
Host smart-116866f3-8118-42a2-8bcb-5b4ac802ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547773557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.547773557
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3651568445
Short name T511
Test name
Test status
Simulation time 74181376 ps
CPU time 3.6 seconds
Started Feb 21 02:57:14 PM PST 24
Finished Feb 21 02:57:18 PM PST 24
Peak memory 208656 kb
Host smart-c5c6cf01-35d9-4450-9ae6-13f7fea4b308
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651568445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3651568445
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1466275787
Short name T864
Test name
Test status
Simulation time 193174487 ps
CPU time 7.47 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:56:54 PM PST 24
Peak memory 207608 kb
Host smart-64c8392e-ce87-4cdc-851b-b0710f32c5f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466275787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1466275787
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1866552553
Short name T528
Test name
Test status
Simulation time 118502500 ps
CPU time 3.34 seconds
Started Feb 21 02:56:55 PM PST 24
Finished Feb 21 02:56:59 PM PST 24
Peak memory 208592 kb
Host smart-fc1dfa35-c2ae-4560-8de7-507c48cc0283
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866552553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1866552553
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3963994930
Short name T783
Test name
Test status
Simulation time 1035423115 ps
CPU time 2.81 seconds
Started Feb 21 02:57:13 PM PST 24
Finished Feb 21 02:57:17 PM PST 24
Peak memory 207768 kb
Host smart-0ff69ea6-2058-462c-a148-b338dbe516cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963994930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3963994930
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3335222488
Short name T76
Test name
Test status
Simulation time 63223330 ps
CPU time 3.03 seconds
Started Feb 21 02:56:59 PM PST 24
Finished Feb 21 02:57:03 PM PST 24
Peak memory 207808 kb
Host smart-229934aa-f12d-433c-a9c7-47d713090dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335222488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3335222488
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3937480133
Short name T187
Test name
Test status
Simulation time 24333000816 ps
CPU time 114.52 seconds
Started Feb 21 02:57:14 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 222432 kb
Host smart-a581d2ad-a6f3-4a16-835f-d875d2e7adf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937480133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3937480133
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2162073615
Short name T172
Test name
Test status
Simulation time 1205769885 ps
CPU time 22.85 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:57:12 PM PST 24
Peak memory 222512 kb
Host smart-56e2c6df-da15-4568-aa3a-755e58d46dea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162073615 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2162073615
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1897083583
Short name T484
Test name
Test status
Simulation time 2134258371 ps
CPU time 54.08 seconds
Started Feb 21 02:57:08 PM PST 24
Finished Feb 21 02:58:04 PM PST 24
Peak memory 214232 kb
Host smart-32dcdfca-3526-4e80-808b-c82026547528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897083583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1897083583
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.324136262
Short name T754
Test name
Test status
Simulation time 289627946 ps
CPU time 3.45 seconds
Started Feb 21 02:56:55 PM PST 24
Finished Feb 21 02:56:59 PM PST 24
Peak memory 210648 kb
Host smart-7517d2f1-ed29-4781-81c1-6272a34a9829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324136262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.324136262
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1444234430
Short name T725
Test name
Test status
Simulation time 18559597 ps
CPU time 0.83 seconds
Started Feb 21 02:57:05 PM PST 24
Finished Feb 21 02:57:07 PM PST 24
Peak memory 205928 kb
Host smart-eab12b78-98ac-42f8-9c49-caab8f9bd462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444234430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1444234430
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3323337388
Short name T619
Test name
Test status
Simulation time 3501597245 ps
CPU time 30.02 seconds
Started Feb 21 02:57:14 PM PST 24
Finished Feb 21 02:57:45 PM PST 24
Peak memory 208276 kb
Host smart-53523eb8-f89c-4be3-8622-d28418661f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323337388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3323337388
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3595025591
Short name T245
Test name
Test status
Simulation time 102880868 ps
CPU time 4.24 seconds
Started Feb 21 02:56:48 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 214204 kb
Host smart-9a562715-0676-42ff-b70a-8ebe32643750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595025591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3595025591
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1863496679
Short name T218
Test name
Test status
Simulation time 48582473 ps
CPU time 2.83 seconds
Started Feb 21 02:56:51 PM PST 24
Finished Feb 21 02:56:54 PM PST 24
Peak memory 209848 kb
Host smart-fe676b16-549b-43e9-a118-88237baadc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863496679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1863496679
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3696916346
Short name T891
Test name
Test status
Simulation time 82869214 ps
CPU time 3.1 seconds
Started Feb 21 02:56:58 PM PST 24
Finished Feb 21 02:57:02 PM PST 24
Peak memory 209116 kb
Host smart-d33fe224-873b-4338-a962-e1cbf19f2a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696916346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3696916346
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3988055732
Short name T283
Test name
Test status
Simulation time 644280909 ps
CPU time 4.97 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 208288 kb
Host smart-08e57d73-122e-45af-8469-d10853f38b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988055732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3988055732
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.64038277
Short name T676
Test name
Test status
Simulation time 109692779 ps
CPU time 4.13 seconds
Started Feb 21 02:57:07 PM PST 24
Finished Feb 21 02:57:11 PM PST 24
Peak memory 206612 kb
Host smart-4f1424e6-5be6-4006-871f-99b2ab965ac2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64038277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.64038277
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2737220417
Short name T859
Test name
Test status
Simulation time 477374656 ps
CPU time 5.53 seconds
Started Feb 21 02:56:46 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 206712 kb
Host smart-a89c4890-888c-4ab7-abea-e6b37e05a3dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737220417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2737220417
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.308441674
Short name T680
Test name
Test status
Simulation time 58685192 ps
CPU time 2.95 seconds
Started Feb 21 02:57:10 PM PST 24
Finished Feb 21 02:57:13 PM PST 24
Peak memory 206488 kb
Host smart-0e74ffab-dec6-4531-9184-8b15c9fe0cf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308441674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.308441674
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.333052350
Short name T550
Test name
Test status
Simulation time 70101870 ps
CPU time 3.05 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 208808 kb
Host smart-4a8265de-9ac0-48b9-ad6e-817505d67e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333052350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.333052350
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3398815802
Short name T419
Test name
Test status
Simulation time 35406144 ps
CPU time 2.1 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 206576 kb
Host smart-0cbc26da-fdfd-48ec-aae1-20c57327e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398815802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3398815802
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.280116770
Short name T264
Test name
Test status
Simulation time 392417701 ps
CPU time 4.76 seconds
Started Feb 21 02:56:47 PM PST 24
Finished Feb 21 02:56:52 PM PST 24
Peak memory 207736 kb
Host smart-4ecedc02-1742-4a32-a43b-adcbe9fe3be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280116770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.280116770
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1826306667
Short name T88
Test name
Test status
Simulation time 72247843 ps
CPU time 0.98 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 206008 kb
Host smart-81c077fe-601c-4f4f-932d-508642771458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826306667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1826306667
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3211279886
Short name T14
Test name
Test status
Simulation time 118433887 ps
CPU time 2.15 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 214268 kb
Host smart-82dcef9f-7740-4ad7-8fd0-aaecd0b057f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211279886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3211279886
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2755492368
Short name T848
Test name
Test status
Simulation time 200308059 ps
CPU time 6.11 seconds
Started Feb 21 02:56:55 PM PST 24
Finished Feb 21 02:57:01 PM PST 24
Peak memory 209360 kb
Host smart-4974a070-2fde-4516-9c59-34c05cc3b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755492368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2755492368
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.85887703
Short name T260
Test name
Test status
Simulation time 682825969 ps
CPU time 15.12 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 215892 kb
Host smart-6d82b59d-a671-4847-85eb-777e10a6a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85887703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.85887703
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4042979235
Short name T629
Test name
Test status
Simulation time 38734185 ps
CPU time 2.25 seconds
Started Feb 21 02:56:52 PM PST 24
Finished Feb 21 02:56:54 PM PST 24
Peak memory 219960 kb
Host smart-7e410822-cc7d-4875-9e6d-b0159585ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042979235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4042979235
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2570748924
Short name T638
Test name
Test status
Simulation time 207882655 ps
CPU time 4.23 seconds
Started Feb 21 02:57:07 PM PST 24
Finished Feb 21 02:57:12 PM PST 24
Peak memory 214196 kb
Host smart-7bfb5f09-8a4b-4f50-a028-84ebeb2aef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570748924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2570748924
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.913493709
Short name T495
Test name
Test status
Simulation time 135945106 ps
CPU time 2.4 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 206516 kb
Host smart-4668522d-bbc4-4025-a8a6-99837a08ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913493709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.913493709
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1818249345
Short name T778
Test name
Test status
Simulation time 176098135 ps
CPU time 5.22 seconds
Started Feb 21 02:57:02 PM PST 24
Finished Feb 21 02:57:08 PM PST 24
Peak memory 206400 kb
Host smart-84b59a12-7903-465d-a2a9-36853e29bf2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818249345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1818249345
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2587921080
Short name T357
Test name
Test status
Simulation time 60924009 ps
CPU time 2.71 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 206644 kb
Host smart-5709616a-b196-4bb3-9f96-51952737c319
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587921080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2587921080
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2075401307
Short name T571
Test name
Test status
Simulation time 318229645 ps
CPU time 8.3 seconds
Started Feb 21 02:57:05 PM PST 24
Finished Feb 21 02:57:14 PM PST 24
Peak memory 208412 kb
Host smart-bdd24d1a-3053-4a7f-ab49-03d19faa9365
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075401307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2075401307
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3600887442
Short name T490
Test name
Test status
Simulation time 99966628 ps
CPU time 2.04 seconds
Started Feb 21 02:57:10 PM PST 24
Finished Feb 21 02:57:13 PM PST 24
Peak memory 208036 kb
Host smart-ec81b274-9c7a-47b4-96bb-d430b874d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600887442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3600887442
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2018364581
Short name T746
Test name
Test status
Simulation time 638778266 ps
CPU time 3.08 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 207860 kb
Host smart-a87aff70-f7c4-4d5d-bb19-49772f23f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018364581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2018364581
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1849607770
Short name T149
Test name
Test status
Simulation time 1887051259 ps
CPU time 18.08 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:48 PM PST 24
Peak memory 222540 kb
Host smart-67363fea-7831-467a-a82a-1962dc688b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849607770 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1849607770
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3009341189
Short name T270
Test name
Test status
Simulation time 67155149 ps
CPU time 3.8 seconds
Started Feb 21 02:57:00 PM PST 24
Finished Feb 21 02:57:04 PM PST 24
Peak memory 206936 kb
Host smart-26c0d387-ee78-47b5-aada-96929f8c12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009341189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3009341189
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1659442797
Short name T657
Test name
Test status
Simulation time 150255480 ps
CPU time 1.66 seconds
Started Feb 21 02:56:53 PM PST 24
Finished Feb 21 02:56:55 PM PST 24
Peak memory 209472 kb
Host smart-f08d09b0-3bc5-41c8-b0d6-87c1d32bf1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659442797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1659442797
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.292863345
Short name T723
Test name
Test status
Simulation time 11871293 ps
CPU time 0.9 seconds
Started Feb 21 02:57:17 PM PST 24
Finished Feb 21 02:57:19 PM PST 24
Peak memory 205828 kb
Host smart-9de0a405-7347-467f-954e-4244ef6398e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292863345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.292863345
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1509469552
Short name T279
Test name
Test status
Simulation time 71709534 ps
CPU time 3.79 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 209896 kb
Host smart-889d24ea-2b22-4390-9b8a-a42d2c8bae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509469552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1509469552
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.461862056
Short name T20
Test name
Test status
Simulation time 137331457 ps
CPU time 3.71 seconds
Started Feb 21 02:56:59 PM PST 24
Finished Feb 21 02:57:04 PM PST 24
Peak memory 208928 kb
Host smart-dc654516-413f-4c90-8ce2-99927703b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461862056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.461862056
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.127383823
Short name T301
Test name
Test status
Simulation time 199579817 ps
CPU time 7.59 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 213872 kb
Host smart-9dffac23-ef59-4835-8ebd-320f49b419af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127383823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.127383823
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.420213403
Short name T54
Test name
Test status
Simulation time 382558249 ps
CPU time 3.38 seconds
Started Feb 21 02:57:10 PM PST 24
Finished Feb 21 02:57:14 PM PST 24
Peak memory 208344 kb
Host smart-d6505d57-3858-4ffd-95ad-bf66c0f095fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420213403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.420213403
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2545757225
Short name T198
Test name
Test status
Simulation time 83771706 ps
CPU time 4.28 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 209804 kb
Host smart-933f55e3-ca89-497d-998f-a447cd1c2ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545757225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2545757225
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.605221398
Short name T852
Test name
Test status
Simulation time 1479267580 ps
CPU time 7.9 seconds
Started Feb 21 02:57:11 PM PST 24
Finished Feb 21 02:57:19 PM PST 24
Peak memory 206624 kb
Host smart-3c37e45e-5bab-4a1f-ab5b-4bd615f02f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605221398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.605221398
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1556169892
Short name T454
Test name
Test status
Simulation time 73423500 ps
CPU time 2.87 seconds
Started Feb 21 02:56:49 PM PST 24
Finished Feb 21 02:56:53 PM PST 24
Peak memory 206568 kb
Host smart-edda0021-e5a1-4470-adc6-e4f1e5d325c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556169892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1556169892
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1180552976
Short name T520
Test name
Test status
Simulation time 168695749 ps
CPU time 6.21 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 208380 kb
Host smart-5fd4036c-d50e-4203-bf50-c6701b0c14bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180552976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1180552976
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3026545900
Short name T838
Test name
Test status
Simulation time 1332529194 ps
CPU time 21.01 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208752 kb
Host smart-6d4b5744-92ea-4ad2-b4be-6d46fb00b012
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026545900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3026545900
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2993292633
Short name T439
Test name
Test status
Simulation time 59457483 ps
CPU time 1.97 seconds
Started Feb 21 02:57:06 PM PST 24
Finished Feb 21 02:57:08 PM PST 24
Peak memory 214212 kb
Host smart-a5cab6ec-027a-48c8-ac24-873a8f41dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993292633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2993292633
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3403666650
Short name T786
Test name
Test status
Simulation time 137580423 ps
CPU time 2.93 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 208076 kb
Host smart-13afb971-4e4a-44d0-bf7d-ffccf52e7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403666650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3403666650
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3615478385
Short name T756
Test name
Test status
Simulation time 8202374336 ps
CPU time 162.51 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 03:00:06 PM PST 24
Peak memory 209752 kb
Host smart-676c56da-ff85-49e4-b223-c0f1b687fb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615478385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3615478385
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.119549215
Short name T171
Test name
Test status
Simulation time 242061006 ps
CPU time 7.39 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 218736 kb
Host smart-5c41146f-d1d8-478f-9d4f-78e72be3d049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119549215 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.119549215
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.321927892
Short name T92
Test name
Test status
Simulation time 378797016 ps
CPU time 4.61 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:29 PM PST 24
Peak memory 209056 kb
Host smart-14648dca-4b6b-40cd-982b-da7e2bedd9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321927892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.321927892
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3930524700
Short name T529
Test name
Test status
Simulation time 603596120 ps
CPU time 3.05 seconds
Started Feb 21 02:57:06 PM PST 24
Finished Feb 21 02:57:09 PM PST 24
Peak memory 210304 kb
Host smart-9b4a6aa4-3b79-40da-871e-fa2dffa6bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930524700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3930524700
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.512823358
Short name T482
Test name
Test status
Simulation time 47805328 ps
CPU time 0.86 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 205888 kb
Host smart-deb442f9-c95f-4274-95c8-59e2d0591b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512823358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.512823358
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3699497324
Short name T574
Test name
Test status
Simulation time 59288301 ps
CPU time 1.53 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 214244 kb
Host smart-cbee587e-6ec7-4a68-9c33-0ded18f351e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699497324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3699497324
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1313759912
Short name T562
Test name
Test status
Simulation time 199513321 ps
CPU time 2.39 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 208468 kb
Host smart-1f0b4edd-2111-4d31-9d7b-e0a3fe2cc7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313759912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1313759912
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1300159761
Short name T837
Test name
Test status
Simulation time 349198195 ps
CPU time 8.99 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 210832 kb
Host smart-48fa8285-a29a-4d17-8ab4-ae619c4127ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300159761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1300159761
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.998821936
Short name T61
Test name
Test status
Simulation time 223452347 ps
CPU time 5.17 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:25 PM PST 24
Peak memory 209628 kb
Host smart-ebc6f4bf-3691-42d2-b459-2d948b37825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998821936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.998821936
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.196998274
Short name T554
Test name
Test status
Simulation time 1522976644 ps
CPU time 15.48 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 218192 kb
Host smart-9e94266b-9930-4f0e-9459-845a9166cdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196998274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.196998274
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2607773132
Short name T428
Test name
Test status
Simulation time 41975991 ps
CPU time 1.77 seconds
Started Feb 21 02:57:17 PM PST 24
Finished Feb 21 02:57:19 PM PST 24
Peak memory 206484 kb
Host smart-09f53ee1-5cf0-4f9f-bf42-eff596ad1a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607773132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2607773132
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.590714005
Short name T630
Test name
Test status
Simulation time 35814080 ps
CPU time 2.49 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 208372 kb
Host smart-122d6ea1-5d95-4daf-b1b9-3414f672bf88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590714005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.590714005
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.224777546
Short name T663
Test name
Test status
Simulation time 82650195 ps
CPU time 2.59 seconds
Started Feb 21 02:57:17 PM PST 24
Finished Feb 21 02:57:20 PM PST 24
Peak memory 207140 kb
Host smart-4f3be178-a297-4fc4-9e46-a8ebfa664206
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224777546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.224777546
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3376637432
Short name T807
Test name
Test status
Simulation time 878350316 ps
CPU time 7.76 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 208332 kb
Host smart-dc0bd289-7f88-44ad-af75-03ee8ba4f8e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376637432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3376637432
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2862731431
Short name T403
Test name
Test status
Simulation time 441781612 ps
CPU time 9.47 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208940 kb
Host smart-21daa65c-4437-4d4e-8d57-c1c247b02eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862731431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2862731431
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3833220923
Short name T667
Test name
Test status
Simulation time 228880912 ps
CPU time 2.9 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 208168 kb
Host smart-63233de4-44d1-4c70-a890-b64b33e14cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833220923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3833220923
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1117858917
Short name T429
Test name
Test status
Simulation time 8984376697 ps
CPU time 88 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 222472 kb
Host smart-4caf610b-86e2-46c8-955f-17707bf2336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117858917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1117858917
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.919188368
Short name T641
Test name
Test status
Simulation time 288893911 ps
CPU time 2.5 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 209904 kb
Host smart-391bafbd-85a1-4371-b559-3efd70825f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919188368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.919188368
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.6727224
Short name T640
Test name
Test status
Simulation time 54536848 ps
CPU time 0.79 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:20 PM PST 24
Peak memory 205904 kb
Host smart-96ea1549-b1cd-4216-baf1-0a678ef83fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6727224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.6727224
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.123337116
Short name T468
Test name
Test status
Simulation time 292768941 ps
CPU time 3.96 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 217360 kb
Host smart-e705e8a7-7e15-4970-be92-9838f1117c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123337116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.123337116
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.376640982
Short name T232
Test name
Test status
Simulation time 592350997 ps
CPU time 6.74 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 207648 kb
Host smart-6717381a-e5bc-43eb-9ea7-dea89ce34d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376640982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.376640982
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2154324495
Short name T566
Test name
Test status
Simulation time 238408949 ps
CPU time 5.58 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:38 PM PST 24
Peak memory 208912 kb
Host smart-74ee4c08-53e4-4951-ae63-aec41c3a51be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154324495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2154324495
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.146391547
Short name T237
Test name
Test status
Simulation time 3459803923 ps
CPU time 40.31 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:58:11 PM PST 24
Peak memory 217596 kb
Host smart-96560082-914f-4508-8f07-dc754951fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146391547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.146391547
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3678556225
Short name T767
Test name
Test status
Simulation time 60537476 ps
CPU time 3.12 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 216036 kb
Host smart-2714fe9e-7a6c-4c26-89c2-e3c242f65f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678556225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3678556225
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.4220991962
Short name T863
Test name
Test status
Simulation time 366097587 ps
CPU time 4.88 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 207432 kb
Host smart-e1a967b5-4cc1-46b8-a71d-45070aa9444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220991962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4220991962
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3538432914
Short name T901
Test name
Test status
Simulation time 367948571 ps
CPU time 4.36 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 208368 kb
Host smart-45bd2e6d-ccc8-4c6e-ad6c-0613cd333209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538432914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3538432914
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2740268455
Short name T844
Test name
Test status
Simulation time 1042944119 ps
CPU time 6.96 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 207724 kb
Host smart-b8b2decc-e3d8-40ed-ac11-d38b53ec115b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740268455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2740268455
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3525850881
Short name T203
Test name
Test status
Simulation time 48058331 ps
CPU time 2.78 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 208504 kb
Host smart-38fe74f5-20f9-4b2a-9108-1e15f39787ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525850881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3525850881
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2030032793
Short name T72
Test name
Test status
Simulation time 69163490 ps
CPU time 3.45 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 208004 kb
Host smart-91e5e5cb-b088-4fab-8ee2-9e70504b6b99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030032793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2030032793
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3584185182
Short name T600
Test name
Test status
Simulation time 196366647 ps
CPU time 2.23 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 208608 kb
Host smart-ddd12bb0-689a-4b8f-9444-52c4d635a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584185182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3584185182
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3946520
Short name T115
Test name
Test status
Simulation time 226344516 ps
CPU time 6.78 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 206332 kb
Host smart-c3461d25-b251-4609-97ea-03e4089f79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3946520
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1777460724
Short name T887
Test name
Test status
Simulation time 1268182531 ps
CPU time 13.63 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:38 PM PST 24
Peak memory 206536 kb
Host smart-e337760f-425c-4624-9999-d3beb486211f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777460724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1777460724
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3293807013
Short name T113
Test name
Test status
Simulation time 1820477756 ps
CPU time 10.5 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 222324 kb
Host smart-1c6ff4ef-377a-44c1-820a-b74e23481e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293807013 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3293807013
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2433789009
Short name T396
Test name
Test status
Simulation time 1170797162 ps
CPU time 31.2 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 218156 kb
Host smart-8086d095-c944-4bdc-b268-5d7b0568e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433789009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2433789009
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3243917114
Short name T494
Test name
Test status
Simulation time 139467703 ps
CPU time 1.94 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 209812 kb
Host smart-744b5e53-5461-48f1-bea7-4035331f9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243917114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3243917114
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3125050811
Short name T592
Test name
Test status
Simulation time 24256230 ps
CPU time 0.81 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 205912 kb
Host smart-719c8fc2-7d05-4f03-bdd9-80fbcf9ad509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125050811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3125050811
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3520166413
Short name T389
Test name
Test status
Simulation time 1127582011 ps
CPU time 58.12 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 214228 kb
Host smart-ae776fc1-960e-4179-a01a-82244a55d007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520166413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3520166413
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2208664169
Short name T628
Test name
Test status
Simulation time 546519283 ps
CPU time 3.46 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 208532 kb
Host smart-e159ceda-5e1a-4eb2-a7e9-2357a3ca7622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208664169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2208664169
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2958887400
Short name T66
Test name
Test status
Simulation time 46487807 ps
CPU time 1.97 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 207128 kb
Host smart-8f6cb1a8-52f3-4b2f-b9dd-058dfcfe78e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958887400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2958887400
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2118676087
Short name T524
Test name
Test status
Simulation time 182857382 ps
CPU time 5.44 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 220868 kb
Host smart-b25b7e0d-467f-4f10-80df-6a4e9821aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118676087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2118676087
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1216298945
Short name T865
Test name
Test status
Simulation time 98988038 ps
CPU time 3.6 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 219996 kb
Host smart-c255913a-e1ef-44e6-b5e4-f37586594e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216298945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1216298945
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.870384460
Short name T230
Test name
Test status
Simulation time 138362353 ps
CPU time 3.77 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 214276 kb
Host smart-4d826027-2a6e-4e57-a5ad-999a709b5224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870384460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.870384460
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3182791348
Short name T227
Test name
Test status
Simulation time 30796834 ps
CPU time 2.25 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 206548 kb
Host smart-a1e997a2-9f56-4e4f-9c86-48511eb43b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182791348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3182791348
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3042416287
Short name T797
Test name
Test status
Simulation time 112880945 ps
CPU time 3.9 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206652 kb
Host smart-f300b7e0-78f0-401b-91d5-52ba713a8d0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042416287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3042416287
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1789273939
Short name T304
Test name
Test status
Simulation time 89540521 ps
CPU time 2.56 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 208440 kb
Host smart-9b466ceb-4e63-4439-bd76-059ba893b7cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789273939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1789273939
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1569943870
Short name T582
Test name
Test status
Simulation time 1554401113 ps
CPU time 11.44 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 206704 kb
Host smart-cff1410b-35dd-4926-ab9b-e2fe4e13f7c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569943870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1569943870
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1175878702
Short name T540
Test name
Test status
Simulation time 31440219 ps
CPU time 2 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 220388 kb
Host smart-ce6e8eee-b6e8-4261-80f9-22915f6a2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175878702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1175878702
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2322283557
Short name T387
Test name
Test status
Simulation time 1228783466 ps
CPU time 30.48 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:58 PM PST 24
Peak memory 207952 kb
Host smart-89eca286-f5f7-4e21-a8d4-75ac14511f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322283557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2322283557
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3927440062
Short name T231
Test name
Test status
Simulation time 827838834 ps
CPU time 20.88 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 222296 kb
Host smart-12799530-6ae7-48fb-95d4-43123eed34a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927440062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3927440062
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2738959352
Short name T173
Test name
Test status
Simulation time 984080772 ps
CPU time 16.3 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 220240 kb
Host smart-b90d526b-7651-49f5-8709-4f0e2d2109e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738959352 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2738959352
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1317227080
Short name T812
Test name
Test status
Simulation time 421687509 ps
CPU time 4.71 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:29 PM PST 24
Peak memory 206992 kb
Host smart-b9be913d-929f-418d-bfb5-7a4b40eef797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317227080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1317227080
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.73198513
Short name T830
Test name
Test status
Simulation time 653814282 ps
CPU time 3.93 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 210100 kb
Host smart-51e9ff7e-7d94-4d3f-bd5f-691c558a0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73198513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.73198513
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.95793952
Short name T500
Test name
Test status
Simulation time 29115242 ps
CPU time 0.96 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 205960 kb
Host smart-338ff513-59a5-4397-9091-9637ee888896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95793952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.95793952
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3271166068
Short name T119
Test name
Test status
Simulation time 32895507 ps
CPU time 2.61 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 214960 kb
Host smart-52373c9e-ac67-4549-aab6-9784680e1cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271166068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3271166068
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1694695716
Short name T501
Test name
Test status
Simulation time 588156400 ps
CPU time 3.07 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 207548 kb
Host smart-86e9aca1-1e84-4482-a410-cbffa331cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694695716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1694695716
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4288095530
Short name T564
Test name
Test status
Simulation time 336243859 ps
CPU time 2.81 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 214228 kb
Host smart-3e712a5e-759f-464d-952b-58f4ffc6f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288095530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4288095530
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4009561407
Short name T808
Test name
Test status
Simulation time 598364881 ps
CPU time 4.1 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:29 PM PST 24
Peak memory 218020 kb
Host smart-800d3a63-1936-4df0-ae2d-d0c9e6a049af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009561407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4009561407
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1763542559
Short name T595
Test name
Test status
Simulation time 109006095 ps
CPU time 3.41 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 208152 kb
Host smart-8947b015-2398-4ae1-b4f9-aec4d133e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763542559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1763542559
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2729805504
Short name T442
Test name
Test status
Simulation time 1032456452 ps
CPU time 6.04 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 206536 kb
Host smart-e3691f0b-81f3-4da1-9d3e-2ce12d63266f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729805504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2729805504
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.937511308
Short name T586
Test name
Test status
Simulation time 137760852 ps
CPU time 1.85 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 206544 kb
Host smart-d1145d7f-6c23-47b2-9a49-a0b2a5204860
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937511308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.937511308
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2713233798
Short name T726
Test name
Test status
Simulation time 639714875 ps
CPU time 10.33 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208284 kb
Host smart-9ce13700-e600-47c3-85db-95d572d277b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713233798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2713233798
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_smoke.476600978
Short name T535
Test name
Test status
Simulation time 44255800 ps
CPU time 1.82 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 206480 kb
Host smart-9f8069c0-3eee-45ca-944d-2d8efbf76664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476600978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.476600978
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.586727401
Short name T881
Test name
Test status
Simulation time 9317436894 ps
CPU time 59.56 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:58:29 PM PST 24
Peak memory 216744 kb
Host smart-7fb96394-7364-429d-b0a5-1ac25b71b038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586727401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.586727401
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3699486408
Short name T174
Test name
Test status
Simulation time 211228870 ps
CPU time 8.39 seconds
Started Feb 21 02:57:16 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 222576 kb
Host smart-a4167e19-577d-45ca-880b-cb3d8f132bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699486408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3699486408
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.648174262
Short name T796
Test name
Test status
Simulation time 126662046 ps
CPU time 2.56 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 208020 kb
Host smart-4b19c68d-7b1a-41a9-ad44-68e382f45adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648174262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.648174262
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.386490589
Short name T364
Test name
Test status
Simulation time 60793810 ps
CPU time 2.21 seconds
Started Feb 21 02:57:48 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 209980 kb
Host smart-60b2088f-0a47-48d0-8aa8-98fdfb9004c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386490589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.386490589
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1681117716
Short name T477
Test name
Test status
Simulation time 23210106 ps
CPU time 0.79 seconds
Started Feb 21 02:56:01 PM PST 24
Finished Feb 21 02:56:02 PM PST 24
Peak memory 205920 kb
Host smart-d5cd0c33-a36c-41f2-9da3-7292f6509258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681117716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1681117716
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2688341822
Short name T795
Test name
Test status
Simulation time 94944083 ps
CPU time 2.39 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:13 PM PST 24
Peak memory 222324 kb
Host smart-02f23bf7-6c9d-40b4-9f45-cdf033c57130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688341822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2688341822
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2164025051
Short name T525
Test name
Test status
Simulation time 52899475 ps
CPU time 3.17 seconds
Started Feb 21 02:56:09 PM PST 24
Finished Feb 21 02:56:12 PM PST 24
Peak memory 209616 kb
Host smart-6bdb929b-be68-4c60-874e-4ddd39ecde41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164025051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2164025051
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1756976990
Short name T616
Test name
Test status
Simulation time 22078954 ps
CPU time 1.76 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 209324 kb
Host smart-e041aae9-35a2-4d35-90dd-b43e8eac6a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756976990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1756976990
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3420892286
Short name T58
Test name
Test status
Simulation time 205532382 ps
CPU time 3.07 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 209672 kb
Host smart-bf15b8b5-3581-4961-b7c1-6fb44a9a7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420892286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3420892286
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3912352762
Short name T818
Test name
Test status
Simulation time 510777175 ps
CPU time 11.95 seconds
Started Feb 21 02:56:09 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 207784 kb
Host smart-2c9f007a-34c7-435c-9b3b-d5b5b3e0fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912352762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3912352762
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.750696736
Short name T4
Test name
Test status
Simulation time 2345368377 ps
CPU time 34.31 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 235688 kb
Host smart-d8941844-904a-4da0-be51-c57df7028f0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750696736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.750696736
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4273517925
Short name T184
Test name
Test status
Simulation time 655301596 ps
CPU time 5.42 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:22 PM PST 24
Peak memory 207356 kb
Host smart-3a29f4c1-b138-44d6-8f4f-e1e1cf3b1d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273517925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4273517925
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3083028299
Short name T534
Test name
Test status
Simulation time 143149798 ps
CPU time 2.47 seconds
Started Feb 21 02:56:30 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 207376 kb
Host smart-eaaf02a4-8f84-40e9-afea-51baace1704d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083028299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3083028299
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2041785447
Short name T806
Test name
Test status
Simulation time 173797684 ps
CPU time 2.67 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:18 PM PST 24
Peak memory 208576 kb
Host smart-fd60a53c-9f56-47a0-9982-6b351e89c662
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041785447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2041785447
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3570317748
Short name T93
Test name
Test status
Simulation time 66860796 ps
CPU time 2.55 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:17 PM PST 24
Peak memory 208536 kb
Host smart-1314c750-7ece-4959-a808-19b44a282293
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570317748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3570317748
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2526495352
Short name T325
Test name
Test status
Simulation time 55902020 ps
CPU time 2.7 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:16 PM PST 24
Peak memory 209372 kb
Host smart-1fef3d10-05e4-454f-bbc6-f44ea35947f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526495352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2526495352
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3081555274
Short name T636
Test name
Test status
Simulation time 108101983 ps
CPU time 4.28 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:15 PM PST 24
Peak memory 208400 kb
Host smart-344a2ffa-3324-4fb0-9cbc-006e53dbd695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081555274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3081555274
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1140032275
Short name T752
Test name
Test status
Simulation time 5109154325 ps
CPU time 71.96 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 217880 kb
Host smart-d76cdfb1-402c-4c95-9d9d-32b4f2a0b219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140032275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1140032275
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.822094272
Short name T426
Test name
Test status
Simulation time 658091281 ps
CPU time 17.58 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:31 PM PST 24
Peak memory 208360 kb
Host smart-b35bc6c7-cf5c-4629-9ff0-dbccbf87d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822094272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.822094272
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.974942829
Short name T433
Test name
Test status
Simulation time 39308423 ps
CPU time 0.91 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:20 PM PST 24
Peak memory 205884 kb
Host smart-537baa57-dcf0-4299-af60-9ece4095a744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974942829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.974942829
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.13071940
Short name T393
Test name
Test status
Simulation time 372599944 ps
CPU time 11.01 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 222300 kb
Host smart-d15fb261-f223-4bad-acc9-a9682759d6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13071940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.13071940
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3863885085
Short name T573
Test name
Test status
Simulation time 169582302 ps
CPU time 2.63 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 208132 kb
Host smart-3c7a1c50-5d6c-4204-8854-1af430fd0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863885085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3863885085
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1468124973
Short name T63
Test name
Test status
Simulation time 60430198 ps
CPU time 2.34 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 207248 kb
Host smart-814b5b5e-718a-46c5-96b0-7dc01e768817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468124973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1468124973
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2704113650
Short name T180
Test name
Test status
Simulation time 166094787 ps
CPU time 3.15 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 208432 kb
Host smart-a670854f-f1da-41c9-b053-11f5fcf07bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704113650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2704113650
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2968898594
Short name T274
Test name
Test status
Simulation time 1619066014 ps
CPU time 11.7 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 211592 kb
Host smart-6799176a-aeb1-4fad-846d-4c325758ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968898594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2968898594
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.202596411
Short name T737
Test name
Test status
Simulation time 103970675 ps
CPU time 3.01 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 209252 kb
Host smart-e7715169-1acf-494d-9768-c0945d350f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202596411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.202596411
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2110749114
Short name T873
Test name
Test status
Simulation time 2250509406 ps
CPU time 13.1 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 209208 kb
Host smart-88baa981-c490-47da-8bd8-0799e97acdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110749114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2110749114
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.256918749
Short name T765
Test name
Test status
Simulation time 196737106 ps
CPU time 3.28 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:38 PM PST 24
Peak memory 207176 kb
Host smart-7e08812b-84f0-4965-a986-2301f095fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256918749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.256918749
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1795030593
Short name T465
Test name
Test status
Simulation time 165558232 ps
CPU time 2.25 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206560 kb
Host smart-b88d99a5-8177-4a80-9438-1c933839902d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795030593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1795030593
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3805945531
Short name T251
Test name
Test status
Simulation time 254526300 ps
CPU time 3.52 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206440 kb
Host smart-07da8b40-44c1-412c-954d-293075475402
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805945531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3805945531
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2406112143
Short name T481
Test name
Test status
Simulation time 815858606 ps
CPU time 3.66 seconds
Started Feb 21 02:57:22 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 208688 kb
Host smart-ba1185f2-5224-414f-9c4b-c5a7fd2dea19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406112143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2406112143
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3326719602
Short name T552
Test name
Test status
Simulation time 54369730 ps
CPU time 2.18 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 214188 kb
Host smart-bfe8cd70-af0e-4f41-a32f-9b07e4bdfc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326719602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3326719602
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1928144133
Short name T649
Test name
Test status
Simulation time 128487779 ps
CPU time 2.39 seconds
Started Feb 21 02:57:17 PM PST 24
Finished Feb 21 02:57:20 PM PST 24
Peak memory 206368 kb
Host smart-5f4bbd7b-64a4-479c-91f8-057d00c2d5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928144133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1928144133
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3175279510
Short name T799
Test name
Test status
Simulation time 313150433 ps
CPU time 3.65 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 207856 kb
Host smart-dc4150a3-b661-46c0-a518-1878e4e19320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175279510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3175279510
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3047476632
Short name T109
Test name
Test status
Simulation time 316979879 ps
CPU time 5.46 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 210344 kb
Host smart-d5ae1918-ca94-45f1-b4ff-c2d9a0df1ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047476632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3047476632
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.352424920
Short name T697
Test name
Test status
Simulation time 10886575 ps
CPU time 0.71 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 205828 kb
Host smart-7500059d-0e52-46b0-9159-7581cfb7e728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352424920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.352424920
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1090650696
Short name T643
Test name
Test status
Simulation time 129156544 ps
CPU time 2.73 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 214196 kb
Host smart-837ccc1c-c292-4c37-b8e3-9086a5dd7c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090650696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1090650696
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2623055961
Short name T696
Test name
Test status
Simulation time 190510133 ps
CPU time 4.7 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 221328 kb
Host smart-cfdc04f5-45b7-4a29-a79c-1de0caa86ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623055961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2623055961
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3605210581
Short name T233
Test name
Test status
Simulation time 34953540 ps
CPU time 2.18 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 208404 kb
Host smart-6c842391-16cd-4344-90db-32a68b03bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605210581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3605210581
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2916538580
Short name T503
Test name
Test status
Simulation time 2382661626 ps
CPU time 26.22 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:54 PM PST 24
Peak memory 208832 kb
Host smart-27db2ca6-a7b6-496d-95b5-5ba169bf2858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916538580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2916538580
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1178426679
Short name T240
Test name
Test status
Simulation time 4812744353 ps
CPU time 40.52 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 220676 kb
Host smart-34fc58fa-ec56-4f66-86a8-858141fb6580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178426679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1178426679
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1478704171
Short name T679
Test name
Test status
Simulation time 419882689 ps
CPU time 2.51 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 206132 kb
Host smart-f58e0372-82ca-4234-8877-9bee40693ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478704171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1478704171
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3069116304
Short name T653
Test name
Test status
Simulation time 1720049582 ps
CPU time 10.48 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 209452 kb
Host smart-2a9780d5-e312-4420-b5b7-486ed640d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069116304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3069116304
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.826403977
Short name T647
Test name
Test status
Simulation time 1657406590 ps
CPU time 7.4 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 208060 kb
Host smart-a4c621d6-d4ab-4627-9c9e-9760592ed5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826403977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.826403977
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2720383580
Short name T353
Test name
Test status
Simulation time 478943342 ps
CPU time 6.06 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 206668 kb
Host smart-dfc32c58-b739-4945-8b73-a714cdf77455
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720383580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2720383580
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2216982451
Short name T13
Test name
Test status
Simulation time 54391748 ps
CPU time 2.92 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206440 kb
Host smart-52d37431-959f-4a73-9aeb-a8f27c209c6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216982451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2216982451
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3516717656
Short name T853
Test name
Test status
Simulation time 407197275 ps
CPU time 4.06 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 208240 kb
Host smart-663e776c-be7b-4299-a2dd-9d65d474757d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516717656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3516717656
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1464807175
Short name T130
Test name
Test status
Simulation time 53523550 ps
CPU time 3.06 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 215328 kb
Host smart-372e8ece-5f54-4fec-9b1c-de5d87cbba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464807175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1464807175
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4163484667
Short name T739
Test name
Test status
Simulation time 263038080 ps
CPU time 2.97 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 208104 kb
Host smart-ebdce557-928b-4962-892f-90d594d47518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163484667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4163484667
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1160832851
Short name T75
Test name
Test status
Simulation time 97106381 ps
CPU time 4.8 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 209724 kb
Host smart-16d6fb8a-f9fb-44fe-af4d-ef44f9977be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160832851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1160832851
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2620257037
Short name T792
Test name
Test status
Simulation time 2296548162 ps
CPU time 8.47 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 210480 kb
Host smart-e20f2923-5afc-4f6d-abfd-cc7e6162b874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620257037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2620257037
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3516217379
Short name T733
Test name
Test status
Simulation time 214666582 ps
CPU time 0.87 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 205948 kb
Host smart-3ff4c7d6-4d94-406a-82d7-19fb1be181aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516217379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3516217379
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3518324490
Short name T633
Test name
Test status
Simulation time 1408727069 ps
CPU time 41.15 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:58:15 PM PST 24
Peak memory 222304 kb
Host smart-15a4b45a-9451-49b3-b772-5bb9a3a27ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518324490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3518324490
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4175402873
Short name T444
Test name
Test status
Simulation time 1022729414 ps
CPU time 6.43 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 209188 kb
Host smart-088f25ed-d76e-4c3e-892d-16d24df352f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175402873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4175402873
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.650770359
Short name T358
Test name
Test status
Simulation time 58343747 ps
CPU time 3.25 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 208364 kb
Host smart-9ec79c6a-a628-401d-b987-ab871c11dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650770359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.650770359
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.441237004
Short name T275
Test name
Test status
Simulation time 83683520 ps
CPU time 4.34 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 211148 kb
Host smart-7fbf75db-ef4a-48ec-b783-b69bf9af0f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441237004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.441237004
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.4160711747
Short name T50
Test name
Test status
Simulation time 70619867 ps
CPU time 4.1 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 219872 kb
Host smart-ed8186d8-e70c-43ed-a1d9-50f0b024a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160711747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4160711747
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3905931958
Short name T343
Test name
Test status
Simulation time 46301688 ps
CPU time 2.77 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 209788 kb
Host smart-beaf4f0a-3aa7-4d14-b501-d6dfef61354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905931958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3905931958
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1039293712
Short name T527
Test name
Test status
Simulation time 1987575909 ps
CPU time 6.4 seconds
Started Feb 21 02:57:32 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 208628 kb
Host smart-8b506961-6396-4f4e-8c26-a8812abaea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039293712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1039293712
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.640638847
Short name T814
Test name
Test status
Simulation time 75736390 ps
CPU time 2.93 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206524 kb
Host smart-154e43cc-0c46-410d-91b7-4207784a55bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640638847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.640638847
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.602896047
Short name T413
Test name
Test status
Simulation time 72408107 ps
CPU time 1.92 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 206332 kb
Host smart-03b4767b-9ded-4aca-9ab6-934294ec42f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602896047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.602896047
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1066742571
Short name T899
Test name
Test status
Simulation time 252046333 ps
CPU time 3.24 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 206348 kb
Host smart-c640ed98-f086-489e-bdfe-a217bb7b2ef1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066742571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1066742571
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3883961724
Short name T648
Test name
Test status
Simulation time 439924872 ps
CPU time 5.25 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:38 PM PST 24
Peak memory 206196 kb
Host smart-abe2b3c1-d1a0-4968-81c1-eff1dc37e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883961724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3883961724
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1713511311
Short name T41
Test name
Test status
Simulation time 1573381837 ps
CPU time 22.71 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:56 PM PST 24
Peak memory 217000 kb
Host smart-0dd4525d-6e6e-4b2d-aa4e-c75e49708165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713511311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1713511311
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3899666492
Short name T181
Test name
Test status
Simulation time 43587383 ps
CPU time 3.15 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:23 PM PST 24
Peak memory 209968 kb
Host smart-a3f184bd-e2e5-482e-b04b-603aae09d7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899666492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3899666492
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3734263155
Short name T29
Test name
Test status
Simulation time 172585106 ps
CPU time 1.7 seconds
Started Feb 21 02:57:31 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 209940 kb
Host smart-926ca087-c8ee-4427-a29d-2c38a615756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734263155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3734263155
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1197255177
Short name T523
Test name
Test status
Simulation time 48813118 ps
CPU time 0.89 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 206040 kb
Host smart-849efd47-a713-45b8-b7f9-c1e28c2928f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197255177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1197255177
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2793366262
Short name T104
Test name
Test status
Simulation time 90644693 ps
CPU time 3.4 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 214224 kb
Host smart-7f4eaaba-7d8d-46a6-9406-b284b00738fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793366262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2793366262
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2858470863
Short name T24
Test name
Test status
Simulation time 103371514 ps
CPU time 3.9 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 214180 kb
Host smart-128cb6b1-b099-435f-8c09-41cb50abff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858470863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2858470863
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2469677572
Short name T883
Test name
Test status
Simulation time 69490011 ps
CPU time 2.65 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 206928 kb
Host smart-ed4ce427-805b-4ab2-a146-2ffd8215244d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469677572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2469677572
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3365200200
Short name T290
Test name
Test status
Simulation time 263134943 ps
CPU time 3.21 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:29 PM PST 24
Peak memory 209304 kb
Host smart-9ae198bc-611b-4986-9b21-04e5e9e50b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365200200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3365200200
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4236496211
Short name T235
Test name
Test status
Simulation time 268363636 ps
CPU time 7.99 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 210616 kb
Host smart-96ee338a-df62-45d1-b9b9-5d82aefff506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236496211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4236496211
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2213158828
Short name T401
Test name
Test status
Simulation time 99277670 ps
CPU time 4.99 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 220040 kb
Host smart-51eba19a-c5b5-4823-96a6-1176e5e023d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213158828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2213158828
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2750516469
Short name T770
Test name
Test status
Simulation time 176511426 ps
CPU time 6.61 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 208808 kb
Host smart-e747c6b2-1ecd-468c-9257-1153b55fb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750516469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2750516469
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.980090662
Short name T878
Test name
Test status
Simulation time 20932104 ps
CPU time 1.74 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 206368 kb
Host smart-f25fc7a6-9b9d-46b4-baa3-04832a7051f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980090662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.980090662
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3103015924
Short name T544
Test name
Test status
Simulation time 1833833614 ps
CPU time 45.99 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 208208 kb
Host smart-72c5e550-2331-4b78-b683-55681f96de8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103015924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3103015924
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.316169281
Short name T502
Test name
Test status
Simulation time 2202869016 ps
CPU time 16.18 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 207708 kb
Host smart-fbf64daf-0b4f-4f83-b3cb-9d5a95d65325
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316169281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.316169281
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3493366821
Short name T868
Test name
Test status
Simulation time 33354376 ps
CPU time 2.2 seconds
Started Feb 21 02:57:22 PM PST 24
Finished Feb 21 02:57:25 PM PST 24
Peak memory 209348 kb
Host smart-09462733-ca13-4957-9d94-82cacefc8eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493366821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3493366821
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.379644154
Short name T584
Test name
Test status
Simulation time 594298742 ps
CPU time 4.31 seconds
Started Feb 21 02:57:19 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 206428 kb
Host smart-13b01e5a-f570-4110-a2af-5edd32318f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379644154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.379644154
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1817987655
Short name T831
Test name
Test status
Simulation time 465661155 ps
CPU time 20.87 seconds
Started Feb 21 02:57:18 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 222388 kb
Host smart-246f1f51-67d4-40c6-8a99-e4feb73eff64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817987655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1817987655
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.623414543
Short name T51
Test name
Test status
Simulation time 252507179 ps
CPU time 9.55 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 219496 kb
Host smart-61ee1985-6d3b-4575-b39f-c1e6de9b0a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623414543 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.623414543
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3486649228
Short name T463
Test name
Test status
Simulation time 177460905 ps
CPU time 5.35 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 208392 kb
Host smart-7b3486e1-507f-46a2-98aa-3a80e95e8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486649228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3486649228
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1790766545
Short name T169
Test name
Test status
Simulation time 4000830871 ps
CPU time 18.49 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:43 PM PST 24
Peak memory 210820 kb
Host smart-a1a6cd7e-197d-4134-a1a4-9a602ac66a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790766545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1790766545
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3798499901
Short name T662
Test name
Test status
Simulation time 16297873 ps
CPU time 0.71 seconds
Started Feb 21 02:57:21 PM PST 24
Finished Feb 21 02:57:22 PM PST 24
Peak memory 205832 kb
Host smart-799f1b22-4a1b-4467-82b5-a0cdbb33cf47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798499901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3798499901
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1144646898
Short name T8
Test name
Test status
Simulation time 88859455 ps
CPU time 2.89 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 217284 kb
Host smart-d1ad19cc-d692-43ad-a7b0-df8009a01e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144646898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1144646898
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1141079908
Short name T826
Test name
Test status
Simulation time 92916073 ps
CPU time 2.69 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 208776 kb
Host smart-5494d178-a4b1-49da-98c6-14264d480f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141079908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1141079908
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2926837343
Short name T335
Test name
Test status
Simulation time 55134397 ps
CPU time 3.37 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 210932 kb
Host smart-6acb1eba-3bce-4d7c-ad84-be210b09b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926837343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2926837343
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1479564946
Short name T219
Test name
Test status
Simulation time 29997378 ps
CPU time 2.42 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 207560 kb
Host smart-cfd8cbc1-d05c-4a46-b312-81c2ef9cd1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479564946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1479564946
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2521743632
Short name T402
Test name
Test status
Simulation time 681167348 ps
CPU time 7.4 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 209592 kb
Host smart-01bb36be-6d30-4e45-9fee-dcd21009fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521743632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2521743632
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3683389453
Short name T305
Test name
Test status
Simulation time 925933558 ps
CPU time 3.62 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 206500 kb
Host smart-a02d90c6-f08b-47f1-b73a-581e5e5655f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683389453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3683389453
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2545848670
Short name T498
Test name
Test status
Simulation time 440035478 ps
CPU time 3.18 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 208388 kb
Host smart-a86d5cbb-7b35-4191-af2d-77a501c5d47c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545848670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2545848670
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1552401789
Short name T856
Test name
Test status
Simulation time 634806299 ps
CPU time 8.9 seconds
Started Feb 21 02:57:17 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 208668 kb
Host smart-987b2859-aa6d-4dcc-86bb-e4b807e55d05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552401789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1552401789
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.287667686
Short name T779
Test name
Test status
Simulation time 476209387 ps
CPU time 5.14 seconds
Started Feb 21 02:57:15 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 208348 kb
Host smart-bf9d1dde-019d-47e3-a5af-f2f8c34986ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287667686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.287667686
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4038548487
Short name T537
Test name
Test status
Simulation time 41650440 ps
CPU time 2.02 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 208556 kb
Host smart-8a94ffc9-02cb-4c49-8a0e-f54842a4579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038548487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4038548487
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2970073302
Short name T416
Test name
Test status
Simulation time 36773063 ps
CPU time 2.23 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 206516 kb
Host smart-e8c95512-33eb-47d0-92c7-0df775bd466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970073302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2970073302
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1351646659
Short name T421
Test name
Test status
Simulation time 15366383 ps
CPU time 0.91 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 205936 kb
Host smart-3024f8c3-641e-4029-bd47-3229cc5ec6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351646659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1351646659
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2701054236
Short name T111
Test name
Test status
Simulation time 2087829813 ps
CPU time 14.98 seconds
Started Feb 21 02:57:16 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 220580 kb
Host smart-99a58dea-c73f-4717-945f-b37bf7be2464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701054236 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2701054236
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3263654206
Short name T821
Test name
Test status
Simulation time 184315343 ps
CPU time 4.96 seconds
Started Feb 21 02:57:20 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 209856 kb
Host smart-7625c0f6-5a93-4fad-a404-876eaa676e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263654206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3263654206
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1994004206
Short name T152
Test name
Test status
Simulation time 84319526 ps
CPU time 2.32 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:30 PM PST 24
Peak memory 209416 kb
Host smart-4425f59d-95f0-43c0-850b-2d97844666ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994004206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1994004206
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.81873985
Short name T89
Test name
Test status
Simulation time 57166660 ps
CPU time 0.92 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 205976 kb
Host smart-fdf6d3a0-17e5-4f0a-82a1-b513af5a2351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81873985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.81873985
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.388884856
Short name T359
Test name
Test status
Simulation time 173096859 ps
CPU time 3.59 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 214236 kb
Host smart-d856f22d-912b-48e2-865a-6a9826641b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388884856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.388884856
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3896915048
Short name T220
Test name
Test status
Simulation time 143369611 ps
CPU time 4.36 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 209520 kb
Host smart-aa50cc10-6f95-4b2f-ac76-15e4aa6605bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896915048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3896915048
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2771916211
Short name T588
Test name
Test status
Simulation time 60305049 ps
CPU time 2.65 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 209596 kb
Host smart-919fc764-d073-47dd-b48b-8f350c554771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771916211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2771916211
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.263974143
Short name T888
Test name
Test status
Simulation time 3742355968 ps
CPU time 49.71 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:58:15 PM PST 24
Peak memory 222516 kb
Host smart-d5d227af-6a0e-445b-8fc5-6c80528a7320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263974143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.263974143
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1945183056
Short name T57
Test name
Test status
Simulation time 47053926 ps
CPU time 3.31 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 214308 kb
Host smart-91ae4534-749d-4935-a94a-14e07e55eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945183056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1945183056
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3740286271
Short name T459
Test name
Test status
Simulation time 173545754 ps
CPU time 5.03 seconds
Started Feb 21 02:57:22 PM PST 24
Finished Feb 21 02:57:27 PM PST 24
Peak memory 207772 kb
Host smart-c77e95a9-8d04-4a71-a629-508fa7b33c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740286271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3740286271
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1931711546
Short name T710
Test name
Test status
Simulation time 7565706168 ps
CPU time 33.49 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:59 PM PST 24
Peak memory 208600 kb
Host smart-d5d1965c-95f8-44f9-bfe3-3fec93f3f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931711546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1931711546
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4022944479
Short name T206
Test name
Test status
Simulation time 69526710 ps
CPU time 3.26 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 208376 kb
Host smart-2c4365b3-149c-48ed-9b22-f5f1a36999f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022944479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4022944479
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.948885750
Short name T816
Test name
Test status
Simulation time 21495994 ps
CPU time 1.87 seconds
Started Feb 21 02:57:22 PM PST 24
Finished Feb 21 02:57:24 PM PST 24
Peak memory 207008 kb
Host smart-8426e88d-66b5-4751-84ff-8ebccde1fd57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948885750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.948885750
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.503776688
Short name T699
Test name
Test status
Simulation time 159049237 ps
CPU time 4.94 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 208552 kb
Host smart-8f51751b-5055-498a-a185-2bddcd1981d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503776688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.503776688
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1945189049
Short name T713
Test name
Test status
Simulation time 686656170 ps
CPU time 19.4 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:49 PM PST 24
Peak memory 214228 kb
Host smart-8a69e2fb-763c-4ce1-a965-9f1c2b330c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945189049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1945189049
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1148836040
Short name T384
Test name
Test status
Simulation time 100527684 ps
CPU time 3.12 seconds
Started Feb 21 02:57:30 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 207832 kb
Host smart-77be8ee8-8591-41b8-9a45-21f47c329247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148836040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1148836040
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1784291670
Short name T832
Test name
Test status
Simulation time 10097357395 ps
CPU time 63.63 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:58:33 PM PST 24
Peak memory 215928 kb
Host smart-5757f5a2-5ce3-4815-8b0a-2f8bc1dd67c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784291670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1784291670
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4223742364
Short name T449
Test name
Test status
Simulation time 405514429 ps
CPU time 4.21 seconds
Started Feb 21 02:57:16 PM PST 24
Finished Feb 21 02:57:21 PM PST 24
Peak memory 214224 kb
Host smart-0d5b9e03-f3c6-4444-801c-52abb7390cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223742364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4223742364
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3103087854
Short name T139
Test name
Test status
Simulation time 110859995 ps
CPU time 3.08 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 209860 kb
Host smart-d4180946-9df2-4017-9217-b282d8fb4238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103087854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3103087854
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3598613890
Short name T632
Test name
Test status
Simulation time 35123077 ps
CPU time 0.76 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 205892 kb
Host smart-2fc86854-2ef9-4a4d-bc06-3207e742b161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598613890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3598613890
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4287722117
Short name T27
Test name
Test status
Simulation time 132617331 ps
CPU time 3.34 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 209768 kb
Host smart-f0b5a998-c55e-4765-8323-5f1a16f49eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287722117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4287722117
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.594801275
Short name T742
Test name
Test status
Simulation time 102440316 ps
CPU time 2.08 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 207068 kb
Host smart-c57eb381-f561-4a93-8dfc-2b52b8697ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594801275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.594801275
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4143095504
Short name T288
Test name
Test status
Simulation time 81336195 ps
CPU time 2.43 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 214204 kb
Host smart-8859da76-cc28-4c0e-94d8-dafec421ecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143095504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4143095504
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1278270327
Short name T759
Test name
Test status
Simulation time 176980338 ps
CPU time 3.65 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208880 kb
Host smart-567f61ab-3400-46ee-bd35-04feed546f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278270327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1278270327
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1272922004
Short name T178
Test name
Test status
Simulation time 259923304 ps
CPU time 4.39 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 208584 kb
Host smart-743e0355-58d3-4099-86a1-111771b80f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272922004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1272922004
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1644705926
Short name T618
Test name
Test status
Simulation time 3005875641 ps
CPU time 22.04 seconds
Started Feb 21 02:57:25 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 208276 kb
Host smart-82cae5b0-5e8c-4d43-aeb0-a21a567c066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644705926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1644705926
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1879144507
Short name T440
Test name
Test status
Simulation time 102904070 ps
CPU time 2.92 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 206612 kb
Host smart-d6d84f21-9ef9-4035-a01b-26f76c793012
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879144507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1879144507
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2130356023
Short name T541
Test name
Test status
Simulation time 1831536160 ps
CPU time 7.76 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:48 PM PST 24
Peak memory 208456 kb
Host smart-6bd3c592-44c9-4285-9b1a-6b593789ec2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130356023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2130356023
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3405352587
Short name T712
Test name
Test status
Simulation time 410393416 ps
CPU time 3.03 seconds
Started Feb 21 02:57:23 PM PST 24
Finished Feb 21 02:57:26 PM PST 24
Peak memory 206568 kb
Host smart-7f1c45ab-f5b3-48b4-bef0-5a9d13cd9c23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405352587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3405352587
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4290716373
Short name T683
Test name
Test status
Simulation time 338831985 ps
CPU time 4.49 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 214192 kb
Host smart-f3d4169c-d101-42ff-b7b3-99e5dcdad2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290716373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4290716373
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3786473980
Short name T423
Test name
Test status
Simulation time 148053757 ps
CPU time 5.08 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 207868 kb
Host smart-585f7aae-468b-4344-b42d-41e5eb924265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786473980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3786473980
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4277370914
Short name T70
Test name
Test status
Simulation time 192161587 ps
CPU time 5.45 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:45 PM PST 24
Peak memory 208948 kb
Host smart-c3caf91d-53d6-47e8-b2e2-d824556007b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277370914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4277370914
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1979070754
Short name T150
Test name
Test status
Simulation time 385422954 ps
CPU time 4 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 210248 kb
Host smart-3c496ace-e8d4-455c-997a-f7458da32f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979070754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1979070754
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2185798445
Short name T703
Test name
Test status
Simulation time 16411477 ps
CPU time 0.96 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:57:31 PM PST 24
Peak memory 206032 kb
Host smart-e4a1df97-143f-4356-bdcc-85b99641b73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185798445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2185798445
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4094473988
Short name T406
Test name
Test status
Simulation time 40135052 ps
CPU time 2.87 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 214496 kb
Host smart-188775ef-8ff6-4aba-8824-cd42e20841df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094473988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4094473988
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3959747394
Short name T867
Test name
Test status
Simulation time 727005186 ps
CPU time 7.08 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 214036 kb
Host smart-53cc1f49-d88d-4a56-9c5d-fb772440baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959747394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3959747394
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.127869519
Short name T249
Test name
Test status
Simulation time 1415535807 ps
CPU time 4.59 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 207664 kb
Host smart-c77d019c-56f5-4015-8ea9-029a8253a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127869519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.127869519
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2384437271
Short name T659
Test name
Test status
Simulation time 4890603020 ps
CPU time 46.34 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:58:26 PM PST 24
Peak memory 219100 kb
Host smart-985ffc78-9db1-43cd-8b6f-db6dc4416d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384437271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2384437271
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2167505258
Short name T238
Test name
Test status
Simulation time 572595025 ps
CPU time 6.65 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:46 PM PST 24
Peak memory 222336 kb
Host smart-900ca1a0-1e25-4687-abdd-0b48f73c4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167505258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2167505258
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3592801554
Short name T877
Test name
Test status
Simulation time 485137829 ps
CPU time 5.56 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:36 PM PST 24
Peak memory 209848 kb
Host smart-740eaac6-369d-4d38-a352-08a383f89a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592801554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3592801554
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2221135882
Short name T329
Test name
Test status
Simulation time 96746058 ps
CPU time 4.74 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 208156 kb
Host smart-7fff89fd-30a8-46b3-818a-67ca2c260d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221135882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2221135882
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.916326816
Short name T702
Test name
Test status
Simulation time 8192943812 ps
CPU time 38.31 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:58:16 PM PST 24
Peak memory 208000 kb
Host smart-b4e9b15f-9d50-4b30-965d-02b2f94be8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916326816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.916326816
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.649245728
Short name T472
Test name
Test status
Simulation time 308288275 ps
CPU time 6.74 seconds
Started Feb 21 02:57:28 PM PST 24
Finished Feb 21 02:57:38 PM PST 24
Peak memory 207584 kb
Host smart-5bd18450-de36-4262-92af-4418eff4aa58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649245728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.649245728
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1248327287
Short name T462
Test name
Test status
Simulation time 501460562 ps
CPU time 15.24 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:48 PM PST 24
Peak memory 208544 kb
Host smart-8cc553ce-90b7-4748-b0cd-af577ed01a17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248327287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1248327287
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.498597045
Short name T436
Test name
Test status
Simulation time 381169169 ps
CPU time 7.39 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:32 PM PST 24
Peak memory 207760 kb
Host smart-710eadf9-4f8c-4406-8cbf-a3c3a95bb33b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498597045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.498597045
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2243214785
Short name T351
Test name
Test status
Simulation time 244057902 ps
CPU time 5.32 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:43 PM PST 24
Peak memory 209656 kb
Host smart-e56c529c-e41b-4b96-ab0a-ff03c16ee8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243214785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2243214785
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.695061373
Short name T450
Test name
Test status
Simulation time 48856750 ps
CPU time 2.72 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:35 PM PST 24
Peak memory 206368 kb
Host smart-cb28b14a-47c1-49d3-bef3-ccc0e2f00ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695061373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.695061373
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1489608570
Short name T217
Test name
Test status
Simulation time 4662857387 ps
CPU time 48.62 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:58:25 PM PST 24
Peak memory 222560 kb
Host smart-ec5a924d-85fb-418b-9332-4df32fb7f817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489608570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1489608570
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3752687370
Short name T847
Test name
Test status
Simulation time 1409547217 ps
CPU time 8.3 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 208712 kb
Host smart-de6e0e48-1ebf-4c7b-b401-fbbb02c072e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752687370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3752687370
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3102988345
Short name T36
Test name
Test status
Simulation time 513618258 ps
CPU time 3.71 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 210072 kb
Host smart-a0ef909f-8da0-46f5-a274-760d790bfd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102988345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3102988345
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4069705695
Short name T427
Test name
Test status
Simulation time 23961430 ps
CPU time 0.91 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 205924 kb
Host smart-ea1a3422-3cd9-44e3-bb9c-e0a9d45cb1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069705695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4069705695
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3166497306
Short name T281
Test name
Test status
Simulation time 120714011 ps
CPU time 2.84 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 213920 kb
Host smart-f36560b3-cb15-4352-9729-c3cfab31ed16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166497306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3166497306
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1738926748
Short name T26
Test name
Test status
Simulation time 119424653 ps
CPU time 3.68 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 222720 kb
Host smart-e6e7a0ec-fe6e-48c9-8384-4f76a2e427a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738926748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1738926748
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3702357289
Short name T822
Test name
Test status
Simulation time 97949790 ps
CPU time 3.04 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 207684 kb
Host smart-1d00df45-801e-4dc4-abe6-f46c350223cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702357289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3702357289
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2817578068
Short name T874
Test name
Test status
Simulation time 1990271153 ps
CPU time 22.55 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 218240 kb
Host smart-0da1a6ea-f921-41a6-8b9a-8905626d9ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817578068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2817578068
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1830478197
Short name T514
Test name
Test status
Simulation time 97041226 ps
CPU time 3.3 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:43 PM PST 24
Peak memory 206028 kb
Host smart-00a5ec5f-950b-41b0-9ea9-d6f51066043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830478197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1830478197
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.953239499
Short name T780
Test name
Test status
Simulation time 202606366 ps
CPU time 3.54 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 207888 kb
Host smart-936e766b-3234-489f-8a92-0b935e488184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953239499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.953239499
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3709488559
Short name T758
Test name
Test status
Simulation time 64917138 ps
CPU time 2.96 seconds
Started Feb 21 02:57:24 PM PST 24
Finished Feb 21 02:57:28 PM PST 24
Peak memory 208076 kb
Host smart-f1ca3a78-87ed-4649-bdb7-597fe6986361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709488559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3709488559
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3615061547
Short name T751
Test name
Test status
Simulation time 265040053 ps
CPU time 3.52 seconds
Started Feb 21 02:57:26 PM PST 24
Finished Feb 21 02:57:33 PM PST 24
Peak memory 207924 kb
Host smart-a8a9f814-afd5-45f0-b088-c26528fc0339
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615061547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3615061547
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2302692225
Short name T464
Test name
Test status
Simulation time 5492352270 ps
CPU time 55.15 seconds
Started Feb 21 02:57:27 PM PST 24
Finished Feb 21 02:58:25 PM PST 24
Peak memory 208312 kb
Host smart-2ad78082-d751-41d3-83ed-f544557b0f51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302692225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2302692225
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3028572983
Short name T614
Test name
Test status
Simulation time 3531043027 ps
CPU time 7.48 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 207720 kb
Host smart-cfb58865-4066-4e3c-9a54-1c14dfe5206e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028572983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3028572983
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4228405891
Short name T555
Test name
Test status
Simulation time 27576506 ps
CPU time 1.7 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 207792 kb
Host smart-537cda20-6942-4c71-8509-83938b336c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228405891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4228405891
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3778357756
Short name T711
Test name
Test status
Simulation time 20800117 ps
CPU time 1.81 seconds
Started Feb 21 02:57:29 PM PST 24
Finished Feb 21 02:57:34 PM PST 24
Peak memory 206428 kb
Host smart-82b7b291-36f2-4640-b15e-e60b2b51ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778357756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3778357756
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2027572920
Short name T114
Test name
Test status
Simulation time 3526229586 ps
CPU time 13.3 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:54 PM PST 24
Peak memory 219052 kb
Host smart-ea7db7c2-6791-4f0e-b91c-bd14b591f4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027572920 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2027572920
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.890065942
Short name T538
Test name
Test status
Simulation time 65282465 ps
CPU time 2.49 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 209676 kb
Host smart-b237b333-ec24-4f5a-8fda-173d94b1ed53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890065942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.890065942
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3779977680
Short name T189
Test name
Test status
Simulation time 360255665 ps
CPU time 3.25 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 209784 kb
Host smart-89c0149c-c013-467d-a47e-657e179ecbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779977680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3779977680
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3440206240
Short name T409
Test name
Test status
Simulation time 38445049 ps
CPU time 0.79 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:37 PM PST 24
Peak memory 205904 kb
Host smart-a121fe4d-8922-47d1-8934-bb18a2f9e85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440206240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3440206240
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.527198191
Short name T394
Test name
Test status
Simulation time 413681395 ps
CPU time 10.68 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 214168 kb
Host smart-d826c4f6-8358-42a2-a7da-a8a3e928ec9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527198191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.527198191
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.858744929
Short name T68
Test name
Test status
Simulation time 83281862 ps
CPU time 2.84 seconds
Started Feb 21 02:57:41 PM PST 24
Finished Feb 21 02:57:44 PM PST 24
Peak memory 209456 kb
Host smart-1d90a4c8-fdda-4111-9335-dca9c4c52109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858744929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.858744929
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2676426055
Short name T347
Test name
Test status
Simulation time 178674473 ps
CPU time 3.07 seconds
Started Feb 21 02:57:39 PM PST 24
Finished Feb 21 02:57:43 PM PST 24
Peak memory 208988 kb
Host smart-7198daa7-f4c0-4737-ae99-acb75f423356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676426055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2676426055
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2497199249
Short name T333
Test name
Test status
Simulation time 65825383 ps
CPU time 2.76 seconds
Started Feb 21 02:57:33 PM PST 24
Finished Feb 21 02:57:39 PM PST 24
Peak memory 210504 kb
Host smart-7e9f021f-e6b0-463a-b2f4-3a98eee2625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497199249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2497199249
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3283331197
Short name T242
Test name
Test status
Simulation time 460662102 ps
CPU time 3.64 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 219680 kb
Host smart-d7f1556f-8c09-41b7-9d1a-915673746615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283331197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3283331197
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.138264183
Short name T307
Test name
Test status
Simulation time 39581163 ps
CPU time 2.26 seconds
Started Feb 21 02:57:48 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 207184 kb
Host smart-9f1c29af-fed9-4c0a-aa6c-eef202e5b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138264183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.138264183
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.521534487
Short name T516
Test name
Test status
Simulation time 97594283 ps
CPU time 2.99 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:54 PM PST 24
Peak memory 206476 kb
Host smart-5e65ab03-04eb-4f57-9779-19236bb28c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521534487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.521534487
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3051444871
Short name T497
Test name
Test status
Simulation time 169583592 ps
CPU time 2.41 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:40 PM PST 24
Peak memory 206424 kb
Host smart-0bb55b86-12c4-4dd1-9314-28114dbf817a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051444871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3051444871
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3038100312
Short name T483
Test name
Test status
Simulation time 292564285 ps
CPU time 4.67 seconds
Started Feb 21 02:57:41 PM PST 24
Finished Feb 21 02:57:46 PM PST 24
Peak memory 206588 kb
Host smart-e0280778-0f52-4fe9-86bf-d4cb2d62f33b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038100312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3038100312
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3128150864
Short name T243
Test name
Test status
Simulation time 708215264 ps
CPU time 5.03 seconds
Started Feb 21 02:57:34 PM PST 24
Finished Feb 21 02:57:41 PM PST 24
Peak memory 208540 kb
Host smart-e080b521-6170-46b2-b3db-21aeccb6447d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128150864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3128150864
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2324465178
Short name T731
Test name
Test status
Simulation time 43568911 ps
CPU time 1.69 seconds
Started Feb 21 02:57:40 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 207968 kb
Host smart-f98da59c-5d54-4c6a-a410-ea2ea57280a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324465178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2324465178
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.923693251
Short name T411
Test name
Test status
Simulation time 374540783 ps
CPU time 7.56 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:58 PM PST 24
Peak memory 207116 kb
Host smart-73a8f32e-f2bb-44ad-b5ef-d587e15615b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923693251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.923693251
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.317003686
Short name T300
Test name
Test status
Simulation time 3678379302 ps
CPU time 87.76 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 216160 kb
Host smart-4922e3cd-6f2c-4453-a022-5b446b1abe4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317003686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.317003686
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.949379521
Short name T108
Test name
Test status
Simulation time 158384881 ps
CPU time 3.85 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:53 PM PST 24
Peak memory 218008 kb
Host smart-9b4b0792-271c-4b47-b238-a3364d544b6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949379521 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.949379521
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.131420037
Short name T327
Test name
Test status
Simulation time 47592702 ps
CPU time 2.62 seconds
Started Feb 21 02:57:38 PM PST 24
Finished Feb 21 02:57:42 PM PST 24
Peak memory 207988 kb
Host smart-98588c6d-7e70-495a-9cf1-4b649a68eed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131420037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.131420037
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2033327900
Short name T658
Test name
Test status
Simulation time 22064981 ps
CPU time 0.8 seconds
Started Feb 21 02:56:13 PM PST 24
Finished Feb 21 02:56:15 PM PST 24
Peak memory 205848 kb
Host smart-c94becea-55b7-488a-bc33-bb4e9a0604ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033327900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2033327900
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2881132717
Short name T116
Test name
Test status
Simulation time 55526314 ps
CPU time 4.11 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 214232 kb
Host smart-639752a3-43c0-41ef-91f4-a27be09b7eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881132717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2881132717
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3840397957
Short name T631
Test name
Test status
Simulation time 349135865 ps
CPU time 2.66 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 222384 kb
Host smart-77659031-5ad4-4c4e-8c21-0c53c8f8b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840397957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3840397957
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3454801045
Short name T485
Test name
Test status
Simulation time 202401654 ps
CPU time 4.43 seconds
Started Feb 21 02:56:26 PM PST 24
Finished Feb 21 02:56:30 PM PST 24
Peak memory 207476 kb
Host smart-aa0969e3-32b3-42c8-ac05-fa389a3fd7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454801045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3454801045
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1573379195
Short name T19
Test name
Test status
Simulation time 250171987 ps
CPU time 5.72 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:17 PM PST 24
Peak memory 222396 kb
Host smart-44afa2e7-b7af-4269-b3ba-03d5e579107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573379195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1573379195
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1722281439
Short name T48
Test name
Test status
Simulation time 1431413647 ps
CPU time 7.22 seconds
Started Feb 21 02:56:19 PM PST 24
Finished Feb 21 02:56:27 PM PST 24
Peak memory 222280 kb
Host smart-270b5a7d-c1d9-4e88-8cd7-dc3d0e34d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722281439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1722281439
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.775014553
Short name T536
Test name
Test status
Simulation time 245057335 ps
CPU time 3.57 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 218760 kb
Host smart-88aae53d-284e-467a-8735-9a06da14990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775014553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.775014553
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2663105766
Short name T819
Test name
Test status
Simulation time 194326346 ps
CPU time 4.74 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:30 PM PST 24
Peak memory 214232 kb
Host smart-2927b3bf-42f0-4b33-88dd-5cc34cf9902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663105766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2663105766
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2790775137
Short name T757
Test name
Test status
Simulation time 62888045 ps
CPU time 2.45 seconds
Started Feb 21 02:56:16 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 206512 kb
Host smart-ae8fdcc6-fbc3-413e-b2f9-53d98206f717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790775137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2790775137
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3500913960
Short name T677
Test name
Test status
Simulation time 86436024 ps
CPU time 3.4 seconds
Started Feb 21 02:56:27 PM PST 24
Finished Feb 21 02:56:31 PM PST 24
Peak memory 208044 kb
Host smart-521d134a-c7c8-421b-a086-ed8a5e172269
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500913960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3500913960
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2475962022
Short name T866
Test name
Test status
Simulation time 219095128 ps
CPU time 6.22 seconds
Started Feb 21 02:56:02 PM PST 24
Finished Feb 21 02:56:09 PM PST 24
Peak memory 208460 kb
Host smart-56b6b6cb-6253-4e3a-8adf-fa003add36c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475962022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2475962022
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4234480350
Short name T602
Test name
Test status
Simulation time 206117647 ps
CPU time 6.91 seconds
Started Feb 21 02:56:26 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 207832 kb
Host smart-47ef50e4-7f21-4f31-8bf5-32fce9e94863
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234480350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4234480350
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.671694858
Short name T728
Test name
Test status
Simulation time 422890826 ps
CPU time 9.87 seconds
Started Feb 21 02:56:11 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 208044 kb
Host smart-e1276efe-7e29-4bff-99e2-8062db9c6160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671694858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.671694858
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1273200202
Short name T447
Test name
Test status
Simulation time 162183822 ps
CPU time 4.82 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:16 PM PST 24
Peak memory 207152 kb
Host smart-b90b2a56-21b5-40e3-9f04-8f2c16bae945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273200202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1273200202
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2116734401
Short name T229
Test name
Test status
Simulation time 349055090 ps
CPU time 14.57 seconds
Started Feb 21 02:56:29 PM PST 24
Finished Feb 21 02:56:44 PM PST 24
Peak memory 216012 kb
Host smart-5e58cdb2-2fc2-453c-8ffe-40a6fa47d8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116734401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2116734401
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2023352749
Short name T311
Test name
Test status
Simulation time 338719210 ps
CPU time 4.61 seconds
Started Feb 21 02:56:29 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 217924 kb
Host smart-ce33d1a2-a775-433d-9239-18ba188da030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023352749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2023352749
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1195612503
Short name T750
Test name
Test status
Simulation time 82271364 ps
CPU time 2.13 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 209596 kb
Host smart-9f08db2a-ed96-4949-8a49-233062e5e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195612503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1195612503
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1132705316
Short name T835
Test name
Test status
Simulation time 73561330 ps
CPU time 1.01 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 205936 kb
Host smart-045ce069-1a9f-47a8-9f34-da734ed55f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132705316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1132705316
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1114819274
Short name T400
Test name
Test status
Simulation time 36698512 ps
CPU time 3.11 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:53 PM PST 24
Peak memory 214224 kb
Host smart-d22292ba-377d-4afd-8ffd-b60ab8c4fdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114819274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1114819274
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.635549432
Short name T885
Test name
Test status
Simulation time 1640825349 ps
CPU time 5.61 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:56 PM PST 24
Peak memory 210028 kb
Host smart-f41ec89f-21d5-435c-b0a8-36bbe21d9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635549432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.635549432
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2185500154
Short name T317
Test name
Test status
Simulation time 1414917286 ps
CPU time 5.87 seconds
Started Feb 21 02:57:38 PM PST 24
Finished Feb 21 02:57:45 PM PST 24
Peak memory 219840 kb
Host smart-1f639831-7089-4c48-a141-e1d68d094398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185500154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2185500154
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1675403922
Short name T239
Test name
Test status
Simulation time 270482406 ps
CPU time 7.14 seconds
Started Feb 21 02:57:56 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 214136 kb
Host smart-d38b61e0-066b-4402-8311-8900cc2c1777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675403922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1675403922
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1908636981
Short name T851
Test name
Test status
Simulation time 184994172 ps
CPU time 5.03 seconds
Started Feb 21 02:57:36 PM PST 24
Finished Feb 21 02:57:43 PM PST 24
Peak memory 222304 kb
Host smart-7c9db01a-6973-4ad8-a9b8-3e4ced5d43b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908636981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1908636981
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1435312786
Short name T575
Test name
Test status
Simulation time 256771199 ps
CPU time 7.95 seconds
Started Feb 21 02:57:38 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 206688 kb
Host smart-c033f712-92f5-4040-9bc4-b18617bc271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435312786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1435312786
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1829897338
Short name T250
Test name
Test status
Simulation time 32611688 ps
CPU time 2.44 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:53 PM PST 24
Peak memory 208200 kb
Host smart-2470ea08-c4ca-4b4f-984c-87f3bf60b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829897338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1829897338
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2309803399
Short name T705
Test name
Test status
Simulation time 399880114 ps
CPU time 8.3 seconds
Started Feb 21 02:57:35 PM PST 24
Finished Feb 21 02:57:45 PM PST 24
Peak memory 208540 kb
Host smart-19dc2e0c-d42e-4055-a2e6-dbd5e0dc9e26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309803399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2309803399
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3765369776
Short name T688
Test name
Test status
Simulation time 460983007 ps
CPU time 9.39 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:59 PM PST 24
Peak memory 208496 kb
Host smart-efa52c3a-511a-4012-9f1c-40cbe8856856
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765369776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3765369776
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1036483733
Short name T568
Test name
Test status
Simulation time 763317595 ps
CPU time 5.83 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:55 PM PST 24
Peak memory 208400 kb
Host smart-a91f7de2-19d7-4f70-8d84-748525b0df48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036483733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1036483733
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2320890970
Short name T228
Test name
Test status
Simulation time 159122613 ps
CPU time 4.07 seconds
Started Feb 21 02:57:57 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 209128 kb
Host smart-6d640017-3fda-4173-97f9-4da7f7ff3d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320890970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2320890970
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3108803081
Short name T475
Test name
Test status
Simulation time 5564583016 ps
CPU time 30.58 seconds
Started Feb 21 02:57:42 PM PST 24
Finished Feb 21 02:58:13 PM PST 24
Peak memory 208256 kb
Host smart-f4e56b01-9762-4db3-b4b3-cf3d2a5c4572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108803081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3108803081
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.4182755583
Short name T90
Test name
Test status
Simulation time 268237740 ps
CPU time 11.11 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:10 PM PST 24
Peak memory 219940 kb
Host smart-b7c2eda9-b455-4f54-9038-afee8d62055f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182755583 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.4182755583
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1837883795
Short name T833
Test name
Test status
Simulation time 121858128 ps
CPU time 5.65 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:55 PM PST 24
Peak memory 209868 kb
Host smart-a3aeff9e-1036-4ec3-9dad-4b24bdcb3826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837883795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1837883795
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.445130570
Short name T160
Test name
Test status
Simulation time 90203630 ps
CPU time 1.58 seconds
Started Feb 21 02:57:56 PM PST 24
Finished Feb 21 02:57:58 PM PST 24
Peak memory 209244 kb
Host smart-e25c5441-65a4-4f4f-a0fd-98b2c0798266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445130570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.445130570
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2301786472
Short name T469
Test name
Test status
Simulation time 24269265 ps
CPU time 0.77 seconds
Started Feb 21 02:57:49 PM PST 24
Finished Feb 21 02:57:50 PM PST 24
Peak memory 205892 kb
Host smart-969c4b16-315b-4823-9ef0-20260eea3b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301786472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2301786472
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.24853006
Short name T298
Test name
Test status
Simulation time 633726867 ps
CPU time 2.77 seconds
Started Feb 21 02:57:50 PM PST 24
Finished Feb 21 02:57:53 PM PST 24
Peak memory 222424 kb
Host smart-bd459978-5580-4452-a214-deb5605c4462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24853006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.24853006
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3594419465
Short name T25
Test name
Test status
Simulation time 298084535 ps
CPU time 5.22 seconds
Started Feb 21 02:57:46 PM PST 24
Finished Feb 21 02:57:52 PM PST 24
Peak memory 210428 kb
Host smart-97110514-8151-4bc7-97f9-61f018be1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594419465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3594419465
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2588565870
Short name T715
Test name
Test status
Simulation time 44117097 ps
CPU time 2.33 seconds
Started Feb 21 02:57:57 PM PST 24
Finished Feb 21 02:58:00 PM PST 24
Peak memory 206660 kb
Host smart-76c3abe4-0d88-45b9-9cad-8034fa71a71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588565870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2588565870
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4270049919
Short name T624
Test name
Test status
Simulation time 62350715 ps
CPU time 3.2 seconds
Started Feb 21 02:57:47 PM PST 24
Finished Feb 21 02:57:51 PM PST 24
Peak memory 209024 kb
Host smart-7bd2cea0-2982-4774-beba-8bac1da3e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270049919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4270049919
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3271156579
Short name T276
Test name
Test status
Simulation time 358250031 ps
CPU time 4.84 seconds
Started Feb 21 02:57:48 PM PST 24
Finished Feb 21 02:57:54 PM PST 24
Peak memory 214136 kb
Host smart-1d4dffb9-2dc8-4de0-92e7-3d9fd529fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271156579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3271156579
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3457353262
Short name T46
Test name
Test status
Simulation time 109187737 ps
CPU time 1.97 seconds
Started Feb 21 02:58:00 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 214236 kb
Host smart-5196fcdc-736d-41c2-8fda-241f544f649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457353262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3457353262
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1265602319
Short name T587
Test name
Test status
Simulation time 322228211 ps
CPU time 4.09 seconds
Started Feb 21 02:57:59 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 218268 kb
Host smart-28f87c43-51eb-49b1-ab99-7bb0375682e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265602319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1265602319
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3843059910
Short name T773
Test name
Test status
Simulation time 134528464 ps
CPU time 3.38 seconds
Started Feb 21 02:58:01 PM PST 24
Finished Feb 21 02:58:06 PM PST 24
Peak memory 208220 kb
Host smart-57def04a-dfab-4149-8b3c-e411be68dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843059910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3843059910
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.552356703
Short name T736
Test name
Test status
Simulation time 295674736 ps
CPU time 3.19 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:01 PM PST 24
Peak memory 208112 kb
Host smart-9b95e750-329a-4fd5-abb1-4f47d1834aee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552356703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.552356703
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.884788622
Short name T202
Test name
Test status
Simulation time 3254361640 ps
CPU time 70.28 seconds
Started Feb 21 02:57:57 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 208448 kb
Host smart-609df69a-5a41-4c23-be2e-195eea05f7d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884788622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.884788622
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2453441993
Short name T268
Test name
Test status
Simulation time 93464265 ps
CPU time 2.03 seconds
Started Feb 21 02:58:06 PM PST 24
Finished Feb 21 02:58:09 PM PST 24
Peak memory 208544 kb
Host smart-7c1d0028-d21e-42ce-94f8-f0f52b9f2b12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453441993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2453441993
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2634914828
Short name T896
Test name
Test status
Simulation time 2694178333 ps
CPU time 15.52 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:13 PM PST 24
Peak memory 209772 kb
Host smart-972e5bb9-dd99-4e4f-b123-56f7c23e7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634914828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2634914828
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.260727590
Short name T565
Test name
Test status
Simulation time 782181416 ps
CPU time 5.58 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:04 PM PST 24
Peak memory 206840 kb
Host smart-4da16f67-b478-452a-bfda-629fec8aaa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260727590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.260727590
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.490160957
Short name T323
Test name
Test status
Simulation time 890766783 ps
CPU time 22.91 seconds
Started Feb 21 02:58:01 PM PST 24
Finished Feb 21 02:58:25 PM PST 24
Peak memory 216588 kb
Host smart-0cbf9aeb-fb1c-4bdc-b1d2-45f95be28de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490160957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.490160957
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.740998589
Short name T721
Test name
Test status
Simulation time 1433250653 ps
CPU time 9.89 seconds
Started Feb 21 02:57:53 PM PST 24
Finished Feb 21 02:58:04 PM PST 24
Peak memory 206924 kb
Host smart-29da96b2-9d0b-44fa-bd17-e961a1230f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740998589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.740998589
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.996619316
Short name T361
Test name
Test status
Simulation time 548608216 ps
CPU time 3.1 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 209472 kb
Host smart-6dfe352a-6438-4c2b-8631-79acdb276321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996619316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.996619316
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3381406242
Short name T800
Test name
Test status
Simulation time 202955319 ps
CPU time 0.73 seconds
Started Feb 21 02:58:10 PM PST 24
Finished Feb 21 02:58:11 PM PST 24
Peak memory 205828 kb
Host smart-6ec185b9-77cc-4531-95dc-42cc10eaaeb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381406242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3381406242
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1300226969
Short name T395
Test name
Test status
Simulation time 1066606353 ps
CPU time 9.02 seconds
Started Feb 21 02:57:59 PM PST 24
Finished Feb 21 02:58:08 PM PST 24
Peak memory 214248 kb
Host smart-7af9f9c1-28c3-436f-9b3a-7f62fb8e268d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300226969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1300226969
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1300595476
Short name T210
Test name
Test status
Simulation time 2591595787 ps
CPU time 63.77 seconds
Started Feb 21 02:58:01 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 222844 kb
Host smart-5d434cfb-e6b5-4eb0-9139-833c55ebe74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300595476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1300595476
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3331260636
Short name T594
Test name
Test status
Simulation time 121003699 ps
CPU time 4.24 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:08 PM PST 24
Peak memory 207900 kb
Host smart-4aa2067b-47f8-4267-8fe5-bbaab5e70d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331260636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3331260636
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3890531747
Short name T543
Test name
Test status
Simulation time 200969725 ps
CPU time 6.03 seconds
Started Feb 21 02:57:56 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 214152 kb
Host smart-deea3243-1a4e-485c-a284-0e7f8f78c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890531747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3890531747
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1178726430
Short name T764
Test name
Test status
Simulation time 551799048 ps
CPU time 6.24 seconds
Started Feb 21 02:58:00 PM PST 24
Finished Feb 21 02:58:06 PM PST 24
Peak memory 209716 kb
Host smart-01df7ffa-b8ae-4afc-88e9-dbae978b1042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178726430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1178726430
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.171690369
Short name T836
Test name
Test status
Simulation time 709574559 ps
CPU time 19.06 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 208292 kb
Host smart-38b89097-cb2c-4a3d-8ce5-66a723fe5b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171690369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.171690369
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1159788107
Short name T716
Test name
Test status
Simulation time 228532720 ps
CPU time 2.86 seconds
Started Feb 21 02:58:12 PM PST 24
Finished Feb 21 02:58:15 PM PST 24
Peak memory 206412 kb
Host smart-68a09e48-949c-438c-9d39-7a1b36bbf261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159788107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1159788107
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2318640755
Short name T383
Test name
Test status
Simulation time 2722851776 ps
CPU time 27.84 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:26 PM PST 24
Peak memory 208244 kb
Host smart-c086261b-e4cf-44ba-97c0-496ec63888f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318640755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2318640755
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1890770371
Short name T507
Test name
Test status
Simulation time 41110157 ps
CPU time 2.3 seconds
Started Feb 21 02:58:05 PM PST 24
Finished Feb 21 02:58:08 PM PST 24
Peak memory 207092 kb
Host smart-b2511fd7-bb56-45df-b188-c685255a171c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890770371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1890770371
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1364004321
Short name T610
Test name
Test status
Simulation time 390014886 ps
CPU time 5.17 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:04 PM PST 24
Peak memory 206436 kb
Host smart-c0b8d31a-7e42-4b6b-9ee7-5fe1e81ac7f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364004321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1364004321
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4205258621
Short name T374
Test name
Test status
Simulation time 20677622 ps
CPU time 1.6 seconds
Started Feb 21 02:58:05 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 214148 kb
Host smart-6a929871-013f-4cd5-82bc-9ccef8dcf225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205258621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4205258621
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3651642977
Short name T886
Test name
Test status
Simulation time 132698587 ps
CPU time 2.23 seconds
Started Feb 21 02:57:46 PM PST 24
Finished Feb 21 02:57:49 PM PST 24
Peak memory 206328 kb
Host smart-bc6fae99-0a79-4d84-b073-c8c9b2921389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651642977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3651642977
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.538053520
Short name T681
Test name
Test status
Simulation time 913398860 ps
CPU time 34.92 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 215948 kb
Host smart-7f2f6f12-b39e-44a7-9c2b-4ba48c8d5ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538053520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.538053520
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2038985917
Short name T605
Test name
Test status
Simulation time 130886143 ps
CPU time 6 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:10 PM PST 24
Peak memory 207696 kb
Host smart-a0ff5778-d4ec-4aac-a318-4f813a459dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038985917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2038985917
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3959287475
Short name T898
Test name
Test status
Simulation time 55684308 ps
CPU time 2.46 seconds
Started Feb 21 02:58:00 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 209836 kb
Host smart-0ab1c3a8-5782-478b-b3b8-21cb0c1bc8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959287475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3959287475
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1650602655
Short name T460
Test name
Test status
Simulation time 36269375 ps
CPU time 0.89 seconds
Started Feb 21 02:58:18 PM PST 24
Finished Feb 21 02:58:19 PM PST 24
Peak memory 205884 kb
Host smart-bd0c1cc6-4a83-403d-8082-d2eb78addd5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650602655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1650602655
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3326629130
Short name T214
Test name
Test status
Simulation time 7240534660 ps
CPU time 37.4 seconds
Started Feb 21 02:58:00 PM PST 24
Finished Feb 21 02:58:38 PM PST 24
Peak memory 222820 kb
Host smart-39cf134d-6aad-4471-b341-c7cbbe1012ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326629130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3326629130
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1974512331
Short name T179
Test name
Test status
Simulation time 247701106 ps
CPU time 2.19 seconds
Started Feb 21 02:57:57 PM PST 24
Finished Feb 21 02:58:00 PM PST 24
Peak memory 214148 kb
Host smart-f3d6a3b3-fae1-4f22-b3db-fb9c7b74692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974512331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1974512331
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.750684057
Short name T441
Test name
Test status
Simulation time 837666460 ps
CPU time 10.03 seconds
Started Feb 21 02:58:30 PM PST 24
Finished Feb 21 02:58:40 PM PST 24
Peak memory 220200 kb
Host smart-5679eca9-cd54-4f7f-bd4d-54b9e36ff6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750684057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.750684057
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1220750048
Short name T690
Test name
Test status
Simulation time 94663115 ps
CPU time 3.05 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 214224 kb
Host smart-438565e1-c4e4-4012-969a-1de9541c16e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220750048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1220750048
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.579988187
Short name T254
Test name
Test status
Simulation time 679803971 ps
CPU time 7.48 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:11 PM PST 24
Peak memory 209100 kb
Host smart-65ca4f32-efa0-4097-867c-769aa1b89668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579988187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.579988187
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4284318769
Short name T532
Test name
Test status
Simulation time 54527832 ps
CPU time 2.95 seconds
Started Feb 21 02:58:14 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 206492 kb
Host smart-705c6555-d51b-419e-b35f-26ab227728d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284318769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4284318769
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1215955294
Short name T839
Test name
Test status
Simulation time 67566809 ps
CPU time 2.5 seconds
Started Feb 21 02:57:56 PM PST 24
Finished Feb 21 02:57:59 PM PST 24
Peak memory 206524 kb
Host smart-c740dc2a-1a43-42e1-9628-c3227e538d44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215955294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1215955294
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.585363685
Short name T656
Test name
Test status
Simulation time 67118237 ps
CPU time 2.38 seconds
Started Feb 21 02:57:59 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 208452 kb
Host smart-d76a8fb2-9691-4045-aac7-f27a8a317f6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585363685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.585363685
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1993702223
Short name T674
Test name
Test status
Simulation time 133295714 ps
CPU time 3.22 seconds
Started Feb 21 02:57:59 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 206544 kb
Host smart-b9cca628-40cc-4e6f-9d09-732ae8645eb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993702223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1993702223
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3183405170
Short name T559
Test name
Test status
Simulation time 67835073 ps
CPU time 2.18 seconds
Started Feb 21 02:58:01 PM PST 24
Finished Feb 21 02:58:03 PM PST 24
Peak memory 208456 kb
Host smart-a5b114c1-42cc-4089-9930-25192d09977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183405170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3183405170
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3073442573
Short name T598
Test name
Test status
Simulation time 246151139 ps
CPU time 2.95 seconds
Started Feb 21 02:57:58 PM PST 24
Finished Feb 21 02:58:01 PM PST 24
Peak memory 206536 kb
Host smart-e4508926-1dee-40de-8fae-76ad311c0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073442573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3073442573
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2865290053
Short name T743
Test name
Test status
Simulation time 808128953 ps
CPU time 32.99 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 214828 kb
Host smart-359cd12c-6323-4892-af61-e9e9f314960c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865290053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2865290053
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1050592514
Short name T675
Test name
Test status
Simulation time 679333735 ps
CPU time 6.39 seconds
Started Feb 21 02:58:37 PM PST 24
Finished Feb 21 02:58:44 PM PST 24
Peak memory 218140 kb
Host smart-fd883b8c-3a6f-4258-9ace-0232cba30d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050592514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1050592514
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.572298030
Short name T673
Test name
Test status
Simulation time 98946036 ps
CPU time 2.97 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:37 PM PST 24
Peak memory 210152 kb
Host smart-266dce0a-df46-4c92-bd6c-169514620251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572298030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.572298030
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.652959073
Short name T707
Test name
Test status
Simulation time 13030851 ps
CPU time 0.96 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:37 PM PST 24
Peak memory 206020 kb
Host smart-63ebba2a-4488-45f0-83e7-cff7cd56df87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652959073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.652959073
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2766583243
Short name T825
Test name
Test status
Simulation time 42077747 ps
CPU time 1.83 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:06 PM PST 24
Peak memory 208560 kb
Host smart-9a7c98d9-12c7-4410-b98b-e97a372b94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766583243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2766583243
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4178755277
Short name T81
Test name
Test status
Simulation time 102601211 ps
CPU time 3.51 seconds
Started Feb 21 02:58:05 PM PST 24
Finished Feb 21 02:58:09 PM PST 24
Peak memory 209544 kb
Host smart-b82e9cfc-a566-4163-8dfb-10da2c7194cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178755277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4178755277
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2134826163
Short name T670
Test name
Test status
Simulation time 132344090 ps
CPU time 3.62 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 217660 kb
Host smart-84b3be2a-8ac0-4958-9f71-37b6efbd3be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134826163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2134826163
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3590613222
Short name T646
Test name
Test status
Simulation time 361337422 ps
CPU time 4.62 seconds
Started Feb 21 02:58:11 PM PST 24
Finished Feb 21 02:58:16 PM PST 24
Peak memory 208740 kb
Host smart-ecd12b0a-7572-483f-9f95-95f5bf433e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590613222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3590613222
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2141573869
Short name T627
Test name
Test status
Simulation time 192288933 ps
CPU time 5.48 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 207752 kb
Host smart-68a5f3eb-8eda-40d5-aba4-85fc343c1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141573869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2141573869
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2354802226
Short name T583
Test name
Test status
Simulation time 757771272 ps
CPU time 4.9 seconds
Started Feb 21 02:58:01 PM PST 24
Finished Feb 21 02:58:07 PM PST 24
Peak memory 208476 kb
Host smart-1e3e4ef1-e2ee-439d-bf88-a04b105684ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354802226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2354802226
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2093444772
Short name T718
Test name
Test status
Simulation time 958799188 ps
CPU time 17.82 seconds
Started Feb 21 02:58:04 PM PST 24
Finished Feb 21 02:58:23 PM PST 24
Peak memory 208576 kb
Host smart-445e5cc1-7b1d-4cc3-97e3-719d81212ac9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093444772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2093444772
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2654050187
Short name T284
Test name
Test status
Simulation time 115496832 ps
CPU time 2.58 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:20 PM PST 24
Peak memory 206560 kb
Host smart-06e3d47c-aad0-4acf-b41a-4c7bf133cbca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654050187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2654050187
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2401834930
Short name T785
Test name
Test status
Simulation time 175195886 ps
CPU time 2.66 seconds
Started Feb 21 02:58:18 PM PST 24
Finished Feb 21 02:58:21 PM PST 24
Peak memory 207840 kb
Host smart-5719d92f-aa02-4b5c-ad87-6778d0719c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401834930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2401834930
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2653834301
Short name T698
Test name
Test status
Simulation time 293080964 ps
CPU time 2.93 seconds
Started Feb 21 02:58:13 PM PST 24
Finished Feb 21 02:58:17 PM PST 24
Peak memory 206292 kb
Host smart-341909ce-2a3b-4a69-9cf5-17436a19ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653834301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2653834301
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.775878422
Short name T47
Test name
Test status
Simulation time 7957762134 ps
CPU time 76.37 seconds
Started Feb 21 02:58:03 PM PST 24
Finished Feb 21 02:59:20 PM PST 24
Peak memory 222636 kb
Host smart-814d4a1a-7964-4175-9bbf-24aa13aaaa15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775878422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.775878422
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2089820666
Short name T791
Test name
Test status
Simulation time 544688561 ps
CPU time 3.21 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 207540 kb
Host smart-9c26aa32-b6a2-434d-b2ac-c2fb2f289f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089820666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2089820666
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2477646163
Short name T142
Test name
Test status
Simulation time 169702677 ps
CPU time 2.52 seconds
Started Feb 21 02:58:15 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 209548 kb
Host smart-8090d23d-11ce-4cff-a0ac-5b629e55bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477646163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2477646163
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2768043704
Short name T510
Test name
Test status
Simulation time 66729857 ps
CPU time 0.74 seconds
Started Feb 21 02:58:34 PM PST 24
Finished Feb 21 02:58:35 PM PST 24
Peak memory 205832 kb
Host smart-7aecd2fa-8055-4015-bb1b-6f90bfc0a40c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768043704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2768043704
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.231545209
Short name T809
Test name
Test status
Simulation time 122443313 ps
CPU time 2.14 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 208408 kb
Host smart-b1602f8f-4e8e-4681-82d6-e23861b1daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231545209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.231545209
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.173118003
Short name T607
Test name
Test status
Simulation time 99927949 ps
CPU time 2.57 seconds
Started Feb 21 02:58:02 PM PST 24
Finished Feb 21 02:58:05 PM PST 24
Peak memory 209696 kb
Host smart-0121a5be-572f-4b41-b6d5-64de38db8359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173118003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.173118003
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3987891094
Short name T170
Test name
Test status
Simulation time 180126840 ps
CPU time 5.59 seconds
Started Feb 21 02:58:32 PM PST 24
Finished Feb 21 02:58:38 PM PST 24
Peak memory 207784 kb
Host smart-4dd151c3-a7bd-495d-8fff-44e2126ee434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987891094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3987891094
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3481508981
Short name T313
Test name
Test status
Simulation time 191172394 ps
CPU time 8.82 seconds
Started Feb 21 02:58:15 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 214232 kb
Host smart-4d7444e2-ba73-4643-b1ca-8c350797c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481508981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3481508981
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.600782576
Short name T811
Test name
Test status
Simulation time 113712857 ps
CPU time 3.43 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 208316 kb
Host smart-3015408b-d5d6-4cf1-b30b-330cd9d94e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600782576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.600782576
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1646063307
Short name T570
Test name
Test status
Simulation time 345338106 ps
CPU time 4.46 seconds
Started Feb 21 02:58:12 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 210052 kb
Host smart-cc2ed08c-c748-4517-8343-cd9ae22d9ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646063307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1646063307
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.645598811
Short name T273
Test name
Test status
Simulation time 110480561 ps
CPU time 4.56 seconds
Started Feb 21 02:58:05 PM PST 24
Finished Feb 21 02:58:10 PM PST 24
Peak memory 206648 kb
Host smart-33c5c16d-377f-4765-9bd6-f3962e04480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645598811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.645598811
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3290553792
Short name T894
Test name
Test status
Simulation time 68699255 ps
CPU time 2.63 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 206592 kb
Host smart-c3fd39dd-7e9f-47fc-931a-ea615e7ba4c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290553792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3290553792
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.148995729
Short name T766
Test name
Test status
Simulation time 37884464 ps
CPU time 2.57 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 208168 kb
Host smart-a9e150d4-1b97-4527-9edf-0cf03da00528
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148995729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.148995729
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3699749121
Short name T531
Test name
Test status
Simulation time 71389418 ps
CPU time 3.56 seconds
Started Feb 21 02:58:02 PM PST 24
Finished Feb 21 02:58:06 PM PST 24
Peak memory 208468 kb
Host smart-b23d16ff-25d8-418f-ba24-42fabe27b271
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699749121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3699749121
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2728988040
Short name T840
Test name
Test status
Simulation time 303259701 ps
CPU time 4.78 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 208072 kb
Host smart-6c86e265-d8dc-4044-8fa0-52aa497e965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728988040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2728988040
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.291992858
Short name T373
Test name
Test status
Simulation time 169897390 ps
CPU time 3.08 seconds
Started Feb 21 02:58:13 PM PST 24
Finished Feb 21 02:58:17 PM PST 24
Peak memory 208292 kb
Host smart-9b40b89f-b10f-461b-90aa-c8a3872a8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291992858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.291992858
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2260259730
Short name T367
Test name
Test status
Simulation time 58901035 ps
CPU time 2.36 seconds
Started Feb 21 02:58:27 PM PST 24
Finished Feb 21 02:58:29 PM PST 24
Peak memory 207964 kb
Host smart-4ac1cc20-5338-4777-954b-b58129905f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260259730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2260259730
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.941732039
Short name T760
Test name
Test status
Simulation time 535555962 ps
CPU time 7.54 seconds
Started Feb 21 02:58:37 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 218276 kb
Host smart-bfb648cd-f06e-4ba8-bc9e-10d172f592c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941732039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.941732039
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1159779495
Short name T382
Test name
Test status
Simulation time 120254477 ps
CPU time 3.09 seconds
Started Feb 21 02:58:15 PM PST 24
Finished Feb 21 02:58:18 PM PST 24
Peak memory 209480 kb
Host smart-8074496e-c35d-4971-8a1d-ef1310e28e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159779495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1159779495
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2038365223
Short name T617
Test name
Test status
Simulation time 24531403 ps
CPU time 0.74 seconds
Started Feb 21 02:58:15 PM PST 24
Finished Feb 21 02:58:16 PM PST 24
Peak memory 205844 kb
Host smart-4ad959da-d549-4401-a6b0-9d928f3ccf6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038365223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2038365223
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.846190901
Short name T360
Test name
Test status
Simulation time 1222357181 ps
CPU time 14.53 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:31 PM PST 24
Peak memory 214704 kb
Host smart-4f85f4d4-8722-4fa8-8fe7-7fd9ebf1e127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846190901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.846190901
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1131521298
Short name T879
Test name
Test status
Simulation time 921599240 ps
CPU time 24.26 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 214612 kb
Host smart-fea6097f-d18d-414c-8448-42c8a164a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131521298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1131521298
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2244646884
Short name T719
Test name
Test status
Simulation time 50279193 ps
CPU time 2.38 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 218416 kb
Host smart-063281c8-56ea-4400-9d89-7d7c1a0080e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244646884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2244646884
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3126050094
Short name T320
Test name
Test status
Simulation time 320207415 ps
CPU time 6.72 seconds
Started Feb 21 02:58:20 PM PST 24
Finished Feb 21 02:58:27 PM PST 24
Peak memory 214232 kb
Host smart-60966128-df71-4346-9425-02142f296b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126050094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3126050094
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3581104659
Short name T727
Test name
Test status
Simulation time 47759146 ps
CPU time 3.25 seconds
Started Feb 21 02:58:20 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 209828 kb
Host smart-a686ce4b-79de-4260-9ef8-71d937df4cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581104659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3581104659
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2440273304
Short name T271
Test name
Test status
Simulation time 535785303 ps
CPU time 3.37 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 206636 kb
Host smart-6902adb9-b3d2-48e4-9419-ecf374d4c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440273304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2440273304
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3072261212
Short name T730
Test name
Test status
Simulation time 3286279738 ps
CPU time 6.09 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 208536 kb
Host smart-e5f3fb8e-4ae6-4b6c-87a8-5d41e80e7b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072261212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3072261212
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2012438285
Short name T589
Test name
Test status
Simulation time 30954597 ps
CPU time 2.34 seconds
Started Feb 21 02:58:29 PM PST 24
Finished Feb 21 02:58:32 PM PST 24
Peak memory 206448 kb
Host smart-4bc4aa33-4128-4c76-8a74-db685fd95c87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012438285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2012438285
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2224192423
Short name T639
Test name
Test status
Simulation time 266365599 ps
CPU time 2.72 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:36 PM PST 24
Peak memory 206400 kb
Host smart-774e7862-7d42-48fc-afcd-bc65251d2815
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224192423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2224192423
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2819125297
Short name T900
Test name
Test status
Simulation time 672276304 ps
CPU time 7.66 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 207560 kb
Host smart-e3e0f209-a750-4cd7-90b0-564563999989
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819125297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2819125297
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3937316256
Short name T724
Test name
Test status
Simulation time 443417722 ps
CPU time 4.55 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:21 PM PST 24
Peak memory 214228 kb
Host smart-7b4e8069-fe25-4767-9104-9cbc25f87bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937316256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3937316256
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2506813981
Short name T379
Test name
Test status
Simulation time 298917637 ps
CPU time 7.43 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 206568 kb
Host smart-b7de85bd-e6b7-4b04-b580-94d0149431a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506813981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2506813981
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1959812932
Short name T297
Test name
Test status
Simulation time 441310569 ps
CPU time 18.67 seconds
Started Feb 21 02:58:11 PM PST 24
Finished Feb 21 02:58:30 PM PST 24
Peak memory 219612 kb
Host smart-d9b1c41a-8343-40dc-a67c-09ef2eddce26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959812932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1959812932
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4237182473
Short name T208
Test name
Test status
Simulation time 212232028 ps
CPU time 4.97 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:42 PM PST 24
Peak memory 219612 kb
Host smart-2fc2ce47-aa63-44e4-b6c6-183981208757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237182473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4237182473
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1940482520
Short name T827
Test name
Test status
Simulation time 47038480 ps
CPU time 0.87 seconds
Started Feb 21 02:58:18 PM PST 24
Finished Feb 21 02:58:19 PM PST 24
Peak memory 205892 kb
Host smart-a13fd13a-4cef-4bbd-a9e4-242f38d900ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940482520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1940482520
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2868046632
Short name T225
Test name
Test status
Simulation time 104636242 ps
CPU time 5.94 seconds
Started Feb 21 02:58:34 PM PST 24
Finished Feb 21 02:58:40 PM PST 24
Peak memory 214148 kb
Host smart-4ec14874-d8de-4d43-b718-d23a17bfd9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868046632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2868046632
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2590995256
Short name T9
Test name
Test status
Simulation time 4174842393 ps
CPU time 35.59 seconds
Started Feb 21 02:58:18 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 222808 kb
Host smart-f522c280-d8f1-4dde-b8de-01a615e4fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590995256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2590995256
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1332160314
Short name T52
Test name
Test status
Simulation time 236715270 ps
CPU time 4.16 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 218204 kb
Host smart-6e905b64-079f-4176-b080-c0038dd1208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332160314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1332160314
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3954222873
Short name T318
Test name
Test status
Simulation time 3447584053 ps
CPU time 37.52 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 214312 kb
Host smart-24430949-2ce7-4ce5-ad69-3172d85d3f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954222873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3954222873
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4115757877
Short name T59
Test name
Test status
Simulation time 237403612 ps
CPU time 3.51 seconds
Started Feb 21 02:58:29 PM PST 24
Finished Feb 21 02:58:32 PM PST 24
Peak memory 209124 kb
Host smart-31c9a615-4f5a-4f67-bd8d-dbb3c7675ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115757877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4115757877
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.4228458614
Short name T666
Test name
Test status
Simulation time 382079622 ps
CPU time 3.45 seconds
Started Feb 21 02:58:16 PM PST 24
Finished Feb 21 02:58:19 PM PST 24
Peak memory 207124 kb
Host smart-b67674b7-436c-43da-933b-b6099a0b6122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228458614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4228458614
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.650723713
Short name T192
Test name
Test status
Simulation time 218665746 ps
CPU time 8.58 seconds
Started Feb 21 02:58:12 PM PST 24
Finished Feb 21 02:58:21 PM PST 24
Peak memory 208424 kb
Host smart-df2dc875-7868-4757-8113-3a875ccb948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650723713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.650723713
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3519144889
Short name T578
Test name
Test status
Simulation time 36087806 ps
CPU time 2.44 seconds
Started Feb 21 02:58:28 PM PST 24
Finished Feb 21 02:58:31 PM PST 24
Peak memory 206396 kb
Host smart-4bc33077-2210-4ebb-ab18-9355d05ea92c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519144889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3519144889
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2463255177
Short name T655
Test name
Test status
Simulation time 252558558 ps
CPU time 7.37 seconds
Started Feb 21 02:58:19 PM PST 24
Finished Feb 21 02:58:27 PM PST 24
Peak memory 207780 kb
Host smart-0e3d81a3-5bf3-4036-a05e-63a6e446a417
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463255177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2463255177
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.738052408
Short name T272
Test name
Test status
Simulation time 729723706 ps
CPU time 5.56 seconds
Started Feb 21 02:58:14 PM PST 24
Finished Feb 21 02:58:20 PM PST 24
Peak memory 206788 kb
Host smart-1f880e31-2c53-444b-adbd-41b7bcee3bbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738052408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.738052408
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4237263099
Short name T869
Test name
Test status
Simulation time 83758919 ps
CPU time 1.82 seconds
Started Feb 21 02:58:11 PM PST 24
Finished Feb 21 02:58:14 PM PST 24
Peak memory 207744 kb
Host smart-678223b7-1d4d-49a8-86fc-073a0b034667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237263099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4237263099
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3727122063
Short name T576
Test name
Test status
Simulation time 152565458 ps
CPU time 4.24 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 206532 kb
Host smart-c5078001-5336-4f22-82c3-f8d5a4262fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727122063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3727122063
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3190537247
Short name T749
Test name
Test status
Simulation time 874729837 ps
CPU time 9.86 seconds
Started Feb 21 02:58:19 PM PST 24
Finished Feb 21 02:58:29 PM PST 24
Peak memory 215320 kb
Host smart-9016447e-bf59-4855-b99a-eedd8316cec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190537247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3190537247
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3683560127
Short name T386
Test name
Test status
Simulation time 380695710 ps
CPU time 4.42 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 207780 kb
Host smart-c5a885c4-6aba-4771-9976-cfc9bd93dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683560127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3683560127
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3575504413
Short name T154
Test name
Test status
Simulation time 100749387 ps
CPU time 2.7 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:20 PM PST 24
Peak memory 209588 kb
Host smart-c21d000c-4497-47ca-b871-7e80dad3f4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575504413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3575504413
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1110412121
Short name T414
Test name
Test status
Simulation time 54516845 ps
CPU time 0.78 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 205832 kb
Host smart-270e7a19-77fd-4e26-9049-d69b4b761ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110412121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1110412121
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3895258413
Short name T332
Test name
Test status
Simulation time 370648925 ps
CPU time 4.02 seconds
Started Feb 21 02:58:09 PM PST 24
Finished Feb 21 02:58:14 PM PST 24
Peak memory 214204 kb
Host smart-4974b99a-ea4b-4728-ba4e-17ba4076923f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895258413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3895258413
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2900390434
Short name T352
Test name
Test status
Simulation time 919560748 ps
CPU time 28.16 seconds
Started Feb 21 02:58:20 PM PST 24
Finished Feb 21 02:58:48 PM PST 24
Peak memory 209296 kb
Host smart-6637a5e3-5583-4401-aa4a-65078f61df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900390434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2900390434
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2123369739
Short name T693
Test name
Test status
Simulation time 484750351 ps
CPU time 7.46 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 208520 kb
Host smart-664f960d-ad46-4f98-a59d-d7c8523cbd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123369739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2123369739
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3717094752
Short name T60
Test name
Test status
Simulation time 245153432 ps
CPU time 5.09 seconds
Started Feb 21 02:58:15 PM PST 24
Finished Feb 21 02:58:21 PM PST 24
Peak memory 209312 kb
Host smart-dbc7598f-b5ee-4587-852a-8cf60f87d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717094752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3717094752
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1148155572
Short name T435
Test name
Test status
Simulation time 101603817 ps
CPU time 3.64 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:21 PM PST 24
Peak memory 207300 kb
Host smart-2444abee-1b3c-4f71-924a-ba28af4f5da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148155572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1148155572
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2291021868
Short name T880
Test name
Test status
Simulation time 310851623 ps
CPU time 2.7 seconds
Started Feb 21 02:58:19 PM PST 24
Finished Feb 21 02:58:22 PM PST 24
Peak memory 206552 kb
Host smart-8106513b-e7d9-4465-8a0c-7f68eee48e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291021868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2291021868
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4211272842
Short name T857
Test name
Test status
Simulation time 151306515 ps
CPU time 5.09 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:42 PM PST 24
Peak memory 207708 kb
Host smart-e5652a6d-c758-4b1f-8207-2e7a3d0f6cda
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211272842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4211272842
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1245346086
Short name T834
Test name
Test status
Simulation time 597582627 ps
CPU time 5.02 seconds
Started Feb 21 02:58:12 PM PST 24
Finished Feb 21 02:58:17 PM PST 24
Peak memory 208516 kb
Host smart-cf43e8ed-543b-45b5-bf88-ab9bc0fba3bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245346086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1245346086
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3976979774
Short name T209
Test name
Test status
Simulation time 300932844 ps
CPU time 6.77 seconds
Started Feb 21 02:58:17 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 208324 kb
Host smart-dc51a4a1-343f-4dd8-ab7e-aefb5fd1c94a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976979774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3976979774
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1618995923
Short name T71
Test name
Test status
Simulation time 730603426 ps
CPU time 3.22 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:36 PM PST 24
Peak memory 209348 kb
Host smart-9bb4d6f2-7e4f-46e4-a1db-7b854fe58c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618995923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1618995923
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1703607968
Short name T895
Test name
Test status
Simulation time 693240779 ps
CPU time 4.4 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 206572 kb
Host smart-df516a81-23e6-457a-9674-79a2e42ec334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703607968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1703607968
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.14899535
Short name T769
Test name
Test status
Simulation time 17577517011 ps
CPU time 167.6 seconds
Started Feb 21 02:58:21 PM PST 24
Finished Feb 21 03:01:09 PM PST 24
Peak memory 214172 kb
Host smart-6a3985a3-0d0b-42e2-836b-87bf1387bf08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14899535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.14899535
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.985402604
Short name T872
Test name
Test status
Simulation time 214672580 ps
CPU time 3.67 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:40 PM PST 24
Peak memory 209968 kb
Host smart-5b3c4e50-d202-488f-a7b7-c1f980a60ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985402604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.985402604
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1965628646
Short name T781
Test name
Test status
Simulation time 136388735 ps
CPU time 3.71 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:48 PM PST 24
Peak memory 209768 kb
Host smart-b735ad68-5fb5-4501-88c1-0f9a94c2e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965628646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1965628646
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3733871337
Short name T876
Test name
Test status
Simulation time 13879057 ps
CPU time 0.74 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:58:42 PM PST 24
Peak memory 205836 kb
Host smart-85eb65c0-faa6-46bc-9af2-07bec3be38aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733871337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3733871337
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1892349738
Short name T407
Test name
Test status
Simulation time 3779806171 ps
CPU time 98.06 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 03:00:12 PM PST 24
Peak memory 217544 kb
Host smart-109bcce1-fabc-49b0-b54e-f1b0d8dff2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892349738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1892349738
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3979868963
Short name T761
Test name
Test status
Simulation time 104278535 ps
CPU time 3.63 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:58:37 PM PST 24
Peak memory 209020 kb
Host smart-ce94f81d-7f40-4e3b-9228-f09ddb8ba55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979868963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3979868963
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3314069182
Short name T612
Test name
Test status
Simulation time 68753734 ps
CPU time 3.39 seconds
Started Feb 21 02:58:37 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 214184 kb
Host smart-3c824737-ae23-46d1-9cdb-4eeb79f42063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314069182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3314069182
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4050540127
Short name T342
Test name
Test status
Simulation time 2200862559 ps
CPU time 24.96 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:59:13 PM PST 24
Peak memory 214288 kb
Host smart-1e8efac8-82fb-4f25-a65b-4be3506af276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050540127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4050540127
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3073568996
Short name T216
Test name
Test status
Simulation time 139259741 ps
CPU time 3.52 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:47 PM PST 24
Peak memory 220300 kb
Host smart-bd26ac4b-73b1-4334-8f2f-d4f4010134cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073568996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3073568996
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2833971725
Short name T344
Test name
Test status
Simulation time 139229396 ps
CPU time 4.41 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 209308 kb
Host smart-6d123a7b-c787-450c-8120-c3e80519e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833971725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2833971725
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4278797453
Short name T572
Test name
Test status
Simulation time 199266907 ps
CPU time 6.42 seconds
Started Feb 21 02:58:37 PM PST 24
Finished Feb 21 02:58:44 PM PST 24
Peak memory 207380 kb
Host smart-7d127f77-34ef-4e3b-9649-604b5d4b3420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278797453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4278797453
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.746781926
Short name T339
Test name
Test status
Simulation time 119528308 ps
CPU time 3.25 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 207956 kb
Host smart-1382e25e-14dc-4f67-8d7d-6e3d449215e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746781926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.746781926
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1537325242
Short name T870
Test name
Test status
Simulation time 3936874590 ps
CPU time 27.98 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 208224 kb
Host smart-6a4fe530-f824-408d-9189-8ca7ec2fb2d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537325242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1537325242
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2384955313
Short name T269
Test name
Test status
Simulation time 222710766 ps
CPU time 7.04 seconds
Started Feb 21 02:58:45 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 206568 kb
Host smart-d24f25ce-84ba-4f69-a7d4-98533a5e53f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384955313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2384955313
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.421100303
Short name T461
Test name
Test status
Simulation time 140307072 ps
CPU time 2.39 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 215932 kb
Host smart-337948c3-e33c-48a7-9b14-19204e892bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421100303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.421100303
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1462450212
Short name T11
Test name
Test status
Simulation time 175633010 ps
CPU time 4.76 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 207908 kb
Host smart-497fba86-f3ce-4adf-9f66-7293bd98893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462450212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1462450212
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1477426394
Short name T69
Test name
Test status
Simulation time 15706189649 ps
CPU time 177.58 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 03:01:56 PM PST 24
Peak memory 222404 kb
Host smart-59e37d78-f2a1-495d-9f42-9316e5579548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477426394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1477426394
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.91386786
Short name T375
Test name
Test status
Simulation time 569567601 ps
CPU time 6.56 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 218236 kb
Host smart-5c0b12ef-5acd-42ec-8179-e5aaed6c5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91386786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.91386786
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.746438837
Short name T671
Test name
Test status
Simulation time 76222260 ps
CPU time 3.33 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 209540 kb
Host smart-40e36bdb-0264-4aa2-9f4b-3a124bfeb0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746438837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.746438837
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3738128790
Short name T412
Test name
Test status
Simulation time 66110721 ps
CPU time 0.93 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:19 PM PST 24
Peak memory 205992 kb
Host smart-dccd63db-3231-497f-bdf7-c50ab34cab31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738128790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3738128790
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1157920379
Short name T388
Test name
Test status
Simulation time 527523215 ps
CPU time 13.51 seconds
Started Feb 21 02:56:14 PM PST 24
Finished Feb 21 02:56:29 PM PST 24
Peak memory 214752 kb
Host smart-fc207c5b-a69e-4906-b371-fe7deb6b5183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157920379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1157920379
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2019439579
Short name T772
Test name
Test status
Simulation time 597641186 ps
CPU time 6.88 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:26 PM PST 24
Peak memory 208548 kb
Host smart-d234765f-e1fc-4384-b92b-e305419e570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019439579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2019439579
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.718721418
Short name T261
Test name
Test status
Simulation time 228345118 ps
CPU time 9.97 seconds
Started Feb 21 02:56:28 PM PST 24
Finished Feb 21 02:56:39 PM PST 24
Peak memory 222296 kb
Host smart-06e17863-98fa-4289-a34d-528897df226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718721418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.718721418
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2845903620
Short name T55
Test name
Test status
Simulation time 124796935 ps
CPU time 2.92 seconds
Started Feb 21 02:56:27 PM PST 24
Finished Feb 21 02:56:31 PM PST 24
Peak memory 219940 kb
Host smart-c7766a64-464c-4d7b-bd2c-fa899ffe594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845903620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2845903620
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1479430478
Short name T255
Test name
Test status
Simulation time 426034445 ps
CPU time 5.4 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:16 PM PST 24
Peak memory 210224 kb
Host smart-a97fecb7-a83c-47bc-ac9e-d72a098936eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479430478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1479430478
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2343839087
Short name T37
Test name
Test status
Simulation time 3443475418 ps
CPU time 24.64 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:50 PM PST 24
Peak memory 236328 kb
Host smart-8a0de20c-b50c-440d-8425-37f0d9d84df8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343839087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2343839087
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3364411234
Short name T456
Test name
Test status
Simulation time 164875089 ps
CPU time 4.77 seconds
Started Feb 21 02:56:18 PM PST 24
Finished Feb 21 02:56:24 PM PST 24
Peak memory 207672 kb
Host smart-40347f62-1d81-4f21-996d-ab8176a40814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364411234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3364411234
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2914188812
Short name T735
Test name
Test status
Simulation time 722891614 ps
CPU time 6.41 seconds
Started Feb 21 02:56:27 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 208200 kb
Host smart-2851c694-da53-4824-8c00-8a33a031cac5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914188812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2914188812
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.260449535
Short name T545
Test name
Test status
Simulation time 208243272 ps
CPU time 6.08 seconds
Started Feb 21 02:56:24 PM PST 24
Finished Feb 21 02:56:31 PM PST 24
Peak memory 207580 kb
Host smart-562d50f5-e882-411e-90a4-564bf7d001e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260449535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.260449535
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.279963734
Short name T774
Test name
Test status
Simulation time 205236667 ps
CPU time 2.54 seconds
Started Feb 21 02:56:19 PM PST 24
Finished Feb 21 02:56:23 PM PST 24
Peak memory 207956 kb
Host smart-4b3e6ece-718e-4c82-ba70-dfc11e1c300c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279963734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.279963734
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1740240603
Short name T434
Test name
Test status
Simulation time 72130715 ps
CPU time 2.11 seconds
Started Feb 21 02:56:10 PM PST 24
Finished Feb 21 02:56:13 PM PST 24
Peak memory 214200 kb
Host smart-591c5eb5-d5b5-48ed-807b-89aa1a875307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740240603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1740240603
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2617391400
Short name T452
Test name
Test status
Simulation time 153355736 ps
CPU time 4.1 seconds
Started Feb 21 02:56:21 PM PST 24
Finished Feb 21 02:56:26 PM PST 24
Peak memory 208424 kb
Host smart-c5da4de2-b711-4bf5-8105-9e2288bdce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617391400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2617391400
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1391485955
Short name T581
Test name
Test status
Simulation time 283749206 ps
CPU time 9.48 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 208416 kb
Host smart-539ec8a1-d754-4430-b047-e6252ad0483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391485955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1391485955
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2660547785
Short name T362
Test name
Test status
Simulation time 223580120 ps
CPU time 2.25 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:28 PM PST 24
Peak memory 209448 kb
Host smart-2ad078d0-89cd-4515-809a-4a58da974bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660547785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2660547785
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3169872660
Short name T513
Test name
Test status
Simulation time 51824196 ps
CPU time 0.78 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 205912 kb
Host smart-7157a429-473e-4c86-9d3b-9f91e0baa93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169872660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3169872660
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3590093982
Short name T753
Test name
Test status
Simulation time 51414483 ps
CPU time 4.16 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:48 PM PST 24
Peak memory 214836 kb
Host smart-855f959e-63cb-4a06-b1fb-d172181fdaf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590093982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3590093982
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1985156740
Short name T542
Test name
Test status
Simulation time 155872115 ps
CPU time 2.8 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 207184 kb
Host smart-98e03ae1-5372-4a9a-94a1-b227864deb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985156740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1985156740
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3857970869
Short name T262
Test name
Test status
Simulation time 588379891 ps
CPU time 4.27 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:52 PM PST 24
Peak memory 214220 kb
Host smart-8508625f-0804-4e63-961e-84059d12591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857970869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3857970869
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1223283463
Short name T846
Test name
Test status
Simulation time 106586444 ps
CPU time 4.05 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 209752 kb
Host smart-44e69c15-9bed-43ad-a010-c93e95611795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223283463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1223283463
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3614137260
Short name T200
Test name
Test status
Simulation time 42549747 ps
CPU time 2.78 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:47 PM PST 24
Peak memory 214224 kb
Host smart-b42e8bf2-eb09-4652-aa02-87af5228862e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614137260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3614137260
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1622273445
Short name T672
Test name
Test status
Simulation time 40132346 ps
CPU time 2.82 seconds
Started Feb 21 02:59:18 PM PST 24
Finished Feb 21 02:59:21 PM PST 24
Peak memory 208236 kb
Host smart-b4ceadbf-15e0-4cf2-b672-a9daee6003f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622273445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1622273445
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2089948379
Short name T580
Test name
Test status
Simulation time 488543772 ps
CPU time 16.55 seconds
Started Feb 21 02:58:45 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 207808 kb
Host smart-dcf118bd-084f-4a1e-9764-83829e82aaf7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089948379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2089948379
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3835592636
Short name T492
Test name
Test status
Simulation time 145588358 ps
CPU time 3.89 seconds
Started Feb 21 02:58:37 PM PST 24
Finished Feb 21 02:58:42 PM PST 24
Peak memory 206640 kb
Host smart-a5c1d0db-cbf4-4a28-b84d-c55d9165fb00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835592636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3835592636
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1531402350
Short name T591
Test name
Test status
Simulation time 411163715 ps
CPU time 2.75 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:58:44 PM PST 24
Peak memory 206532 kb
Host smart-aa4402df-8964-4d9b-8362-d0a914d7a8e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531402350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1531402350
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.164133255
Short name T183
Test name
Test status
Simulation time 65358390 ps
CPU time 2.05 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 207756 kb
Host smart-713489bb-fbfe-423f-a0d4-8d90c6ea8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164133255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.164133255
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1486192989
Short name T732
Test name
Test status
Simulation time 182818482 ps
CPU time 2.84 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 206516 kb
Host smart-59879a59-e480-41a7-b1ff-f3d300b28918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486192989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1486192989
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3048701036
Short name T303
Test name
Test status
Simulation time 383620757 ps
CPU time 5.29 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 214228 kb
Host smart-8baf10f4-4a8d-4067-a27c-6978d0e14fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048701036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3048701036
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2739793250
Short name T53
Test name
Test status
Simulation time 538265461 ps
CPU time 3.23 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 209940 kb
Host smart-9bae1921-6deb-4e6a-a81d-8c36076c37bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739793250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2739793250
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1446371529
Short name T625
Test name
Test status
Simulation time 48551876 ps
CPU time 0.85 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 205812 kb
Host smart-0eb03d21-4329-4250-aec6-519a4281fcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446371529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1446371529
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.409050419
Short name T368
Test name
Test status
Simulation time 131109552 ps
CPU time 2.78 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 214268 kb
Host smart-14d2aeb4-8ace-4c0f-a6e0-0bbcdc265569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409050419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.409050419
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3854308095
Short name T604
Test name
Test status
Simulation time 431674320 ps
CPU time 10.93 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 208236 kb
Host smart-3fe1e879-7376-4ab3-a524-08961f0a313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854308095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3854308095
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2997504591
Short name T720
Test name
Test status
Simulation time 201299812 ps
CPU time 5.75 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 209716 kb
Host smart-378bb7fb-60dc-4596-b317-a1a00eda0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997504591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2997504591
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3634711840
Short name T561
Test name
Test status
Simulation time 2400385200 ps
CPU time 23.27 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:20 PM PST 24
Peak memory 214136 kb
Host smart-1e57b984-b2cd-4b66-bc33-950332fb6b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634711840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3634711840
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3677147066
Short name T747
Test name
Test status
Simulation time 129104768 ps
CPU time 4.24 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 209452 kb
Host smart-4564cc14-d7ab-4bc8-81b9-84d1429c447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677147066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3677147066
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.429216771
Short name T763
Test name
Test status
Simulation time 1141059934 ps
CPU time 5.31 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 207388 kb
Host smart-a2650b97-1622-4c41-aea2-fdc04cd7ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429216771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.429216771
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2173485124
Short name T186
Test name
Test status
Simulation time 816972227 ps
CPU time 5.71 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 207652 kb
Host smart-08522886-4d10-4f3d-9fb9-7f28cf588134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173485124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2173485124
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2506842214
Short name T473
Test name
Test status
Simulation time 549080930 ps
CPU time 4.26 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 208344 kb
Host smart-9ac3e5fd-e98b-45fd-ba7f-36e46b5a1a68
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506842214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2506842214
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3286317110
Short name T813
Test name
Test status
Simulation time 2772746648 ps
CPU time 36.53 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:34 PM PST 24
Peak memory 208720 kb
Host smart-03eb3ca8-21bb-432c-a4f0-b56e03822a27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286317110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3286317110
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2963609745
Short name T789
Test name
Test status
Simulation time 54526990 ps
CPU time 3.04 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 206508 kb
Host smart-174b7f94-74c7-4cc4-a2bd-9044c57ce37c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963609745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2963609745
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2723284190
Short name T875
Test name
Test status
Simulation time 2402664707 ps
CPU time 30.71 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:28 PM PST 24
Peak memory 208764 kb
Host smart-f256ed0a-7587-4a60-84a0-36941175b42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723284190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2723284190
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2041507249
Short name T476
Test name
Test status
Simulation time 61346457 ps
CPU time 3.14 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 208312 kb
Host smart-b2b08a47-18e4-49da-a552-c102a22453e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041507249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2041507249
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.239282208
Short name T42
Test name
Test status
Simulation time 7438581965 ps
CPU time 37.33 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:37 PM PST 24
Peak memory 222464 kb
Host smart-159b786e-fc25-44b2-9425-972a6a78327e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239282208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.239282208
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3862839529
Short name T112
Test name
Test status
Simulation time 438739085 ps
CPU time 16.35 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:12 PM PST 24
Peak memory 222596 kb
Host smart-8c586a70-f55d-4825-af92-e6190538a72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862839529 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3862839529
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3670170430
Short name T714
Test name
Test status
Simulation time 46946792 ps
CPU time 3.01 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 206936 kb
Host smart-a102f52a-577b-42b5-921c-feefea3d67b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670170430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3670170430
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2939437796
Short name T424
Test name
Test status
Simulation time 131021791 ps
CPU time 1.95 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 209572 kb
Host smart-1c84b38a-3141-48a9-808a-331db7158a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939437796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2939437796
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4147005709
Short name T437
Test name
Test status
Simulation time 30776106 ps
CPU time 0.88 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:46 PM PST 24
Peak memory 206056 kb
Host smart-4a4335a2-79ce-4e47-b90f-10e8399cf74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147005709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4147005709
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2345159773
Short name T265
Test name
Test status
Simulation time 96896694 ps
CPU time 3.95 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 214240 kb
Host smart-8a5e29dc-2f5a-47a7-ac50-03604bc03f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345159773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2345159773
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2046070717
Short name T23
Test name
Test status
Simulation time 263280101 ps
CPU time 2.66 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 217736 kb
Host smart-0f0915da-d45d-476c-ae79-65fbc1644351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046070717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2046070717
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.301106804
Short name T257
Test name
Test status
Simulation time 132138999 ps
CPU time 2.41 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 207208 kb
Host smart-63f28b1b-2a09-46f5-982a-0c48a541e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301106804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.301106804
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.573517345
Short name T84
Test name
Test status
Simulation time 98089569 ps
CPU time 2.7 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 208716 kb
Host smart-e9b2832c-6f9c-46d9-8ce9-84430141fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573517345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.573517345
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3447926767
Short name T234
Test name
Test status
Simulation time 7245870381 ps
CPU time 58.95 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:57 PM PST 24
Peak memory 230900 kb
Host smart-dcca88a8-1ce9-40be-93ee-fabdc7f162c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447926767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3447926767
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4179387433
Short name T399
Test name
Test status
Simulation time 174175066 ps
CPU time 4.25 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 208884 kb
Host smart-33dbcbc0-f132-4886-ae8b-fe4a945bc760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179387433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4179387433
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4279622218
Short name T613
Test name
Test status
Simulation time 1627728236 ps
CPU time 52.1 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:52 PM PST 24
Peak memory 217256 kb
Host smart-99d24d48-d03c-4351-9287-e76a44346fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279622218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4279622218
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2144417021
Short name T893
Test name
Test status
Simulation time 396612125 ps
CPU time 7.62 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 207744 kb
Host smart-018117bb-d50c-4b84-b8e2-05deb33f03ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144417021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2144417021
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4240647948
Short name T606
Test name
Test status
Simulation time 55186895 ps
CPU time 2.24 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 208528 kb
Host smart-ae5a7a66-97ec-490e-8541-0f5e07c6e63f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240647948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4240647948
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1680851424
Short name T292
Test name
Test status
Simulation time 580480811 ps
CPU time 4.68 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 208188 kb
Host smart-6f07e375-de0c-40fc-9dfa-3511fc44502c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680851424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1680851424
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1267049537
Short name T784
Test name
Test status
Simulation time 311520254 ps
CPU time 3.88 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:40 PM PST 24
Peak memory 208300 kb
Host smart-a9d49f79-d483-4a98-befc-ce7b773eb790
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267049537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1267049537
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2041818008
Short name T319
Test name
Test status
Simulation time 28584187 ps
CPU time 2.41 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 218348 kb
Host smart-77d87a08-7d94-4cff-96b6-7d4f3a263e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041818008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2041818008
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3938988158
Short name T378
Test name
Test status
Simulation time 104247619 ps
CPU time 3.01 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 207016 kb
Host smart-b5f2ccbf-a60d-47cc-94d2-62cb201fe064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938988158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3938988158
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2642668902
Short name T12
Test name
Test status
Simulation time 5540913562 ps
CPU time 115.04 seconds
Started Feb 21 02:58:41 PM PST 24
Finished Feb 21 03:00:37 PM PST 24
Peak memory 208520 kb
Host smart-03ffd735-0d11-4e3b-8b3f-40b32ad5dca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642668902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2642668902
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3793569797
Short name T744
Test name
Test status
Simulation time 312882663 ps
CPU time 12.53 seconds
Started Feb 21 02:58:21 PM PST 24
Finished Feb 21 02:58:34 PM PST 24
Peak memory 220344 kb
Host smart-87d422b3-088c-4fcb-883b-dadb3093af8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793569797 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3793569797
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2296753166
Short name T204
Test name
Test status
Simulation time 215007978 ps
CPU time 9.15 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:10 PM PST 24
Peak memory 214244 kb
Host smart-a7297d16-a6e6-44e1-be40-579d0f8dfdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296753166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2296753166
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1505234336
Short name T539
Test name
Test status
Simulation time 48913716 ps
CPU time 2.55 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 209416 kb
Host smart-85157a3e-6e66-4dbe-a442-f060e030227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505234336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1505234336
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.125978779
Short name T415
Test name
Test status
Simulation time 9680655 ps
CPU time 0.8 seconds
Started Feb 21 02:58:36 PM PST 24
Finished Feb 21 02:58:38 PM PST 24
Peak memory 205900 kb
Host smart-ea0e5c36-c610-40d7-b72e-ce24b852fb88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125978779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.125978779
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3479806788
Short name T215
Test name
Test status
Simulation time 137800925 ps
CPU time 2.17 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 219324 kb
Host smart-4aa6b1f5-9166-476e-a4fb-1640038c1ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479806788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3479806788
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.813995395
Short name T504
Test name
Test status
Simulation time 598377025 ps
CPU time 16.51 seconds
Started Feb 21 02:58:25 PM PST 24
Finished Feb 21 02:58:42 PM PST 24
Peak memory 218424 kb
Host smart-01458f5c-a259-4c2d-9ed6-248fe038a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813995395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.813995395
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3223125238
Short name T85
Test name
Test status
Simulation time 302695701 ps
CPU time 5.2 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 222376 kb
Host smart-4255b2da-41f5-4014-b8c5-8e7c240ea155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223125238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3223125238
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.231482096
Short name T741
Test name
Test status
Simulation time 862536136 ps
CPU time 5.86 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 208396 kb
Host smart-3f429875-8952-4174-8cd5-7f6cef17fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231482096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.231482096
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1426804186
Short name T615
Test name
Test status
Simulation time 289358626 ps
CPU time 11.69 seconds
Started Feb 21 02:58:41 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 218352 kb
Host smart-b5d2de16-d994-46ce-a9fc-1e6d4762a563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426804186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1426804186
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3602203993
Short name T420
Test name
Test status
Simulation time 101750386 ps
CPU time 2.72 seconds
Started Feb 21 02:58:21 PM PST 24
Finished Feb 21 02:58:24 PM PST 24
Peak memory 206400 kb
Host smart-f33b1dcd-5f91-4db3-bc10-9ada76c1b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602203993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3602203993
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3218163405
Short name T77
Test name
Test status
Simulation time 411991787 ps
CPU time 2.97 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 206588 kb
Host smart-e4e603b0-3dd4-4d42-b3bb-111f908e0aca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218163405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3218163405
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3127364851
Short name T380
Test name
Test status
Simulation time 75424285 ps
CPU time 1.84 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 206664 kb
Host smart-3ecec74f-0417-43a8-82f4-a7d55811e98c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127364851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3127364851
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4283253336
Short name T794
Test name
Test status
Simulation time 70310850 ps
CPU time 3.21 seconds
Started Feb 21 02:58:41 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 206612 kb
Host smart-8f4981df-c429-48d9-88e6-b268e4a988e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283253336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4283253336
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1360953646
Short name T486
Test name
Test status
Simulation time 31331593 ps
CPU time 1.98 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:37 PM PST 24
Peak memory 206960 kb
Host smart-fe425b32-1ec4-4fc9-9143-702275265179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360953646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1360953646
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3378579413
Short name T521
Test name
Test status
Simulation time 21406480 ps
CPU time 1.88 seconds
Started Feb 21 02:58:34 PM PST 24
Finished Feb 21 02:58:37 PM PST 24
Peak memory 208140 kb
Host smart-e869c7c2-d5d5-49ae-b6e6-d960483113d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378579413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3378579413
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1092730301
Short name T740
Test name
Test status
Simulation time 1046431874 ps
CPU time 4.6 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 207752 kb
Host smart-8c810a06-a7a3-442b-b29c-52611edd8cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092730301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1092730301
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3484216708
Short name T652
Test name
Test status
Simulation time 427432422 ps
CPU time 2.55 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 209644 kb
Host smart-865a673c-6eb7-4eb3-bcf7-2edc08bd61cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484216708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3484216708
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3141085129
Short name T518
Test name
Test status
Simulation time 20778187 ps
CPU time 0.86 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 205904 kb
Host smart-5a8f02ca-0f5f-4a89-9d4b-f2cb54cc5028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141085129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3141085129
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3931448006
Short name T861
Test name
Test status
Simulation time 105671120 ps
CPU time 2.77 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 214152 kb
Host smart-9c11ae21-1e94-482b-98c6-d856afb452aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931448006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3931448006
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2291901229
Short name T397
Test name
Test status
Simulation time 206483150 ps
CPU time 5 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:58:46 PM PST 24
Peak memory 208552 kb
Host smart-421ead35-3876-4b27-b585-f5f651f1f26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291901229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2291901229
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2624107511
Short name T828
Test name
Test status
Simulation time 117713894 ps
CPU time 5.48 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 214232 kb
Host smart-7e54d8e6-cb8e-4dfd-b001-f82cb2e88ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624107511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2624107511
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.152622312
Short name T222
Test name
Test status
Simulation time 347758219 ps
CPU time 2.95 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:46 PM PST 24
Peak memory 219680 kb
Host smart-23ae37d1-44a7-4fdf-a861-6dd633ae9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152622312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.152622312
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1751462320
Short name T637
Test name
Test status
Simulation time 2609207622 ps
CPU time 9.07 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 208924 kb
Host smart-32f7254d-455c-4f9c-8436-25ef3e93fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751462320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1751462320
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.62267717
Short name T324
Test name
Test status
Simulation time 390027852 ps
CPU time 4.94 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 208272 kb
Host smart-f7cb0e06-e3ed-4c07-a6db-4d252799f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62267717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.62267717
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2087204454
Short name T729
Test name
Test status
Simulation time 147217465 ps
CPU time 2.56 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 206572 kb
Host smart-fcb7d79e-d441-471e-88e7-f1d3aa41ce98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087204454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2087204454
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.376203825
Short name T350
Test name
Test status
Simulation time 108583767 ps
CPU time 2.49 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 206516 kb
Host smart-85c3b03a-99fd-49f9-aba2-17bcb174f4e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376203825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.376203825
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1307294867
Short name T97
Test name
Test status
Simulation time 2655768743 ps
CPU time 23.87 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 208176 kb
Host smart-a7747f75-ebc2-4b60-92bd-d6044c795f35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307294867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1307294867
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3429759256
Short name T496
Test name
Test status
Simulation time 11465428612 ps
CPU time 25.94 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:59:14 PM PST 24
Peak memory 216452 kb
Host smart-b8d701e2-0eb7-473d-8bc7-e1ccf3d8ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429759256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3429759256
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3936998737
Short name T185
Test name
Test status
Simulation time 886744472 ps
CPU time 6.06 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 206556 kb
Host smart-f2f0b1eb-8dd4-41c5-aeba-bf020257450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936998737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3936998737
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2648673603
Short name T266
Test name
Test status
Simulation time 1381930218 ps
CPU time 36.38 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:59:27 PM PST 24
Peak memory 214264 kb
Host smart-59597daf-d0d7-4af6-90bd-b0e3484b1a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648673603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2648673603
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.239036711
Short name T597
Test name
Test status
Simulation time 260685670 ps
CPU time 1.81 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 210072 kb
Host smart-428370b7-2b23-4494-9873-688bbe32be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239036711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.239036711
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3812436577
Short name T417
Test name
Test status
Simulation time 42516689 ps
CPU time 0.87 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 205856 kb
Host smart-c8ceabd9-08cf-41af-a365-5ac6f08909ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812436577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3812436577
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.540201141
Short name T408
Test name
Test status
Simulation time 191319903 ps
CPU time 4.05 seconds
Started Feb 21 02:58:35 PM PST 24
Finished Feb 21 02:58:39 PM PST 24
Peak memory 214216 kb
Host smart-565e3975-4547-49c2-8b22-460b05e8124c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540201141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.540201141
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1789379546
Short name T817
Test name
Test status
Simulation time 54928304 ps
CPU time 2.31 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:47 PM PST 24
Peak memory 208500 kb
Host smart-1e50b0d1-0964-4bb6-9cd2-ac5260de9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789379546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1789379546
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3279392289
Short name T845
Test name
Test status
Simulation time 484031221 ps
CPU time 1.76 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 208080 kb
Host smart-14e346f5-3794-4ff9-afb4-3f0539bb84ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279392289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3279392289
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1671285512
Short name T370
Test name
Test status
Simulation time 399977523 ps
CPU time 7.62 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 208896 kb
Host smart-09a5048a-8050-47e7-a9c8-1b7223215545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671285512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1671285512
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1432628643
Short name T493
Test name
Test status
Simulation time 143517555 ps
CPU time 3.66 seconds
Started Feb 21 02:58:43 PM PST 24
Finished Feb 21 02:58:47 PM PST 24
Peak memory 216320 kb
Host smart-caea5e7c-da9f-402a-b8da-7cdc75f0846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432628643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1432628643
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2540528040
Short name T871
Test name
Test status
Simulation time 186573285 ps
CPU time 6.47 seconds
Started Feb 21 02:58:34 PM PST 24
Finished Feb 21 02:58:41 PM PST 24
Peak memory 209012 kb
Host smart-1eb55d21-243b-4896-b3cc-2bb4c4aa098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540528040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2540528040
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2607069990
Short name T508
Test name
Test status
Simulation time 879254095 ps
CPU time 7.09 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 207596 kb
Host smart-d71c41ac-f53f-4bac-8165-09e02ad1c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607069990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2607069990
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.167070318
Short name T201
Test name
Test status
Simulation time 3081428358 ps
CPU time 55.9 seconds
Started Feb 21 02:58:33 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 208812 kb
Host smart-6ca2d821-19a8-4424-9d88-33bdbe3ed26c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167070318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.167070318
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.91210059
Short name T95
Test name
Test status
Simulation time 2129277279 ps
CPU time 50.74 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:45 PM PST 24
Peak memory 208616 kb
Host smart-a0b3507a-6f55-4e80-9350-61b1a4de75dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91210059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.91210059
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3524641657
Short name T553
Test name
Test status
Simulation time 212710444 ps
CPU time 6.02 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 207552 kb
Host smart-95c275b5-3bf3-4508-9195-6343413c700b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524641657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3524641657
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.488015993
Short name T664
Test name
Test status
Simulation time 28537515 ps
CPU time 1.52 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 213784 kb
Host smart-40acef96-5d83-4893-be0c-3e1d5933403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488015993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.488015993
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2015839054
Short name T466
Test name
Test status
Simulation time 141677560 ps
CPU time 2.17 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:48 PM PST 24
Peak memory 206232 kb
Host smart-19396ea7-1c3f-406b-9ac2-ab16956cea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015839054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2015839054
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.762608533
Short name T293
Test name
Test status
Simulation time 264138275 ps
CPU time 3.68 seconds
Started Feb 21 02:58:40 PM PST 24
Finished Feb 21 02:58:45 PM PST 24
Peak memory 207164 kb
Host smart-a6751d05-7427-4eb8-8e15-c5c27ddc1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762608533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.762608533
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4075379755
Short name T143
Test name
Test status
Simulation time 268398327 ps
CPU time 2.18 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 209824 kb
Host smart-4c3434a9-ac9e-481e-8e4f-eb9d7344cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075379755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4075379755
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.442882623
Short name T567
Test name
Test status
Simulation time 52938639 ps
CPU time 0.86 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 205836 kb
Host smart-5832a92e-f5f5-4d76-9c2e-00439ef313b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442882623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.442882623
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1201246572
Short name T787
Test name
Test status
Simulation time 175905528 ps
CPU time 5.73 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 214516 kb
Host smart-1f4fdc80-51b5-47ca-a985-e495f8bda21d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201246572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1201246572
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2039162999
Short name T890
Test name
Test status
Simulation time 176648757 ps
CPU time 4.86 seconds
Started Feb 21 02:58:57 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 221176 kb
Host smart-b62bfffd-756d-449f-a42f-99025f8d93b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039162999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2039162999
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1839261222
Short name T577
Test name
Test status
Simulation time 46639923 ps
CPU time 1.52 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 207180 kb
Host smart-5e0e984d-5186-478a-8994-454b4f18c108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839261222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1839261222
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1334024978
Short name T824
Test name
Test status
Simulation time 442084092 ps
CPU time 5.21 seconds
Started Feb 21 02:58:45 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 208444 kb
Host smart-fcbe51b2-5a23-4efc-a0bd-62a4d6289651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334024978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1334024978
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1394473113
Short name T196
Test name
Test status
Simulation time 260676546 ps
CPU time 5.03 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 222508 kb
Host smart-2795bd41-c53f-4cfd-b003-83647df112a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394473113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1394473113
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.650383906
Short name T603
Test name
Test status
Simulation time 64723490 ps
CPU time 3.52 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 207456 kb
Host smart-36966b67-f807-4fc2-a131-3ced63e64b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650383906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.650383906
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3268428829
Short name T558
Test name
Test status
Simulation time 4307605614 ps
CPU time 24.29 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:25 PM PST 24
Peak memory 218400 kb
Host smart-0b953cf8-b8fc-4f8b-87a2-2da83701ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268428829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3268428829
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2842014889
Short name T509
Test name
Test status
Simulation time 22346310 ps
CPU time 1.82 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 206940 kb
Host smart-7ef41bbc-8a73-46c5-a24c-4916b34394b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842014889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2842014889
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4197501269
Short name T820
Test name
Test status
Simulation time 80958556 ps
CPU time 2.8 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 207120 kb
Host smart-5c1999fc-206a-4960-bd2e-3e8425488333
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197501269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4197501269
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3805954181
Short name T422
Test name
Test status
Simulation time 318701260 ps
CPU time 3.4 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 206512 kb
Host smart-5c0ff717-a003-42f9-94e3-631f1b6a6b15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805954181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3805954181
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.468479073
Short name T599
Test name
Test status
Simulation time 945763980 ps
CPU time 23.69 seconds
Started Feb 21 02:59:04 PM PST 24
Finished Feb 21 02:59:29 PM PST 24
Peak memory 207760 kb
Host smart-5856696d-a7b9-45e1-8c28-2ceccebded09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468479073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.468479073
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2513643280
Short name T609
Test name
Test status
Simulation time 220709689 ps
CPU time 3.18 seconds
Started Feb 21 02:58:55 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 209300 kb
Host smart-b0ce2f36-ea62-4c27-b179-7ad53989e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513643280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2513643280
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1144707780
Short name T197
Test name
Test status
Simulation time 137024355 ps
CPU time 2.19 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 208168 kb
Host smart-a1316df0-5f46-4bd4-a69d-0a07c77ea1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144707780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1144707780
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1575012182
Short name T45
Test name
Test status
Simulation time 83780280 ps
CPU time 4.08 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:05 PM PST 24
Peak memory 215384 kb
Host smart-983c4b9b-ec75-4610-bb0a-46e3feac4062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575012182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1575012182
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2208191490
Short name T843
Test name
Test status
Simulation time 65155334 ps
CPU time 4.12 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:08 PM PST 24
Peak memory 209800 kb
Host smart-a0439f26-f4d5-4401-9d83-544679aa933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208191490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2208191490
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2397768679
Short name T190
Test name
Test status
Simulation time 81540770 ps
CPU time 2.21 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 209592 kb
Host smart-eed24a17-961d-4d8b-a0cb-c59601bdb2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397768679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2397768679
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.430827434
Short name T467
Test name
Test status
Simulation time 36434465 ps
CPU time 0.75 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 205308 kb
Host smart-e24ed934-d95c-4df5-a438-4e01c5e30660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430827434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.430827434
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1986888392
Short name T762
Test name
Test status
Simulation time 71253142 ps
CPU time 4.97 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 214148 kb
Host smart-e0e93834-72db-4735-a1a9-e4e5f4a53e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986888392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1986888392
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.319057067
Short name T21
Test name
Test status
Simulation time 1488750624 ps
CPU time 51.12 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 209300 kb
Host smart-81c36516-3aaa-48c4-a7da-42fa1d617dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319057067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.319057067
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2194297389
Short name T738
Test name
Test status
Simulation time 470650666 ps
CPU time 2.37 seconds
Started Feb 21 02:59:02 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 214292 kb
Host smart-b6cbf3f9-7b8f-4593-863c-99369a65270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194297389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2194297389
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4196716129
Short name T644
Test name
Test status
Simulation time 121445434 ps
CPU time 5.29 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 209360 kb
Host smart-e1f39634-86a3-44ec-9064-44b32c58e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196716129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4196716129
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3693089315
Short name T841
Test name
Test status
Simulation time 2012557307 ps
CPU time 15.78 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:18 PM PST 24
Peak memory 214188 kb
Host smart-bba76b6d-caf2-49d0-92b9-212631c0e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693089315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3693089315
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1968235286
Short name T798
Test name
Test status
Simulation time 147248522 ps
CPU time 2.59 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 219372 kb
Host smart-8f95b651-35ba-4d77-ad7f-07fa4550f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968235286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1968235286
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1172627244
Short name T701
Test name
Test status
Simulation time 351364030 ps
CPU time 3.8 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 206824 kb
Host smart-f387fc7a-c208-4cd0-850f-76ff99b3c521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172627244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1172627244
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2012250194
Short name T263
Test name
Test status
Simulation time 1701254016 ps
CPU time 10.12 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:11 PM PST 24
Peak memory 208208 kb
Host smart-8c18651b-03f3-45ab-b9cb-a60f579d1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012250194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2012250194
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3560844454
Short name T782
Test name
Test status
Simulation time 226290940 ps
CPU time 6.36 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 208296 kb
Host smart-f1371c02-5be1-498a-acec-fe0824b1836e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560844454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3560844454
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3246898930
Short name T546
Test name
Test status
Simulation time 85177313 ps
CPU time 3.18 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 206612 kb
Host smart-b56a95c2-2fde-4aae-baa7-4fc3d019ede3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246898930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3246898930
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2379007994
Short name T661
Test name
Test status
Simulation time 70317095 ps
CPU time 3.57 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 208332 kb
Host smart-f328a7eb-939d-4c13-9da3-ad498012bbf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379007994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2379007994
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1317369676
Short name T446
Test name
Test status
Simulation time 102458153 ps
CPU time 3.36 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 208484 kb
Host smart-c224ae39-94f8-47e6-8b1a-6cbed34dac2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317369676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1317369676
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2642311869
Short name T682
Test name
Test status
Simulation time 247942706 ps
CPU time 3.38 seconds
Started Feb 21 02:58:59 PM PST 24
Finished Feb 21 02:59:03 PM PST 24
Peak memory 206560 kb
Host smart-aa192b1c-b071-4cee-bb04-005eb5c41906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642311869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2642311869
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.353594143
Short name T207
Test name
Test status
Simulation time 104557422 ps
CPU time 3.6 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 208252 kb
Host smart-125f37cb-81fb-4977-93c9-febef92e4c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353594143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.353594143
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.232454401
Short name T194
Test name
Test status
Simulation time 188627390 ps
CPU time 7.72 seconds
Started Feb 21 02:59:03 PM PST 24
Finished Feb 21 02:59:11 PM PST 24
Peak memory 207796 kb
Host smart-65296cde-db69-4220-a36e-b5fff105fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232454401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.232454401
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3011880190
Short name T512
Test name
Test status
Simulation time 234159516 ps
CPU time 2.38 seconds
Started Feb 21 02:58:56 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 209692 kb
Host smart-c28390b8-c0de-43c7-866b-b18ef2a614b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011880190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3011880190
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4174539416
Short name T74
Test name
Test status
Simulation time 36648022 ps
CPU time 0.91 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 205892 kb
Host smart-d7de7245-18dc-438f-95dd-b68dd45e9273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174539416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4174539416
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4198831638
Short name T34
Test name
Test status
Simulation time 317634088 ps
CPU time 4.64 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:59 PM PST 24
Peak memory 209272 kb
Host smart-87e1d3d1-c9b1-48d1-bb0e-86cc9ddf5b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198831638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4198831638
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.177994845
Short name T556
Test name
Test status
Simulation time 66436758 ps
CPU time 3.2 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 218032 kb
Host smart-381b7020-12f1-4135-89d8-3ea62017cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177994845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.177994845
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3765332909
Short name T547
Test name
Test status
Simulation time 1857423111 ps
CPU time 7.57 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 209156 kb
Host smart-37cc2b96-819e-44c5-8199-da9f70a83a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765332909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3765332909
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2954103542
Short name T338
Test name
Test status
Simulation time 569008060 ps
CPU time 5.65 seconds
Started Feb 21 02:58:42 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 210304 kb
Host smart-7a3abf78-9032-4176-8442-c4967d496a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954103542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2954103542
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4244261123
Short name T569
Test name
Test status
Simulation time 411465136 ps
CPU time 3.35 seconds
Started Feb 21 02:58:49 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 215260 kb
Host smart-6c54bef9-a93e-4310-be19-1fd2a23a22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244261123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4244261123
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1102856360
Short name T310
Test name
Test status
Simulation time 629697646 ps
CPU time 4.75 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 206692 kb
Host smart-b2b614d2-9df7-4895-aa80-d50f83fff3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102856360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1102856360
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2582444178
Short name T267
Test name
Test status
Simulation time 479621330 ps
CPU time 3.61 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 206412 kb
Host smart-56d10abc-c56a-41dc-9d87-7a1bde367e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582444178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2582444178
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3807027919
Short name T775
Test name
Test status
Simulation time 103606038 ps
CPU time 2.41 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:55 PM PST 24
Peak memory 206280 kb
Host smart-74cfabe9-514c-44d9-bce7-1a628d8b9de9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807027919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3807027919
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2558173596
Short name T470
Test name
Test status
Simulation time 127850958 ps
CPU time 2.52 seconds
Started Feb 21 02:58:48 PM PST 24
Finished Feb 21 02:58:50 PM PST 24
Peak memory 206864 kb
Host smart-3d49660e-aa34-4e91-a088-9cdd587669c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558173596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2558173596
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3154748971
Short name T182
Test name
Test status
Simulation time 71920226 ps
CPU time 3.57 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:56 PM PST 24
Peak memory 207716 kb
Host smart-8d410d3f-5118-4175-8b6f-4a4939ccb7de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154748971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3154748971
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3333305992
Short name T802
Test name
Test status
Simulation time 545585029 ps
CPU time 5 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 222332 kb
Host smart-38baa158-ca14-431d-a880-9639045454c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333305992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3333305992
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2235105141
Short name T488
Test name
Test status
Simulation time 62600519 ps
CPU time 2.26 seconds
Started Feb 21 02:58:45 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 206580 kb
Host smart-4f22cb68-3200-4394-a876-91be77a6e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235105141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2235105141
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.4021719370
Short name T882
Test name
Test status
Simulation time 141335572 ps
CPU time 4.44 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:49 PM PST 24
Peak memory 207272 kb
Host smart-23b6aca4-721e-443b-a3d3-7158eee0c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021719370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4021719370
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1914102548
Short name T626
Test name
Test status
Simulation time 33134843 ps
CPU time 1.97 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 209324 kb
Host smart-395c6e28-9bef-427b-87f1-bc199c62225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914102548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1914102548
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2456867214
Short name T517
Test name
Test status
Simulation time 15811772 ps
CPU time 1 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 205660 kb
Host smart-b5e66294-41cd-4e43-9c50-aa2b50bd47ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456867214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2456867214
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3709552597
Short name T390
Test name
Test status
Simulation time 134376948 ps
CPU time 4.73 seconds
Started Feb 21 02:58:47 PM PST 24
Finished Feb 21 02:58:52 PM PST 24
Peak memory 214224 kb
Host smart-6f66c67a-f5da-4f47-9825-83327d4b0c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709552597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3709552597
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1250269525
Short name T678
Test name
Test status
Simulation time 1220569889 ps
CPU time 7.71 seconds
Started Feb 21 02:59:01 PM PST 24
Finished Feb 21 02:59:09 PM PST 24
Peak memory 214256 kb
Host smart-0d7c44cb-5957-4705-822b-a73b3ed2ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250269525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1250269525
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.770634016
Short name T448
Test name
Test status
Simulation time 478720163 ps
CPU time 3.43 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 207392 kb
Host smart-7f0ed6ca-ed38-4e42-b89a-df93d3c4db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770634016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.770634016
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3276616876
Short name T371
Test name
Test status
Simulation time 466300860 ps
CPU time 5.71 seconds
Started Feb 21 02:58:51 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 214272 kb
Host smart-e9926d43-67e4-4d54-b309-8193b9c3b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276616876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3276616876
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.95401692
Short name T755
Test name
Test status
Simulation time 1191359810 ps
CPU time 7.41 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:59:00 PM PST 24
Peak memory 222340 kb
Host smart-a9efdc40-e9f0-4142-a259-97f179912999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95401692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.95401692
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.907981276
Short name T295
Test name
Test status
Simulation time 63624671 ps
CPU time 3.64 seconds
Started Feb 21 02:58:52 PM PST 24
Finished Feb 21 02:58:57 PM PST 24
Peak memory 209252 kb
Host smart-0f21c19d-52f1-4dbc-b1d5-db80a06e987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907981276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.907981276
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3712506455
Short name T669
Test name
Test status
Simulation time 289309509 ps
CPU time 7.74 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 207228 kb
Host smart-a1cb0af4-d7b5-41ca-9aa8-543041be65f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712506455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3712506455
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3386045600
Short name T438
Test name
Test status
Simulation time 756552966 ps
CPU time 6.62 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:06 PM PST 24
Peak memory 207436 kb
Host smart-74b74c41-6182-46fd-b1ce-fa4c7e153c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386045600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3386045600
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2618120733
Short name T691
Test name
Test status
Simulation time 186095642 ps
CPU time 6.1 seconds
Started Feb 21 02:58:44 PM PST 24
Finished Feb 21 02:58:52 PM PST 24
Peak memory 207564 kb
Host smart-44d0a4ca-169e-4d00-969b-62f13f5b19b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618120733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2618120733
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3716272808
Short name T381
Test name
Test status
Simulation time 80857309 ps
CPU time 1.88 seconds
Started Feb 21 02:58:58 PM PST 24
Finished Feb 21 02:59:01 PM PST 24
Peak memory 206976 kb
Host smart-5b1f4640-ddf7-404f-b725-35dc165adb1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716272808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3716272808
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1452188270
Short name T474
Test name
Test status
Simulation time 162395246 ps
CPU time 5.09 seconds
Started Feb 21 02:58:45 PM PST 24
Finished Feb 21 02:58:51 PM PST 24
Peak memory 208272 kb
Host smart-df351f0f-dccb-400f-ad7c-c795f972f06a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452188270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1452188270
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3265172669
Short name T199
Test name
Test status
Simulation time 97225487 ps
CPU time 4.18 seconds
Started Feb 21 02:59:00 PM PST 24
Finished Feb 21 02:59:04 PM PST 24
Peak memory 209488 kb
Host smart-c3a8dc47-fd6e-4e73-9094-3ad6e9e8885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265172669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3265172669
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2845754315
Short name T815
Test name
Test status
Simulation time 343584968 ps
CPU time 6.59 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:58:54 PM PST 24
Peak memory 206536 kb
Host smart-064dcb41-757c-4454-94db-b622d1336c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845754315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2845754315
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.963338314
Short name T805
Test name
Test status
Simulation time 1335634900 ps
CPU time 8.89 seconds
Started Feb 21 02:58:53 PM PST 24
Finished Feb 21 02:59:02 PM PST 24
Peak memory 209612 kb
Host smart-054268a1-ecb1-476e-868f-a59f2346e7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963338314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.963338314
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3315447755
Short name T593
Test name
Test status
Simulation time 862248503 ps
CPU time 20 seconds
Started Feb 21 02:58:46 PM PST 24
Finished Feb 21 02:59:07 PM PST 24
Peak memory 208040 kb
Host smart-6d88798a-38dd-4565-85d2-04c8e7513052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315447755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3315447755
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3244641369
Short name T148
Test name
Test status
Simulation time 246379095 ps
CPU time 3.08 seconds
Started Feb 21 02:58:50 PM PST 24
Finished Feb 21 02:58:53 PM PST 24
Peak memory 209684 kb
Host smart-41e265d7-7338-4d75-a2be-862fbe2ee653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244641369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3244641369
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3719821660
Short name T548
Test name
Test status
Simulation time 13983165 ps
CPU time 0.83 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 205948 kb
Host smart-e1e21124-e66f-449f-8db5-f4e0efda69b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719821660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3719821660
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2416738116
Short name T392
Test name
Test status
Simulation time 1505109832 ps
CPU time 78.67 seconds
Started Feb 21 02:56:27 PM PST 24
Finished Feb 21 02:57:47 PM PST 24
Peak memory 218128 kb
Host smart-3b14a3f0-97f2-48f3-ae33-dc736fa972ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416738116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2416738116
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2902498341
Short name T18
Test name
Test status
Simulation time 893732612 ps
CPU time 3.14 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:38 PM PST 24
Peak memory 214684 kb
Host smart-8bd96640-04b4-4b4a-8f8d-1e558a552fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902498341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2902498341
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.113620585
Short name T810
Test name
Test status
Simulation time 166074313 ps
CPU time 1.97 seconds
Started Feb 21 02:56:30 PM PST 24
Finished Feb 21 02:56:32 PM PST 24
Peak memory 207048 kb
Host smart-6f4aa77d-0533-4f56-ac40-65319b23ccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113620585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.113620585
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2468478063
Short name T369
Test name
Test status
Simulation time 118869994 ps
CPU time 4.18 seconds
Started Feb 21 02:56:30 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 214168 kb
Host smart-232858b2-1174-4633-affe-0fa1f5c30f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468478063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2468478063
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2656598489
Short name T860
Test name
Test status
Simulation time 1086200251 ps
CPU time 8.19 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 210508 kb
Host smart-9a87fa87-3592-48f9-a9b5-c452f8162373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656598489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2656598489
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1943113395
Short name T491
Test name
Test status
Simulation time 197289163 ps
CPU time 2.73 seconds
Started Feb 21 02:56:30 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 214240 kb
Host smart-f35dc6c1-192b-4c33-b1ca-51dbaf375e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943113395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1943113395
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3668929654
Short name T385
Test name
Test status
Simulation time 240136987 ps
CPU time 3.35 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:22 PM PST 24
Peak memory 207300 kb
Host smart-031b8c3d-96fe-4c10-bf6d-c925327a5185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668929654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3668929654
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2370863612
Short name T533
Test name
Test status
Simulation time 200658127 ps
CPU time 3 seconds
Started Feb 21 02:56:29 PM PST 24
Finished Feb 21 02:56:32 PM PST 24
Peak memory 206572 kb
Host smart-ce23c419-49f1-4b4f-9ed5-4b4fb166f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370863612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2370863612
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2682619938
Short name T480
Test name
Test status
Simulation time 300370096 ps
CPU time 3.27 seconds
Started Feb 21 02:56:22 PM PST 24
Finished Feb 21 02:56:26 PM PST 24
Peak memory 208356 kb
Host smart-231538d3-b53e-43b1-9529-228fcda1860c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682619938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2682619938
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2181571731
Short name T376
Test name
Test status
Simulation time 97675108 ps
CPU time 2.41 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:28 PM PST 24
Peak memory 206648 kb
Host smart-2bbe7c48-7dd7-43ef-aa57-fa5a45917060
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181571731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2181571731
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.492435614
Short name T331
Test name
Test status
Simulation time 123037920 ps
CPU time 3.62 seconds
Started Feb 21 02:56:17 PM PST 24
Finished Feb 21 02:56:21 PM PST 24
Peak memory 206916 kb
Host smart-fbe600aa-2faa-4f37-8aae-b9024b362997
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492435614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.492435614
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.955897095
Short name T579
Test name
Test status
Simulation time 199917417 ps
CPU time 4.99 seconds
Started Feb 21 02:56:43 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 218236 kb
Host smart-b59b96c6-70ef-495d-817c-f7bb764e2cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955897095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.955897095
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1422133296
Short name T455
Test name
Test status
Simulation time 20834548 ps
CPU time 1.7 seconds
Started Feb 21 02:56:25 PM PST 24
Finished Feb 21 02:56:27 PM PST 24
Peak memory 207144 kb
Host smart-9d7d1f38-6d57-4d9e-9b1c-f11567409a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422133296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1422133296
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.918912661
Short name T285
Test name
Test status
Simulation time 2279509678 ps
CPU time 77.64 seconds
Started Feb 21 02:56:44 PM PST 24
Finished Feb 21 02:58:02 PM PST 24
Peak memory 214764 kb
Host smart-e0b30570-67cf-4fd0-817d-aa79a185cf55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918912661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.918912661
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4091431610
Short name T40
Test name
Test status
Simulation time 256177970 ps
CPU time 8.16 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 222448 kb
Host smart-9f22c31a-8e69-48a8-88c0-6ff506dc7e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091431610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4091431610
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.644499135
Short name T15
Test name
Test status
Simulation time 632447277 ps
CPU time 8.87 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 207300 kb
Host smart-d13b4a38-2e2d-46a5-91bf-fcb68a159fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644499135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.644499135
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.110635214
Short name T161
Test name
Test status
Simulation time 34057100 ps
CPU time 1.92 seconds
Started Feb 21 02:56:30 PM PST 24
Finished Feb 21 02:56:32 PM PST 24
Peak memory 209452 kb
Host smart-19126865-20c5-4bb2-b92e-2f30200a9b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110635214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.110635214
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3540277969
Short name T596
Test name
Test status
Simulation time 20073952 ps
CPU time 0.85 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:38 PM PST 24
Peak memory 205916 kb
Host smart-bc474c09-0a0a-4564-a827-e9e0a43e9365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540277969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3540277969
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.295999041
Short name T823
Test name
Test status
Simulation time 90846800 ps
CPU time 2.73 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 218124 kb
Host smart-3a1b1416-2666-4685-adfa-2b89386fc032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295999041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.295999041
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2251996013
Short name T478
Test name
Test status
Simulation time 764162842 ps
CPU time 9.08 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 214184 kb
Host smart-9d8d3c99-d367-4eb9-82f8-c963521d5e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251996013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2251996013
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4056596903
Short name T312
Test name
Test status
Simulation time 280860925 ps
CPU time 8.57 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 211004 kb
Host smart-85eb8aaf-d9a5-4020-9214-118f4ec2d55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056596903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4056596903
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4090846068
Short name T585
Test name
Test status
Simulation time 228334799 ps
CPU time 3.78 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 208696 kb
Host smart-c646d00a-32b7-4a11-90b7-460ab20eff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090846068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4090846068
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3578503492
Short name T244
Test name
Test status
Simulation time 227632973 ps
CPU time 4.48 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 214176 kb
Host smart-e0993f8d-8399-4734-8f3f-de77c7e91ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578503492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3578503492
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.800717754
Short name T277
Test name
Test status
Simulation time 134262213 ps
CPU time 3.02 seconds
Started Feb 21 02:56:44 PM PST 24
Finished Feb 21 02:56:47 PM PST 24
Peak memory 207184 kb
Host smart-181ac384-630a-4830-b9f1-69b4453871ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800717754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.800717754
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.233311320
Short name T280
Test name
Test status
Simulation time 112701727 ps
CPU time 3.43 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 208880 kb
Host smart-1e1a9c81-9224-4bef-a658-eb7009eb68d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233311320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.233311320
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.383136887
Short name T768
Test name
Test status
Simulation time 233151404 ps
CPU time 8.16 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 208364 kb
Host smart-161fb500-d492-44cf-86a9-d596d09a86b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383136887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.383136887
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2546153050
Short name T506
Test name
Test status
Simulation time 15530068038 ps
CPU time 84.69 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:57:56 PM PST 24
Peak memory 208832 kb
Host smart-2cccb3fd-3436-4459-80c1-4ebcc1a3c48a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546153050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2546153050
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2917288824
Short name T346
Test name
Test status
Simulation time 209644047 ps
CPU time 3.4 seconds
Started Feb 21 02:56:29 PM PST 24
Finished Feb 21 02:56:32 PM PST 24
Peak memory 207308 kb
Host smart-8588a6cd-f649-41e9-933c-0d563670adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917288824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2917288824
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3495879948
Short name T621
Test name
Test status
Simulation time 340952647 ps
CPU time 3.63 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 208180 kb
Host smart-de5c6935-8fc6-486c-b6bd-247dc6f1d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495879948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3495879948
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.903134978
Short name T287
Test name
Test status
Simulation time 404976703 ps
CPU time 5.21 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 210316 kb
Host smart-b04f5e9f-eef6-427f-adf6-c2e0fa2adbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903134978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.903134978
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1929209634
Short name T366
Test name
Test status
Simulation time 282869612 ps
CPU time 1.83 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 208284 kb
Host smart-af3f72cb-3a69-4201-8d4c-567fd4aef291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929209634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1929209634
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.669464495
Short name T479
Test name
Test status
Simulation time 57251430 ps
CPU time 0.82 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 205892 kb
Host smart-cbe68d07-4834-4dba-a6ce-d4175bfbeef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669464495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.669464495
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1371278802
Short name T321
Test name
Test status
Simulation time 61183806 ps
CPU time 3.41 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:38 PM PST 24
Peak memory 214512 kb
Host smart-8371e8d7-050d-4bbd-9d6f-85d89b628077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371278802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1371278802
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2466487596
Short name T7
Test name
Test status
Simulation time 49338994 ps
CPU time 1.95 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 214696 kb
Host smart-4b9e9940-5bba-403a-96bb-8c8fef4459e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466487596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2466487596
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.69148177
Short name T431
Test name
Test status
Simulation time 32572046 ps
CPU time 2.3 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 207448 kb
Host smart-cb46d397-b173-45b6-9280-1a1f852da8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69148177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.69148177
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.580261774
Short name T78
Test name
Test status
Simulation time 317650531 ps
CPU time 4.06 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:38 PM PST 24
Peak memory 209532 kb
Host smart-8306ae8c-8fb8-41df-a8a4-a40b2c1842be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580261774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.580261774
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1798220437
Short name T259
Test name
Test status
Simulation time 981479347 ps
CPU time 13.96 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:49 PM PST 24
Peak memory 210684 kb
Host smart-00b82e1a-8a5a-4c1a-b5a7-6a60b69ce698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798220437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1798220437
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3566778863
Short name T601
Test name
Test status
Simulation time 144888424 ps
CPU time 3.64 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 209436 kb
Host smart-3de3868d-ac0d-4d5e-97a4-7da8647f8ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566778863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3566778863
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3845321682
Short name T526
Test name
Test status
Simulation time 5231573800 ps
CPU time 33.35 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:57:08 PM PST 24
Peak memory 214284 kb
Host smart-a6d57311-5a98-49bc-81cf-db831666cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845321682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3845321682
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.321991763
Short name T892
Test name
Test status
Simulation time 810684100 ps
CPU time 6.36 seconds
Started Feb 21 02:56:44 PM PST 24
Finished Feb 21 02:56:51 PM PST 24
Peak memory 206464 kb
Host smart-1fad7e8e-f685-401a-bacd-9382abfbe9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321991763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.321991763
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2143911405
Short name T522
Test name
Test status
Simulation time 508080737 ps
CPU time 4.6 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 206588 kb
Host smart-ba3aa045-8a49-4703-831e-37b292e4845c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143911405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2143911405
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3716549498
Short name T309
Test name
Test status
Simulation time 230856773 ps
CPU time 4.15 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 208248 kb
Host smart-81eec7f9-cf4c-41d5-9db5-6687e982db5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716549498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3716549498
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3838198706
Short name T717
Test name
Test status
Simulation time 1030091454 ps
CPU time 3.97 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:39 PM PST 24
Peak memory 206616 kb
Host smart-97c029eb-4807-4b54-9cd1-cd9e7fcad263
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838198706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3838198706
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2164213823
Short name T623
Test name
Test status
Simulation time 88864437 ps
CPU time 3.41 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 215788 kb
Host smart-90b44dd3-43dc-4233-9078-cc1ecd967441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164213823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2164213823
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3426819214
Short name T432
Test name
Test status
Simulation time 91339088 ps
CPU time 2.09 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 208252 kb
Host smart-92d12832-c9d3-4db7-96d3-bd583cbaa968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426819214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3426819214
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2175378946
Short name T689
Test name
Test status
Simulation time 1060650054 ps
CPU time 6.93 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 207400 kb
Host smart-a262c2b3-19a0-4dba-b86c-8f4a36478f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175378946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2175378946
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4173934320
Short name T734
Test name
Test status
Simulation time 33060102 ps
CPU time 1.7 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:33 PM PST 24
Peak memory 209984 kb
Host smart-793e8a19-a36a-4354-81e6-b1038fc12c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173934320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4173934320
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.552966325
Short name T634
Test name
Test status
Simulation time 94762719 ps
CPU time 0.83 seconds
Started Feb 21 02:56:42 PM PST 24
Finished Feb 21 02:56:43 PM PST 24
Peak memory 205912 kb
Host smart-740cdee9-d1a2-4aa9-947a-f474b37d649a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552966325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.552966325
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2608006124
Short name T252
Test name
Test status
Simulation time 180108562 ps
CPU time 8.61 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:44 PM PST 24
Peak memory 214304 kb
Host smart-44bcf3aa-0594-49e5-b12c-92905599e75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608006124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2608006124
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1657729223
Short name T256
Test name
Test status
Simulation time 64744978 ps
CPU time 2 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 209696 kb
Host smart-e4c306a8-0acf-4946-9774-b261caf00bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657729223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1657729223
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.302835423
Short name T86
Test name
Test status
Simulation time 316052205 ps
CPU time 7.89 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 218296 kb
Host smart-2fed0472-ebd1-4d46-bdd4-3e71f479e7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302835423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.302835423
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2197951599
Short name T620
Test name
Test status
Simulation time 253345471 ps
CPU time 2.38 seconds
Started Feb 21 02:56:36 PM PST 24
Finished Feb 21 02:56:39 PM PST 24
Peak memory 219952 kb
Host smart-69fedbd2-5903-41a9-99aa-5f2e4a291cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197951599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2197951599
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.765104454
Short name T790
Test name
Test status
Simulation time 253506532 ps
CPU time 3.42 seconds
Started Feb 21 02:56:42 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 209108 kb
Host smart-e59c64df-e332-4a07-ad1b-17383493c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765104454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.765104454
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4289692473
Short name T855
Test name
Test status
Simulation time 329022987 ps
CPU time 6.4 seconds
Started Feb 21 02:56:35 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 207660 kb
Host smart-93ffc2a4-9a41-4acd-81ce-d4daf6d5b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289692473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4289692473
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3010752820
Short name T748
Test name
Test status
Simulation time 244183731 ps
CPU time 3.06 seconds
Started Feb 21 02:56:39 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 208468 kb
Host smart-ad34683a-28f8-47ef-a1e5-1fa07b772de1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010752820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3010752820
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3108191640
Short name T695
Test name
Test status
Simulation time 79654304 ps
CPU time 3.98 seconds
Started Feb 21 02:56:43 PM PST 24
Finished Feb 21 02:56:48 PM PST 24
Peak memory 208308 kb
Host smart-05bf020d-2400-4b62-9c5c-9ccb49720765
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108191640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3108191640
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1839840542
Short name T94
Test name
Test status
Simulation time 328050182 ps
CPU time 2.93 seconds
Started Feb 21 02:56:31 PM PST 24
Finished Feb 21 02:56:34 PM PST 24
Peak memory 206568 kb
Host smart-5d191560-adf7-4a52-918d-98f685b81cd9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839840542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1839840542
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1170360955
Short name T131
Test name
Test status
Simulation time 1125912418 ps
CPU time 5.54 seconds
Started Feb 21 02:56:40 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 209176 kb
Host smart-e3f5a2c1-fe4b-4733-b223-0b8555f878ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170360955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1170360955
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.514455956
Short name T651
Test name
Test status
Simulation time 501264784 ps
CPU time 2.5 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 207064 kb
Host smart-a394e381-adee-4635-9824-713b1df11bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514455956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.514455956
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3838468400
Short name T67
Test name
Test status
Simulation time 5172629010 ps
CPU time 20.54 seconds
Started Feb 21 02:56:37 PM PST 24
Finished Feb 21 02:56:58 PM PST 24
Peak memory 214624 kb
Host smart-f1918bc7-b832-4b87-a3d6-421ccc4c2517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838468400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3838468400
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4190105107
Short name T793
Test name
Test status
Simulation time 254971722 ps
CPU time 4.13 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 208884 kb
Host smart-cee685ab-1efe-4e86-975e-c6a8491e0239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190105107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4190105107
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3269626435
Short name T560
Test name
Test status
Simulation time 39714716 ps
CPU time 2.08 seconds
Started Feb 21 02:56:40 PM PST 24
Finished Feb 21 02:56:42 PM PST 24
Peak memory 209656 kb
Host smart-eb7acafe-f368-478c-8537-2eda0f7fc21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269626435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3269626435
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1686639574
Short name T745
Test name
Test status
Simulation time 74887461 ps
CPU time 1 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 205896 kb
Host smart-6e655066-30a8-4b06-877b-d7f547ddba5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686639574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1686639574
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2141915618
Short name T405
Test name
Test status
Simulation time 275329978 ps
CPU time 6.31 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 215312 kb
Host smart-a31ddaca-ea82-461f-9ee0-e97831336302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141915618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2141915618
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3334755155
Short name T549
Test name
Test status
Simulation time 88135234 ps
CPU time 2.81 seconds
Started Feb 21 02:56:42 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 209524 kb
Host smart-a68bf317-dd32-40d7-94c8-92311064b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334755155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3334755155
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2335184006
Short name T372
Test name
Test status
Simulation time 98108075 ps
CPU time 4.56 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:43 PM PST 24
Peak memory 214248 kb
Host smart-f38aa5fa-5921-4678-a2f2-5a972be6bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335184006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2335184006
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.995968552
Short name T83
Test name
Test status
Simulation time 444013541 ps
CPU time 5.73 seconds
Started Feb 21 02:56:40 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 214136 kb
Host smart-9a83fdfe-4f47-4493-b704-c2ae5295ca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995968552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.995968552
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2042890273
Short name T829
Test name
Test status
Simulation time 158540361 ps
CPU time 3.6 seconds
Started Feb 21 02:56:36 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 209060 kb
Host smart-c2d00925-8d08-4d75-9474-0dbb7dca187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042890273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2042890273
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1338641968
Short name T804
Test name
Test status
Simulation time 104296098 ps
CPU time 4.94 seconds
Started Feb 21 02:56:40 PM PST 24
Finished Feb 21 02:56:45 PM PST 24
Peak memory 209520 kb
Host smart-b60f4b64-33ac-4468-a016-ca057509b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338641968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1338641968
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4088690557
Short name T551
Test name
Test status
Simulation time 102530631 ps
CPU time 2.89 seconds
Started Feb 21 02:56:38 PM PST 24
Finished Feb 21 02:56:41 PM PST 24
Peak memory 208268 kb
Host smart-4b9cc883-81c9-4ee0-a450-4ccd12a75dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088690557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4088690557
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2335141188
Short name T349
Test name
Test status
Simulation time 59375037 ps
CPU time 3.16 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:36 PM PST 24
Peak memory 206676 kb
Host smart-bef4a215-589b-4a0c-95d5-e621de30ed5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335141188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2335141188
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.975241122
Short name T709
Test name
Test status
Simulation time 146785349 ps
CPU time 2.86 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 208676 kb
Host smart-0b647ca5-54e1-4c29-a482-b08c16d7db1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975241122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.975241122
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1118175968
Short name T489
Test name
Test status
Simulation time 76643513 ps
CPU time 2 seconds
Started Feb 21 02:56:32 PM PST 24
Finished Feb 21 02:56:35 PM PST 24
Peak memory 206788 kb
Host smart-5b026d2b-ce7f-4d8b-b25b-ff1ff609b575
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118175968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1118175968
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2933531514
Short name T73
Test name
Test status
Simulation time 357292430 ps
CPU time 4.09 seconds
Started Feb 21 02:56:36 PM PST 24
Finished Feb 21 02:56:40 PM PST 24
Peak memory 206512 kb
Host smart-bad3f3a0-3a81-4458-ad08-e08ad38c07aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933531514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2933531514
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2667704366
Short name T557
Test name
Test status
Simulation time 605019807 ps
CPU time 24.29 seconds
Started Feb 21 02:56:34 PM PST 24
Finished Feb 21 02:56:59 PM PST 24
Peak memory 216208 kb
Host smart-87d8a419-ebed-45a0-8f1e-e0a35f2c09b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667704366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2667704366
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.349231909
Short name T299
Test name
Test status
Simulation time 1837186426 ps
CPU time 21.24 seconds
Started Feb 21 02:56:36 PM PST 24
Finished Feb 21 02:56:58 PM PST 24
Peak memory 222600 kb
Host smart-1cb04c47-6d25-4725-90c8-4d9fef593904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349231909 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.349231909
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1143674454
Short name T686
Test name
Test status
Simulation time 641692053 ps
CPU time 5.03 seconds
Started Feb 21 02:56:41 PM PST 24
Finished Feb 21 02:56:46 PM PST 24
Peak memory 208832 kb
Host smart-6cf42496-7dca-400f-9b80-8fe23938145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143674454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1143674454
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2589514719
Short name T884
Test name
Test status
Simulation time 315643863 ps
CPU time 3.53 seconds
Started Feb 21 02:56:33 PM PST 24
Finished Feb 21 02:56:37 PM PST 24
Peak memory 210476 kb
Host smart-d52fa54e-70ae-4f82-9e4c-4f75c7879742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589514719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2589514719
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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