Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11750

1

T1

22

T2

10

T3

6

auto[Attestation]

8303

1

T1

5

T2

8

T3

10

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3002	1			T1	10		T2	2		T3	7
auto[Aes]	3529	1			T1	3		T2	1		T3	2
auto[Kmac]	3637	1			T1	1		T2	3		T3	1
auto[Otbn]	3585	1			T1	9		T2	6		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8282	1			T1	8		T2	8		T3	8
auto[OpGenId]	6300	1			T1	4		T2	6		T3	4
auto[OpGenSwOut]	6303	1			T1	17		T2	6		T3	6
auto[OpGenHwOut]	7450	1			T1	6		T2	6		T3	6
auto[OpDisable]	132	1			T17	1		T44	1		T42	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10836

1

T1

12

T2

13

T3

14

auto[OpDoneFail]

17631

1

T1

23

T2

13

T3

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6315	1			T1	13		T2	1		T3	1
auto[StInit]	4530	1			T1	1		T2	3		T3	1
auto[StCreatorRootKey]	3258	1			T1	3		T2	4		T3	3
auto[StOwnerIntKey]	2844	1			T1	5		T2	3		T3	6
auto[StOwnerKey]	2492	1			T1	2		T2	4		T3	6
auto[StDisabled]	7970	1			T1	11		T2	11		T3	7
auto[StInvalid]	1058	1			T34	29		T35	17		T36	27

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	306	1			T1	3		T13	1		T81	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	124	1			T12	1		T82	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T1	1		T2	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T1	1		T3	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	81	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	206	1			T1	1		T12	3		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	30	1			T34	1		T35	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T12	1		T13	3		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	148	1			T12	1		T41	1		T24	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T128	1		T26	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T1	1		T134	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	57	1			T12	1		T82	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T83	1		T41	1		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T52	1		T187	1		T188	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	319	1			T23	1		T41	4		T42	7
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T23	1		T33	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T16	1		T26	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T42	1		T189	1		T100	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T83	1		T100	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	202	1			T2	1		T15	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	26	1			T35	1		T36	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	301	1			T1	5		T128	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T13	1		T81	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T12	2		T26	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T1	1		T13	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T12	1		T13	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	226	1			T1	1		T2	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T34	2		T35	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T115	1		T191	1		T126	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	152	1			T12	1		T13	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	81	1			T128	1		T41	2		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T41	1		T42	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	69	1			T3	1		T41	3		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	210	1			T1	1		T3	1		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T36	2		T192	1		T187	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	75	1			T50	2		T115	1		T193	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T23	2		T33	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	85	1			T26	2		T42	2		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T3	1		T68	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T15	1		T189	2		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	197	1			T1	1		T12	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	26	1			T35	1		T36	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	68	1			T41	1		T42	2		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	143	1			T23	2		T83	1		T51	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T12	1		T41	3		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T12	1		T84	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	75	1			T12	1		T41	2		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	232	1			T12	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T35	2		T52	1		T192	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T41	1		T42	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	140	1			T2	1		T42	2		T100	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T12	1		T13	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T83	1		T41	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	70	1			T2	1		T41	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T3	1		T12	1		T128	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	32	1			T34	3		T36	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	311	1			T1	2		T13	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T85	2		T76	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T13	1		T41	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T3	1		T12	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	29	1			T42	1		T100	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T13	1		T82	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	48	1			T36	2		T192	2		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	449	1			T81	1		T128	1		T99	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	164	1			T12	1		T23	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	118	1			T81	1		T51	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T68	1		T99	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T12	2		T99	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	255	1			T12	3		T13	1		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	44	1			T34	2		T35	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	467	1			T12	1		T15	1		T199	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	151	1			T12	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T129	1		T75	1		T190	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T17	1		T129	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T12	1		T131	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	329	1			T1	1		T2	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T34	1		T35	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	436	1			T1	2		T12	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	140	1			T12	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T42	2		T100	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	90	1			T12	1		T41	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	86	1			T2	1		T12	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	302	1			T2	1		T17	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	41	1			T34	1		T36	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T41	1		T42	1		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T15	1		T42	2		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T3	1		T12	2		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T133	1		T42	3		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T3	1		T12	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	167	1			T41	1		T42	4		T120	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	45	1			T34	2		T35	2		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T41	1		T192	2		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	136	1			T12	1		T51	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T1	1		T81	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T13	1		T41	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	94	1			T42	1		T202	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	271	1			T2	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T34	1		T35	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T42	1		T50	1		T192	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	136	1			T12	1		T17	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T81	1		T199	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	112	1			T3	1		T12	1		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	76	1			T12	1		T199	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	276	1			T2	1		T13	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	25	1			T59	1		T188	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	51	1			T41	1		T42	1		T192	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	126	1			T12	2		T23	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T2	1		T3	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T68	1		T135	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	89	1			T135	1		T42	2		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	262	1			T12	1		T15	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T34	1		T36	3		T192	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	216	1			T1	3		T2	2		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	684	1			T1	4		T3	1		T12	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	212	1			T1	1		T12	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	705	1			T12	2		T13	3		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T16	1		T83	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	672	1			T2	1		T15	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	211	1			T1	1		T12	3		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	704	1			T1	6		T2	1		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T3	1		T128	1		T41	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	471	1			T1	1		T3	1		T12	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	202	1			T15	1		T68	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	438	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T12	3		T84	1		T41	7
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	490	1			T12	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	219	1			T2	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	467	1			T2	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	165	1			T3	1		T12	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	678	1			T1	2		T13	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	271	1			T12	2		T68	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	936	1			T12	4		T13	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T12	1		T17	1		T129	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	989	1			T1	1		T2	1		T12	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T2	1		T12	2		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	930	1			T1	2		T2	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T3	1		T12	3		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	402	1			T3	1		T15	1		T34	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	267	1			T1	1		T13	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	498	1			T2	1		T3	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T3	1		T12	2		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	520	1			T2	1		T12	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	307	1			T2	1		T3	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	485	1			T12	3		T15	1		T82	1