Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32693

1

T1

39

T2

28

T3

26

auto[1]

259

1

T13

2

T120

13

T77

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32703	1			T1	39		T2	28		T3	26
auto[134217728:268435455]	8	1			T229	1		T231	1		T259	1
auto[268435456:402653183]	10	1			T120	1		T138	1		T139	1
auto[402653184:536870911]	6	1			T120	1		T139	1		T259	1
auto[536870912:671088639]	11	1			T120	1		T258	1		T245	1
auto[671088640:805306367]	9	1			T138	1		T139	1		T315	3
auto[805306368:939524095]	11	1			T120	1		T139	1		T349	1
auto[939524096:1073741823]	6	1			T258	1		T139	1		T249	1
auto[1073741824:1207959551]	14	1			T120	1		T77	1		T382	1
auto[1207959552:1342177279]	9	1			T120	1		T77	1		T259	1
auto[1342177280:1476395007]	8	1			T120	1		T77	2		T349	1
auto[1476395008:1610612735]	8	1			T120	2		T231	1		T258	1
auto[1610612736:1744830463]	12	1			T120	1		T137	1		T258	1
auto[1744830464:1879048191]	6	1			T258	1		T138	1		T360	1
auto[1879048192:2013265919]	8	1			T77	1		T231	1		T349	2
auto[2013265920:2147483647]	7	1			T276	1		T393	2		T394	1
auto[2147483648:2281701375]	6	1			T77	1		T229	1		T245	1
auto[2281701376:2415919103]	11	1			T120	1		T258	1		T360	1
auto[2415919104:2550136831]	3	1			T259	1		T223	1		T395	1
auto[2550136832:2684354559]	11	1			T225	1		T245	1		T382	1
auto[2684354560:2818572287]	7	1			T258	1		T259	1		T225	1
auto[2818572288:2952790015]	9	1			T13	1		T120	1		T229	1
auto[2952790016:3087007743]	12	1			T137	1		T349	1		T315	1
auto[3087007744:3221225471]	9	1			T13	1		T245	2		T349	1
auto[3221225472:3355443199]	3	1			T396	1		T397	1		T395	1
auto[3355443200:3489660927]	7	1			T250	1		T270	1		T398	1
auto[3489660928:3623878655]	4	1			T361	1		T396	1		T320	1
auto[3623878656:3758096383]	7	1			T225	1		T251	1		T287	1
auto[3758096384:3892314111]	6	1			T120	1		T259	1		T245	1
auto[3892314112:4026531839]	6	1			T229	1		T258	1		T139	1
auto[4026531840:4160749567]	6	1			T245	1		T358	1		T396	1
auto[4160749568:4294967295]	9	1			T137	1		T139	1		T245	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	30	34	53.12	30

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[1476395008:1610612735]]	[auto[0]]	--	--	11
[auto[1744830464:1879048191] - auto[4160749568:4294967295]]	[auto[0]]	--	--	19

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32692	1			T1	39		T2	28		T3	26
auto[0:134217727]	auto[1]	11	1			T258	1		T259	1		T315	1
auto[134217728:268435455]	auto[1]	8	1			T229	1		T231	1		T259	1
auto[268435456:402653183]	auto[1]	10	1			T120	1		T138	1		T139	1
auto[402653184:536870911]	auto[1]	6	1			T120	1		T139	1		T259	1
auto[536870912:671088639]	auto[1]	11	1			T120	1		T258	1		T245	1
auto[671088640:805306367]	auto[1]	9	1			T138	1		T139	1		T315	3
auto[805306368:939524095]	auto[1]	11	1			T120	1		T139	1		T349	1
auto[939524096:1073741823]	auto[1]	6	1			T258	1		T139	1		T249	1
auto[1073741824:1207959551]	auto[1]	14	1			T120	1		T77	1		T382	1
auto[1207959552:1342177279]	auto[1]	9	1			T120	1		T77	1		T259	1
auto[1342177280:1476395007]	auto[1]	8	1			T120	1		T77	2		T349	1
auto[1476395008:1610612735]	auto[1]	8	1			T120	2		T231	1		T258	1
auto[1610612736:1744830463]	auto[0]	1	1			T271	1		-	-		-	-
auto[1610612736:1744830463]	auto[1]	11	1			T120	1		T137	1		T258	1
auto[1744830464:1879048191]	auto[1]	6	1			T258	1		T138	1		T360	1
auto[1879048192:2013265919]	auto[1]	8	1			T77	1		T231	1		T349	2
auto[2013265920:2147483647]	auto[1]	7	1			T276	1		T393	2		T394	1
auto[2147483648:2281701375]	auto[1]	6	1			T77	1		T229	1		T245	1
auto[2281701376:2415919103]	auto[1]	11	1			T120	1		T258	1		T360	1
auto[2415919104:2550136831]	auto[1]	3	1			T259	1		T223	1		T395	1
auto[2550136832:2684354559]	auto[1]	11	1			T225	1		T245	1		T382	1
auto[2684354560:2818572287]	auto[1]	7	1			T258	1		T259	1		T225	1
auto[2818572288:2952790015]	auto[1]	9	1			T13	1		T120	1		T229	1
auto[2952790016:3087007743]	auto[1]	12	1			T137	1		T349	1		T315	1
auto[3087007744:3221225471]	auto[1]	9	1			T13	1		T245	2		T349	1
auto[3221225472:3355443199]	auto[1]	3	1			T396	1		T397	1		T395	1
auto[3355443200:3489660927]	auto[1]	7	1			T250	1		T270	1		T398	1
auto[3489660928:3623878655]	auto[1]	4	1			T361	1		T396	1		T320	1
auto[3623878656:3758096383]	auto[1]	7	1			T225	1		T251	1		T287	1
auto[3758096384:3892314111]	auto[1]	6	1			T120	1		T259	1		T245	1
auto[3892314112:4026531839]	auto[1]	6	1			T229	1		T258	1		T139	1
auto[4026531840:4160749567]	auto[1]	6	1			T245	1		T358	1		T396	1
auto[4160749568:4294967295]	auto[1]	9	1			T137	1		T139	1		T245	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1598

1

T1

7

T12

8

T13

2

auto[1]

1761

1

T1

3

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T1	2		T12	2		T15	1
auto[134217728:268435455]	109	1			T12	1		T26	1		T35	1
auto[268435456:402653183]	106	1			T12	1		T23	1		T128	1
auto[402653184:536870911]	125	1			T2	1		T12	1		T13	1
auto[536870912:671088639]	119	1			T15	1		T68	1		T128	1
auto[671088640:805306367]	101	1			T51	1		T25	1		T42	7
auto[805306368:939524095]	114	1			T1	2		T2	1		T12	2
auto[939524096:1073741823]	98	1			T42	1		T4	1		T189	1
auto[1073741824:1207959551]	114	1			T26	1		T41	1		T42	5
auto[1207959552:1342177279]	103	1			T14	1		T23	1		T26	1
auto[1342177280:1476395007]	94	1			T13	1		T14	1		T51	1
auto[1476395008:1610612735]	103	1			T14	1		T42	4		T4	1
auto[1610612736:1744830463]	107	1			T15	1		T41	1		T42	3
auto[1744830464:1879048191]	128	1			T81	1		T23	1		T127	1
auto[1879048192:2013265919]	111	1			T1	1		T12	1		T81	1
auto[2013265920:2147483647]	105	1			T12	1		T23	1		T41	1
auto[2147483648:2281701375]	109	1			T68	1		T128	1		T26	1
auto[2281701376:2415919103]	99	1			T1	1		T3	1		T34	1
auto[2415919104:2550136831]	111	1			T13	1		T82	1		T127	1
auto[2550136832:2684354559]	97	1			T13	1		T51	1		T41	1
auto[2684354560:2818572287]	92	1			T82	1		T51	2		T42	1
auto[2818572288:2952790015]	111	1			T12	2		T15	1		T42	1
auto[2952790016:3087007743]	108	1			T1	1		T2	1		T3	1
auto[3087007744:3221225471]	91	1			T41	1		T24	1		T25	1
auto[3221225472:3355443199]	102	1			T15	1		T34	1		T42	1
auto[3355443200:3489660927]	92	1			T14	1		T24	1		T42	1
auto[3489660928:3623878655]	94	1			T1	1		T12	2		T14	1
auto[3623878656:3758096383]	101	1			T1	1		T82	1		T127	1
auto[3758096384:3892314111]	95	1			T1	1		T17	1		T42	3
auto[3892314112:4026531839]	112	1			T3	1		T12	1		T14	1
auto[4026531840:4160749567]	102	1			T25	1		T42	2		T4	1
auto[4160749568:4294967295]	113	1			T100	1		T297	1		T59	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T12	2		T42	1		T4	1
auto[0:134217727]	auto[1]	48	1			T1	2		T15	1		T127	1
auto[134217728:268435455]	auto[0]	51	1			T36	1		T25	1		T42	1
auto[134217728:268435455]	auto[1]	58	1			T12	1		T26	1		T35	1
auto[268435456:402653183]	auto[0]	46	1			T23	1		T41	1		T35	1
auto[268435456:402653183]	auto[1]	60	1			T12	1		T128	1		T36	1
auto[402653184:536870911]	auto[0]	45	1			T12	1		T47	1		T192	1
auto[402653184:536870911]	auto[1]	80	1			T2	1		T13	1		T127	1
auto[536870912:671088639]	auto[0]	60	1			T42	1		T78	1		T47	2
auto[536870912:671088639]	auto[1]	59	1			T15	1		T68	1		T128	1
auto[671088640:805306367]	auto[0]	48	1			T51	1		T42	3		T100	1
auto[671088640:805306367]	auto[1]	53	1			T25	1		T42	4		T55	1
auto[805306368:939524095]	auto[0]	61	1			T1	2		T12	1		T13	1
auto[805306368:939524095]	auto[1]	53	1			T2	1		T12	1		T34	1
auto[939524096:1073741823]	auto[0]	44	1			T42	1		T4	1		T189	1
auto[939524096:1073741823]	auto[1]	54	1			T77	1		T295	1		T210	1
auto[1073741824:1207959551]	auto[0]	55	1			T26	1		T42	2		T5	1
auto[1073741824:1207959551]	auto[1]	59	1			T41	1		T42	3		T54	1
auto[1207959552:1342177279]	auto[0]	52	1			T14	1		T23	1		T41	1
auto[1207959552:1342177279]	auto[1]	51	1			T26	1		T100	2		T297	1
auto[1342177280:1476395007]	auto[0]	44	1			T14	1		T41	1		T35	1
auto[1342177280:1476395007]	auto[1]	50	1			T13	1		T51	1		T41	1
auto[1476395008:1610612735]	auto[0]	46	1			T42	2		T297	1		T77	1
auto[1476395008:1610612735]	auto[1]	57	1			T14	1		T42	2		T4	1
auto[1610612736:1744830463]	auto[0]	54	1			T42	2		T120	1		T187	1
auto[1610612736:1744830463]	auto[1]	53	1			T15	1		T41	1		T42	1
auto[1744830464:1879048191]	auto[0]	62	1			T81	1		T23	1		T127	1
auto[1744830464:1879048191]	auto[1]	66	1			T100	1		T297	2		T5	1
auto[1879048192:2013265919]	auto[0]	57	1			T1	1		T12	1		T51	1
auto[1879048192:2013265919]	auto[1]	54	1			T81	1		T25	1		T59	1
auto[2013265920:2147483647]	auto[0]	44	1			T12	1		T41	1		T295	1
auto[2013265920:2147483647]	auto[1]	61	1			T23	1		T36	1		T42	2
auto[2147483648:2281701375]	auto[0]	48	1			T68	1		T41	1		T42	1
auto[2147483648:2281701375]	auto[1]	61	1			T128	1		T26	1		T41	1
auto[2281701376:2415919103]	auto[0]	49	1			T1	1		T34	1		T120	1
auto[2281701376:2415919103]	auto[1]	50	1			T3	1		T77	1		T78	1
auto[2415919104:2550136831]	auto[0]	51	1			T41	1		T27	1		T197	1
auto[2415919104:2550136831]	auto[1]	60	1			T13	1		T82	1		T127	1
auto[2550136832:2684354559]	auto[0]	42	1			T13	1		T41	1		T42	1
auto[2550136832:2684354559]	auto[1]	55	1			T51	1		T137	1		T47	1
auto[2684354560:2818572287]	auto[0]	48	1			T42	1		T120	1		T52	1
auto[2684354560:2818572287]	auto[1]	44	1			T82	1		T51	2		T54	1
auto[2818572288:2952790015]	auto[0]	61	1			T42	1		T268	1		T47	2
auto[2818572288:2952790015]	auto[1]	50	1			T12	2		T15	1		T55	1
auto[2952790016:3087007743]	auto[0]	53	1			T42	2		T78	1		T87	1
auto[2952790016:3087007743]	auto[1]	55	1			T1	1		T2	1		T3	1
auto[3087007744:3221225471]	auto[0]	41	1			T41	1		T24	1		T25	1
auto[3087007744:3221225471]	auto[1]	50	1			T100	1		T230	1		T234	1
auto[3221225472:3355443199]	auto[0]	52	1			T15	1		T42	1		T4	2
auto[3221225472:3355443199]	auto[1]	50	1			T34	1		T189	1		T200	1
auto[3355443200:3489660927]	auto[0]	42	1			T24	1		T295	1		T20	1
auto[3355443200:3489660927]	auto[1]	50	1			T14	1		T42	1		T60	1
auto[3489660928:3623878655]	auto[0]	41	1			T1	1		T12	1		T14	1
auto[3489660928:3623878655]	auto[1]	53	1			T12	1		T15	1		T82	1
auto[3623878656:3758096383]	auto[0]	50	1			T1	1		T82	1		T127	1
auto[3623878656:3758096383]	auto[1]	51	1			T42	1		T55	1		T59	1
auto[3758096384:3892314111]	auto[0]	44	1			T1	1		T42	1		T89	1
auto[3758096384:3892314111]	auto[1]	51	1			T17	1		T42	2		T268	2
auto[3892314112:4026531839]	auto[0]	62	1			T12	1		T14	1		T42	1
auto[3892314112:4026531839]	auto[1]	50	1			T3	1		T36	1		T42	1
auto[4026531840:4160749567]	auto[0]	53	1			T25	1		T42	1		T67	1
auto[4026531840:4160749567]	auto[1]	49	1			T42	1		T4	1		T89	1
auto[4160749568:4294967295]	auto[0]	47	1			T87	1		T255	1		T188	1
auto[4160749568:4294967295]	auto[1]	66	1			T100	1		T297	1		T59	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1590

1

T1

10

T12

7

T13

2

auto[1]

1769

1

T2

3

T3

3

T12

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T23	1		T128	1		T41	1
auto[134217728:268435455]	105	1			T12	2		T15	1		T25	1
auto[268435456:402653183]	106	1			T12	2		T127	1		T51	2
auto[402653184:536870911]	115	1			T14	1		T127	2		T26	1
auto[536870912:671088639]	119	1			T3	1		T51	1		T25	1
auto[671088640:805306367]	107	1			T14	1		T15	1		T36	1
auto[805306368:939524095]	97	1			T127	1		T42	3		T54	1
auto[939524096:1073741823]	116	1			T3	1		T13	1		T25	1
auto[1073741824:1207959551]	112	1			T12	2		T14	1		T23	1
auto[1207959552:1342177279]	97	1			T1	1		T81	1		T82	1
auto[1342177280:1476395007]	91	1			T12	1		T15	1		T81	1
auto[1476395008:1610612735]	106	1			T26	1		T36	1		T230	1
auto[1610612736:1744830463]	115	1			T1	1		T12	1		T15	1
auto[1744830464:1879048191]	101	1			T12	2		T41	2		T42	3
auto[1879048192:2013265919]	104	1			T14	1		T82	1		T41	1
auto[2013265920:2147483647]	94	1			T34	1		T51	1		T42	3
auto[2147483648:2281701375]	104	1			T13	1		T127	1		T26	1
auto[2281701376:2415919103]	103	1			T12	1		T128	1		T41	1
auto[2415919104:2550136831]	105	1			T1	1		T2	1		T42	2
auto[2550136832:2684354559]	101	1			T12	1		T82	1		T34	2
auto[2684354560:2818572287]	108	1			T1	1		T24	1		T25	1
auto[2818572288:2952790015]	114	1			T1	1		T13	1		T14	1
auto[2952790016:3087007743]	108	1			T12	1		T26	1		T42	2
auto[3087007744:3221225471]	96	1			T2	1		T42	3		T67	1
auto[3221225472:3355443199]	107	1			T82	1		T42	2		T120	1
auto[3355443200:3489660927]	111	1			T15	1		T23	1		T41	1
auto[3489660928:3623878655]	110	1			T13	1		T14	1		T68	1
auto[3623878656:3758096383]	102	1			T1	1		T12	1		T68	1
auto[3758096384:3892314111]	123	1			T41	1		T25	1		T42	1
auto[3892314112:4026531839]	104	1			T1	1		T3	1		T23	2
auto[4026531840:4160749567]	84	1			T1	2		T15	1		T23	1
auto[4160749568:4294967295]	86	1			T1	1		T2	1		T13	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T41	1		T42	2		T85	1
auto[0:134217727]	auto[1]	52	1			T23	1		T128	1		T42	2
auto[134217728:268435455]	auto[0]	48	1			T12	1		T25	1		T85	1
auto[134217728:268435455]	auto[1]	57	1			T12	1		T15	1		T42	2
auto[268435456:402653183]	auto[0]	50	1			T12	1		T127	1		T51	1
auto[268435456:402653183]	auto[1]	56	1			T12	1		T51	1		T77	1
auto[402653184:536870911]	auto[0]	55	1			T27	1		T77	1		T137	1
auto[402653184:536870911]	auto[1]	60	1			T14	1		T127	2		T26	1
auto[536870912:671088639]	auto[0]	59	1			T42	1		T120	1		T100	1
auto[536870912:671088639]	auto[1]	60	1			T3	1		T51	1		T25	1
auto[671088640:805306367]	auto[0]	53	1			T14	1		T42	3		T85	1
auto[671088640:805306367]	auto[1]	54	1			T15	1		T36	1		T100	1
auto[805306368:939524095]	auto[0]	48	1			T127	1		T42	1		T92	1
auto[805306368:939524095]	auto[1]	49	1			T42	2		T54	1		T100	1
auto[939524096:1073741823]	auto[0]	52	1			T42	1		T47	1		T265	1
auto[939524096:1073741823]	auto[1]	64	1			T3	1		T13	1		T25	1
auto[1073741824:1207959551]	auto[0]	50	1			T12	1		T14	1		T23	1
auto[1073741824:1207959551]	auto[1]	62	1			T12	1		T41	1		T4	1
auto[1207959552:1342177279]	auto[0]	53	1			T1	1		T81	1		T82	1
auto[1207959552:1342177279]	auto[1]	44	1			T41	1		T100	1		T65	1
auto[1342177280:1476395007]	auto[0]	45	1			T42	1		T55	1		T67	2
auto[1342177280:1476395007]	auto[1]	46	1			T12	1		T15	1		T81	1
auto[1476395008:1610612735]	auto[0]	49	1			T87	1		T255	1		T187	1
auto[1476395008:1610612735]	auto[1]	57	1			T26	1		T36	1		T230	1
auto[1610612736:1744830463]	auto[0]	52	1			T1	1		T35	1		T120	2
auto[1610612736:1744830463]	auto[1]	63	1			T12	1		T15	1		T17	1
auto[1744830464:1879048191]	auto[0]	42	1			T12	1		T41	1		T42	3
auto[1744830464:1879048191]	auto[1]	59	1			T12	1		T41	1		T100	1
auto[1879048192:2013265919]	auto[0]	48	1			T14	1		T42	1		T87	1
auto[1879048192:2013265919]	auto[1]	56	1			T82	1		T41	1		T4	1
auto[2013265920:2147483647]	auto[0]	44	1			T42	3		T120	1		T190	1
auto[2013265920:2147483647]	auto[1]	50	1			T34	1		T51	1		T189	1
auto[2147483648:2281701375]	auto[0]	55	1			T13	1		T36	1		T42	1
auto[2147483648:2281701375]	auto[1]	49	1			T127	1		T26	1		T42	1
auto[2281701376:2415919103]	auto[0]	51	1			T12	1		T24	1		T25	1
auto[2281701376:2415919103]	auto[1]	52	1			T128	1		T41	1		T42	1
auto[2415919104:2550136831]	auto[0]	44	1			T1	1		T42	1		T4	1
auto[2415919104:2550136831]	auto[1]	61	1			T2	1		T42	1		T55	1
auto[2550136832:2684354559]	auto[0]	50	1			T12	1		T34	1		T51	1
auto[2550136832:2684354559]	auto[1]	51	1			T82	1		T34	1		T42	4
auto[2684354560:2818572287]	auto[0]	54	1			T1	1		T24	1		T25	1
auto[2684354560:2818572287]	auto[1]	54	1			T42	1		T100	1		T224	1
auto[2818572288:2952790015]	auto[0]	51	1			T1	1		T13	1		T189	1
auto[2818572288:2952790015]	auto[1]	63	1			T14	1		T41	1		T36	1
auto[2952790016:3087007743]	auto[0]	56	1			T12	1		T42	2		T195	1
auto[2952790016:3087007743]	auto[1]	52	1			T26	1		T100	1		T47	1
auto[3087007744:3221225471]	auto[0]	48	1			T42	2		T59	1		T234	1
auto[3087007744:3221225471]	auto[1]	48	1			T2	1		T42	1		T67	1
auto[3221225472:3355443199]	auto[0]	48	1			T42	1		T85	1		T268	1
auto[3221225472:3355443199]	auto[1]	59	1			T82	1		T42	1		T120	1
auto[3355443200:3489660927]	auto[0]	50	1			T15	1		T23	1		T41	1
auto[3355443200:3489660927]	auto[1]	61	1			T47	1		T28	2		T277	1
auto[3489660928:3623878655]	auto[0]	45	1			T14	1		T27	1		T338	1
auto[3489660928:3623878655]	auto[1]	65	1			T13	1		T68	1		T42	2
auto[3623878656:3758096383]	auto[0]	44	1			T1	1		T238	1		T63	1
auto[3623878656:3758096383]	auto[1]	58	1			T12	1		T68	1		T226	1
auto[3758096384:3892314111]	auto[0]	53	1			T41	1		T25	1		T137	1
auto[3758096384:3892314111]	auto[1]	70	1			T42	1		T89	1		T100	1
auto[3892314112:4026531839]	auto[0]	49	1			T1	1		T23	2		T35	1
auto[3892314112:4026531839]	auto[1]	55	1			T3	1		T42	2		T78	1
auto[4026531840:4160749567]	auto[0]	47	1			T1	2		T15	1		T23	1
auto[4026531840:4160749567]	auto[1]	37	1			T128	1		T297	1		T67	1
auto[4160749568:4294967295]	auto[0]	41	1			T1	1		T42	2		T283	1
auto[4160749568:4294967295]	auto[1]	45	1			T2	1		T13	1		T34	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1582

1

T1

7

T2

1

T12

6

auto[1]

1778

1

T1

3

T2

2

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T1	1		T3	1		T13	1
auto[134217728:268435455]	102	1			T17	1		T51	1		T25	2
auto[268435456:402653183]	95	1			T34	1		T41	2		T25	1
auto[402653184:536870911]	85	1			T1	1		T2	1		T3	1
auto[536870912:671088639]	98	1			T51	1		T41	1		T42	3
auto[671088640:805306367]	84	1			T13	1		T41	2		T42	4
auto[805306368:939524095]	107	1			T2	1		T42	3		T297	1
auto[939524096:1073741823]	105	1			T12	1		T23	1		T41	1
auto[1073741824:1207959551]	107	1			T26	2		T41	1		T42	2
auto[1207959552:1342177279]	102	1			T12	1		T68	1		T42	1
auto[1342177280:1476395007]	119	1			T14	1		T15	1		T26	1
auto[1476395008:1610612735]	110	1			T12	1		T127	1		T42	1
auto[1610612736:1744830463]	99	1			T12	1		T15	2		T42	1
auto[1744830464:1879048191]	115	1			T1	1		T23	1		T128	1
auto[1879048192:2013265919]	109	1			T12	2		T68	1		T41	1
auto[2013265920:2147483647]	98	1			T1	1		T12	1		T14	1
auto[2147483648:2281701375]	129	1			T12	2		T13	1		T82	1
auto[2281701376:2415919103]	100	1			T13	1		T23	1		T34	1
auto[2415919104:2550136831]	89	1			T1	2		T12	2		T15	1
auto[2550136832:2684354559]	109	1			T12	1		T36	1		T42	2
auto[2684354560:2818572287]	131	1			T12	1		T14	1		T15	1
auto[2818572288:2952790015]	101	1			T13	1		T15	1		T42	1
auto[2952790016:3087007743]	108	1			T42	4		T230	1		T59	1
auto[3087007744:3221225471]	103	1			T127	3		T35	1		T42	1
auto[3221225472:3355443199]	101	1			T81	1		T82	1		T41	1
auto[3355443200:3489660927]	114	1			T1	1		T12	1		T82	1
auto[3489660928:3623878655]	96	1			T1	2		T2	1		T82	1
auto[3623878656:3758096383]	107	1			T42	3		T100	1		T297	1
auto[3758096384:3892314111]	111	1			T1	1		T14	1		T23	1
auto[3892314112:4026531839]	91	1			T3	1		T51	1		T24	1
auto[4026531840:4160749567]	105	1			T14	1		T51	1		T42	3
auto[4160749568:4294967295]	113	1			T81	1		T189	1		T89	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T1	1		T14	1		T25	1
auto[0:134217727]	auto[1]	58	1			T3	1		T13	1		T34	1
auto[134217728:268435455]	auto[0]	41	1			T25	1		T42	1		T197	1
auto[134217728:268435455]	auto[1]	61	1			T17	1		T51	1		T25	1
auto[268435456:402653183]	auto[0]	51	1			T41	1		T25	1		T42	1
auto[268435456:402653183]	auto[1]	44	1			T34	1		T41	1		T4	1
auto[402653184:536870911]	auto[0]	33	1			T1	1		T41	1		T42	1
auto[402653184:536870911]	auto[1]	52	1			T2	1		T3	1		T51	1
auto[536870912:671088639]	auto[0]	41	1			T51	1		T41	1		T42	2
auto[536870912:671088639]	auto[1]	57	1			T42	1		T268	1		T47	1
auto[671088640:805306367]	auto[0]	38	1			T42	1		T47	1		T192	1
auto[671088640:805306367]	auto[1]	46	1			T13	1		T41	2		T42	3
auto[805306368:939524095]	auto[0]	47	1			T2	1		T42	1		T384	1
auto[805306368:939524095]	auto[1]	60	1			T42	2		T297	1		T59	1
auto[939524096:1073741823]	auto[0]	53	1			T12	1		T23	1		T41	1
auto[939524096:1073741823]	auto[1]	52	1			T61	1		T28	1		T258	1
auto[1073741824:1207959551]	auto[0]	56	1			T41	1		T42	1		T85	1
auto[1073741824:1207959551]	auto[1]	51	1			T26	2		T42	1		T189	1
auto[1207959552:1342177279]	auto[0]	44	1			T47	1		T265	1		T188	1
auto[1207959552:1342177279]	auto[1]	58	1			T12	1		T68	1		T42	1
auto[1342177280:1476395007]	auto[0]	52	1			T26	1		T24	1		T25	1
auto[1342177280:1476395007]	auto[1]	67	1			T14	1		T15	1		T36	2
auto[1476395008:1610612735]	auto[0]	58	1			T12	1		T4	1		T85	1
auto[1476395008:1610612735]	auto[1]	52	1			T127	1		T42	1		T89	1
auto[1610612736:1744830463]	auto[0]	40	1			T12	1		T42	1		T295	2
auto[1610612736:1744830463]	auto[1]	59	1			T15	2		T67	1		T47	1
auto[1744830464:1879048191]	auto[0]	52	1			T23	1		T42	1		T77	1
auto[1744830464:1879048191]	auto[1]	63	1			T1	1		T128	1		T41	2
auto[1879048192:2013265919]	auto[0]	48	1			T41	1		T35	1		T42	1
auto[1879048192:2013265919]	auto[1]	61	1			T12	2		T68	1		T42	1
auto[2013265920:2147483647]	auto[0]	45	1			T12	1		T14	1		T42	1
auto[2013265920:2147483647]	auto[1]	53	1			T1	1		T47	1		T50	1
auto[2147483648:2281701375]	auto[0]	57	1			T42	2		T238	1		T295	1
auto[2147483648:2281701375]	auto[1]	72	1			T12	2		T13	1		T82	1
auto[2281701376:2415919103]	auto[0]	52	1			T13	1		T23	1		T34	1
auto[2281701376:2415919103]	auto[1]	48	1			T128	1		T42	1		T47	1
auto[2415919104:2550136831]	auto[0]	48	1			T1	2		T12	1		T15	1
auto[2415919104:2550136831]	auto[1]	41	1			T12	1		T128	1		T243	1
auto[2550136832:2684354559]	auto[0]	47	1			T12	1		T42	1		T100	1
auto[2550136832:2684354559]	auto[1]	62	1			T36	1		T42	1		T100	1
auto[2684354560:2818572287]	auto[0]	68	1			T15	1		T23	1		T51	1
auto[2684354560:2818572287]	auto[1]	63	1			T12	1		T14	1		T26	1
auto[2818572288:2952790015]	auto[0]	60	1			T265	1		T108	1		T61	1
auto[2818572288:2952790015]	auto[1]	41	1			T13	1		T15	1		T42	1
auto[2952790016:3087007743]	auto[0]	47	1			T42	1		T230	1		T78	1
auto[2952790016:3087007743]	auto[1]	61	1			T42	3		T59	1		T77	1
auto[3087007744:3221225471]	auto[0]	54	1			T127	1		T35	1		T42	1
auto[3087007744:3221225471]	auto[1]	49	1			T127	2		T120	1		T89	1
auto[3221225472:3355443199]	auto[0]	45	1			T81	1		T42	1		T52	1
auto[3221225472:3355443199]	auto[1]	56	1			T82	1		T41	1		T86	1
auto[3355443200:3489660927]	auto[0]	53	1			T1	1		T42	2		T4	1
auto[3355443200:3489660927]	auto[1]	61	1			T12	1		T82	1		T42	1
auto[3489660928:3623878655]	auto[0]	44	1			T1	2		T82	1		T23	1
auto[3489660928:3623878655]	auto[1]	52	1			T2	1		T26	1		T42	1
auto[3623878656:3758096383]	auto[0]	54	1			T42	2		T88	1		T47	1
auto[3623878656:3758096383]	auto[1]	53	1			T42	1		T100	1		T297	1
auto[3758096384:3892314111]	auto[0]	53	1			T14	1		T35	1		T42	1
auto[3758096384:3892314111]	auto[1]	58	1			T1	1		T23	1		T34	1
auto[3892314112:4026531839]	auto[0]	38	1			T25	1		T77	1		T78	1
auto[3892314112:4026531839]	auto[1]	53	1			T3	1		T51	1		T24	1
auto[4026531840:4160749567]	auto[0]	55	1			T14	1		T42	1		T230	1
auto[4026531840:4160749567]	auto[1]	50	1			T51	1		T42	2		T120	1
auto[4160749568:4294967295]	auto[0]	49	1			T85	1		T297	1		T235	1
auto[4160749568:4294967295]	auto[1]	64	1			T81	1		T189	1		T89	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1583

1

T1

9

T12

7

T13

1

auto[1]

1776

1

T1

1

T2

3

T3

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T1	1		T23	1		T42	2
auto[134217728:268435455]	96	1			T15	1		T82	1		T41	2
auto[268435456:402653183]	106	1			T3	1		T12	1		T13	1
auto[402653184:536870911]	103	1			T1	1		T14	1		T26	1
auto[536870912:671088639]	84	1			T12	1		T127	1		T51	1
auto[671088640:805306367]	99	1			T2	1		T17	1		T55	1
auto[805306368:939524095]	106	1			T1	1		T2	1		T12	2
auto[939524096:1073741823]	125	1			T81	1		T35	1		T42	1
auto[1073741824:1207959551]	92	1			T41	1		T42	2		T268	1
auto[1207959552:1342177279]	107	1			T1	1		T25	1		T189	2
auto[1342177280:1476395007]	103	1			T1	1		T12	1		T14	1
auto[1476395008:1610612735]	109	1			T1	1		T12	1		T41	1
auto[1610612736:1744830463]	113	1			T82	2		T51	1		T41	3
auto[1744830464:1879048191]	96	1			T41	1		T42	2		T195	1
auto[1879048192:2013265919]	110	1			T3	1		T13	1		T14	1
auto[2013265920:2147483647]	113	1			T3	1		T13	1		T26	1
auto[2147483648:2281701375]	122	1			T81	1		T42	1		T120	1
auto[2281701376:2415919103]	97	1			T1	1		T12	1		T23	1
auto[2415919104:2550136831]	105	1			T2	1		T34	1		T51	1
auto[2550136832:2684354559]	111	1			T12	1		T25	1		T42	1
auto[2684354560:2818572287]	115	1			T14	1		T15	1		T34	1
auto[2818572288:2952790015]	77	1			T12	1		T23	2		T42	1
auto[2952790016:3087007743]	84	1			T12	1		T297	1		T190	1
auto[3087007744:3221225471]	116	1			T1	1		T12	2		T35	1
auto[3221225472:3355443199]	116	1			T68	1		T34	1		T51	1
auto[3355443200:3489660927]	116	1			T12	1		T42	1		T54	1
auto[3489660928:3623878655]	119	1			T15	1		T23	1		T51	1
auto[3623878656:3758096383]	94	1			T1	1		T12	1		T15	1
auto[3758096384:3892314111]	119	1			T127	2		T128	1		T26	1
auto[3892314112:4026531839]	103	1			T13	1		T14	1		T36	1
auto[4026531840:4160749567]	104	1			T1	1		T15	2		T82	1
auto[4160749568:4294967295]	90	1			T13	1		T68	1		T34	1