Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2947

1

T1

10

T2

3

T3

3

auto[1]

310

1

T120

5

T77

5

T137

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T3	1		T42	4		T230	1
auto[134217728:268435455]	95	1			T1	1		T15	1		T41	2
auto[268435456:402653183]	104	1			T1	2		T25	1		T87	1
auto[402653184:536870911]	125	1			T3	2		T15	1		T41	1
auto[536870912:671088639]	97	1			T13	1		T120	1		T89	1
auto[671088640:805306367]	90	1			T42	1		T89	1		T78	1
auto[805306368:939524095]	114	1			T2	1		T82	1		T41	1
auto[939524096:1073741823]	73	1			T12	1		T23	1		T137	1
auto[1073741824:1207959551]	119	1			T15	1		T81	1		T34	1
auto[1207959552:1342177279]	113	1			T12	2		T68	1		T34	1
auto[1342177280:1476395007]	107	1			T1	1		T14	1		T41	1
auto[1476395008:1610612735]	94	1			T42	1		T77	1		T200	1
auto[1610612736:1744830463]	99	1			T12	1		T82	1		T41	1
auto[1744830464:1879048191]	121	1			T12	2		T23	1		T41	1
auto[1879048192:2013265919]	84	1			T82	1		T24	1		T36	2
auto[2013265920:2147483647]	111	1			T128	1		T35	1		T42	2
auto[2147483648:2281701375]	107	1			T26	1		T42	1		T120	1
auto[2281701376:2415919103]	90	1			T2	1		T13	1		T17	1
auto[2415919104:2550136831]	96	1			T12	2		T42	3		T100	1
auto[2550136832:2684354559]	95	1			T23	1		T26	2		T25	1
auto[2684354560:2818572287]	109	1			T12	1		T13	1		T68	1
auto[2818572288:2952790015]	98	1			T15	1		T42	2		T120	1
auto[2952790016:3087007743]	106	1			T1	1		T13	1		T42	1
auto[3087007744:3221225471]	95	1			T1	1		T82	1		T51	1
auto[3221225472:3355443199]	114	1			T1	1		T12	2		T42	1
auto[3355443200:3489660927]	118	1			T1	1		T2	1		T13	1
auto[3489660928:3623878655]	92	1			T23	1		T41	1		T42	1
auto[3623878656:3758096383]	104	1			T1	1		T12	1		T14	1
auto[3758096384:3892314111]	97	1			T1	1		T15	1		T81	1
auto[3892314112:4026531839]	98	1			T41	1		T42	1		T87	2
auto[4026531840:4160749567]	109	1			T12	1		T34	1		T36	1
auto[4160749568:4294967295]	93	1			T41	1		T42	1		T120	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	78	1			T3	1		T42	4		T230	1
auto[0:134217727]	auto[1]	12	1			T77	1		T349	1		T249	1
auto[134217728:268435455]	auto[0]	91	1			T1	1		T15	1		T41	2
auto[134217728:268435455]	auto[1]	4	1			T229	1		T393	1		T397	1
auto[268435456:402653183]	auto[0]	92	1			T1	2		T25	1		T87	1
auto[268435456:402653183]	auto[1]	12	1			T258	1		T138	1		T400	1
auto[402653184:536870911]	auto[0]	114	1			T3	2		T15	1		T41	1
auto[402653184:536870911]	auto[1]	11	1			T258	1		T245	1		T315	1
auto[536870912:671088639]	auto[0]	93	1			T13	1		T89	1		T67	2
auto[536870912:671088639]	auto[1]	4	1			T120	1		T259	1		T225	1
auto[671088640:805306367]	auto[0]	82	1			T42	1		T89	1		T78	1
auto[671088640:805306367]	auto[1]	8	1			T258	1		T315	1		T400	1
auto[805306368:939524095]	auto[0]	100	1			T2	1		T82	1		T41	1
auto[805306368:939524095]	auto[1]	14	1			T138	1		T259	1		T245	1
auto[939524096:1073741823]	auto[0]	68	1			T12	1		T23	1		T137	1
auto[939524096:1073741823]	auto[1]	5	1			T358	1		T251	1		T221	1
auto[1073741824:1207959551]	auto[0]	110	1			T15	1		T81	1		T34	1
auto[1073741824:1207959551]	auto[1]	9	1			T120	1		T349	2		T276	2
auto[1207959552:1342177279]	auto[0]	103	1			T12	2		T68	1		T34	1
auto[1207959552:1342177279]	auto[1]	10	1			T231	1		T259	1		T225	1
auto[1342177280:1476395007]	auto[0]	93	1			T1	1		T14	1		T41	1
auto[1342177280:1476395007]	auto[1]	14	1			T360	1		T245	1		T250	1
auto[1476395008:1610612735]	auto[0]	88	1			T42	1		T200	1		T47	2
auto[1476395008:1610612735]	auto[1]	6	1			T77	1		T245	1		T403	1
auto[1610612736:1744830463]	auto[0]	90	1			T12	1		T82	1		T41	1
auto[1610612736:1744830463]	auto[1]	9	1			T258	2		T349	2		T361	1
auto[1744830464:1879048191]	auto[0]	110	1			T12	2		T23	1		T41	1
auto[1744830464:1879048191]	auto[1]	11	1			T258	1		T138	1		T139	1
auto[1879048192:2013265919]	auto[0]	76	1			T82	1		T24	1		T36	2
auto[1879048192:2013265919]	auto[1]	8	1			T225	1		T245	1		T250	1
auto[2013265920:2147483647]	auto[0]	102	1			T128	1		T35	1		T42	2
auto[2013265920:2147483647]	auto[1]	9	1			T258	1		T225	1		T245	1
auto[2147483648:2281701375]	auto[0]	97	1			T26	1		T42	1		T120	1
auto[2147483648:2281701375]	auto[1]	10	1			T231	2		T259	1		T361	1
auto[2281701376:2415919103]	auto[0]	82	1			T2	1		T13	1		T17	1
auto[2281701376:2415919103]	auto[1]	8	1			T396	2		T320	1		T369	1
auto[2415919104:2550136831]	auto[0]	84	1			T12	2		T42	3		T100	1
auto[2415919104:2550136831]	auto[1]	12	1			T77	1		T231	1		T139	1
auto[2550136832:2684354559]	auto[0]	85	1			T23	1		T26	2		T25	1
auto[2550136832:2684354559]	auto[1]	10	1			T120	2		T229	1		T258	1
auto[2684354560:2818572287]	auto[0]	99	1			T12	1		T13	1		T68	1
auto[2684354560:2818572287]	auto[1]	10	1			T231	1		T138	1		T225	1
auto[2818572288:2952790015]	auto[0]	85	1			T15	1		T42	2		T120	1
auto[2818572288:2952790015]	auto[1]	13	1			T225	1		T249	1		T315	2
auto[2952790016:3087007743]	auto[0]	96	1			T1	1		T13	1		T42	1
auto[2952790016:3087007743]	auto[1]	10	1			T231	1		T138	1		T245	1
auto[3087007744:3221225471]	auto[0]	87	1			T1	1		T82	1		T51	1
auto[3087007744:3221225471]	auto[1]	8	1			T231	1		T258	2		T138	1
auto[3221225472:3355443199]	auto[0]	100	1			T1	1		T12	2		T42	1
auto[3221225472:3355443199]	auto[1]	14	1			T258	1		T245	1		T358	1
auto[3355443200:3489660927]	auto[0]	107	1			T1	1		T2	1		T13	1
auto[3355443200:3489660927]	auto[1]	11	1			T77	1		T231	1		T225	1
auto[3489660928:3623878655]	auto[0]	80	1			T23	1		T41	1		T42	1
auto[3489660928:3623878655]	auto[1]	12	1			T137	1		T231	1		T259	1
auto[3623878656:3758096383]	auto[0]	91	1			T1	1		T12	1		T14	1
auto[3623878656:3758096383]	auto[1]	13	1			T229	2		T258	1		T138	1
auto[3758096384:3892314111]	auto[0]	93	1			T1	1		T15	1		T81	1
auto[3758096384:3892314111]	auto[1]	4	1			T229	1		T393	1		T357	1
auto[3892314112:4026531839]	auto[0]	89	1			T41	1		T42	1		T87	2
auto[3892314112:4026531839]	auto[1]	9	1			T231	1		T258	1		T349	1
auto[4026531840:4160749567]	auto[0]	99	1			T12	1		T34	1		T36	1
auto[4026531840:4160749567]	auto[1]	10	1			T120	1		T231	2		T245	1
auto[4160749568:4294967295]	auto[0]	83	1			T41	1		T42	1		T120	1
auto[4160749568:4294967295]	auto[1]	10	1			T77	1		T231	1		T245	1