Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.06 98.26 100.00 99.11 98.41 91.73


Total test records in report: 1087
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T1005 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2637357358 Feb 25 01:46:18 PM PST 24 Feb 25 01:46:39 PM PST 24 6657009076 ps
T1006 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.941459054 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:16 PM PST 24 263645037 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1758273470 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:54 PM PST 24 116404853 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.661554463 Feb 25 01:45:59 PM PST 24 Feb 25 01:46:01 PM PST 24 20014371 ps
T1009 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.923067678 Feb 25 01:46:20 PM PST 24 Feb 25 01:46:23 PM PST 24 149711967 ps
T1010 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3863737648 Feb 25 01:46:08 PM PST 24 Feb 25 01:46:13 PM PST 24 157747073 ps
T1011 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.214392897 Feb 25 01:46:20 PM PST 24 Feb 25 01:46:24 PM PST 24 159646427 ps
T1012 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3351658027 Feb 25 01:45:56 PM PST 24 Feb 25 01:45:58 PM PST 24 129454886 ps
T1013 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.290859011 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:37 PM PST 24 29826609 ps
T1014 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2308515572 Feb 25 01:46:17 PM PST 24 Feb 25 01:46:19 PM PST 24 229238930 ps
T1015 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3705992041 Feb 25 01:45:59 PM PST 24 Feb 25 01:46:04 PM PST 24 288271772 ps
T1016 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1461718537 Feb 25 01:46:21 PM PST 24 Feb 25 01:46:22 PM PST 24 10162768 ps
T1017 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1367480783 Feb 25 01:46:22 PM PST 24 Feb 25 01:46:24 PM PST 24 96945614 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1541349807 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:59 PM PST 24 728788626 ps
T1019 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3397868926 Feb 25 01:46:18 PM PST 24 Feb 25 01:46:31 PM PST 24 2358352835 ps
T1020 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1045800120 Feb 25 01:46:07 PM PST 24 Feb 25 01:46:11 PM PST 24 128497039 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.470154014 Feb 25 01:46:07 PM PST 24 Feb 25 01:46:16 PM PST 24 1809374062 ps
T1022 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.433773296 Feb 25 01:46:19 PM PST 24 Feb 25 01:46:26 PM PST 24 826907026 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3470005599 Feb 25 01:46:25 PM PST 24 Feb 25 01:46:27 PM PST 24 16816106 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.190044876 Feb 25 01:46:01 PM PST 24 Feb 25 01:46:03 PM PST 24 23689212 ps
T1025 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4242581497 Feb 25 01:46:12 PM PST 24 Feb 25 01:46:15 PM PST 24 32862274 ps
T1026 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.621970919 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:37 PM PST 24 8229317 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3101053733 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:04 PM PST 24 174371357 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3585751045 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:02 PM PST 24 94604096 ps
T1029 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1119367254 Feb 25 01:45:55 PM PST 24 Feb 25 01:46:00 PM PST 24 95620370 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3759012052 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:03 PM PST 24 277269883 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3455395096 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:55 PM PST 24 587662283 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.65310117 Feb 25 01:46:10 PM PST 24 Feb 25 01:46:11 PM PST 24 201765671 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1821334288 Feb 25 01:46:13 PM PST 24 Feb 25 01:46:16 PM PST 24 410248952 ps
T1034 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3443126849 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:00 PM PST 24 276603760 ps
T1035 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1055317336 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:33 PM PST 24 34593022 ps
T1036 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3196976381 Feb 25 01:45:53 PM PST 24 Feb 25 01:45:56 PM PST 24 158726037 ps
T170 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3301262669 Feb 25 01:46:26 PM PST 24 Feb 25 01:46:31 PM PST 24 142031937 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3660432082 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:53 PM PST 24 152425310 ps
T1038 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1010739158 Feb 25 01:46:30 PM PST 24 Feb 25 01:46:31 PM PST 24 24879847 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.575520335 Feb 25 01:46:10 PM PST 24 Feb 25 01:46:12 PM PST 24 51450942 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.677938332 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:06 PM PST 24 51949643 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1180847424 Feb 25 01:45:52 PM PST 24 Feb 25 01:46:00 PM PST 24 1174243404 ps
T152 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.827923465 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:19 PM PST 24 1601057532 ps
T1042 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.194654038 Feb 25 01:46:32 PM PST 24 Feb 25 01:46:32 PM PST 24 39628903 ps
T1043 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1851103079 Feb 25 01:46:26 PM PST 24 Feb 25 01:46:31 PM PST 24 135360076 ps
T1044 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.850215495 Feb 25 01:46:20 PM PST 24 Feb 25 01:46:23 PM PST 24 319827207 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.607996712 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:09 PM PST 24 984902968 ps
T1046 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.629582387 Feb 25 01:46:21 PM PST 24 Feb 25 01:46:23 PM PST 24 44669032 ps
T162 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1166639558 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:12 PM PST 24 2024870354 ps
T1047 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2287132477 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:34 PM PST 24 17511899 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1835762126 Feb 25 01:45:55 PM PST 24 Feb 25 01:45:56 PM PST 24 34996602 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3033748497 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:50 PM PST 24 106652662 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1485616528 Feb 25 01:45:56 PM PST 24 Feb 25 01:45:59 PM PST 24 372617751 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3096049979 Feb 25 01:45:55 PM PST 24 Feb 25 01:45:56 PM PST 24 18137145 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2290243469 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:54 PM PST 24 271918731 ps
T156 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2627473 Feb 25 01:46:13 PM PST 24 Feb 25 01:46:22 PM PST 24 768959843 ps
T1053 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.466956555 Feb 25 01:46:18 PM PST 24 Feb 25 01:46:33 PM PST 24 1431179736 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1506996220 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:53 PM PST 24 53854253 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3634391107 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:11 PM PST 24 25166567 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.438545612 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:02 PM PST 24 159336922 ps
T1057 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.404838827 Feb 25 01:46:32 PM PST 24 Feb 25 01:46:33 PM PST 24 42436936 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1825182455 Feb 25 01:45:58 PM PST 24 Feb 25 01:45:59 PM PST 24 22760288 ps
T1059 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2565851522 Feb 25 01:46:01 PM PST 24 Feb 25 01:46:02 PM PST 24 52782608 ps
T1060 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2173851909 Feb 25 01:46:39 PM PST 24 Feb 25 01:46:40 PM PST 24 18268590 ps
T1061 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3836132835 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:38 PM PST 24 27887907 ps
T1062 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4041163678 Feb 25 01:46:19 PM PST 24 Feb 25 01:46:20 PM PST 24 17571829 ps
T1063 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3504289984 Feb 25 01:46:23 PM PST 24 Feb 25 01:46:31 PM PST 24 724679568 ps
T1064 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3416474437 Feb 25 01:46:30 PM PST 24 Feb 25 01:46:31 PM PST 24 10219101 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1873495036 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:04 PM PST 24 114611636 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3774387830 Feb 25 01:46:16 PM PST 24 Feb 25 01:46:24 PM PST 24 249764870 ps
T1067 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1487003498 Feb 25 01:46:07 PM PST 24 Feb 25 01:46:09 PM PST 24 176157670 ps
T1068 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4009455421 Feb 25 01:46:28 PM PST 24 Feb 25 01:46:29 PM PST 24 18918371 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3071409844 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:11 PM PST 24 132409891 ps
T1070 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1535928164 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:11 PM PST 24 16318624 ps
T1071 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.972891013 Feb 25 01:46:20 PM PST 24 Feb 25 01:46:22 PM PST 24 77212477 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3123203516 Feb 25 01:46:09 PM PST 24 Feb 25 01:46:11 PM PST 24 103397804 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1918114330 Feb 25 01:46:18 PM PST 24 Feb 25 01:46:19 PM PST 24 20124310 ps
T1074 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1906863849 Feb 25 01:46:11 PM PST 24 Feb 25 01:46:12 PM PST 24 34189298 ps
T1075 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.496088783 Feb 25 01:45:58 PM PST 24 Feb 25 01:45:59 PM PST 24 11899687 ps
T1076 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1632637507 Feb 25 01:46:30 PM PST 24 Feb 25 01:46:31 PM PST 24 11911006 ps
T1077 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2640351184 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:03 PM PST 24 357389630 ps
T1078 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2778535934 Feb 25 01:46:28 PM PST 24 Feb 25 01:46:30 PM PST 24 20523010 ps
T1079 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2740284342 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:34 PM PST 24 17271521 ps
T1080 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.628858018 Feb 25 01:46:03 PM PST 24 Feb 25 01:46:06 PM PST 24 76751995 ps
T1081 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1547865071 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:58 PM PST 24 764291736 ps
T1082 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4022613724 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:57 PM PST 24 183985504 ps
T1083 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.980112643 Feb 25 01:46:17 PM PST 24 Feb 25 01:46:18 PM PST 24 44610145 ps
T1084 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4277820408 Feb 25 01:46:13 PM PST 24 Feb 25 01:46:17 PM PST 24 56170358 ps
T1085 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2877901819 Feb 25 01:46:32 PM PST 24 Feb 25 01:46:33 PM PST 24 86947649 ps
T1086 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2771577212 Feb 25 01:46:14 PM PST 24 Feb 25 01:46:17 PM PST 24 234062555 ps
T1087 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1428988811 Feb 25 01:46:13 PM PST 24 Feb 25 01:46:17 PM PST 24 164263129 ps

Test location /workspace/coverage/default/27.keymgr_stress_all.2524456788
Short name T12
Test name
Test status
Simulation time 299231835 ps
CPU time 8.21 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 214728 kb
Host smart-835636bf-8ade-468c-89da-430a80114856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524456788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2524456788
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2950084632
Short name T42
Test name
Test status
Simulation time 11142800712 ps
CPU time 73.26 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:43:26 PM PST 24
Peak memory 215804 kb
Host smart-39ada6d6-2e0a-4d55-a321-b764f3dac5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950084632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2950084632
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.380585401
Short name T41
Test name
Test status
Simulation time 1107829910 ps
CPU time 22.9 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 220420 kb
Host smart-1f463124-c51a-4536-9700-18e23cfce776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380585401 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.380585401
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.646034775
Short name T6
Test name
Test status
Simulation time 11927254289 ps
CPU time 204.63 seconds
Started Feb 25 02:40:19 PM PST 24
Finished Feb 25 02:43:44 PM PST 24
Peak memory 275160 kb
Host smart-d8d622c3-dea4-4964-8603-250f4badf8f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646034775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.646034775
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3677758533
Short name T61
Test name
Test status
Simulation time 4393231280 ps
CPU time 35.1 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 216900 kb
Host smart-3f2cf701-37a8-4efb-b00a-d0fc0ba39a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677758533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3677758533
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1653137731
Short name T7
Test name
Test status
Simulation time 4220667323 ps
CPU time 46.46 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 221464 kb
Host smart-f185dc0d-08ab-4cb9-a96f-20ae519c0f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653137731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1653137731
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2083624924
Short name T120
Test name
Test status
Simulation time 855102550 ps
CPU time 14.75 seconds
Started Feb 25 02:40:54 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 215360 kb
Host smart-68ee3c03-eac7-44c2-ab7e-ad0e7bdf2240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083624924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2083624924
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2674370331
Short name T117
Test name
Test status
Simulation time 217242801 ps
CPU time 7.1 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:28 PM PST 24
Peak memory 213812 kb
Host smart-dd6d9628-6749-418f-a1d1-2d0d0eacae93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674370331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2674370331
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2471059260
Short name T244
Test name
Test status
Simulation time 685188313 ps
CPU time 29.46 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 222216 kb
Host smart-cc2466fa-9d3d-49d5-a465-eefe38726c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471059260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2471059260
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2303117740
Short name T45
Test name
Test status
Simulation time 2311577236 ps
CPU time 20.57 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 222448 kb
Host smart-8be34d25-5c04-4d69-90f9-95930dfdec15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303117740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2303117740
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3466674621
Short name T47
Test name
Test status
Simulation time 2037749108 ps
CPU time 24.48 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 222492 kb
Host smart-522ad7fe-d09b-49b1-84c9-3820cffbe4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466674621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3466674621
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1990067211
Short name T20
Test name
Test status
Simulation time 192092615 ps
CPU time 5.55 seconds
Started Feb 25 02:40:54 PM PST 24
Finished Feb 25 02:41:00 PM PST 24
Peak memory 214288 kb
Host smart-23b1d7cd-3f20-4ddd-91f3-6f34e2ee68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990067211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1990067211
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2187883518
Short name T258
Test name
Test status
Simulation time 940966702 ps
CPU time 11.97 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 213228 kb
Host smart-0e2f3386-ea18-41ca-bf30-710263da9d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187883518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2187883518
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3383274096
Short name T397
Test name
Test status
Simulation time 904631120 ps
CPU time 48.43 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 214228 kb
Host smart-240da31d-6b9f-4456-9e4d-6503c5a1abdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383274096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3383274096
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.739211439
Short name T115
Test name
Test status
Simulation time 487418901 ps
CPU time 23.67 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 222464 kb
Host smart-cd51bca5-b7a8-4d84-8a45-ffbbd22d7d3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739211439 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.739211439
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.41191508
Short name T36
Test name
Test status
Simulation time 67935367 ps
CPU time 3.94 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 209916 kb
Host smart-fb847f99-8437-429b-ae37-c874a4467474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41191508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.41191508
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2511053465
Short name T349
Test name
Test status
Simulation time 185313172 ps
CPU time 9.84 seconds
Started Feb 25 02:41:50 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 215572 kb
Host smart-7798d9b7-0c00-42d0-bf65-72b949dd046b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511053465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2511053465
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3097546505
Short name T64
Test name
Test status
Simulation time 2001662557 ps
CPU time 47.5 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 219940 kb
Host smart-91f856f8-36db-4ea9-8da0-177c76d52c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097546505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3097546505
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1061619746
Short name T163
Test name
Test status
Simulation time 72574362 ps
CPU time 2.1 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:42:55 PM PST 24
Peak memory 209352 kb
Host smart-76ade971-dd97-4cce-a225-0bc75cf0b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061619746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1061619746
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1424655881
Short name T395
Test name
Test status
Simulation time 2128172178 ps
CPU time 111.6 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:44:07 PM PST 24
Peak memory 213884 kb
Host smart-1f6918a5-bd5c-4e51-b333-8987a85a8e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424655881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1424655881
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1573371883
Short name T108
Test name
Test status
Simulation time 346180758 ps
CPU time 12.04 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 215576 kb
Host smart-199bb6d8-4a8e-46ed-87b6-b02764769436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573371883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1573371883
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3034675624
Short name T205
Test name
Test status
Simulation time 638740327 ps
CPU time 32.62 seconds
Started Feb 25 02:41:44 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 222448 kb
Host smart-96ca858a-4cfe-4035-a3c4-f485d3f2d16b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034675624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3034675624
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.606949929
Short name T231
Test name
Test status
Simulation time 1420569182 ps
CPU time 17.23 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:54 PM PST 24
Peak memory 214388 kb
Host smart-d4fcd0b6-b780-4b09-9c67-338eed732c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606949929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.606949929
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.537953299
Short name T38
Test name
Test status
Simulation time 59174888 ps
CPU time 2.83 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 219828 kb
Host smart-dbdb271e-0b41-40a3-bdb9-ec7059904e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537953299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.537953299
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.581618981
Short name T963
Test name
Test status
Simulation time 677400663 ps
CPU time 8.88 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 213728 kb
Host smart-c39e8945-8a18-4a23-b697-1ff0f2415a82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581618981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.581618981
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3664698650
Short name T31
Test name
Test status
Simulation time 120786671 ps
CPU time 2.59 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 211416 kb
Host smart-55986370-362d-43b9-af62-39e74ececd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664698650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3664698650
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2112614156
Short name T18
Test name
Test status
Simulation time 115664101 ps
CPU time 4.52 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 210008 kb
Host smart-668d983e-d05d-49df-adab-fc05b1d2c21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112614156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2112614156
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3884882892
Short name T250
Test name
Test status
Simulation time 249024179 ps
CPU time 13.51 seconds
Started Feb 25 02:40:03 PM PST 24
Finished Feb 25 02:40:17 PM PST 24
Peak memory 214936 kb
Host smart-568f5767-ec92-4e2a-98c6-024dc78e3566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884882892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3884882892
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2142960224
Short name T34
Test name
Test status
Simulation time 702541743 ps
CPU time 7.2 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:09 PM PST 24
Peak memory 209796 kb
Host smart-3fd253cf-2f9f-42b4-a429-cc63358c3fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142960224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2142960224
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2362841981
Short name T112
Test name
Test status
Simulation time 239293737 ps
CPU time 12.71 seconds
Started Feb 25 02:41:39 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 222412 kb
Host smart-a7479ffc-7058-499f-907d-1a68e60b0ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362841981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2362841981
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.874727354
Short name T315
Test name
Test status
Simulation time 294652390 ps
CPU time 7.83 seconds
Started Feb 25 02:41:59 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 214540 kb
Host smart-509a6921-ea99-402d-b089-68598b7a2850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874727354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.874727354
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.836032964
Short name T219
Test name
Test status
Simulation time 3388821838 ps
CPU time 38.13 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:51 PM PST 24
Peak memory 215916 kb
Host smart-1b2275af-7a79-424a-8356-0269d755453d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836032964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.836032964
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2505240989
Short name T97
Test name
Test status
Simulation time 10543892 ps
CPU time 0.89 seconds
Started Feb 25 02:40:06 PM PST 24
Finished Feb 25 02:40:07 PM PST 24
Peak memory 205812 kb
Host smart-4899b70b-e8f5-497f-9ef7-69021ad344e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505240989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2505240989
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.827923465
Short name T152
Test name
Test status
Simulation time 1601057532 ps
CPU time 9.86 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 208532 kb
Host smart-2f9dcdd4-b1ab-45b9-a747-08ef7bfcdc48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827923465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.827923465
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3374105634
Short name T28
Test name
Test status
Simulation time 153398570 ps
CPU time 4.49 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:08 PM PST 24
Peak memory 210192 kb
Host smart-3026ad43-61e3-4445-a047-493fa57b7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374105634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3374105634
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.367648701
Short name T265
Test name
Test status
Simulation time 641134056 ps
CPU time 9.21 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 214200 kb
Host smart-99efb75a-ea9f-4438-90db-879935eac870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367648701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.367648701
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3515287270
Short name T396
Test name
Test status
Simulation time 867887303 ps
CPU time 12.61 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:20 PM PST 24
Peak memory 215384 kb
Host smart-84501e92-cb7f-42b9-a4d7-5132e31b74ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515287270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3515287270
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1357570427
Short name T50
Test name
Test status
Simulation time 774736979 ps
CPU time 14.53 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:40:36 PM PST 24
Peak memory 222484 kb
Host smart-3329f235-d629-43ea-82b2-58329558f89d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357570427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1357570427
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1848824368
Short name T72
Test name
Test status
Simulation time 4023747905 ps
CPU time 92.26 seconds
Started Feb 25 02:42:18 PM PST 24
Finished Feb 25 02:43:50 PM PST 24
Peak memory 219732 kb
Host smart-64b11702-6f7b-4f34-a93a-f18c371ce84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848824368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1848824368
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.394497596
Short name T166
Test name
Test status
Simulation time 106426411 ps
CPU time 5.6 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:29 PM PST 24
Peak memory 208688 kb
Host smart-726ef59e-b14c-46fb-8cf8-0dbd2f3732df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394497596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.394497596
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3982869321
Short name T359
Test name
Test status
Simulation time 6519005534 ps
CPU time 71.66 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:41:57 PM PST 24
Peak memory 207760 kb
Host smart-1592cc88-ff33-45e3-8f04-9bf456cda699
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982869321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3982869321
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2818374136
Short name T220
Test name
Test status
Simulation time 500558637 ps
CPU time 28.23 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 214580 kb
Host smart-c303bbd2-5336-466c-ae88-797d379c50b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818374136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2818374136
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.677408979
Short name T259
Test name
Test status
Simulation time 53296770 ps
CPU time 4.06 seconds
Started Feb 25 02:41:39 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 214164 kb
Host smart-e8eb0444-2e9b-403c-bd1d-c73160bff03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677408979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.677408979
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2101236699
Short name T323
Test name
Test status
Simulation time 53072130782 ps
CPU time 344.44 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:48:18 PM PST 24
Peak memory 222364 kb
Host smart-00404763-ea12-466b-9bcc-87e75c840717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101236699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2101236699
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2107790929
Short name T85
Test name
Test status
Simulation time 2154488343 ps
CPU time 23.01 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:43:01 PM PST 24
Peak memory 210364 kb
Host smart-d9d13d95-975d-4d3a-a58f-398a3acf3850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107790929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2107790929
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2745297753
Short name T59
Test name
Test status
Simulation time 39493899 ps
CPU time 2.91 seconds
Started Feb 25 02:41:05 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 211644 kb
Host smart-1d97fc52-1d74-4ff5-9008-be0a956cb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745297753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2745297753
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4120189649
Short name T76
Test name
Test status
Simulation time 95205999 ps
CPU time 1.93 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:56 PM PST 24
Peak memory 216568 kb
Host smart-d1d971b9-7aab-46df-b9b7-6d5ecfa94f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120189649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4120189649
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3869076340
Short name T313
Test name
Test status
Simulation time 3704087994 ps
CPU time 31.55 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 208620 kb
Host smart-85eebf74-52d5-40e1-923a-edac3f339f0f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869076340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3869076340
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.19209876
Short name T284
Test name
Test status
Simulation time 221569739 ps
CPU time 3.56 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 221808 kb
Host smart-0fb1ef59-ddeb-4fcc-a59e-d3fe64a5001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19209876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.19209876
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2580260728
Short name T898
Test name
Test status
Simulation time 70822845 ps
CPU time 3.73 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 214140 kb
Host smart-bcb2da72-ab89-48a9-9bd1-9ff76cb8d983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580260728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2580260728
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2864391683
Short name T52
Test name
Test status
Simulation time 299789592 ps
CPU time 3.61 seconds
Started Feb 25 02:41:51 PM PST 24
Finished Feb 25 02:41:54 PM PST 24
Peak memory 210916 kb
Host smart-977c9385-a96b-4ec3-b4ce-8dc33c5d4ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864391683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2864391683
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.252373194
Short name T330
Test name
Test status
Simulation time 387754485 ps
CPU time 8.46 seconds
Started Feb 25 02:40:36 PM PST 24
Finished Feb 25 02:40:45 PM PST 24
Peak memory 210192 kb
Host smart-0a121940-2798-4492-b17d-1bd7ef8c55b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252373194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.252373194
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1813727678
Short name T218
Test name
Test status
Simulation time 500609009 ps
CPU time 24.18 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 214816 kb
Host smart-48217d95-06ea-45c4-bdab-458ff07ea54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813727678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1813727678
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1782561454
Short name T445
Test name
Test status
Simulation time 219717748 ps
CPU time 4.82 seconds
Started Feb 25 02:42:40 PM PST 24
Finished Feb 25 02:42:50 PM PST 24
Peak memory 222360 kb
Host smart-693b6f4c-308e-4d82-a6a3-76356de364a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782561454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1782561454
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.12061682
Short name T165
Test name
Test status
Simulation time 253915299 ps
CPU time 6.41 seconds
Started Feb 25 01:46:04 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 208404 kb
Host smart-30cf7f74-0da2-4252-8b0f-b20d25ceff7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.12061682
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2182328803
Short name T173
Test name
Test status
Simulation time 427376908 ps
CPU time 10.61 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:09 PM PST 24
Peak memory 213580 kb
Host smart-a62ca532-1981-4b7e-9dd4-1967a8c159b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182328803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2182328803
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.536644397
Short name T113
Test name
Test status
Simulation time 567218474 ps
CPU time 6.82 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 215588 kb
Host smart-8af28b2d-7c43-4b5a-9772-18cb1e763e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536644397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.536644397
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4008976509
Short name T111
Test name
Test status
Simulation time 1537657175 ps
CPU time 5.15 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 222688 kb
Host smart-5e92d5fe-6d89-4355-8c90-4ed199b3d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008976509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4008976509
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1406783543
Short name T197
Test name
Test status
Simulation time 17727103770 ps
CPU time 36.02 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 207620 kb
Host smart-27affc88-4c5a-4eb4-8e52-8040f819f4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406783543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1406783543
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3948839328
Short name T332
Test name
Test status
Simulation time 323872292 ps
CPU time 10.1 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:22 PM PST 24
Peak memory 222276 kb
Host smart-e71caf13-b927-4865-a1e3-41f137c6380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948839328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3948839328
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.1814122859
Short name T128
Test name
Test status
Simulation time 1179179537 ps
CPU time 6.49 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 214128 kb
Host smart-cdfd745d-ff71-4b98-b28d-0c1e8bbd3ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814122859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1814122859
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2890218476
Short name T251
Test name
Test status
Simulation time 192390491 ps
CPU time 4.03 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:42:01 PM PST 24
Peak memory 214228 kb
Host smart-2a6b1eb5-8093-4bbc-b568-8b538c56351f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890218476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2890218476
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1894964672
Short name T436
Test name
Test status
Simulation time 372707581 ps
CPU time 5.83 seconds
Started Feb 25 02:42:04 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 208584 kb
Host smart-1ca25ca0-09c3-42a9-8ba4-9ad55fc6f81e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894964672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1894964672
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1714981136
Short name T311
Test name
Test status
Simulation time 62444349 ps
CPU time 2.51 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 214176 kb
Host smart-795c427b-b320-499c-bae2-40c11904f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714981136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1714981136
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3301262669
Short name T170
Test name
Test status
Simulation time 142031937 ps
CPU time 5.05 seconds
Started Feb 25 01:46:26 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 208712 kb
Host smart-68e49a00-e6ef-4d40-b3b1-96e3b8b8c1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301262669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3301262669
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1779462060
Short name T158
Test name
Test status
Simulation time 63158174 ps
CPU time 2.23 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 209912 kb
Host smart-7ab437e8-df91-4cc3-85d3-970787badf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779462060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1779462060
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4084225376
Short name T222
Test name
Test status
Simulation time 82249820 ps
CPU time 2.1 seconds
Started Feb 25 02:40:39 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 214080 kb
Host smart-8bd8e038-9cad-45e5-8ddb-6df1ac5bc302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084225376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4084225376
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1914719785
Short name T40
Test name
Test status
Simulation time 364941715 ps
CPU time 1.93 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 209792 kb
Host smart-7f99951d-1743-45d4-bf8c-63efe6ccf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914719785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1914719785
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4067496310
Short name T281
Test name
Test status
Simulation time 239442852 ps
CPU time 5.84 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:40:55 PM PST 24
Peak memory 222328 kb
Host smart-332d6bef-8ad4-41aa-9a74-f9a711ca775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067496310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4067496310
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4167914646
Short name T3
Test name
Test status
Simulation time 1632321395 ps
CPU time 16.01 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 208944 kb
Host smart-538e88b3-3ac1-4fdf-9d02-79065fedb98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167914646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4167914646
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3392441706
Short name T344
Test name
Test status
Simulation time 181580987 ps
CPU time 3.76 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 214196 kb
Host smart-a9fc20c6-d782-4761-955b-306e7510e63f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392441706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3392441706
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3970416442
Short name T375
Test name
Test status
Simulation time 49188772 ps
CPU time 3.4 seconds
Started Feb 25 02:41:23 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 222068 kb
Host smart-33fc2a37-df3a-4e38-a847-9864a1c12cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970416442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3970416442
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2758502797
Short name T9
Test name
Test status
Simulation time 232061280 ps
CPU time 3.4 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 221764 kb
Host smart-37de7e3c-e12f-44df-aeb0-72a481850d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758502797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2758502797
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1502646063
Short name T14
Test name
Test status
Simulation time 914275986 ps
CPU time 10.02 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 214676 kb
Host smart-15994f59-61dc-4326-86cb-47fbf730e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502646063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1502646063
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.519960192
Short name T892
Test name
Test status
Simulation time 5183270853 ps
CPU time 33.85 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 216636 kb
Host smart-7ee037fe-76c0-411e-bc61-6a8d28ad1459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519960192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.519960192
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1539248004
Short name T217
Test name
Test status
Simulation time 710183483 ps
CPU time 4.82 seconds
Started Feb 25 02:41:44 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 217204 kb
Host smart-5ec954e4-3894-4e69-a443-27c429b1172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539248004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1539248004
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3720440380
Short name T366
Test name
Test status
Simulation time 220607644 ps
CPU time 11.89 seconds
Started Feb 25 02:42:18 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 221524 kb
Host smart-11e4696a-5820-4031-8994-b71ac2f47b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720440380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3720440380
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.4066440568
Short name T245
Test name
Test status
Simulation time 1123316789 ps
CPU time 17.49 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:48 PM PST 24
Peak memory 214144 kb
Host smart-70b3d563-1784-4e75-bc1c-7cf5fd557023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066440568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4066440568
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2078609945
Short name T357
Test name
Test status
Simulation time 75280996 ps
CPU time 4.29 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 214156 kb
Host smart-702aea49-c344-4d78-b390-24f9add5e667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078609945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2078609945
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3114548023
Short name T299
Test name
Test status
Simulation time 591128960 ps
CPU time 8.04 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:37 PM PST 24
Peak memory 214080 kb
Host smart-b7f2fcf3-7c8d-423b-9401-0e45e5a8fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114548023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3114548023
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2918441929
Short name T319
Test name
Test status
Simulation time 375199462 ps
CPU time 19.78 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 214740 kb
Host smart-2db9c495-5f2f-41ef-908c-71cd050de570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918441929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2918441929
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3891317946
Short name T161
Test name
Test status
Simulation time 171376178 ps
CPU time 3.37 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 213624 kb
Host smart-c176c4d6-4ea2-475b-ab77-3b9c5ce96419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891317946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3891317946
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2410137900
Short name T159
Test name
Test status
Simulation time 4368129478 ps
CPU time 8.98 seconds
Started Feb 25 01:46:22 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 208832 kb
Host smart-7788d333-6a37-488f-9a66-bcce576c011a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410137900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2410137900
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2694843022
Short name T172
Test name
Test status
Simulation time 382204138 ps
CPU time 6.29 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:29 PM PST 24
Peak memory 208696 kb
Host smart-fe3fb824-6e7b-47ff-9c9b-dc2961badd4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694843022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2694843022
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4039388356
Short name T157
Test name
Test status
Simulation time 223282264 ps
CPU time 2.97 seconds
Started Feb 25 02:40:40 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 209664 kb
Host smart-accbd811-de12-462b-8352-2bc666e40eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039388356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4039388356
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1536613024
Short name T401
Test name
Test status
Simulation time 39206374 ps
CPU time 2.76 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:40:52 PM PST 24
Peak memory 215356 kb
Host smart-bd21a209-e3a3-43ae-9e65-e110af2c8dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536613024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1536613024
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.446376223
Short name T280
Test name
Test status
Simulation time 318466681 ps
CPU time 5.38 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 222280 kb
Host smart-269bc490-8e2f-4d23-97c5-c5168d75c288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446376223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.446376223
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1337519883
Short name T180
Test name
Test status
Simulation time 2532910138 ps
CPU time 22.45 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 222584 kb
Host smart-b80cfcd6-98e7-49c0-a84b-d4e536d901c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337519883 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1337519883
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3532260639
Short name T370
Test name
Test status
Simulation time 3096032729 ps
CPU time 49.49 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 215212 kb
Host smart-9a56dccd-40ee-4357-a10e-7d94957d1322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532260639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3532260639
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2208859896
Short name T336
Test name
Test status
Simulation time 247839727 ps
CPU time 6.4 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 220172 kb
Host smart-6c6b5db3-4b2c-4a45-8212-9faf746ce0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208859896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2208859896
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.126430620
Short name T405
Test name
Test status
Simulation time 40981629 ps
CPU time 3.21 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:50 PM PST 24
Peak memory 214988 kb
Host smart-8be5d616-dc93-42ea-9a5b-955977153d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126430620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.126430620
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3131774657
Short name T179
Test name
Test status
Simulation time 1917748359 ps
CPU time 27.11 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 222520 kb
Host smart-1dcd1db5-cca9-4e7a-a3f3-b2580fc72a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131774657 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3131774657
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.845304859
Short name T214
Test name
Test status
Simulation time 119471958 ps
CPU time 5.14 seconds
Started Feb 25 02:41:44 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 220068 kb
Host smart-26cfecc4-17aa-456e-9b43-724bdaea6e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845304859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.845304859
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3146913944
Short name T328
Test name
Test status
Simulation time 106920474 ps
CPU time 3.62 seconds
Started Feb 25 02:42:17 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 207292 kb
Host smart-fbef9396-a3a0-4bf1-895d-138c27fda20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146913944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3146913944
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2405209343
Short name T271
Test name
Test status
Simulation time 91318348 ps
CPU time 3.76 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:29 PM PST 24
Peak memory 215364 kb
Host smart-afd31068-39e5-4edd-a9f3-1285c1a42d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405209343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2405209343
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3669056916
Short name T237
Test name
Test status
Simulation time 3979362440 ps
CPU time 57.63 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 226332 kb
Host smart-cea3fc5f-8eab-495c-85c4-744dd43914c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669056916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3669056916
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1547865071
Short name T1081
Test name
Test status
Simulation time 764291736 ps
CPU time 5.06 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:58 PM PST 24
Peak memory 205240 kb
Host smart-ba28dbe1-8ae4-4997-9923-68ae8a9854a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547865071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
547865071
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2584026117
Short name T943
Test name
Test status
Simulation time 1509975684 ps
CPU time 12.99 seconds
Started Feb 25 01:45:57 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 205196 kb
Host smart-e290bc8a-b9c3-4ada-8373-1f3b365d3331
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584026117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
584026117
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.469972111
Short name T932
Test name
Test status
Simulation time 25527222 ps
CPU time 0.98 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 205160 kb
Host smart-5e0e7407-7f86-4157-870e-10f864a28ed0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469972111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.469972111
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1835762126
Short name T1048
Test name
Test status
Simulation time 34996602 ps
CPU time 1.42 seconds
Started Feb 25 01:45:55 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 213640 kb
Host smart-95a24679-3881-4540-831c-cce8c1c86f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835762126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1835762126
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1665459886
Short name T938
Test name
Test status
Simulation time 72932590 ps
CPU time 0.85 seconds
Started Feb 25 01:46:05 PM PST 24
Finished Feb 25 01:46:05 PM PST 24
Peak memory 205180 kb
Host smart-ba66167c-80b9-4e46-bfd7-dc76759d3113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665459886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1665459886
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1923094924
Short name T952
Test name
Test status
Simulation time 39422912 ps
CPU time 0.72 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 205180 kb
Host smart-2396d527-6964-40f0-9707-93335bcd2ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923094924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1923094924
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.334690904
Short name T144
Test name
Test status
Simulation time 63957042 ps
CPU time 1.88 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 205372 kb
Host smart-dd1a93c2-2748-408d-892c-13f5c23eb275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334690904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.334690904
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3455395096
Short name T1031
Test name
Test status
Simulation time 587662283 ps
CPU time 4.95 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 213820 kb
Host smart-09a6beaa-1e2e-45bf-8e62-d5ae40064f33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455395096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3455395096
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1119367254
Short name T1029
Test name
Test status
Simulation time 95620370 ps
CPU time 4.75 seconds
Started Feb 25 01:45:55 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 219724 kb
Host smart-cdf18500-2c34-4606-9ad2-738bc6319427
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119367254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1119367254
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3351658027
Short name T1012
Test name
Test status
Simulation time 129454886 ps
CPU time 1.84 seconds
Started Feb 25 01:45:56 PM PST 24
Finished Feb 25 01:45:58 PM PST 24
Peak memory 213588 kb
Host smart-6ced2622-f735-4767-8151-df4c51784a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351658027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3351658027
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3320246500
Short name T150
Test name
Test status
Simulation time 1299237892 ps
CPU time 12.91 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 208732 kb
Host smart-053c8561-0c53-46f3-85fb-0041410be863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320246500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3320246500
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1180847424
Short name T1041
Test name
Test status
Simulation time 1174243404 ps
CPU time 7.79 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 205344 kb
Host smart-b9ad62f7-0605-4a29-8e94-1a55d005cf57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180847424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
180847424
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3014852360
Short name T947
Test name
Test status
Simulation time 499628825 ps
CPU time 12.11 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:15 PM PST 24
Peak memory 205288 kb
Host smart-e237c7fb-9d38-4a64-b74e-5e748afc5a75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014852360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
014852360
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1756705878
Short name T992
Test name
Test status
Simulation time 441189555 ps
CPU time 1.19 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 205252 kb
Host smart-c7b2f005-216d-479c-93fd-435bbd52dc25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756705878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
756705878
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2290243469
Short name T1052
Test name
Test status
Simulation time 271918731 ps
CPU time 2.28 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 216932 kb
Host smart-753b954b-4179-4246-98a4-117996580f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290243469 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2290243469
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1879651490
Short name T142
Test name
Test status
Simulation time 126651441 ps
CPU time 1.15 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 205368 kb
Host smart-c0f1840b-6109-484f-854b-13404602dfe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879651490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1879651490
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.323433888
Short name T919
Test name
Test status
Simulation time 124820771 ps
CPU time 0.84 seconds
Started Feb 25 01:45:56 PM PST 24
Finished Feb 25 01:45:57 PM PST 24
Peak memory 205176 kb
Host smart-5d542691-ac17-4642-ad1f-f9ec69551304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323433888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.323433888
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1851395416
Short name T143
Test name
Test status
Simulation time 242672122 ps
CPU time 2.51 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 205368 kb
Host smart-49d28464-66ab-45c6-b0f7-7acef79fcf15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851395416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1851395416
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3196976381
Short name T1036
Test name
Test status
Simulation time 158726037 ps
CPU time 3.12 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 213840 kb
Host smart-ec7ecb65-2483-4b7f-ad93-0cbeb87ff8c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196976381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3196976381
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4023740414
Short name T953
Test name
Test status
Simulation time 284439049 ps
CPU time 4.71 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:57 PM PST 24
Peak memory 219564 kb
Host smart-b1d95912-c43c-48c5-b240-264597e911b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023740414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4023740414
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2837364014
Short name T972
Test name
Test status
Simulation time 59358944 ps
CPU time 1.64 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 205388 kb
Host smart-2f1e3989-5e8a-4747-a756-9151fe4d4661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837364014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2837364014
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2123159873
Short name T1001
Test name
Test status
Simulation time 119846518 ps
CPU time 1.23 seconds
Started Feb 25 01:46:12 PM PST 24
Finished Feb 25 01:46:13 PM PST 24
Peak memory 205432 kb
Host smart-fb34f56f-3133-4156-a5c3-66fe5e43ecf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123159873 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2123159873
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1885132456
Short name T977
Test name
Test status
Simulation time 9861146 ps
CPU time 1.03 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:14 PM PST 24
Peak memory 205328 kb
Host smart-7bc67462-a772-47e3-ac0e-1d05d6f171a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885132456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1885132456
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3747283446
Short name T966
Test name
Test status
Simulation time 14737836 ps
CPU time 0.75 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:14 PM PST 24
Peak memory 205028 kb
Host smart-47ba6ba4-351b-4880-9819-a3deaad7c3dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747283446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3747283446
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.120748486
Short name T954
Test name
Test status
Simulation time 19779823 ps
CPU time 1.38 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:08 PM PST 24
Peak memory 205324 kb
Host smart-0371a2e2-7212-47a5-9c67-312675368536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120748486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.120748486
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1045800120
Short name T1020
Test name
Test status
Simulation time 128497039 ps
CPU time 2.99 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 213884 kb
Host smart-0d103b18-3c6c-414c-9cb1-a6c68e68cc9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045800120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1045800120
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.229299934
Short name T988
Test name
Test status
Simulation time 310517771 ps
CPU time 3.79 seconds
Started Feb 25 01:46:08 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213820 kb
Host smart-8b6e1e50-f48a-4741-94f8-9730e2032ba8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229299934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.229299934
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4242581497
Short name T1025
Test name
Test status
Simulation time 32862274 ps
CPU time 2.13 seconds
Started Feb 25 01:46:12 PM PST 24
Finished Feb 25 01:46:15 PM PST 24
Peak memory 221292 kb
Host smart-7439395f-123a-4e27-aeb4-177d9bbcf2c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242581497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4242581497
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.26814113
Short name T925
Test name
Test status
Simulation time 90875709 ps
CPU time 1.09 seconds
Started Feb 25 01:46:11 PM PST 24
Finished Feb 25 01:46:13 PM PST 24
Peak memory 205328 kb
Host smart-43a902bc-61ea-446c-a650-72cc8a1387f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814113 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.26814113
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.65310117
Short name T1032
Test name
Test status
Simulation time 201765671 ps
CPU time 0.98 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205196 kb
Host smart-3a61c9d8-fef5-4ecc-a937-83b6e1c40e79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65310117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.65310117
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3645104229
Short name T929
Test name
Test status
Simulation time 48195365 ps
CPU time 0.86 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 205068 kb
Host smart-7fccc848-a524-43b7-94a4-d0475064eceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645104229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3645104229
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2771577212
Short name T1086
Test name
Test status
Simulation time 234062555 ps
CPU time 2.73 seconds
Started Feb 25 01:46:14 PM PST 24
Finished Feb 25 01:46:17 PM PST 24
Peak memory 205312 kb
Host smart-9c8c8cba-485d-4ac3-a315-4b8f4d1007fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771577212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2771577212
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.740585190
Short name T973
Test name
Test status
Simulation time 424300045 ps
CPU time 2.99 seconds
Started Feb 25 01:46:08 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 213816 kb
Host smart-3e2c291d-f51a-48b0-a405-85fb0c6201b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740585190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.740585190
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4277820408
Short name T1084
Test name
Test status
Simulation time 56170358 ps
CPU time 3.87 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:17 PM PST 24
Peak memory 221740 kb
Host smart-9cfe3ba7-4a8e-4474-a15a-eb0cfcbbd630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277820408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4277820408
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3397868926
Short name T1019
Test name
Test status
Simulation time 2358352835 ps
CPU time 13.08 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 208704 kb
Host smart-62c2e6d1-4748-49e4-a358-63f2dd376a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397868926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3397868926
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2954988032
Short name T967
Test name
Test status
Simulation time 199462636 ps
CPU time 1.97 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213496 kb
Host smart-82c8808a-1574-4867-b35c-91814064df0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954988032 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2954988032
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1535928164
Short name T1070
Test name
Test status
Simulation time 16318624 ps
CPU time 1.17 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205296 kb
Host smart-95c7e2aa-52b5-4b3d-8b0d-d6d2e572305e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535928164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1535928164
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.14023060
Short name T917
Test name
Test status
Simulation time 19248683 ps
CPU time 0.73 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 205188 kb
Host smart-f4f7f2d8-707d-4c9b-befb-84d87a0eec05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14023060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.14023060
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3071409844
Short name T1069
Test name
Test status
Simulation time 132409891 ps
CPU time 2.05 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205412 kb
Host smart-088844c6-5167-4779-bf43-85058ddd4c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071409844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3071409844
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3863737648
Short name T1010
Test name
Test status
Simulation time 157747073 ps
CPU time 4.68 seconds
Started Feb 25 01:46:08 PM PST 24
Finished Feb 25 01:46:13 PM PST 24
Peak memory 213736 kb
Host smart-f1e18c01-8753-485c-b316-c99e2e5091a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863737648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3863737648
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3774387830
Short name T1066
Test name
Test status
Simulation time 249764870 ps
CPU time 8.23 seconds
Started Feb 25 01:46:16 PM PST 24
Finished Feb 25 01:46:24 PM PST 24
Peak memory 213856 kb
Host smart-95da3e9a-71c8-4c53-b1df-4a67425c3d84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774387830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3774387830
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2140192081
Short name T931
Test name
Test status
Simulation time 153059467 ps
CPU time 1.4 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 213644 kb
Host smart-f02f1276-caa4-433d-afc8-4dbca9e67e03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140192081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2140192081
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2546482148
Short name T1004
Test name
Test status
Simulation time 215186628 ps
CPU time 5.74 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 208884 kb
Host smart-99114ac1-640a-449e-bd0b-40fda5558897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546482148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2546482148
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2975842327
Short name T940
Test name
Test status
Simulation time 63703100 ps
CPU time 1.27 seconds
Started Feb 25 01:46:19 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 213608 kb
Host smart-f9af3dfe-1ac1-4ec9-98a4-a175e7955fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975842327 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2975842327
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2196490711
Short name T1002
Test name
Test status
Simulation time 15329921 ps
CPU time 0.95 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 205160 kb
Host smart-2c3328ba-80bc-4c07-8e5f-f14faf357743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196490711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2196490711
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3698640493
Short name T985
Test name
Test status
Simulation time 14926471 ps
CPU time 0.74 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 205096 kb
Host smart-54713fe6-c45f-4ae9-b494-0441d83db8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698640493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3698640493
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.923067678
Short name T1009
Test name
Test status
Simulation time 149711967 ps
CPU time 3.25 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:23 PM PST 24
Peak memory 205360 kb
Host smart-a366e48e-d879-4922-9e50-f4de6256c6c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923067678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.923067678
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1487003498
Short name T1067
Test name
Test status
Simulation time 176157670 ps
CPU time 1.51 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:09 PM PST 24
Peak memory 213676 kb
Host smart-8da36640-ec04-44f4-9295-7d7100f1d479
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487003498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1487003498
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2408426716
Short name T982
Test name
Test status
Simulation time 285713938 ps
CPU time 7.12 seconds
Started Feb 25 01:46:11 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 213804 kb
Host smart-0ab36bcd-aefa-4e56-8e90-c312d1a64426
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408426716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2408426716
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1821334288
Short name T1033
Test name
Test status
Simulation time 410248952 ps
CPU time 2.89 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 213312 kb
Host smart-e16242bb-6971-476e-bdcf-cb5455fb4cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821334288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1821334288
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2627473
Short name T156
Test name
Test status
Simulation time 768959843 ps
CPU time 9.79 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 208792 kb
Host smart-97b0ba5f-4d1b-430e-94a7-b47a7c242b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.2627473
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1758558264
Short name T989
Test name
Test status
Simulation time 127321581 ps
CPU time 2.17 seconds
Started Feb 25 01:46:28 PM PST 24
Finished Feb 25 01:46:30 PM PST 24
Peak memory 213616 kb
Host smart-839fb77c-0719-4c25-8817-cd3d36c0d0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758558264 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1758558264
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1746349285
Short name T976
Test name
Test status
Simulation time 101310815 ps
CPU time 1.55 seconds
Started Feb 25 01:46:22 PM PST 24
Finished Feb 25 01:46:24 PM PST 24
Peak memory 205208 kb
Host smart-33a4ef05-a28f-4175-ab06-a8617127a0a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746349285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1746349285
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2639736111
Short name T935
Test name
Test status
Simulation time 12694994 ps
CPU time 0.68 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 205172 kb
Host smart-7bcc907e-acfe-4306-a67a-840f592e60bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639736111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2639736111
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.850215495
Short name T1044
Test name
Test status
Simulation time 319827207 ps
CPU time 3.34 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:23 PM PST 24
Peak memory 205328 kb
Host smart-b0eb7c37-3f9d-45e2-9e38-6e2d4ae8c9e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850215495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.850215495
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2637357358
Short name T1005
Test name
Test status
Simulation time 6657009076 ps
CPU time 21.27 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 215112 kb
Host smart-fce173ba-12fa-497c-9bf5-829fe1f831be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637357358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2637357358
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.901242591
Short name T939
Test name
Test status
Simulation time 197587527 ps
CPU time 4.73 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:25 PM PST 24
Peak memory 213688 kb
Host smart-7f12fcf3-fe50-4d87-ae68-778ac12f7e37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901242591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.901242591
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.629582387
Short name T1046
Test name
Test status
Simulation time 44669032 ps
CPU time 1.74 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:23 PM PST 24
Peak memory 213476 kb
Host smart-403498bb-7f1a-4f1f-83ed-1f8c1743576a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629582387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.629582387
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.400942703
Short name T149
Test name
Test status
Simulation time 443922109 ps
CPU time 4.71 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:26 PM PST 24
Peak memory 208868 kb
Host smart-bb29facc-ffab-41e4-85b7-2a8558ec71dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400942703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.400942703
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2778535934
Short name T1078
Test name
Test status
Simulation time 20523010 ps
CPU time 1.25 seconds
Started Feb 25 01:46:28 PM PST 24
Finished Feb 25 01:46:30 PM PST 24
Peak memory 213600 kb
Host smart-9961ce4d-7a0a-4a39-9ae7-bcf53cbe7bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778535934 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2778535934
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1498589724
Short name T969
Test name
Test status
Simulation time 30961336 ps
CPU time 1.59 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 205224 kb
Host smart-8cb45c86-5aea-4c4b-8220-e1aa327e03f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498589724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1498589724
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4009455421
Short name T1068
Test name
Test status
Simulation time 18918371 ps
CPU time 0.84 seconds
Started Feb 25 01:46:28 PM PST 24
Finished Feb 25 01:46:29 PM PST 24
Peak memory 205132 kb
Host smart-963fc791-4dba-458b-8ab5-c082528d8f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009455421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4009455421
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2669211743
Short name T974
Test name
Test status
Simulation time 114413556 ps
CPU time 4.17 seconds
Started Feb 25 01:46:16 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 205340 kb
Host smart-f2f9099c-99bd-4e94-aa2b-9453f1fa4314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669211743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2669211743
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2337081351
Short name T123
Test name
Test status
Simulation time 315534775 ps
CPU time 5.94 seconds
Started Feb 25 01:46:19 PM PST 24
Finished Feb 25 01:46:25 PM PST 24
Peak memory 222048 kb
Host smart-30c393db-6094-4388-8d05-033b27cdeac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337081351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2337081351
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3504289984
Short name T1063
Test name
Test status
Simulation time 724679568 ps
CPU time 7.83 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 213756 kb
Host smart-a602b66b-3f24-439e-8bd4-dff65b375b32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504289984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3504289984
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1180149349
Short name T961
Test name
Test status
Simulation time 90401062 ps
CPU time 2.25 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 213628 kb
Host smart-61cc86a2-6682-4d07-9bd3-5e4482ee5a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180149349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1180149349
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.980112643
Short name T1083
Test name
Test status
Simulation time 44610145 ps
CPU time 1.31 seconds
Started Feb 25 01:46:17 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 205528 kb
Host smart-5f020921-1be9-43c5-a29d-291d509270e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980112643 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.980112643
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4041163678
Short name T1062
Test name
Test status
Simulation time 17571829 ps
CPU time 1.08 seconds
Started Feb 25 01:46:19 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 205312 kb
Host smart-d51bea72-1f84-4759-b0dd-1162103c3057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041163678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4041163678
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1189817899
Short name T965
Test name
Test status
Simulation time 38397405 ps
CPU time 0.72 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 205112 kb
Host smart-8c343488-bfcf-4421-8781-ff95b114f843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189817899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1189817899
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4020040026
Short name T146
Test name
Test status
Simulation time 46026998 ps
CPU time 1.45 seconds
Started Feb 25 01:46:14 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 205404 kb
Host smart-643ba109-3637-4ee3-bf4e-961f918455fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020040026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4020040026
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1653896351
Short name T959
Test name
Test status
Simulation time 451674266 ps
CPU time 13.16 seconds
Started Feb 25 01:46:19 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 213696 kb
Host smart-f81b9eeb-c9ca-494e-a93d-217a7e0b088e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653896351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1653896351
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.466956555
Short name T1053
Test name
Test status
Simulation time 1431179736 ps
CPU time 14.01 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 219756 kb
Host smart-0f8f6e85-87c9-4dc0-94ed-a1597064f315
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466956555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.466956555
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1851103079
Short name T1043
Test name
Test status
Simulation time 135360076 ps
CPU time 4.77 seconds
Started Feb 25 01:46:26 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 213580 kb
Host smart-3abca82b-df52-429d-9a47-85af1c04ab07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851103079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1851103079
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2568826486
Short name T999
Test name
Test status
Simulation time 179331233 ps
CPU time 6.17 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:24 PM PST 24
Peak memory 208996 kb
Host smart-48bce833-24ba-4000-a801-b063ee33d4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568826486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2568826486
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1242623776
Short name T979
Test name
Test status
Simulation time 206381218 ps
CPU time 1.8 seconds
Started Feb 25 01:46:25 PM PST 24
Finished Feb 25 01:46:27 PM PST 24
Peak memory 213692 kb
Host smart-eab4b1d4-c5e4-4fea-9e1d-8a7b2e52b4c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242623776 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1242623776
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.675535898
Short name T948
Test name
Test status
Simulation time 102163921 ps
CPU time 1.09 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:21 PM PST 24
Peak memory 205252 kb
Host smart-f847f796-a639-4757-b1fd-20df6e46ca81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675535898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.675535898
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2507865055
Short name T941
Test name
Test status
Simulation time 14864521 ps
CPU time 0.92 seconds
Started Feb 25 01:46:16 PM PST 24
Finished Feb 25 01:46:17 PM PST 24
Peak memory 205348 kb
Host smart-a2bb32ca-dda0-416a-ada3-abb915a5cd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507865055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2507865055
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.972891013
Short name T1071
Test name
Test status
Simulation time 77212477 ps
CPU time 2.26 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 205376 kb
Host smart-00b197c4-2937-495f-b2ad-f03dcbabff42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972891013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.972891013
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.214392897
Short name T1011
Test name
Test status
Simulation time 159646427 ps
CPU time 3.88 seconds
Started Feb 25 01:46:20 PM PST 24
Finished Feb 25 01:46:24 PM PST 24
Peak memory 213784 kb
Host smart-92502275-5a4d-4a6c-81ea-a7c8155cc62d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214392897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.214392897
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2308515572
Short name T1014
Test name
Test status
Simulation time 229238930 ps
CPU time 2.2 seconds
Started Feb 25 01:46:17 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 213504 kb
Host smart-8720c29a-cede-4131-b79f-bcb701d85596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308515572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2308515572
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1058774603
Short name T926
Test name
Test status
Simulation time 167361983 ps
CPU time 1.57 seconds
Started Feb 25 01:46:28 PM PST 24
Finished Feb 25 01:46:30 PM PST 24
Peak memory 213640 kb
Host smart-3772f51f-6c85-4bec-9101-0f5a850f7ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058774603 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1058774603
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1918114330
Short name T1073
Test name
Test status
Simulation time 20124310 ps
CPU time 1.24 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 205312 kb
Host smart-0b860704-fe15-4bd1-b0cf-37df2d7db451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918114330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1918114330
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2433503123
Short name T914
Test name
Test status
Simulation time 22891420 ps
CPU time 0.74 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:21 PM PST 24
Peak memory 205132 kb
Host smart-6230b75d-001f-4876-80f4-27ca0486bf27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433503123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2433503123
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2341154064
Short name T1000
Test name
Test status
Simulation time 329022842 ps
CPU time 2.26 seconds
Started Feb 25 01:46:24 PM PST 24
Finished Feb 25 01:46:26 PM PST 24
Peak memory 205392 kb
Host smart-05843aa3-f24f-477a-b54b-19d982bb5e83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341154064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2341154064
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1367480783
Short name T1017
Test name
Test status
Simulation time 96945614 ps
CPU time 1.81 seconds
Started Feb 25 01:46:22 PM PST 24
Finished Feb 25 01:46:24 PM PST 24
Peak memory 213772 kb
Host smart-5925c8b8-f56c-4504-be3c-7a4f98ab92ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367480783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1367480783
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3028707217
Short name T960
Test name
Test status
Simulation time 722183541 ps
CPU time 8.5 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 213728 kb
Host smart-fb3b4da2-85ea-4535-8f4e-949c03173929
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028707217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3028707217
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3858411285
Short name T956
Test name
Test status
Simulation time 65885851 ps
CPU time 2.71 seconds
Started Feb 25 01:46:22 PM PST 24
Finished Feb 25 01:46:25 PM PST 24
Peak memory 215796 kb
Host smart-5d368302-1434-4ab2-be18-e34a79173a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858411285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3858411285
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3470005599
Short name T1023
Test name
Test status
Simulation time 16816106 ps
CPU time 1.44 seconds
Started Feb 25 01:46:25 PM PST 24
Finished Feb 25 01:46:27 PM PST 24
Peak memory 213668 kb
Host smart-406e718c-0e4c-4f37-982b-6e9db3ad631a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470005599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3470005599
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1461718537
Short name T1016
Test name
Test status
Simulation time 10162768 ps
CPU time 0.93 seconds
Started Feb 25 01:46:21 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 205104 kb
Host smart-730efd3a-9bb0-4788-855c-61df1c00b441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461718537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1461718537
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.13094100
Short name T922
Test name
Test status
Simulation time 36965123 ps
CPU time 0.84 seconds
Started Feb 25 01:46:18 PM PST 24
Finished Feb 25 01:46:19 PM PST 24
Peak memory 205184 kb
Host smart-040272b0-7658-4ae5-8f40-94bb6e22f34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.13094100
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1689366370
Short name T141
Test name
Test status
Simulation time 491587932 ps
CPU time 3.46 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:27 PM PST 24
Peak memory 213688 kb
Host smart-623b1e99-9513-4b47-be48-31e20f6da21c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689366370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1689366370
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.433773296
Short name T1022
Test name
Test status
Simulation time 826907026 ps
CPU time 6.38 seconds
Started Feb 25 01:46:19 PM PST 24
Finished Feb 25 01:46:26 PM PST 24
Peak memory 213756 kb
Host smart-92e90aa1-ed02-4bec-aec9-ffe1beb0cbcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433773296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.433773296
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3540960202
Short name T995
Test name
Test status
Simulation time 114900203 ps
CPU time 3.71 seconds
Started Feb 25 01:46:16 PM PST 24
Finished Feb 25 01:46:20 PM PST 24
Peak memory 213836 kb
Host smart-df78d22e-26fc-4f92-a352-a1e5e09a0b71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540960202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3540960202
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3306600983
Short name T924
Test name
Test status
Simulation time 477008686 ps
CPU time 3.21 seconds
Started Feb 25 01:46:23 PM PST 24
Finished Feb 25 01:46:26 PM PST 24
Peak memory 215616 kb
Host smart-c3e59efd-13f7-4d8d-bce2-1b7b4d6098a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306600983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3306600983
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1829938806
Short name T145
Test name
Test status
Simulation time 494420169 ps
CPU time 18.39 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:21 PM PST 24
Peak memory 205220 kb
Host smart-435ac5aa-6145-49e7-962b-c32cd919d8d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829938806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
829938806
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2009635853
Short name T975
Test name
Test status
Simulation time 941085250 ps
CPU time 15.41 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:46:08 PM PST 24
Peak memory 205232 kb
Host smart-6ffe94a1-16fc-498a-8445-f12f95b4c270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009635853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
009635853
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1506996220
Short name T1054
Test name
Test status
Simulation time 53854253 ps
CPU time 1.07 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 205292 kb
Host smart-8d068b68-4963-427f-8108-47d3882a7a3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506996220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
506996220
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3033748497
Short name T1049
Test name
Test status
Simulation time 106652662 ps
CPU time 1.03 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:50 PM PST 24
Peak memory 205328 kb
Host smart-c4d37b80-fba6-4e8f-abe3-a0a49c747313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033748497 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3033748497
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1758273470
Short name T1007
Test name
Test status
Simulation time 116404853 ps
CPU time 1.66 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 205220 kb
Host smart-731207fb-e505-4acb-afea-c398fd220812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758273470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1758273470
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1825182455
Short name T1058
Test name
Test status
Simulation time 22760288 ps
CPU time 0.69 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 205104 kb
Host smart-b473064b-3c2a-4212-85c7-7743c4d218e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825182455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1825182455
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2116600284
Short name T984
Test name
Test status
Simulation time 97067065 ps
CPU time 3.75 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 205384 kb
Host smart-0a1f385a-7331-4db7-8633-dff566776130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116600284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2116600284
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.729471446
Short name T122
Test name
Test status
Simulation time 334621455 ps
CPU time 6.75 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 213820 kb
Host smart-be9ceda6-d21d-40c9-b373-7d6db6761190
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729471446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.729471446
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3759012052
Short name T1030
Test name
Test status
Simulation time 277269883 ps
CPU time 4.34 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:03 PM PST 24
Peak memory 219560 kb
Host smart-ef994d95-16f7-4d12-b1a5-09566a184fad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759012052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3759012052
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2081318395
Short name T955
Test name
Test status
Simulation time 300041118 ps
CPU time 2.18 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 205344 kb
Host smart-5d97723d-f40a-4297-8338-6e36b079352d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081318395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2081318395
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1173564394
Short name T160
Test name
Test status
Simulation time 594545919 ps
CPU time 4.89 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:57 PM PST 24
Peak memory 209024 kb
Host smart-10ee683b-7668-47ef-b21d-3c82b21d5ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173564394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1173564394
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3989792265
Short name T923
Test name
Test status
Simulation time 13209347 ps
CPU time 0.91 seconds
Started Feb 25 01:46:28 PM PST 24
Finished Feb 25 01:46:29 PM PST 24
Peak memory 205056 kb
Host smart-9c929824-bc12-4c9c-a1de-8060f84e9937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989792265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3989792265
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4265356577
Short name T957
Test name
Test status
Simulation time 10330229 ps
CPU time 0.8 seconds
Started Feb 25 01:46:15 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 205100 kb
Host smart-674ca49b-9918-44e1-8c7e-c2937741e1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265356577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4265356577
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.882380891
Short name T994
Test name
Test status
Simulation time 39839138 ps
CPU time 0.79 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205188 kb
Host smart-b3dc3689-4009-4fd7-a566-e5b0f0a43a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882380891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.882380891
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2877901819
Short name T1085
Test name
Test status
Simulation time 86947649 ps
CPU time 0.86 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205128 kb
Host smart-883cad47-f408-467e-8791-2b973233493a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877901819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2877901819
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1823736283
Short name T937
Test name
Test status
Simulation time 18080820 ps
CPU time 0.74 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205096 kb
Host smart-b2aba97f-892f-4806-9cdf-1e2f4eb328c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823736283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1823736283
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3836132835
Short name T1061
Test name
Test status
Simulation time 27887907 ps
CPU time 0.69 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:38 PM PST 24
Peak memory 205132 kb
Host smart-60cb947b-c3fb-4e67-b2d2-15d080be70b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836132835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3836132835
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3078340251
Short name T997
Test name
Test status
Simulation time 70142807 ps
CPU time 0.79 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205172 kb
Host smart-8f070cdb-de20-4f7a-a90b-867c26a84f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078340251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3078340251
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.194654038
Short name T1042
Test name
Test status
Simulation time 39628903 ps
CPU time 0.69 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205088 kb
Host smart-ea490756-6c99-4c1a-9773-783b7ed908ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194654038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.194654038
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.404838827
Short name T1057
Test name
Test status
Simulation time 42436936 ps
CPU time 0.68 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205184 kb
Host smart-74c6fc21-2acb-4370-9880-835b27c59bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404838827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.404838827
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2740284342
Short name T1079
Test name
Test status
Simulation time 17271521 ps
CPU time 0.76 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 205100 kb
Host smart-f9927204-85b6-4428-a03d-a4fca59189c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740284342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2740284342
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4022613724
Short name T1082
Test name
Test status
Simulation time 183985504 ps
CPU time 4.54 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:57 PM PST 24
Peak memory 205312 kb
Host smart-e0693ab9-6394-4b8f-8923-97b051cb5ed4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022613724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
022613724
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.241032434
Short name T942
Test name
Test status
Simulation time 1166224795 ps
CPU time 17.24 seconds
Started Feb 25 01:46:04 PM PST 24
Finished Feb 25 01:46:22 PM PST 24
Peak memory 205004 kb
Host smart-31aba620-04cf-40e6-9166-6369c0e89d88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241032434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.241032434
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3660432082
Short name T1037
Test name
Test status
Simulation time 152425310 ps
CPU time 1.1 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 205216 kb
Host smart-c85044d0-e6d9-43f0-9daa-d70cee429699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660432082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
660432082
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4281439939
Short name T154
Test name
Test status
Simulation time 128262924 ps
CPU time 1.67 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 213424 kb
Host smart-061e6236-79ad-4872-893b-945b7d90aa49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281439939 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4281439939
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4011723130
Short name T971
Test name
Test status
Simulation time 146040370 ps
CPU time 1.12 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 205308 kb
Host smart-38ead95d-225d-4593-bdc4-c27470e7b2e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011723130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4011723130
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3105918389
Short name T930
Test name
Test status
Simulation time 11495861 ps
CPU time 0.86 seconds
Started Feb 25 01:46:04 PM PST 24
Finished Feb 25 01:46:05 PM PST 24
Peak memory 205176 kb
Host smart-52b7a199-4eb6-4399-b18f-cf702d1c4f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105918389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3105918389
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.438545612
Short name T1056
Test name
Test status
Simulation time 159336922 ps
CPU time 3.3 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:02 PM PST 24
Peak memory 205236 kb
Host smart-fa15c348-3765-4e70-933f-b40c26f57bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438545612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.438545612
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2960116828
Short name T964
Test name
Test status
Simulation time 151013118 ps
CPU time 2.55 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 213752 kb
Host smart-2d058089-3c49-4930-90b5-dcb9a0d537f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960116828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2960116828
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1541349807
Short name T1018
Test name
Test status
Simulation time 728788626 ps
CPU time 6.57 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 213872 kb
Host smart-73d67094-0371-4e5f-bcc5-da50451fa636
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541349807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1541349807
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3101053733
Short name T1027
Test name
Test status
Simulation time 174371357 ps
CPU time 5.7 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 213504 kb
Host smart-927dd0fe-c464-44f2-b693-f649809a2e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101053733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3101053733
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1010739158
Short name T1038
Test name
Test status
Simulation time 24879847 ps
CPU time 0.88 seconds
Started Feb 25 01:46:30 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 205180 kb
Host smart-af1a5aca-6471-4fda-b72c-d28e07de6078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010739158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1010739158
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.782876255
Short name T978
Test name
Test status
Simulation time 12873428 ps
CPU time 0.72 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205032 kb
Host smart-1f18ba98-630c-4bc2-9c1a-79df9e52b21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782876255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.782876255
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3416474437
Short name T1064
Test name
Test status
Simulation time 10219101 ps
CPU time 0.73 seconds
Started Feb 25 01:46:30 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 205096 kb
Host smart-d5f9beb4-9e95-4d5e-a2fa-5b4f935828b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416474437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3416474437
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.206418467
Short name T993
Test name
Test status
Simulation time 175545793 ps
CPU time 0.86 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 205120 kb
Host smart-8e574281-13cd-4af4-92d7-522843b1f17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206418467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.206418467
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1055317336
Short name T1035
Test name
Test status
Simulation time 34593022 ps
CPU time 0.72 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 205176 kb
Host smart-a1339121-d07b-48f3-abef-520abc084fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055317336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1055317336
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.621970919
Short name T1026
Test name
Test status
Simulation time 8229317 ps
CPU time 0.8 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:37 PM PST 24
Peak memory 205184 kb
Host smart-0bfee6c9-5063-40c2-939d-fabbcbdad827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621970919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.621970919
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2287132477
Short name T1047
Test name
Test status
Simulation time 17511899 ps
CPU time 0.8 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 205180 kb
Host smart-57452de9-1ca3-4b2f-aedb-8e25373bb0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287132477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2287132477
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1743704557
Short name T968
Test name
Test status
Simulation time 33154230 ps
CPU time 0.69 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205092 kb
Host smart-e219f5c6-b58b-4269-9d21-a2f56a4871d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743704557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1743704557
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.290859011
Short name T1013
Test name
Test status
Simulation time 29826609 ps
CPU time 0.78 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:37 PM PST 24
Peak memory 205124 kb
Host smart-3f75d40a-5f9e-4bc7-9e0f-7b20e8b8defc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290859011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.290859011
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1486877051
Short name T915
Test name
Test status
Simulation time 38128929 ps
CPU time 0.81 seconds
Started Feb 25 01:46:38 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 205092 kb
Host smart-ee6fe739-254b-4d02-a5d7-99f9887ef270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486877051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1486877051
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3705992041
Short name T1015
Test name
Test status
Simulation time 288271772 ps
CPU time 4.4 seconds
Started Feb 25 01:45:59 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 205364 kb
Host smart-86b1cbb0-a83f-4b75-b105-0e767ff791ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705992041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
705992041
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.470154014
Short name T1021
Test name
Test status
Simulation time 1809374062 ps
CPU time 8.67 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 205256 kb
Host smart-ace664e6-51d1-4bbb-bb66-48e2c43a72aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470154014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.470154014
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.657921117
Short name T933
Test name
Test status
Simulation time 42522502 ps
CPU time 1.16 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 205288 kb
Host smart-a3c254b3-1ee6-4fb0-8b41-3acb56868061
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657921117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.657921117
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1873495036
Short name T1065
Test name
Test status
Simulation time 114611636 ps
CPU time 1.62 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 213408 kb
Host smart-c62862fe-6599-4a6a-8608-6cadec3d97ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873495036 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1873495036
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3096049979
Short name T1051
Test name
Test status
Simulation time 18137145 ps
CPU time 0.92 seconds
Started Feb 25 01:45:55 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 205328 kb
Host smart-5003feea-aad6-43cf-83f4-a3c298fb844a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096049979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3096049979
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2585416133
Short name T950
Test name
Test status
Simulation time 49058970 ps
CPU time 0.78 seconds
Started Feb 25 01:46:00 PM PST 24
Finished Feb 25 01:46:01 PM PST 24
Peak memory 205160 kb
Host smart-6ef72619-0450-4931-97c4-e5c1635ac09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585416133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2585416133
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.661554463
Short name T1008
Test name
Test status
Simulation time 20014371 ps
CPU time 1.43 seconds
Started Feb 25 01:45:59 PM PST 24
Finished Feb 25 01:46:01 PM PST 24
Peak memory 205436 kb
Host smart-d2db5246-e04b-4d46-b484-df059729395a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661554463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.661554463
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1485616528
Short name T1050
Test name
Test status
Simulation time 372617751 ps
CPU time 3.29 seconds
Started Feb 25 01:45:56 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 213836 kb
Host smart-c53fb5fe-f3bc-493d-8236-5a1f1eb7ca89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485616528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1485616528
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1610111830
Short name T996
Test name
Test status
Simulation time 851359611 ps
CPU time 4.96 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213676 kb
Host smart-29f6fca8-5f00-4b2d-8304-afc540ba21bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610111830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1610111830
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.677938332
Short name T1040
Test name
Test status
Simulation time 51949643 ps
CPU time 3.34 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 213416 kb
Host smart-5f8ee799-aaa6-46f6-a0a8-20812c5d9c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677938332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.677938332
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2259991545
Short name T171
Test name
Test status
Simulation time 487357075 ps
CPU time 4.1 seconds
Started Feb 25 01:45:57 PM PST 24
Finished Feb 25 01:46:01 PM PST 24
Peak memory 208420 kb
Host smart-cd8f1e84-49aa-4709-baa2-4fe2cdc01e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259991545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2259991545
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1717509075
Short name T944
Test name
Test status
Simulation time 34450473 ps
CPU time 0.71 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 205176 kb
Host smart-18b97693-cdeb-4224-ba2a-319d84df9c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717509075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1717509075
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.882602418
Short name T951
Test name
Test status
Simulation time 12027254 ps
CPU time 0.73 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:37 PM PST 24
Peak memory 205188 kb
Host smart-641e4da0-f205-443d-b59d-445d89675eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882602418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.882602418
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1632637507
Short name T1076
Test name
Test status
Simulation time 11911006 ps
CPU time 0.79 seconds
Started Feb 25 01:46:30 PM PST 24
Finished Feb 25 01:46:31 PM PST 24
Peak memory 205192 kb
Host smart-5692452d-4306-4226-854f-9d1171e3835b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632637507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1632637507
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2548675312
Short name T986
Test name
Test status
Simulation time 12719758 ps
CPU time 0.72 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205068 kb
Host smart-545bae7b-009d-4b17-9465-4166687d9a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548675312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2548675312
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4239939446
Short name T958
Test name
Test status
Simulation time 37063563 ps
CPU time 0.74 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205144 kb
Host smart-2c72d7c5-1462-4356-9b6c-a08df7f21e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239939446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4239939446
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4061068048
Short name T946
Test name
Test status
Simulation time 12851620 ps
CPU time 0.67 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205188 kb
Host smart-0045a1fd-9dce-4a5e-aa5f-1773c6f314ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061068048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4061068048
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1185994054
Short name T945
Test name
Test status
Simulation time 11007622 ps
CPU time 0.8 seconds
Started Feb 25 01:46:29 PM PST 24
Finished Feb 25 01:46:30 PM PST 24
Peak memory 205064 kb
Host smart-d51646f4-7c71-4045-8abe-bbfc17e91600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185994054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1185994054
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.184584042
Short name T962
Test name
Test status
Simulation time 18550616 ps
CPU time 0.72 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 205092 kb
Host smart-82a073a6-bf32-4192-99e3-2ec042508748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184584042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.184584042
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.86842330
Short name T920
Test name
Test status
Simulation time 19462647 ps
CPU time 0.75 seconds
Started Feb 25 01:46:34 PM PST 24
Finished Feb 25 01:46:35 PM PST 24
Peak memory 205176 kb
Host smart-14ca2067-c061-44af-98c1-0da4c23bab54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86842330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.86842330
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2173851909
Short name T1060
Test name
Test status
Simulation time 18268590 ps
CPU time 0.72 seconds
Started Feb 25 01:46:39 PM PST 24
Finished Feb 25 01:46:40 PM PST 24
Peak memory 205072 kb
Host smart-f34a8758-93ba-4568-9168-b3bc1169aeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173851909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2173851909
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2507804668
Short name T970
Test name
Test status
Simulation time 60169753 ps
CPU time 2.03 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:09 PM PST 24
Peak memory 218504 kb
Host smart-da9efbbb-ae3e-4a36-9301-70b503cb7dd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507804668 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2507804668
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1294131441
Short name T981
Test name
Test status
Simulation time 24687240 ps
CPU time 1.25 seconds
Started Feb 25 01:45:56 PM PST 24
Finished Feb 25 01:45:58 PM PST 24
Peak memory 205240 kb
Host smart-2e1af394-6c5f-47b2-97fe-20dad1dee5f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294131441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1294131441
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.496088783
Short name T1075
Test name
Test status
Simulation time 11899687 ps
CPU time 0.77 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 205216 kb
Host smart-34d0a3c0-4e6d-46f6-ad5b-9cd949b90a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496088783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.496088783
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3863229766
Short name T998
Test name
Test status
Simulation time 66003932 ps
CPU time 2.52 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 205312 kb
Host smart-72be3fd3-dd9b-4aaf-a8f9-7ceb6b6191fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863229766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3863229766
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.628858018
Short name T1080
Test name
Test status
Simulation time 76751995 ps
CPU time 2.65 seconds
Started Feb 25 01:46:03 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 213876 kb
Host smart-3cbc0f9a-865d-421c-b780-e23ef26d5c03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628858018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.628858018
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2640351184
Short name T1077
Test name
Test status
Simulation time 357389630 ps
CPU time 4.18 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:03 PM PST 24
Peak memory 213896 kb
Host smart-44af291b-86fa-4acf-87af-62cd43369b52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640351184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2640351184
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.581849599
Short name T934
Test name
Test status
Simulation time 180326108 ps
CPU time 3.43 seconds
Started Feb 25 01:46:03 PM PST 24
Finished Feb 25 01:46:07 PM PST 24
Peak memory 213628 kb
Host smart-f191c620-f782-4bbd-8a1d-b854845e66be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581849599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.581849599
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1166639558
Short name T162
Test name
Test status
Simulation time 2024870354 ps
CPU time 10.52 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 208564 kb
Host smart-e93353d1-fd2b-4175-abb3-1a9e806a7de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166639558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1166639558
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.961978392
Short name T983
Test name
Test status
Simulation time 99838209 ps
CPU time 1.18 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 205448 kb
Host smart-36575fe1-0d5a-4800-92ea-be5b12060d5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961978392 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.961978392
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3087914564
Short name T980
Test name
Test status
Simulation time 15418012 ps
CPU time 1.11 seconds
Started Feb 25 01:46:03 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 205296 kb
Host smart-a0bb72d1-e052-4437-ad81-c45d70f359bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087914564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3087914564
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3564014809
Short name T918
Test name
Test status
Simulation time 8862536 ps
CPU time 0.79 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:03 PM PST 24
Peak memory 205072 kb
Host smart-3414a731-2b7b-4182-8ad0-0f1aaef98d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564014809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3564014809
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3443126849
Short name T1034
Test name
Test status
Simulation time 276603760 ps
CPU time 1.39 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 205384 kb
Host smart-8dd7fdff-9dbc-4691-a9d6-b1ae6d4f598a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443126849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3443126849
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1286722205
Short name T119
Test name
Test status
Simulation time 228723093 ps
CPU time 5.88 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:08 PM PST 24
Peak memory 213784 kb
Host smart-fcdbb596-048f-4ead-b09d-73920900b46c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286722205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1286722205
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.607996712
Short name T1045
Test name
Test status
Simulation time 984902968 ps
CPU time 6.27 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:09 PM PST 24
Peak memory 213788 kb
Host smart-e4429d4c-b21d-4560-b819-bf51d77092a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607996712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.607996712
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2577173998
Short name T921
Test name
Test status
Simulation time 388807473 ps
CPU time 3.11 seconds
Started Feb 25 01:46:01 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 213536 kb
Host smart-89827b26-c13c-4126-9119-9b409ea401d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577173998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2577173998
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1574338224
Short name T167
Test name
Test status
Simulation time 586002914 ps
CPU time 6.56 seconds
Started Feb 25 01:45:57 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 213584 kb
Host smart-c1bd95f2-213b-4cad-bf2f-c7e351a9e5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574338224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1574338224
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3963183867
Short name T928
Test name
Test status
Simulation time 48941262 ps
CPU time 1.46 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 213648 kb
Host smart-db2a021d-7660-4bd0-a032-aa746182056d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963183867 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3963183867
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.190044876
Short name T1024
Test name
Test status
Simulation time 23689212 ps
CPU time 1.18 seconds
Started Feb 25 01:46:01 PM PST 24
Finished Feb 25 01:46:03 PM PST 24
Peak memory 205244 kb
Host smart-39bea721-8ab4-473e-9819-89c91241b6ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190044876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.190044876
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2565851522
Short name T1059
Test name
Test status
Simulation time 52782608 ps
CPU time 0.84 seconds
Started Feb 25 01:46:01 PM PST 24
Finished Feb 25 01:46:02 PM PST 24
Peak memory 205092 kb
Host smart-b5eae532-3690-4336-accf-62d1ffebd44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565851522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2565851522
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3585751045
Short name T1028
Test name
Test status
Simulation time 94604096 ps
CPU time 3.73 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:02 PM PST 24
Peak memory 205384 kb
Host smart-b694c1a9-9e95-4af6-9b5a-1f2a9849ab95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585751045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3585751045
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2706768446
Short name T1003
Test name
Test status
Simulation time 145225389 ps
CPU time 4.57 seconds
Started Feb 25 01:45:57 PM PST 24
Finished Feb 25 01:46:02 PM PST 24
Peak memory 221944 kb
Host smart-6839cc76-b757-44e9-b9da-d9c09fe5f558
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706768446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2706768446
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.279775578
Short name T121
Test name
Test status
Simulation time 454908701 ps
CPU time 9.76 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213704 kb
Host smart-f34eb0d3-7390-4bf1-94b2-8ceafd2b1445
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279775578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.279775578
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.547312018
Short name T916
Test name
Test status
Simulation time 36207749 ps
CPU time 2.4 seconds
Started Feb 25 01:46:00 PM PST 24
Finished Feb 25 01:46:02 PM PST 24
Peak memory 214588 kb
Host smart-e5c9cdce-5226-4d54-8f49-deb80dfad1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547312018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.547312018
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1086776218
Short name T148
Test name
Test status
Simulation time 363287353 ps
CPU time 1.78 seconds
Started Feb 25 01:46:08 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 213572 kb
Host smart-ad45b479-ec47-4630-8cc1-a39e48bfde7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086776218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1086776218
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1907490578
Short name T147
Test name
Test status
Simulation time 21942038 ps
CPU time 1.31 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205308 kb
Host smart-6a8b2a10-c6da-47b7-8f75-473cc91a9600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907490578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1907490578
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3667536882
Short name T949
Test name
Test status
Simulation time 25551873 ps
CPU time 0.77 seconds
Started Feb 25 01:46:08 PM PST 24
Finished Feb 25 01:46:09 PM PST 24
Peak memory 205164 kb
Host smart-48a24497-6105-4f95-9cca-305ebf4ea97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667536882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3667536882
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3123203516
Short name T1072
Test name
Test status
Simulation time 103397804 ps
CPU time 1.6 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205368 kb
Host smart-ef3ad72e-42a4-49e9-9fe8-aff12b87239d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123203516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3123203516
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.875554824
Short name T936
Test name
Test status
Simulation time 279914831 ps
CPU time 3.17 seconds
Started Feb 25 01:46:07 PM PST 24
Finished Feb 25 01:46:10 PM PST 24
Peak memory 218136 kb
Host smart-739141ee-ae63-4fd0-bcc8-e584cdc2f104
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875554824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.875554824
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4245064416
Short name T118
Test name
Test status
Simulation time 672885462 ps
CPU time 6.87 seconds
Started Feb 25 01:46:00 PM PST 24
Finished Feb 25 01:46:07 PM PST 24
Peak memory 213824 kb
Host smart-050b5d4c-dced-482c-8e55-59d278b01ae1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245064416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4245064416
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1530084325
Short name T991
Test name
Test status
Simulation time 56875786 ps
CPU time 2.24 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:00 PM PST 24
Peak memory 213572 kb
Host smart-ee862d67-2bc1-41d1-a0e2-986af77eac99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530084325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1530084325
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1057214707
Short name T927
Test name
Test status
Simulation time 169330092 ps
CPU time 6.22 seconds
Started Feb 25 01:46:11 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 208624 kb
Host smart-ce03b12f-600c-4ca7-bdea-5dba72fee879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057214707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1057214707
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.575520335
Short name T1039
Test name
Test status
Simulation time 51450942 ps
CPU time 1.62 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213552 kb
Host smart-3a180250-d586-48c9-a4c3-5f71468d9bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575520335 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.575520335
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3634391107
Short name T1055
Test name
Test status
Simulation time 25166567 ps
CPU time 1.54 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:11 PM PST 24
Peak memory 205328 kb
Host smart-f86dabaa-946a-4b6b-be0d-7d660741c259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634391107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3634391107
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1906863849
Short name T1074
Test name
Test status
Simulation time 34189298 ps
CPU time 0.71 seconds
Started Feb 25 01:46:11 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 205116 kb
Host smart-03fb392d-6477-41e2-aa17-a49f9d46561e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906863849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1906863849
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4161049854
Short name T987
Test name
Test status
Simulation time 289311193 ps
CPU time 4.39 seconds
Started Feb 25 01:46:14 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 205328 kb
Host smart-d7524802-80ae-43c8-9010-da96d367a97f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161049854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4161049854
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3113030201
Short name T116
Test name
Test status
Simulation time 49091677 ps
CPU time 1.94 seconds
Started Feb 25 01:46:10 PM PST 24
Finished Feb 25 01:46:12 PM PST 24
Peak memory 213852 kb
Host smart-65824168-c4f5-48fe-b132-f68b7f0178fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113030201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3113030201
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1428988811
Short name T1087
Test name
Test status
Simulation time 164263129 ps
CPU time 3.59 seconds
Started Feb 25 01:46:13 PM PST 24
Finished Feb 25 01:46:17 PM PST 24
Peak memory 213576 kb
Host smart-a35fa680-00d4-46dc-8415-fde222fe27a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428988811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1428988811
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2447335798
Short name T990
Test name
Test status
Simulation time 143884882 ps
CPU time 3.47 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:13 PM PST 24
Peak memory 213580 kb
Host smart-71bc077d-4bc7-43c5-a362-1ba7999be4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447335798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2447335798
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.941459054
Short name T1006
Test name
Test status
Simulation time 263645037 ps
CPU time 5.67 seconds
Started Feb 25 01:46:09 PM PST 24
Finished Feb 25 01:46:16 PM PST 24
Peak memory 209004 kb
Host smart-ce49b87a-ce11-42c7-a354-93e3e8ca7b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941459054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
941459054
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1951122099
Short name T595
Test name
Test status
Simulation time 211842311 ps
CPU time 3.39 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:13 PM PST 24
Peak memory 209340 kb
Host smart-76d17519-9a23-411f-9376-a9b29fd289b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951122099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1951122099
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2713074025
Short name T44
Test name
Test status
Simulation time 108727561 ps
CPU time 1.46 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 207192 kb
Host smart-1158b26d-b43b-4a84-b3a1-25831b30dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713074025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2713074025
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1929152125
Short name T624
Test name
Test status
Simulation time 180036862 ps
CPU time 5.46 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:15 PM PST 24
Peak memory 214304 kb
Host smart-3df73738-a979-4f72-852d-f74fe1353610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929152125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1929152125
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.366797691
Short name T262
Test name
Test status
Simulation time 679668189 ps
CPU time 7.51 seconds
Started Feb 25 02:40:05 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 222292 kb
Host smart-59d8d3f2-70ab-4623-b247-c7d5fffd6613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366797691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.366797691
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1907641284
Short name T57
Test name
Test status
Simulation time 93564766 ps
CPU time 4.78 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 210116 kb
Host smart-698daf10-bb1d-4a16-b2b8-03542a7c684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907641284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1907641284
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1902870204
Short name T585
Test name
Test status
Simulation time 212138013 ps
CPU time 5.28 seconds
Started Feb 25 02:40:08 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 208564 kb
Host smart-865c825b-5893-4bce-9b29-2887f4a227b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902870204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1902870204
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2584351107
Short name T11
Test name
Test status
Simulation time 1080115551 ps
CPU time 28.97 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:37 PM PST 24
Peak memory 232656 kb
Host smart-2391e1f5-db1e-4183-8392-d58c290687b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584351107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2584351107
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1182323939
Short name T591
Test name
Test status
Simulation time 568963754 ps
CPU time 6.48 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 208032 kb
Host smart-e90a9f22-dac0-473a-bd6a-ebadc2af1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182323939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1182323939
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4054140795
Short name T718
Test name
Test status
Simulation time 1582637661 ps
CPU time 10.68 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:20 PM PST 24
Peak memory 207612 kb
Host smart-0e1234df-a4cf-432b-83f2-6af37ad345bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054140795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4054140795
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2352819215
Short name T887
Test name
Test status
Simulation time 173176402 ps
CPU time 6.99 seconds
Started Feb 25 02:39:59 PM PST 24
Finished Feb 25 02:40:07 PM PST 24
Peak memory 206836 kb
Host smart-4fbd9167-0af2-4c2d-9d95-0d22bbc13fd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352819215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2352819215
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.110872979
Short name T616
Test name
Test status
Simulation time 1048086440 ps
CPU time 23.55 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 208704 kb
Host smart-bb75cef1-373d-4da8-86d2-7351966a64e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110872979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.110872979
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1927484840
Short name T283
Test name
Test status
Simulation time 175220354 ps
CPU time 2.57 seconds
Started Feb 25 02:40:05 PM PST 24
Finished Feb 25 02:40:08 PM PST 24
Peak memory 209780 kb
Host smart-297d799f-0f99-4920-8a83-df5789b3b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927484840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1927484840
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2536684636
Short name T439
Test name
Test status
Simulation time 154717658 ps
CPU time 4.46 seconds
Started Feb 25 02:39:59 PM PST 24
Finished Feb 25 02:40:04 PM PST 24
Peak memory 206884 kb
Host smart-3137f64b-d74d-46cc-b59c-fdb35a4ddaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536684636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2536684636
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.580563731
Short name T496
Test name
Test status
Simulation time 884895449 ps
CPU time 11.41 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:19 PM PST 24
Peak memory 220672 kb
Host smart-8b6a7ecd-ea8e-482e-ac33-66ff656c9e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580563731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.580563731
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3940962651
Short name T859
Test name
Test status
Simulation time 62565458 ps
CPU time 4.06 seconds
Started Feb 25 02:40:08 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 207116 kb
Host smart-bfa33bfe-75c9-49d7-a3fa-d96d6dc59476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940962651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3940962651
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.735375437
Short name T753
Test name
Test status
Simulation time 86224089 ps
CPU time 1.49 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 208268 kb
Host smart-f1ece673-b999-4be0-88d1-0b36668ab664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735375437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.735375437
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2198375400
Short name T408
Test name
Test status
Simulation time 9153259 ps
CPU time 0.71 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:09 PM PST 24
Peak memory 205884 kb
Host smart-ef0bd289-fc0a-49ec-b975-467d71f9e940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198375400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2198375400
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2307386050
Short name T696
Test name
Test status
Simulation time 185391575 ps
CPU time 4.71 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:15 PM PST 24
Peak memory 209584 kb
Host smart-7c53eadd-dc7e-4ce7-b380-1b4e2b5fd3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307386050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2307386050
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.4210859168
Short name T836
Test name
Test status
Simulation time 4197529334 ps
CPU time 36.89 seconds
Started Feb 25 02:40:04 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 209840 kb
Host smart-60bfd088-e739-4f38-8a17-a7bed855f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210859168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4210859168
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4179233547
Short name T312
Test name
Test status
Simulation time 72313054 ps
CPU time 2.88 seconds
Started Feb 25 02:40:06 PM PST 24
Finished Feb 25 02:40:09 PM PST 24
Peak memory 220280 kb
Host smart-deed9ca5-d444-4182-95dd-cb30d3a9e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179233547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4179233547
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3609391344
Short name T334
Test name
Test status
Simulation time 98679192 ps
CPU time 3.78 seconds
Started Feb 25 02:40:15 PM PST 24
Finished Feb 25 02:40:19 PM PST 24
Peak memory 211312 kb
Host smart-dab6cd36-5b21-4dc6-bce8-1f16b8da91a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609391344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3609391344
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.882721140
Short name T904
Test name
Test status
Simulation time 120242591 ps
CPU time 3 seconds
Started Feb 25 02:40:04 PM PST 24
Finished Feb 25 02:40:08 PM PST 24
Peak memory 209676 kb
Host smart-6f923207-4f60-44df-870a-967be11d052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882721140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.882721140
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3262117766
Short name T712
Test name
Test status
Simulation time 195001787 ps
CPU time 5.44 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:15 PM PST 24
Peak memory 207344 kb
Host smart-a0e982a0-272b-4ffc-9756-aa5af719c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262117766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3262117766
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4274731297
Short name T10
Test name
Test status
Simulation time 6665296448 ps
CPU time 117.61 seconds
Started Feb 25 02:40:06 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 251976 kb
Host smart-20bc50e0-cef7-4af5-9124-2fa6dac5144b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274731297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4274731297
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1325945310
Short name T240
Test name
Test status
Simulation time 273228627 ps
CPU time 3.46 seconds
Started Feb 25 02:40:15 PM PST 24
Finished Feb 25 02:40:18 PM PST 24
Peak memory 208056 kb
Host smart-ab052ac6-702b-4cf1-a7df-3b80e5e82e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325945310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1325945310
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2164528216
Short name T569
Test name
Test status
Simulation time 571446007 ps
CPU time 4.86 seconds
Started Feb 25 02:40:04 PM PST 24
Finished Feb 25 02:40:10 PM PST 24
Peak memory 208268 kb
Host smart-28fec398-877c-42b4-a127-ff822d949475
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164528216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2164528216
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2775936027
Short name T586
Test name
Test status
Simulation time 15136491607 ps
CPU time 24.08 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:32 PM PST 24
Peak memory 208052 kb
Host smart-061792d4-b3d4-42cd-8739-32056476e1a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775936027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2775936027
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1187831766
Short name T782
Test name
Test status
Simulation time 5001228465 ps
CPU time 25.43 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:36 PM PST 24
Peak memory 207660 kb
Host smart-1f85ff6b-7653-492e-b50c-9b22dcc5eeb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187831766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1187831766
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.999826808
Short name T431
Test name
Test status
Simulation time 56128400 ps
CPU time 1.96 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:10 PM PST 24
Peak memory 206952 kb
Host smart-6cb60ec5-c36c-4900-84fc-cbe33d313317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999826808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.999826808
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2525393981
Short name T414
Test name
Test status
Simulation time 165767118 ps
CPU time 2.87 seconds
Started Feb 25 02:40:08 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 207124 kb
Host smart-861847ce-b472-4df5-a30f-a3b6f6b1d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525393981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2525393981
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.689521275
Short name T182
Test name
Test status
Simulation time 110441421 ps
CPU time 1.18 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 205664 kb
Host smart-fceefe9f-47fa-4595-8f19-a88817642bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689521275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.689521275
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1071509322
Short name T70
Test name
Test status
Simulation time 487970665 ps
CPU time 20.79 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 222524 kb
Host smart-81ea0b0a-88d3-4501-95f4-3874b074f3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071509322 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1071509322
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3489601815
Short name T448
Test name
Test status
Simulation time 1127704983 ps
CPU time 13.62 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:21 PM PST 24
Peak memory 214196 kb
Host smart-fd35b5d2-d5ee-45e1-ba41-ac6c72a5d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489601815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3489601815
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2805018428
Short name T185
Test name
Test status
Simulation time 54342837 ps
CPU time 2.42 seconds
Started Feb 25 02:40:05 PM PST 24
Finished Feb 25 02:40:08 PM PST 24
Peak memory 209472 kb
Host smart-8ba40317-3d7c-4992-b4e6-c485ebec23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805018428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2805018428
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4227039587
Short name T670
Test name
Test status
Simulation time 10284351 ps
CPU time 0.72 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 205876 kb
Host smart-ff843a21-6b24-498d-a12b-f3a5ae1109df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227039587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4227039587
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.958352695
Short name T882
Test name
Test status
Simulation time 183130755 ps
CPU time 6.08 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 209552 kb
Host smart-8e27d669-1643-465a-93ad-137eb5382dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958352695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.958352695
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.81023824
Short name T256
Test name
Test status
Simulation time 50037764 ps
CPU time 3.21 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 209824 kb
Host smart-c486d30b-faa8-47c2-b5d0-78ecb4c44905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81023824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.81023824
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1709791994
Short name T745
Test name
Test status
Simulation time 121157142 ps
CPU time 5.41 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:55 PM PST 24
Peak memory 214204 kb
Host smart-25518e30-01a3-4712-a308-c39f81d6ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709791994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1709791994
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3549910201
Short name T604
Test name
Test status
Simulation time 324890774 ps
CPU time 3.13 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 214008 kb
Host smart-db0c3f31-9532-42e6-8839-268635cc8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549910201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3549910201
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3485337251
Short name T832
Test name
Test status
Simulation time 209126548 ps
CPU time 7.8 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:40:57 PM PST 24
Peak memory 209656 kb
Host smart-023a1561-0027-423a-9b5a-11e278d2fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485337251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3485337251
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1918806869
Short name T545
Test name
Test status
Simulation time 1449503114 ps
CPU time 28.36 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 208128 kb
Host smart-cde64de9-4d47-4da3-a8a3-1ec01013530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918806869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1918806869
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3003343882
Short name T427
Test name
Test status
Simulation time 67480996 ps
CPU time 2.48 seconds
Started Feb 25 02:40:40 PM PST 24
Finished Feb 25 02:40:42 PM PST 24
Peak memory 208304 kb
Host smart-3b8b0f79-6349-451c-8155-b7e244a3bc3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003343882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3003343882
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1444066828
Short name T680
Test name
Test status
Simulation time 33964366 ps
CPU time 2.37 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:40 PM PST 24
Peak memory 206564 kb
Host smart-3ba0194d-ab4a-4dec-8f54-f9a14c4e16d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444066828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1444066828
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2765891977
Short name T876
Test name
Test status
Simulation time 62995732 ps
CPU time 1.64 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 207424 kb
Host smart-ade672ab-9804-43b0-b16a-c4007d4a8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765891977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2765891977
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.926122139
Short name T812
Test name
Test status
Simulation time 121544316 ps
CPU time 4.22 seconds
Started Feb 25 02:40:38 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 208152 kb
Host smart-cbeaeb0c-0f86-4d7e-b0f6-05976a503708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926122139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.926122139
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.900006556
Short name T140
Test name
Test status
Simulation time 922737135 ps
CPU time 16.22 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 215920 kb
Host smart-9bf39739-18cf-4d8a-9f06-12a7d8613c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900006556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.900006556
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2367329059
Short name T132
Test name
Test status
Simulation time 440768271 ps
CPU time 27.85 seconds
Started Feb 25 02:40:40 PM PST 24
Finished Feb 25 02:41:08 PM PST 24
Peak memory 222456 kb
Host smart-1118e364-d45e-45b0-80e8-f187e16986f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367329059 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2367329059
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1080354426
Short name T912
Test name
Test status
Simulation time 417694904 ps
CPU time 3.88 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 208660 kb
Host smart-fcbffe6b-29b5-4073-93fa-5cecfba52eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080354426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1080354426
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.476399754
Short name T744
Test name
Test status
Simulation time 42237020 ps
CPU time 1.88 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 209244 kb
Host smart-b5f09349-9dd9-426f-86e7-cf3f7ff74215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476399754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.476399754
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1360380853
Short name T867
Test name
Test status
Simulation time 109930279 ps
CPU time 0.79 seconds
Started Feb 25 02:40:50 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 205884 kb
Host smart-bbe720dc-36a7-4f18-beb9-f82c76ad50b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360380853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1360380853
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1810228575
Short name T229
Test name
Test status
Simulation time 37907282 ps
CPU time 3 seconds
Started Feb 25 02:40:50 PM PST 24
Finished Feb 25 02:40:54 PM PST 24
Peak memory 214212 kb
Host smart-e99311f4-bc6b-4bab-9daa-d6d05936bfb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810228575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1810228575
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4145767422
Short name T241
Test name
Test status
Simulation time 237582353 ps
CPU time 3.56 seconds
Started Feb 25 02:40:38 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 214300 kb
Host smart-a50d93f1-9981-4575-868f-c2f6b50f76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145767422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4145767422
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3964961585
Short name T577
Test name
Test status
Simulation time 65221413 ps
CPU time 2.74 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:40 PM PST 24
Peak memory 207156 kb
Host smart-46536296-7509-4383-90ab-0d8894d83dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964961585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3964961585
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.619794117
Short name T509
Test name
Test status
Simulation time 72252051 ps
CPU time 3.35 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 214196 kb
Host smart-99f62ffe-fb60-4604-a94e-96f139fd81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619794117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.619794117
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.149002795
Short name T717
Test name
Test status
Simulation time 2204392664 ps
CPU time 25.19 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 221376 kb
Host smart-dcacf661-400b-46cf-a817-e3804c117221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149002795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.149002795
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3361912823
Short name T4
Test name
Test status
Simulation time 221581177 ps
CPU time 3.56 seconds
Started Feb 25 02:40:39 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 215268 kb
Host smart-07f06e86-74a8-4858-84d8-679367d8acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361912823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3361912823
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2408310644
Short name T82
Test name
Test status
Simulation time 125643276 ps
CPU time 2.35 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:52 PM PST 24
Peak memory 207680 kb
Host smart-70d859db-7ecf-41bf-ab3a-12f7a71b43a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408310644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2408310644
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.401148410
Short name T824
Test name
Test status
Simulation time 276706932 ps
CPU time 3.54 seconds
Started Feb 25 02:40:50 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 208332 kb
Host smart-d87cae4a-3085-43a3-9ace-0e7e4d300ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401148410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.401148410
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3646324852
Short name T440
Test name
Test status
Simulation time 23582987 ps
CPU time 1.84 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 208188 kb
Host smart-e451a742-989a-4c05-821e-3be19c6a3dd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646324852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3646324852
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2625128704
Short name T549
Test name
Test status
Simulation time 4654365891 ps
CPU time 72.86 seconds
Started Feb 25 02:40:36 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 208672 kb
Host smart-1d33e10d-16d1-4b34-9a5c-e000bea02456
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625128704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2625128704
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1130881878
Short name T135
Test name
Test status
Simulation time 745567855 ps
CPU time 19.26 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 207720 kb
Host smart-a2d06e40-46fa-4daa-9a55-ffc1ecaf0d35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130881878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1130881878
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3878484589
Short name T239
Test name
Test status
Simulation time 129694843 ps
CPU time 4.41 seconds
Started Feb 25 02:40:43 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 218180 kb
Host smart-e9350aa8-2d90-44d0-9759-143549625f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878484589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3878484589
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4147909165
Short name T548
Test name
Test status
Simulation time 2503286430 ps
CPU time 14.76 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 207952 kb
Host smart-157e2e7d-c309-4285-ac9a-07ed3ba6dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147909165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4147909165
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1799610165
Short name T791
Test name
Test status
Simulation time 516426757 ps
CPU time 3.89 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:49 PM PST 24
Peak memory 207372 kb
Host smart-b91cdcb9-0af8-466a-8aeb-38ce1408d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799610165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1799610165
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1737502818
Short name T628
Test name
Test status
Simulation time 12458437 ps
CPU time 0.94 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 205884 kb
Host smart-8b50cbc3-f816-4e05-b7f9-59626bcd9d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737502818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1737502818
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.831275633
Short name T139
Test name
Test status
Simulation time 689849107 ps
CPU time 5.74 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 214796 kb
Host smart-5f5cf770-1124-41b8-b0d7-de6b8ff665e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831275633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.831275633
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.743198898
Short name T890
Test name
Test status
Simulation time 66407905 ps
CPU time 3.5 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 209276 kb
Host smart-8384c519-9a3c-4be6-b573-ba7dae8fb172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743198898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.743198898
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.533410466
Short name T757
Test name
Test status
Simulation time 250866725 ps
CPU time 3.66 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:49 PM PST 24
Peak memory 209160 kb
Host smart-9d912d42-408a-4c26-be6d-10f4b087fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533410466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.533410466
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2919774396
Short name T852
Test name
Test status
Simulation time 26633737 ps
CPU time 2.2 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 208280 kb
Host smart-5415f522-0a93-41f2-a501-1d8ad72bba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919774396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2919774396
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.285818949
Short name T865
Test name
Test status
Simulation time 1334515404 ps
CPU time 39.93 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 222272 kb
Host smart-6d9c9c56-e575-4c5d-b6f4-3af00707c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285818949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.285818949
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3362244411
Short name T207
Test name
Test status
Simulation time 37054352 ps
CPU time 2.55 seconds
Started Feb 25 02:40:43 PM PST 24
Finished Feb 25 02:40:46 PM PST 24
Peak memory 219728 kb
Host smart-f9f1da23-9750-4406-a24a-67665171085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362244411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3362244411
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3902525357
Short name T341
Test name
Test status
Simulation time 194384427 ps
CPU time 6.87 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 208856 kb
Host smart-b4af6fd6-48c3-4003-a557-34530f5a04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902525357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3902525357
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3255748805
Short name T494
Test name
Test status
Simulation time 732888087 ps
CPU time 3.24 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 206208 kb
Host smart-09917b2f-cab4-4619-9713-f547ae336f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255748805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3255748805
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4246286943
Short name T460
Test name
Test status
Simulation time 66392644 ps
CPU time 3.28 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 208252 kb
Host smart-9c5b3039-db5c-4ca0-9082-8a94b7b43e6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246286943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4246286943
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1816722297
Short name T279
Test name
Test status
Simulation time 133698117 ps
CPU time 4.05 seconds
Started Feb 25 02:40:40 PM PST 24
Finished Feb 25 02:40:44 PM PST 24
Peak memory 206408 kb
Host smart-6749b8a2-6b12-4903-819d-91ee931b5a5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816722297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1816722297
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.449381365
Short name T556
Test name
Test status
Simulation time 145113314 ps
CPU time 2.76 seconds
Started Feb 25 02:40:38 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 208608 kb
Host smart-146a43b6-86a4-4e17-bbd4-0740ec1d6c83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449381365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.449381365
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2589262182
Short name T348
Test name
Test status
Simulation time 91822512 ps
CPU time 2.81 seconds
Started Feb 25 02:40:43 PM PST 24
Finished Feb 25 02:40:46 PM PST 24
Peak memory 208032 kb
Host smart-6a867e0a-1a38-4c4b-b4fd-03f5c3067c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589262182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2589262182
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1365547454
Short name T860
Test name
Test status
Simulation time 247266435 ps
CPU time 3.35 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 208496 kb
Host smart-643fe020-1a90-4c41-8ff5-bd95d200395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365547454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1365547454
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3643205676
Short name T183
Test name
Test status
Simulation time 240369480 ps
CPU time 9.84 seconds
Started Feb 25 02:40:40 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 214912 kb
Host smart-70eaf7d9-eaf3-443d-b7c2-990459b20246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643205676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3643205676
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1098695418
Short name T794
Test name
Test status
Simulation time 111843269 ps
CPU time 2.71 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 207152 kb
Host smart-38d075ee-485c-4def-97d5-c72268a70e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098695418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1098695418
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4143199086
Short name T467
Test name
Test status
Simulation time 8741730 ps
CPU time 0.74 seconds
Started Feb 25 02:40:50 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 205872 kb
Host smart-65a03bf6-7ad6-4d2d-ab69-1df7e3b10fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143199086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4143199086
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2815850939
Short name T361
Test name
Test status
Simulation time 311166993 ps
CPU time 9.21 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:40:59 PM PST 24
Peak memory 214112 kb
Host smart-68f57ee8-36a7-4bba-977f-ff3d0e0c215e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815850939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2815850939
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2791880543
Short name T39
Test name
Test status
Simulation time 1991926537 ps
CPU time 6.02 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 214212 kb
Host smart-d33a88d3-8c46-410b-a874-c0d1c500dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791880543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2791880543
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1976193398
Short name T570
Test name
Test status
Simulation time 91056764 ps
CPU time 3.8 seconds
Started Feb 25 02:40:49 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 214160 kb
Host smart-daeb293c-f3db-477e-98ac-88f01dd5795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976193398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1976193398
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1630294211
Short name T600
Test name
Test status
Simulation time 5709063106 ps
CPU time 34.34 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 222356 kb
Host smart-017f5890-4530-4445-b040-47f48181a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630294211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1630294211
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2186134831
Short name T188
Test name
Test status
Simulation time 408331229 ps
CPU time 6.23 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 214184 kb
Host smart-d1ece886-23c9-4592-a783-378da14b76ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186134831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2186134831
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2004834301
Short name T726
Test name
Test status
Simulation time 125498862 ps
CPU time 3.08 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 208216 kb
Host smart-d075fd80-c026-47da-aa1b-36e79628141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004834301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2004834301
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3072051331
Short name T514
Test name
Test status
Simulation time 362780002 ps
CPU time 4.8 seconds
Started Feb 25 02:40:42 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 208432 kb
Host smart-1304c8d1-f737-45b9-8709-4e36558ee253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072051331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3072051331
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1742260136
Short name T528
Test name
Test status
Simulation time 405800489 ps
CPU time 6.39 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 206444 kb
Host smart-0d42226a-b9ae-4e27-ac3e-c5251788a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742260136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1742260136
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3574500847
Short name T202
Test name
Test status
Simulation time 249610931 ps
CPU time 6.02 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 206656 kb
Host smart-43792afc-4da5-4ce4-a605-70d2c0774d3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574500847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3574500847
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.282465262
Short name T769
Test name
Test status
Simulation time 659667777 ps
CPU time 6.27 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 208356 kb
Host smart-d47813d9-066a-4645-988b-7b4069fe64f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282465262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.282465262
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3220243350
Short name T811
Test name
Test status
Simulation time 40090243 ps
CPU time 2.44 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 206576 kb
Host smart-56cc921c-91cf-4126-ad78-f2a8202d7321
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220243350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3220243350
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.927728907
Short name T868
Test name
Test status
Simulation time 179607159 ps
CPU time 4.38 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:40:54 PM PST 24
Peak memory 208340 kb
Host smart-20f04d5e-e3fc-448c-a4b3-ffa7d5ed02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927728907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.927728907
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.467830390
Short name T551
Test name
Test status
Simulation time 455810054 ps
CPU time 4.7 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:42 PM PST 24
Peak memory 206552 kb
Host smart-0db0e292-d87b-4d8f-9f4b-116d07e5ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467830390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.467830390
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.51584530
Short name T612
Test name
Test status
Simulation time 821657684 ps
CPU time 15.79 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 217088 kb
Host smart-fd6831d2-30f6-4015-aef5-72a81f2ba773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51584530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.51584530
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3630387609
Short name T71
Test name
Test status
Simulation time 277615613 ps
CPU time 11.57 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:41:01 PM PST 24
Peak memory 222516 kb
Host smart-892a8f15-fc9c-410f-b9fe-43eee31ff882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630387609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3630387609
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2428158727
Short name T843
Test name
Test status
Simulation time 310257308 ps
CPU time 7.52 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 208892 kb
Host smart-e1730d6c-55ff-4d67-bdbc-e6ca9972ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428158727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2428158727
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1971054385
Short name T169
Test name
Test status
Simulation time 86750751 ps
CPU time 3.55 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 209536 kb
Host smart-4d8cb918-13e1-4f52-bce5-9aba92163cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971054385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1971054385
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1164978174
Short name T634
Test name
Test status
Simulation time 14214558 ps
CPU time 0.71 seconds
Started Feb 25 02:40:54 PM PST 24
Finished Feb 25 02:40:55 PM PST 24
Peak memory 205736 kb
Host smart-b8a4390c-89eb-4140-9eb5-f0b035fab33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164978174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1164978174
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1045633464
Short name T774
Test name
Test status
Simulation time 179466552 ps
CPU time 5.76 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 209408 kb
Host smart-a7e2f4a0-0e6b-4172-add3-4248609fa59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045633464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1045633464
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3679005664
Short name T568
Test name
Test status
Simulation time 101629197 ps
CPU time 2.47 seconds
Started Feb 25 02:40:43 PM PST 24
Finished Feb 25 02:40:46 PM PST 24
Peak memory 209044 kb
Host smart-d5b902fa-0ff5-4bb0-80f0-7ac3507c1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679005664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3679005664
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1484961552
Short name T857
Test name
Test status
Simulation time 2221339351 ps
CPU time 47.91 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 209204 kb
Host smart-c62f9124-6925-40d9-a58c-5e1b84f223a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484961552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1484961552
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1194377158
Short name T651
Test name
Test status
Simulation time 50387633 ps
CPU time 2.55 seconds
Started Feb 25 02:40:51 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 209200 kb
Host smart-a77924f7-ba82-496b-a9ff-dcf101ae77ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194377158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1194377158
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.250271787
Short name T1
Test name
Test status
Simulation time 63724476 ps
CPU time 4.07 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:40:54 PM PST 24
Peak memory 210320 kb
Host smart-065380e8-57f6-44ca-a263-27b4b46a2f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250271787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.250271787
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2341319631
Short name T614
Test name
Test status
Simulation time 389404497 ps
CPU time 5.77 seconds
Started Feb 25 02:40:48 PM PST 24
Finished Feb 25 02:40:55 PM PST 24
Peak memory 207692 kb
Host smart-774e90d0-b041-471a-bd18-901b7da419f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341319631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2341319631
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1188582983
Short name T390
Test name
Test status
Simulation time 52290410 ps
CPU time 2.99 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 206512 kb
Host smart-14273d1b-be95-4dc7-bbda-630367027462
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188582983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1188582983
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3035099573
Short name T290
Test name
Test status
Simulation time 1579795003 ps
CPU time 40.14 seconds
Started Feb 25 02:40:47 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 207824 kb
Host smart-71739e98-c2ff-4190-86e2-90c0856e7b76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035099573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3035099573
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.274513128
Short name T432
Test name
Test status
Simulation time 117024756 ps
CPU time 3.22 seconds
Started Feb 25 02:40:57 PM PST 24
Finished Feb 25 02:41:01 PM PST 24
Peak memory 208376 kb
Host smart-dca894a4-7393-4c89-92fd-bb972e082df1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274513128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.274513128
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1610656467
Short name T486
Test name
Test status
Simulation time 549520804 ps
CPU time 4.04 seconds
Started Feb 25 02:40:46 PM PST 24
Finished Feb 25 02:40:54 PM PST 24
Peak memory 214200 kb
Host smart-7700d365-548d-4cab-880d-e73a3e0c44f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610656467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1610656467
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3030370221
Short name T695
Test name
Test status
Simulation time 46452520 ps
CPU time 2.42 seconds
Started Feb 25 02:40:44 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 207676 kb
Host smart-38fb3fc6-3686-4e69-8316-0688623574a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030370221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3030370221
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.4093321520
Short name T195
Test name
Test status
Simulation time 681834033 ps
CPU time 6.03 seconds
Started Feb 25 02:40:45 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 207904 kb
Host smart-08b68e6c-aaf6-4e01-9ab6-5e7442f8a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093321520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.4093321520
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3805865904
Short name T654
Test name
Test status
Simulation time 132150538 ps
CPU time 1.42 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 209444 kb
Host smart-1ae0a8d2-458c-4928-8a14-6a714461459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805865904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3805865904
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1001037077
Short name T611
Test name
Test status
Simulation time 24335034 ps
CPU time 0.74 seconds
Started Feb 25 02:41:01 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 205896 kb
Host smart-0399adc2-54b3-43f3-a820-e51a1959519e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001037077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1001037077
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3642407324
Short name T29
Test name
Test status
Simulation time 235812479 ps
CPU time 6.37 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 220124 kb
Host smart-38afd5ec-200b-424e-87f1-5c4373452a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642407324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3642407324
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.468853660
Short name T615
Test name
Test status
Simulation time 31190316 ps
CPU time 2.03 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 207584 kb
Host smart-ad8c68ae-6672-4f62-baab-2be846e6246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468853660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.468853660
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3028897733
Short name T563
Test name
Test status
Simulation time 93442553 ps
CPU time 4.91 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 220128 kb
Host smart-1233c0db-2ef7-4224-b9ad-a4f4141ee09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028897733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3028897733
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1287601106
Short name T636
Test name
Test status
Simulation time 414567530 ps
CPU time 4.14 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 207288 kb
Host smart-d71476b2-fcf0-4d60-a66a-73c2750a58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287601106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1287601106
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1156293267
Short name T105
Test name
Test status
Simulation time 695909315 ps
CPU time 3.77 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 208236 kb
Host smart-c9d3eed2-6207-4866-a6d9-02a7770d4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156293267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1156293267
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3427386736
Short name T388
Test name
Test status
Simulation time 590968165 ps
CPU time 5.15 seconds
Started Feb 25 02:40:53 PM PST 24
Finished Feb 25 02:40:59 PM PST 24
Peak memory 208160 kb
Host smart-7b3c1725-b81b-40c2-895f-5b830c6572e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427386736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3427386736
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1210004764
Short name T641
Test name
Test status
Simulation time 78421603 ps
CPU time 1.78 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 206564 kb
Host smart-1192f910-8464-4cfe-9546-672c64f56142
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210004764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1210004764
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1747781534
Short name T469
Test name
Test status
Simulation time 59867391 ps
CPU time 3.02 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 208164 kb
Host smart-90498317-b7c8-4a57-968d-db50736c5c94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747781534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1747781534
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.831387129
Short name T821
Test name
Test status
Simulation time 57343266 ps
CPU time 2.27 seconds
Started Feb 25 02:40:53 PM PST 24
Finished Feb 25 02:40:56 PM PST 24
Peak memory 210064 kb
Host smart-e99f8c8d-9a34-4135-95ad-fe5fc5997ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831387129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.831387129
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1841710088
Short name T799
Test name
Test status
Simulation time 816092237 ps
CPU time 5.69 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 207676 kb
Host smart-1b687c74-8d19-49a5-8e68-9e8365500a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841710088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1841710088
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.527666267
Short name T684
Test name
Test status
Simulation time 3127788045 ps
CPU time 33.46 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:37 PM PST 24
Peak memory 221784 kb
Host smart-5980ed0b-3ec8-4343-9b36-554822ae813d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527666267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.527666267
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1296187498
Short name T504
Test name
Test status
Simulation time 637498920 ps
CPU time 6.62 seconds
Started Feb 25 02:41:07 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 218264 kb
Host smart-207961ce-db05-4565-9e8f-0f9831a99052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296187498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1296187498
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1083190540
Short name T377
Test name
Test status
Simulation time 85522376 ps
CPU time 3.61 seconds
Started Feb 25 02:40:53 PM PST 24
Finished Feb 25 02:40:57 PM PST 24
Peak memory 209808 kb
Host smart-26141bcf-d7a4-40d6-9520-96a69009e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083190540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1083190540
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.444605965
Short name T658
Test name
Test status
Simulation time 10942453 ps
CPU time 0.71 seconds
Started Feb 25 02:40:57 PM PST 24
Finished Feb 25 02:40:58 PM PST 24
Peak memory 205892 kb
Host smart-47674723-dbc2-45f1-8790-565e531e0514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444605965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.444605965
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3378815787
Short name T13
Test name
Test status
Simulation time 46959581 ps
CPU time 3.4 seconds
Started Feb 25 02:40:56 PM PST 24
Finished Feb 25 02:41:00 PM PST 24
Peak memory 214956 kb
Host smart-75f33f1f-5333-4c63-b284-7411bef3e4ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378815787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3378815787
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.949672632
Short name T174
Test name
Test status
Simulation time 143140530 ps
CPU time 5.11 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 214508 kb
Host smart-304c0cbd-a922-4d1f-b597-35c778685f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949672632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.949672632
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.671762414
Short name T763
Test name
Test status
Simulation time 231179737 ps
CPU time 3.25 seconds
Started Feb 25 02:41:06 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 218320 kb
Host smart-c9818650-0ecf-450f-9f67-66e7a76d162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671762414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.671762414
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1963866223
Short name T88
Test name
Test status
Simulation time 1105918057 ps
CPU time 25.22 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:23 PM PST 24
Peak memory 208484 kb
Host smart-4fb993ff-047a-45a9-a4f6-0f22ae108027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963866223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1963866223
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3632827812
Short name T236
Test name
Test status
Simulation time 713452121 ps
CPU time 24.87 seconds
Started Feb 25 02:41:00 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 214152 kb
Host smart-9570b578-0f1c-4e84-a6db-010927a06571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632827812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3632827812
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2198091576
Short name T578
Test name
Test status
Simulation time 212472287 ps
CPU time 2.58 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 214280 kb
Host smart-29a99265-ed1f-4a73-a4da-87bf68aa3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198091576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2198091576
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4011075031
Short name T689
Test name
Test status
Simulation time 47679954 ps
CPU time 3.14 seconds
Started Feb 25 02:41:06 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 206608 kb
Host smart-656e843a-c19a-4c59-b858-fdb2330721b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011075031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4011075031
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3985384537
Short name T686
Test name
Test status
Simulation time 1979880825 ps
CPU time 53.41 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:54 PM PST 24
Peak memory 207664 kb
Host smart-5e1d78cf-13fa-4cac-927c-4062f1213f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985384537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3985384537
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3371884746
Short name T792
Test name
Test status
Simulation time 246778106 ps
CPU time 6.28 seconds
Started Feb 25 02:40:56 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 207696 kb
Host smart-3e9b04bc-90ca-4e19-9450-cafc5f3a13a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371884746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3371884746
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.219200170
Short name T833
Test name
Test status
Simulation time 213603614 ps
CPU time 3.12 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 206588 kb
Host smart-ef3d7d11-859b-4385-aac4-150d01ff067b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219200170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.219200170
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3398785814
Short name T434
Test name
Test status
Simulation time 199485357 ps
CPU time 5.87 seconds
Started Feb 25 02:41:05 PM PST 24
Finished Feb 25 02:41:11 PM PST 24
Peak memory 207624 kb
Host smart-067352c5-137e-4fb1-9ec2-8d2b7bc41974
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398785814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3398785814
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1260961789
Short name T224
Test name
Test status
Simulation time 225374996 ps
CPU time 1.52 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:01 PM PST 24
Peak memory 207508 kb
Host smart-f7cbcae3-15e7-4993-b63c-2f23e82c5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260961789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1260961789
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2050230404
Short name T542
Test name
Test status
Simulation time 205248089 ps
CPU time 2.68 seconds
Started Feb 25 02:41:00 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 208212 kb
Host smart-9a1e80e2-7992-4e9d-9598-f3c1261a9926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050230404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2050230404
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.527901870
Short name T736
Test name
Test status
Simulation time 5961779906 ps
CPU time 51.6 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:50 PM PST 24
Peak memory 214908 kb
Host smart-558808ed-273e-486b-adff-a66c3c6c0cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527901870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.527901870
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.130682488
Short name T164
Test name
Test status
Simulation time 141384789 ps
CPU time 3.1 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 209928 kb
Host smart-17ab3d87-2722-46e6-b0da-5abd478a22b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130682488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.130682488
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1008254652
Short name T564
Test name
Test status
Simulation time 21102550 ps
CPU time 0.76 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 205888 kb
Host smart-c0bf5f93-5211-48d6-b002-2108fbb90ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008254652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1008254652
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3423193522
Short name T889
Test name
Test status
Simulation time 165036861 ps
CPU time 3.38 seconds
Started Feb 25 02:41:01 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 214252 kb
Host smart-0e311c24-34fd-4773-a2f0-8d83b6aa5d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423193522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3423193522
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1241562527
Short name T781
Test name
Test status
Simulation time 38297702 ps
CPU time 2.57 seconds
Started Feb 25 02:40:57 PM PST 24
Finished Feb 25 02:41:00 PM PST 24
Peak memory 208420 kb
Host smart-11d7f6e5-5d82-40b5-8f53-f55bda765bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241562527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1241562527
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1570265196
Short name T901
Test name
Test status
Simulation time 256567081 ps
CPU time 7.79 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:11 PM PST 24
Peak memory 209332 kb
Host smart-8cfe37e9-c599-443d-99cd-aad736509a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570265196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1570265196
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.166290579
Short name T476
Test name
Test status
Simulation time 74895821 ps
CPU time 1.68 seconds
Started Feb 25 02:41:00 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 206068 kb
Host smart-374586a9-d757-4dad-bb4e-00fe4165db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166290579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.166290579
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2125303733
Short name T798
Test name
Test status
Simulation time 600105075 ps
CPU time 14.3 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 209188 kb
Host smart-1d1b0e31-cc63-4401-80f3-98f47d96f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125303733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2125303733
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3455038950
Short name T810
Test name
Test status
Simulation time 108234975 ps
CPU time 3.27 seconds
Started Feb 25 02:40:59 PM PST 24
Finished Feb 25 02:41:03 PM PST 24
Peak memory 208212 kb
Host smart-2e3a8424-6d0e-4f0a-a0d0-e530a0a14b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455038950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3455038950
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3985633712
Short name T642
Test name
Test status
Simulation time 5284479171 ps
CPU time 58.03 seconds
Started Feb 25 02:41:05 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 207836 kb
Host smart-355afabb-7cab-4294-b4d4-2bc54e805fa2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985633712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3985633712
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2364809298
Short name T228
Test name
Test status
Simulation time 186622077 ps
CPU time 2.69 seconds
Started Feb 25 02:40:52 PM PST 24
Finished Feb 25 02:40:55 PM PST 24
Peak memory 208336 kb
Host smart-d584d3af-9741-45fa-a228-3a5ff5312635
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364809298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2364809298
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2220429692
Short name T883
Test name
Test status
Simulation time 46508175 ps
CPU time 2.62 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 208540 kb
Host smart-3d8596ba-cfb8-4dfd-a0f8-d75d1d62f3fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220429692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2220429692
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.367439328
Short name T274
Test name
Test status
Simulation time 88774845 ps
CPU time 2.9 seconds
Started Feb 25 02:41:07 PM PST 24
Finished Feb 25 02:41:10 PM PST 24
Peak memory 208372 kb
Host smart-5ff63134-6daf-4518-9280-1aa8a5f832e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367439328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.367439328
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2542567950
Short name T406
Test name
Test status
Simulation time 978193069 ps
CPU time 7.05 seconds
Started Feb 25 02:40:58 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 207724 kb
Host smart-a6b3d95b-975f-4f1a-b5d0-ad9d04849c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542567950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2542567950
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.502525000
Short name T46
Test name
Test status
Simulation time 11204704794 ps
CPU time 238.11 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 222324 kb
Host smart-05be6f34-c390-4f95-91bb-9beff21cf00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502525000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.502525000
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2600829477
Short name T53
Test name
Test status
Simulation time 484905158 ps
CPU time 19.17 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:22 PM PST 24
Peak memory 221980 kb
Host smart-db2099c5-ad13-43e9-bcb2-3eda7cfa7ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600829477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2600829477
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.697655589
Short name T181
Test name
Test status
Simulation time 126669574 ps
CPU time 3.25 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 209896 kb
Host smart-b3bb1e33-62cf-458e-8d3c-4115ca73629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697655589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.697655589
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.33567136
Short name T724
Test name
Test status
Simulation time 16634561 ps
CPU time 0.74 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 205904 kb
Host smart-cc050b17-557b-4293-b6a9-a4994cf7ef04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.33567136
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2716627430
Short name T428
Test name
Test status
Simulation time 21103534 ps
CPU time 1.65 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 208192 kb
Host smart-14ba1041-2e10-4a31-a72c-da61b2d12036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716627430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2716627430
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1428534460
Short name T254
Test name
Test status
Simulation time 78246232 ps
CPU time 3.89 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 214196 kb
Host smart-95a589ab-c2a1-45fc-82d3-1a22629b309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428534460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1428534460
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1400324182
Short name T333
Test name
Test status
Simulation time 102831172 ps
CPU time 3.79 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:06 PM PST 24
Peak memory 210000 kb
Host smart-bb66f443-0250-46f2-a05b-bf2a3e5d9163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400324182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1400324182
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4066393764
Short name T367
Test name
Test status
Simulation time 49202468 ps
CPU time 3.77 seconds
Started Feb 25 02:41:07 PM PST 24
Finished Feb 25 02:41:11 PM PST 24
Peak memory 207812 kb
Host smart-5a97e78c-855c-4ef7-8b87-497426424926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066393764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4066393764
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1013906629
Short name T758
Test name
Test status
Simulation time 56142114 ps
CPU time 3.69 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 207192 kb
Host smart-7f9a02d1-426a-43af-859a-22c19001edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013906629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1013906629
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2863277700
Short name T831
Test name
Test status
Simulation time 38557212 ps
CPU time 1.79 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 206440 kb
Host smart-749e0e6e-d01e-49c5-93cb-6193a4b66551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863277700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2863277700
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2640627566
Short name T327
Test name
Test status
Simulation time 391704006 ps
CPU time 3.79 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 208256 kb
Host smart-73c4c1ce-4184-475a-8ace-082a82497da7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640627566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2640627566
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.901802486
Short name T362
Test name
Test status
Simulation time 863964131 ps
CPU time 6.05 seconds
Started Feb 25 02:41:07 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 207980 kb
Host smart-3774378e-b9d8-49b5-8f30-be06483da5dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901802486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.901802486
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2699788238
Short name T471
Test name
Test status
Simulation time 356264148 ps
CPU time 3.83 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 208352 kb
Host smart-70ef3187-abd7-425a-b6ba-5fa4328b7573
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699788238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2699788238
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.754981158
Short name T481
Test name
Test status
Simulation time 602415411 ps
CPU time 7.77 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:11 PM PST 24
Peak memory 208224 kb
Host smart-2d614997-f79e-464c-913b-29a2c591831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754981158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.754981158
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1626628806
Short name T539
Test name
Test status
Simulation time 195494599 ps
CPU time 2.67 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 208304 kb
Host smart-9554e095-185d-479f-8be5-799a5f8e8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626628806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1626628806
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3983215868
Short name T669
Test name
Test status
Simulation time 123026164 ps
CPU time 6.73 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 215552 kb
Host smart-b1e0fa74-4ce6-4344-9f14-0e9f1b312789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983215868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3983215868
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1970962139
Short name T613
Test name
Test status
Simulation time 302465107 ps
CPU time 9.12 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:20 PM PST 24
Peak memory 222440 kb
Host smart-d0e7a789-6538-41bb-bb29-67da478db38d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970962139 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1970962139
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.370451359
Short name T567
Test name
Test status
Simulation time 237230478 ps
CPU time 6.65 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:11 PM PST 24
Peak memory 208492 kb
Host smart-fb30281e-eb60-4bef-911c-759db567523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370451359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.370451359
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4231195288
Short name T842
Test name
Test status
Simulation time 168568004 ps
CPU time 3.9 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 210220 kb
Host smart-9308b681-8a8a-4b9f-a209-525bf6882ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231195288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4231195288
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.872907891
Short name T538
Test name
Test status
Simulation time 47389150 ps
CPU time 0.86 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 205888 kb
Host smart-108bbf54-e5ca-42ac-affc-f00f6685919b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872907891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.872907891
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.365191860
Short name T287
Test name
Test status
Simulation time 268501165 ps
CPU time 7.7 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:12 PM PST 24
Peak memory 214148 kb
Host smart-0079e115-ffcb-42db-a3e2-69fddc288a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365191860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.365191860
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4206509099
Short name T485
Test name
Test status
Simulation time 227741196 ps
CPU time 7.09 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:22 PM PST 24
Peak memory 222604 kb
Host smart-8ecfa441-1708-469c-8b80-c083094ca75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206509099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4206509099
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1166343838
Short name T631
Test name
Test status
Simulation time 47964865 ps
CPU time 2.67 seconds
Started Feb 25 02:41:16 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 209656 kb
Host smart-407ea135-8273-405b-9dee-9c0712ec887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166343838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1166343838
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.137557337
Short name T355
Test name
Test status
Simulation time 402112242 ps
CPU time 4.94 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:20 PM PST 24
Peak memory 214308 kb
Host smart-dd88522e-abbf-4c81-9c04-46e6616db3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137557337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.137557337
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2276042894
Short name T443
Test name
Test status
Simulation time 86646164 ps
CPU time 2.16 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 211220 kb
Host smart-465208cf-0fbb-437c-a286-671de87ab71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276042894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2276042894
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3049605944
Short name T727
Test name
Test status
Simulation time 297303547 ps
CPU time 4.63 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 219992 kb
Host smart-191185dd-0757-47ca-b29a-cf65e45ec843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049605944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3049605944
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1243219601
Short name T874
Test name
Test status
Simulation time 309034795 ps
CPU time 7.48 seconds
Started Feb 25 02:41:05 PM PST 24
Finished Feb 25 02:41:12 PM PST 24
Peak memory 206984 kb
Host smart-a6663269-1cf4-4c59-85b7-eb0e99f12553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243219601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1243219601
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3763085144
Short name T593
Test name
Test status
Simulation time 305196162 ps
CPU time 3.87 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:08 PM PST 24
Peak memory 206908 kb
Host smart-fa3745fe-12fb-4b2c-ac53-7b2edaf2b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763085144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3763085144
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4181779203
Short name T475
Test name
Test status
Simulation time 38246813 ps
CPU time 1.73 seconds
Started Feb 25 02:41:04 PM PST 24
Finished Feb 25 02:41:06 PM PST 24
Peak memory 207048 kb
Host smart-3e65c9c7-1f8f-4cfe-b596-972316c35dc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181779203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4181779203
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3591868602
Short name T705
Test name
Test status
Simulation time 201022998 ps
CPU time 2.91 seconds
Started Feb 25 02:41:02 PM PST 24
Finished Feb 25 02:41:06 PM PST 24
Peak memory 206340 kb
Host smart-5cd48829-cf5e-4a20-942b-96cb344ae5e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591868602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3591868602
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.591453657
Short name T493
Test name
Test status
Simulation time 119194748 ps
CPU time 2.33 seconds
Started Feb 25 02:41:07 PM PST 24
Finished Feb 25 02:41:09 PM PST 24
Peak memory 206576 kb
Host smart-e6137bc0-714a-4f94-acf7-282957189513
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591453657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.591453657
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3236909566
Short name T288
Test name
Test status
Simulation time 96556844 ps
CPU time 3.04 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 207904 kb
Host smart-5109ac39-c908-4d28-8c41-3bedb6148379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236909566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3236909566
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1152648114
Short name T739
Test name
Test status
Simulation time 81171231 ps
CPU time 1.87 seconds
Started Feb 25 02:41:03 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 206140 kb
Host smart-cdbd7fc7-97d6-4728-a885-91f83fa82770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152648114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1152648114
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3955168543
Short name T206
Test name
Test status
Simulation time 482590975 ps
CPU time 24.27 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 215012 kb
Host smart-4bce4518-21b6-498e-ae3b-846bc96c6618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955168543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3955168543
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2922187852
Short name T296
Test name
Test status
Simulation time 934938622 ps
CPU time 6.37 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 214240 kb
Host smart-94817a68-4c03-4402-aea3-6aa1fb9fe76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922187852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2922187852
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3875511042
Short name T580
Test name
Test status
Simulation time 44769261 ps
CPU time 2.1 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 209200 kb
Host smart-180dba83-f55e-4c3c-a5e6-6c60f7242e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875511042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3875511042
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.503467421
Short name T96
Test name
Test status
Simulation time 20110002 ps
CPU time 0.94 seconds
Started Feb 25 02:40:15 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 206000 kb
Host smart-8016b6f7-e00d-4e7b-bc96-dcacd8b4559c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503467421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.503467421
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1922036441
Short name T394
Test name
Test status
Simulation time 2240621577 ps
CPU time 59.65 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 215280 kb
Host smart-41d2c48b-b13f-49fb-ba3e-a7bb594b8fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922036441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1922036441
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1437499623
Short name T32
Test name
Test status
Simulation time 135730005 ps
CPU time 5.1 seconds
Started Feb 25 02:40:11 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 218100 kb
Host smart-8733bf81-1cfb-47fc-bdad-ccfcdeb52249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437499623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1437499623
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3104998291
Short name T69
Test name
Test status
Simulation time 91946765 ps
CPU time 2.27 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:09 PM PST 24
Peak memory 218196 kb
Host smart-e1ccdeb4-d870-4a82-894e-cc609fdda2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104998291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3104998291
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2801380981
Short name T700
Test name
Test status
Simulation time 300474910 ps
CPU time 4.99 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 208924 kb
Host smart-1b359419-818c-4fcb-b66b-3389a77bcc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801380981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2801380981
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3771763363
Short name T35
Test name
Test status
Simulation time 696187423 ps
CPU time 7.92 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 210364 kb
Host smart-0ae9f59c-6c8b-4710-be44-9f4b6c7d2ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771763363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3771763363
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.997742819
Short name T449
Test name
Test status
Simulation time 146435642 ps
CPU time 4.07 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 206692 kb
Host smart-fcb2e41b-eda8-455f-a4f6-bcd6d4a4b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997742819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.997742819
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.4179195483
Short name T622
Test name
Test status
Simulation time 110043180 ps
CPU time 5.35 seconds
Started Feb 25 02:40:11 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 209076 kb
Host smart-8e92edf0-ecae-492c-b263-913723194e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179195483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4179195483
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4284335673
Short name T101
Test name
Test status
Simulation time 1558661575 ps
CPU time 21.44 seconds
Started Feb 25 02:40:05 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 232748 kb
Host smart-ecd618d7-0855-4da5-ba28-7fa4f4118f7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284335673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4284335673
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3680957501
Short name T661
Test name
Test status
Simulation time 116932330 ps
CPU time 4.81 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 206540 kb
Host smart-999ef218-0630-4b9c-9480-b7df9cf8b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680957501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3680957501
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3619328408
Short name T80
Test name
Test status
Simulation time 43777389 ps
CPU time 1.88 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 206476 kb
Host smart-c34f3600-5161-44c3-a5b2-925f32caeeaa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619328408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3619328408
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3579595284
Short name T584
Test name
Test status
Simulation time 66787861 ps
CPU time 3.36 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 207560 kb
Host smart-042ef0ad-970a-4a9a-924a-93aa01bbb3b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579595284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3579595284
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1311842630
Short name T257
Test name
Test status
Simulation time 656550704 ps
CPU time 4.4 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 205936 kb
Host smart-006403e6-a7de-4154-ab67-226aa9922ec7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311842630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1311842630
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1493944965
Short name T657
Test name
Test status
Simulation time 121174318 ps
CPU time 4.32 seconds
Started Feb 25 02:40:09 PM PST 24
Finished Feb 25 02:40:14 PM PST 24
Peak memory 218160 kb
Host smart-8523d66a-1dcc-48f0-b44e-cd16b6e0f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493944965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1493944965
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3405832238
Short name T590
Test name
Test status
Simulation time 32887993 ps
CPU time 2.27 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:10 PM PST 24
Peak memory 206336 kb
Host smart-da302470-06f0-4023-94e1-9df865fe30e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405832238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3405832238
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.970721990
Short name T213
Test name
Test status
Simulation time 9555232210 ps
CPU time 51.18 seconds
Started Feb 25 02:40:11 PM PST 24
Finished Feb 25 02:41:02 PM PST 24
Peak memory 222368 kb
Host smart-8a856b32-0e85-4f3b-b2d0-8e07f986301b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970721990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.970721990
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3792976078
Short name T814
Test name
Test status
Simulation time 32003256 ps
CPU time 2.8 seconds
Started Feb 25 02:40:04 PM PST 24
Finished Feb 25 02:40:08 PM PST 24
Peak memory 207256 kb
Host smart-435cf110-fd44-41f4-980e-4d1ce4091d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792976078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3792976078
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1082490826
Short name T719
Test name
Test status
Simulation time 68141503 ps
CPU time 2.35 seconds
Started Feb 25 02:40:08 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 209960 kb
Host smart-a35c8feb-953c-4674-980c-109a54ddc2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082490826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1082490826
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3776791534
Short name T498
Test name
Test status
Simulation time 17006430 ps
CPU time 0.83 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:13 PM PST 24
Peak memory 205828 kb
Host smart-099eb15b-7afd-4e5d-b457-0f27e4f5eafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776791534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3776791534
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3913049987
Short name T320
Test name
Test status
Simulation time 244951542 ps
CPU time 4.67 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 215056 kb
Host smart-b56737fc-1a04-4b4b-99e1-7d25dd73988c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913049987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3913049987
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2535994854
Short name T30
Test name
Test status
Simulation time 217362520 ps
CPU time 9.59 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:22 PM PST 24
Peak memory 209560 kb
Host smart-389eda30-9c00-48d5-8ea2-87d115cbba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535994854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2535994854
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4049092042
Short name T489
Test name
Test status
Simulation time 197673681 ps
CPU time 3.89 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 207996 kb
Host smart-d668b7dd-60d1-4e06-bfb2-0a5a6a446849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049092042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4049092042
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.196846547
Short name T827
Test name
Test status
Simulation time 1174435374 ps
CPU time 4.93 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 208092 kb
Host smart-157d2154-9cb5-454e-ba25-743179d33cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196846547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.196846547
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2494880010
Short name T847
Test name
Test status
Simulation time 103750111 ps
CPU time 2.63 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 207780 kb
Host smart-99c80a16-f80f-4284-8822-9532dd484ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494880010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2494880010
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.496500390
Short name T851
Test name
Test status
Simulation time 246687363 ps
CPU time 3.07 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 209540 kb
Host smart-df119b57-1b2a-40bf-9188-7e6bc279252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496500390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.496500390
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1768607377
Short name T273
Test name
Test status
Simulation time 3288630664 ps
CPU time 20.85 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 208112 kb
Host smart-5a2f189b-522a-4814-b091-878aedd1b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768607377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1768607377
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2932800698
Short name T531
Test name
Test status
Simulation time 644826167 ps
CPU time 16.49 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:28 PM PST 24
Peak memory 207768 kb
Host smart-c53e2935-6e7d-4fc7-b5a0-ecf73d33bf5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932800698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2932800698
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.552423932
Short name T688
Test name
Test status
Simulation time 43391293 ps
CPU time 2.55 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 207760 kb
Host smart-42567206-b5e2-4754-8429-cee7b4da2dea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552423932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.552423932
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4217944961
Short name T435
Test name
Test status
Simulation time 247558183 ps
CPU time 5.42 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 206384 kb
Host smart-74a98a00-9d8e-4564-9a08-a2fb719228b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217944961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4217944961
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.979003202
Short name T796
Test name
Test status
Simulation time 1014108358 ps
CPU time 11.09 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 214172 kb
Host smart-d51cbaeb-8892-4aa5-8d8e-1ab9dddd6226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979003202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.979003202
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.802528667
Short name T602
Test name
Test status
Simulation time 23592452 ps
CPU time 1.9 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 206376 kb
Host smart-0fb96b24-d1c5-435d-8e0e-b7355bfce1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802528667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.802528667
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.526229525
Short name T895
Test name
Test status
Simulation time 1550657687 ps
CPU time 40.73 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 215928 kb
Host smart-db3eddd0-06d9-4662-965f-46653f6325e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526229525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.526229525
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.646755181
Short name T858
Test name
Test status
Simulation time 126555453 ps
CPU time 2.65 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 208588 kb
Host smart-8a127ede-f484-4ed3-b671-e5a4c6a3f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646755181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.646755181
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2951390783
Short name T381
Test name
Test status
Simulation time 3046333684 ps
CPU time 4.49 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 210404 kb
Host smart-6be6c3f5-acf4-4914-a853-6ab6215fc46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951390783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2951390783
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.362794775
Short name T893
Test name
Test status
Simulation time 49247640 ps
CPU time 0.74 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 205928 kb
Host smart-c8a17615-2ea7-421d-9b3d-fe38157addf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362794775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.362794775
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3224722129
Short name T270
Test name
Test status
Simulation time 60341790 ps
CPU time 4.31 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 214132 kb
Host smart-f509c168-c67a-4b0d-b720-45d3fdabaf5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224722129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3224722129
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2847950553
Short name T22
Test name
Test status
Simulation time 823200681 ps
CPU time 4.09 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 222688 kb
Host smart-463230c6-50ee-42f2-bf79-c6cd867ed3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847950553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2847950553
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1813213183
Short name T65
Test name
Test status
Simulation time 275498022 ps
CPU time 3.27 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 218276 kb
Host smart-eac2790c-d419-470e-8356-d606b1f2eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813213183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1813213183
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2512839807
Short name T278
Test name
Test status
Simulation time 241517004 ps
CPU time 6.7 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 220864 kb
Host smart-24c301cc-b118-4330-8abc-020bc220c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512839807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2512839807
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3449009823
Short name T351
Test name
Test status
Simulation time 153387544 ps
CPU time 7.14 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 222300 kb
Host smart-c824d72d-fa8a-40e9-8268-f1b3b717b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449009823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3449009823
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2952560338
Short name T60
Test name
Test status
Simulation time 813744195 ps
CPU time 3.67 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 208620 kb
Host smart-0411f3da-4bd6-4dbc-8441-b40d2a36ec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952560338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2952560338
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.543545816
Short name T708
Test name
Test status
Simulation time 7249005333 ps
CPU time 50.45 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:42:02 PM PST 24
Peak memory 214292 kb
Host smart-f16f3742-04c6-4335-a08b-03e56e65da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543545816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.543545816
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.714889639
Short name T326
Test name
Test status
Simulation time 140038982 ps
CPU time 2.57 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 206320 kb
Host smart-0fe61c53-7690-4aa3-955c-7d46250ae68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714889639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.714889639
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2344362353
Short name T713
Test name
Test status
Simulation time 519786114 ps
CPU time 3.01 seconds
Started Feb 25 02:41:12 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 206588 kb
Host smart-2bb102b6-ed3f-463d-a8c8-d33deabdfec4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344362353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2344362353
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2306310915
Short name T497
Test name
Test status
Simulation time 42846595 ps
CPU time 2.49 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 206636 kb
Host smart-1b2f11ef-f32e-40c2-99ce-9de4a12d67f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306310915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2306310915
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1269437596
Short name T543
Test name
Test status
Simulation time 390210605 ps
CPU time 4.73 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 206584 kb
Host smart-133439e8-17eb-4f02-a2fe-657b0df2432b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269437596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1269437596
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.473343453
Short name T81
Test name
Test status
Simulation time 95148757 ps
CPU time 2.06 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 218264 kb
Host smart-6eae8b01-6cf8-47c6-9c6a-515dc64bfc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473343453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.473343453
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1057069620
Short name T385
Test name
Test status
Simulation time 21618777 ps
CPU time 1.87 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 207964 kb
Host smart-6adf729f-02fb-4801-bfac-f2b838a38e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057069620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1057069620
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2880774095
Short name T715
Test name
Test status
Simulation time 123170099 ps
CPU time 4.62 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 216044 kb
Host smart-5d48f3a7-3d8c-4eec-8194-7eaf4dc5bd6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880774095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2880774095
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4174143547
Short name T749
Test name
Test status
Simulation time 226329446 ps
CPU time 14.2 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:26 PM PST 24
Peak memory 220468 kb
Host smart-98956384-a371-487d-b18e-d09d46086959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174143547 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4174143547
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.907053436
Short name T780
Test name
Test status
Simulation time 118843525 ps
CPU time 5.39 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 209660 kb
Host smart-987b73cb-d7e0-4b78-9130-c6fc9d60ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907053436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.907053436
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1840422894
Short name T98
Test name
Test status
Simulation time 52975526 ps
CPU time 1.64 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 209304 kb
Host smart-da61e698-55cf-468e-a71b-e606f3627347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840422894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1840422894
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3009386400
Short name T681
Test name
Test status
Simulation time 64844090 ps
CPU time 0.8 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:41:31 PM PST 24
Peak memory 205808 kb
Host smart-6fbdc173-3b68-46c8-96e5-eba258490ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009386400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3009386400
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2057919029
Short name T249
Test name
Test status
Simulation time 91001301 ps
CPU time 2.16 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 214236 kb
Host smart-31519614-0081-4913-83ee-608c94f9fbb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057919029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2057919029
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2110006148
Short name T208
Test name
Test status
Simulation time 119539709 ps
CPU time 5.51 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 218256 kb
Host smart-088a96ec-ad7b-4bd7-961b-c091d8f55950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110006148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2110006148
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1651028643
Short name T67
Test name
Test status
Simulation time 144614664 ps
CPU time 4.09 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 209688 kb
Host smart-e7e82780-2c7c-4408-9a7c-95a998d05d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651028643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1651028643
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2768268026
Short name T89
Test name
Test status
Simulation time 39353296 ps
CPU time 2.81 seconds
Started Feb 25 02:41:16 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 208348 kb
Host smart-e3b37338-61dd-4ecc-8612-6ce99219f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768268026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2768268026
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3728467856
Short name T298
Test name
Test status
Simulation time 2983936009 ps
CPU time 30.89 seconds
Started Feb 25 02:41:09 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 222352 kb
Host smart-262e3332-1022-4391-bba2-f84727d6b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728467856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3728467856
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2977314832
Short name T639
Test name
Test status
Simulation time 158065405 ps
CPU time 2.88 seconds
Started Feb 25 02:41:13 PM PST 24
Finished Feb 25 02:41:16 PM PST 24
Peak memory 214208 kb
Host smart-7c48124f-a7ef-4fb5-908f-24a9519f3a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977314832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2977314832
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3132917744
Short name T424
Test name
Test status
Simulation time 521870397 ps
CPU time 8.12 seconds
Started Feb 25 02:41:10 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 209880 kb
Host smart-ed7a224a-97cf-4ed4-93d9-c2cab86d6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132917744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3132917744
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4060640452
Short name T289
Test name
Test status
Simulation time 51493716 ps
CPU time 2.04 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 208244 kb
Host smart-be797950-1894-4a80-a233-3479fd8acc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060640452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4060640452
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.615975685
Short name T199
Test name
Test status
Simulation time 178060335 ps
CPU time 2.71 seconds
Started Feb 25 02:41:15 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 208336 kb
Host smart-b071733e-9ecc-4676-b247-de908a216cbb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615975685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.615975685
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.593922298
Short name T906
Test name
Test status
Simulation time 4070034051 ps
CPU time 43.74 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:55 PM PST 24
Peak memory 207712 kb
Host smart-25e06695-9c72-41cf-b9bc-dc7bef27c04e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593922298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.593922298
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2768865041
Short name T110
Test name
Test status
Simulation time 172581930 ps
CPU time 2.75 seconds
Started Feb 25 02:41:17 PM PST 24
Finished Feb 25 02:41:19 PM PST 24
Peak memory 207112 kb
Host smart-9ad2765b-6c31-403c-abff-f202e93a6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768865041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2768865041
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.939133981
Short name T430
Test name
Test status
Simulation time 19425415 ps
CPU time 1.65 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 206372 kb
Host smart-37456f96-b561-466d-9a41-7d42891e28cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939133981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.939133981
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1129130578
Short name T260
Test name
Test status
Simulation time 1119095697 ps
CPU time 18.37 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 222616 kb
Host smart-6f6acd2d-ce0a-4f5c-ba5c-14f41aee90c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129130578 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1129130578
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.555817066
Short name T252
Test name
Test status
Simulation time 216509870 ps
CPU time 5.24 seconds
Started Feb 25 02:41:11 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 207116 kb
Host smart-9d789714-cd4c-4cd1-9d63-3d6e2d2a5a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555817066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.555817066
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2594611672
Short name T683
Test name
Test status
Simulation time 264341469 ps
CPU time 3.11 seconds
Started Feb 25 02:41:14 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 209912 kb
Host smart-9daa63a8-5c54-46fd-9560-2b282047eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594611672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2594611672
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1794242640
Short name T519
Test name
Test status
Simulation time 20496625 ps
CPU time 0.75 seconds
Started Feb 25 02:41:23 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 205808 kb
Host smart-ee6d7cc5-5dfd-40fa-8a1f-1db77a7a2e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794242640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1794242640
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.703437712
Short name T907
Test name
Test status
Simulation time 65603174 ps
CPU time 2.74 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 214328 kb
Host smart-e59051f4-7185-495b-abdc-4b0f699ba550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703437712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.703437712
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1509321064
Short name T561
Test name
Test status
Simulation time 158907165 ps
CPU time 2.96 seconds
Started Feb 25 02:41:29 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 208956 kb
Host smart-3f6c8692-8d38-456f-bb90-0dd5a548109a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509321064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1509321064
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1749170855
Short name T354
Test name
Test status
Simulation time 3984594009 ps
CPU time 37.98 seconds
Started Feb 25 02:41:27 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 222272 kb
Host smart-7f7b280c-f475-45bd-9e7e-acad20dabe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749170855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1749170855
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2161091419
Short name T818
Test name
Test status
Simulation time 410084745 ps
CPU time 2.64 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 215408 kb
Host smart-426a00b9-e6b4-4ddb-a6f5-3aa2ea616d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161091419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2161091419
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.911473876
Short name T444
Test name
Test status
Simulation time 481105113 ps
CPU time 6.67 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:41:29 PM PST 24
Peak memory 218112 kb
Host smart-c5dc33f3-96c2-454a-b34d-fe69c01bbdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911473876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.911473876
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2575524198
Short name T678
Test name
Test status
Simulation time 54649553 ps
CPU time 3.04 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 206552 kb
Host smart-09850ad3-acb4-421e-954e-43a8e63eca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575524198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2575524198
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1975071022
Short name T765
Test name
Test status
Simulation time 126962990 ps
CPU time 3.3 seconds
Started Feb 25 02:41:21 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 207200 kb
Host smart-50466396-c0a0-41b1-94f7-cd1a5769f817
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975071022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1975071022
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3308964487
Short name T412
Test name
Test status
Simulation time 1123030766 ps
CPU time 4.18 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 206508 kb
Host smart-2fd60188-af28-4ba1-ba31-53b1f4390148
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308964487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3308964487
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1762928511
Short name T693
Test name
Test status
Simulation time 123628063 ps
CPU time 2.79 seconds
Started Feb 25 02:41:25 PM PST 24
Finished Feb 25 02:41:29 PM PST 24
Peak memory 206676 kb
Host smart-7b236cf5-c9c0-47c4-ad58-ecebf0d9d138
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762928511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1762928511
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2827750630
Short name T723
Test name
Test status
Simulation time 109359247 ps
CPU time 2.97 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 208848 kb
Host smart-865f29b2-9018-4769-8b01-c6df9b5344af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827750630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2827750630
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2051356246
Short name T835
Test name
Test status
Simulation time 571328696 ps
CPU time 12.84 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 207440 kb
Host smart-458ee7fc-f4cd-4a93-a17a-62722c511a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051356246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2051356246
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4010923395
Short name T368
Test name
Test status
Simulation time 159532938 ps
CPU time 7.56 seconds
Started Feb 25 02:41:27 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 207220 kb
Host smart-29b90bb1-0698-4e84-bad4-daf0efa493db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010923395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4010923395
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.903183961
Short name T665
Test name
Test status
Simulation time 488162413 ps
CPU time 6.88 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 222528 kb
Host smart-fe9b871a-899a-4256-b7d3-9c46f81528e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903183961 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.903183961
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2490815133
Short name T345
Test name
Test status
Simulation time 16949509668 ps
CPU time 84.17 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 222444 kb
Host smart-3b319445-bf57-4abe-b93f-56401c826eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490815133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2490815133
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2196543314
Short name T49
Test name
Test status
Simulation time 845942757 ps
CPU time 9.31 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 210104 kb
Host smart-b08a5098-c4ae-4883-b60b-57d8029a8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196543314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2196543314
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1653429583
Short name T452
Test name
Test status
Simulation time 16881354 ps
CPU time 1.02 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 205932 kb
Host smart-b4f57045-6056-4703-8b60-25172c3a9689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653429583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1653429583
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1636409884
Short name T837
Test name
Test status
Simulation time 1372338401 ps
CPU time 29.73 seconds
Started Feb 25 02:41:27 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 222676 kb
Host smart-f4935178-ff5b-4169-b15c-c56db020154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636409884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1636409884
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1354226235
Short name T554
Test name
Test status
Simulation time 64505968 ps
CPU time 2.05 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:28 PM PST 24
Peak memory 207660 kb
Host smart-47bce052-d94c-48fc-b7e2-5f3e8bfb2a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354226235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1354226235
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1942607480
Short name T94
Test name
Test status
Simulation time 1460913629 ps
CPU time 43.49 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 222344 kb
Host smart-67a00bae-e7c8-44d0-84c7-c54dc289914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942607480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1942607480
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2164487218
Short name T513
Test name
Test status
Simulation time 75747091 ps
CPU time 3.18 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 219912 kb
Host smart-85986a8d-61d3-456e-8ecb-6928e2709a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164487218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2164487218
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1952902629
Short name T720
Test name
Test status
Simulation time 1993308321 ps
CPU time 5.67 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:37 PM PST 24
Peak memory 218176 kb
Host smart-c5098096-edf4-48d9-91b0-cbd81dc9f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952902629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1952902629
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3151935764
Short name T771
Test name
Test status
Simulation time 56316087 ps
CPU time 2.9 seconds
Started Feb 25 02:41:32 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 207840 kb
Host smart-8f2bbf8f-d5d8-4ccd-a9a2-887f591682b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151935764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3151935764
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3080849120
Short name T512
Test name
Test status
Simulation time 38135712 ps
CPU time 2.53 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:28 PM PST 24
Peak memory 208216 kb
Host smart-3811a04d-5c9c-4c2c-bbd2-064f7cf5e172
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080849120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3080849120
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3686793384
Short name T734
Test name
Test status
Simulation time 501322224 ps
CPU time 7.84 seconds
Started Feb 25 02:41:30 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 206548 kb
Host smart-ad32d32e-720f-4127-9aa9-ece3d244c12e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686793384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3686793384
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4259879830
Short name T828
Test name
Test status
Simulation time 3041808633 ps
CPU time 22.82 seconds
Started Feb 25 02:41:25 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 208736 kb
Host smart-88a78f08-e70e-48da-a164-6b9521931b84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259879830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4259879830
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2292200739
Short name T109
Test name
Test status
Simulation time 460502841 ps
CPU time 9.71 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 207832 kb
Host smart-60a40a92-a375-4d60-ab21-8f9a7be5e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292200739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2292200739
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2487358007
Short name T587
Test name
Test status
Simulation time 1592357931 ps
CPU time 15.85 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:44 PM PST 24
Peak memory 208416 kb
Host smart-61d92413-5e84-4594-874d-c7a3e6d6b0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487358007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2487358007
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1181946263
Short name T566
Test name
Test status
Simulation time 1029958789 ps
CPU time 10.11 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 214832 kb
Host smart-22d27076-cb4d-44e7-9106-b279bea66f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181946263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1181946263
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.59212968
Short name T124
Test name
Test status
Simulation time 1142794096 ps
CPU time 14 seconds
Started Feb 25 02:41:31 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 222516 kb
Host smart-f40e96e3-8415-4818-afd7-c5c996de01e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59212968 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.59212968
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3922024064
Short name T477
Test name
Test status
Simulation time 304999548 ps
CPU time 4.01 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 207008 kb
Host smart-53709938-6e37-48b6-a9cc-a8ee2fa24400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922024064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3922024064
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3028839888
Short name T732
Test name
Test status
Simulation time 110250479 ps
CPU time 3.55 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 210508 kb
Host smart-5601f3c7-5326-40f5-ac30-cdd5d8ca5c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028839888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3028839888
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2837809457
Short name T623
Test name
Test status
Simulation time 37455510 ps
CPU time 0.74 seconds
Started Feb 25 02:41:38 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 205888 kb
Host smart-7ac45489-e2ef-41ec-8d65-cc9bb05b663e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837809457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2837809457
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2245671980
Short name T532
Test name
Test status
Simulation time 31192801 ps
CPU time 1.66 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 209044 kb
Host smart-a2825304-5d0a-491d-8a35-dd18531b0bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245671980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2245671980
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3879226
Short name T303
Test name
Test status
Simulation time 1375369433 ps
CPU time 11.15 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 222264 kb
Host smart-e03ba171-1a9e-49e0-8d6d-a47bb4b760bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3879226
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.2540814795
Short name T864
Test name
Test status
Simulation time 307636006 ps
CPU time 6.46 seconds
Started Feb 25 02:41:27 PM PST 24
Finished Feb 25 02:41:33 PM PST 24
Peak memory 206816 kb
Host smart-7578eaac-b586-42da-bbee-4fce4a47cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540814795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2540814795
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1841330681
Short name T462
Test name
Test status
Simulation time 277878747 ps
CPU time 3.53 seconds
Started Feb 25 02:41:25 PM PST 24
Finished Feb 25 02:41:29 PM PST 24
Peak memory 208316 kb
Host smart-5da22e2e-231f-4a84-8518-08513de9da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841330681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1841330681
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2886980127
Short name T750
Test name
Test status
Simulation time 328871415 ps
CPU time 7.24 seconds
Started Feb 25 02:41:25 PM PST 24
Finished Feb 25 02:41:32 PM PST 24
Peak memory 207844 kb
Host smart-0ba919e1-d321-40e0-8e60-340a8cf6413c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886980127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2886980127
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1347153923
Short name T786
Test name
Test status
Simulation time 136481016 ps
CPU time 2.71 seconds
Started Feb 25 02:41:24 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 208168 kb
Host smart-71ed36ca-f1ce-43b6-9a41-bb589f67d744
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347153923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1347153923
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3221329039
Short name T879
Test name
Test status
Simulation time 143895746 ps
CPU time 5.01 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:33 PM PST 24
Peak memory 208024 kb
Host smart-4213cbf1-8be4-42a7-ae46-7296ab54e7d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221329039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3221329039
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2043753225
Short name T238
Test name
Test status
Simulation time 67589754 ps
CPU time 3.57 seconds
Started Feb 25 02:41:26 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 209600 kb
Host smart-8dc7f6ed-019b-45cd-ab90-4f7c25769dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043753225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2043753225
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4074073001
Short name T621
Test name
Test status
Simulation time 194157375 ps
CPU time 2.85 seconds
Started Feb 25 02:41:22 PM PST 24
Finished Feb 25 02:41:25 PM PST 24
Peak memory 208144 kb
Host smart-8bcbaf3e-4f89-4f1c-810b-286c8d260e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074073001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4074073001
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2525428930
Short name T277
Test name
Test status
Simulation time 451127054 ps
CPU time 11.33 seconds
Started Feb 25 02:41:23 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 216116 kb
Host smart-86aad99a-8ce9-4db8-905b-7d64d1984770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525428930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2525428930
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.599845876
Short name T352
Test name
Test status
Simulation time 227147904 ps
CPU time 9.51 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 222616 kb
Host smart-62a0c97a-aa0a-4079-8832-a0b9b96b5cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599845876 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.599845876
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.746274779
Short name T226
Test name
Test status
Simulation time 223653776 ps
CPU time 3.08 seconds
Started Feb 25 02:41:27 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 207152 kb
Host smart-428fe963-65c1-4c2e-8021-4e2c29b68e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746274779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.746274779
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3270246356
Short name T153
Test name
Test status
Simulation time 65850649 ps
CPU time 1.86 seconds
Started Feb 25 02:41:28 PM PST 24
Finished Feb 25 02:41:30 PM PST 24
Peak memory 209856 kb
Host smart-10bf1d76-0deb-4a3b-affa-d79599999c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270246356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3270246356
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1279332530
Short name T682
Test name
Test status
Simulation time 47972102 ps
CPU time 0.92 seconds
Started Feb 25 02:41:40 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 205808 kb
Host smart-c941757e-4a2f-44a5-ac26-b0cb7514de94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279332530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1279332530
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.374130222
Short name T373
Test name
Test status
Simulation time 264585588 ps
CPU time 3 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 214200 kb
Host smart-e115caf4-d32e-4484-b3c7-7e59cc60f3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374130222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.374130222
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2511806458
Short name T192
Test name
Test status
Simulation time 2348138203 ps
CPU time 45.08 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 222344 kb
Host smart-cfd9fb9d-387e-4b89-b5df-b1287d6027c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511806458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2511806458
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4007832285
Short name T127
Test name
Test status
Simulation time 66003942 ps
CPU time 1.54 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:37 PM PST 24
Peak memory 206096 kb
Host smart-e5a01ccf-ad2e-49a5-ae35-f7b2490b2b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007832285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4007832285
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4007552572
Short name T282
Test name
Test status
Simulation time 113456527 ps
CPU time 2.81 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 208416 kb
Host smart-e2e5c440-0634-4d52-bbee-14fa6f476640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007552572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4007552572
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1265914464
Short name T626
Test name
Test status
Simulation time 2326177416 ps
CPU time 56.91 seconds
Started Feb 25 02:41:42 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 208680 kb
Host smart-8ae32836-8862-4f24-9fca-f3fea7e9d632
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265914464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1265914464
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1591176301
Short name T506
Test name
Test status
Simulation time 728262272 ps
CPU time 5.94 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 207572 kb
Host smart-ae49baf5-52a6-4e6b-b248-ee4ad47f5fef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591176301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1591176301
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2571699170
Short name T741
Test name
Test status
Simulation time 64348004 ps
CPU time 3.03 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 207680 kb
Host smart-cc7f12ab-cfe0-4d01-a4c8-3286a1ca146e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571699170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2571699170
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2621549324
Short name T659
Test name
Test status
Simulation time 20428301 ps
CPU time 1.77 seconds
Started Feb 25 02:41:40 PM PST 24
Finished Feb 25 02:41:42 PM PST 24
Peak memory 214976 kb
Host smart-dd133fec-d88c-45d0-818e-88d8fc5a7e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621549324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2621549324
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1751855583
Short name T777
Test name
Test status
Simulation time 246255093 ps
CPU time 2.81 seconds
Started Feb 25 02:41:40 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 206720 kb
Host smart-9c207f76-147a-418f-9e62-b33a737111c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751855583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1751855583
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3442324756
Short name T189
Test name
Test status
Simulation time 533382418 ps
CPU time 4.59 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 214200 kb
Host smart-6c94f526-33bd-4345-9505-8bd89d4b8ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442324756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3442324756
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2752978560
Short name T656
Test name
Test status
Simulation time 137110482 ps
CPU time 1.75 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:41:36 PM PST 24
Peak memory 209760 kb
Host smart-f9b022e3-8044-4b17-ab04-ca1a124325b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752978560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2752978560
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1427292841
Short name T589
Test name
Test status
Simulation time 45543952 ps
CPU time 0.78 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 205896 kb
Host smart-5bbbedc8-9674-4782-b6e6-879d269b1331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427292841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1427292841
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1161394892
Short name T404
Test name
Test status
Simulation time 1290035444 ps
CPU time 65.24 seconds
Started Feb 25 02:41:38 PM PST 24
Finished Feb 25 02:42:43 PM PST 24
Peak memory 215308 kb
Host smart-e6bdef6f-0315-4f69-b789-33fb4738ce3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161394892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1161394892
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2129151626
Short name T801
Test name
Test status
Simulation time 87287726 ps
CPU time 3.32 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 210000 kb
Host smart-237dcd20-8080-4dae-a9a1-a17fab7e23d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129151626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2129151626
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1085572781
Short name T603
Test name
Test status
Simulation time 2936707201 ps
CPU time 15.95 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 208028 kb
Host smart-48e6be82-4ea6-4058-8544-214e9bb7d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085572781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1085572781
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3687966908
Short name T335
Test name
Test status
Simulation time 2252886925 ps
CPU time 39.35 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:42:26 PM PST 24
Peak memory 217380 kb
Host smart-91539c9b-90c4-4c57-bf05-442fd4cd9f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687966908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3687966908
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3987890459
Short name T307
Test name
Test status
Simulation time 10345183942 ps
CPU time 64.8 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 222868 kb
Host smart-dd28ad9e-39d1-4d38-99c1-23ca39700ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987890459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3987890459
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1798061765
Short name T209
Test name
Test status
Simulation time 48158153 ps
CPU time 2.45 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 209504 kb
Host smart-5c386351-d6d2-476a-99bc-e34f3ba3649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798061765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1798061765
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3262678690
Short name T816
Test name
Test status
Simulation time 2385036306 ps
CPU time 7.5 seconds
Started Feb 25 02:41:39 PM PST 24
Finished Feb 25 02:41:46 PM PST 24
Peak memory 208840 kb
Host smart-05e356ec-ce5f-4e06-86b1-d35407089824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262678690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3262678690
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3616619840
Short name T450
Test name
Test status
Simulation time 222018065 ps
CPU time 3.27 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 206388 kb
Host smart-de7f748d-c9cb-4c02-b871-8145d88a35a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616619840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3616619840
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1319194633
Short name T198
Test name
Test status
Simulation time 700332899 ps
CPU time 6.98 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 207860 kb
Host smart-95ac0a1f-905c-43e5-b2ce-827a5a267856
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319194633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1319194633
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1105963288
Short name T342
Test name
Test status
Simulation time 1027673304 ps
CPU time 5.16 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:42 PM PST 24
Peak memory 206432 kb
Host smart-550335af-98dd-46e6-91c0-f4e90e4b3d28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105963288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1105963288
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1682132994
Short name T505
Test name
Test status
Simulation time 21716361 ps
CPU time 1.76 seconds
Started Feb 25 02:41:41 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 206568 kb
Host smart-dd08369c-9995-4236-9c2b-4d266fee6252
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682132994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1682132994
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.574128357
Short name T200
Test name
Test status
Simulation time 394028219 ps
CPU time 2.96 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:41:37 PM PST 24
Peak memory 209252 kb
Host smart-f5787d0d-8df2-4142-856a-4781e51f3530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574128357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.574128357
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3719066013
Short name T483
Test name
Test status
Simulation time 1540886975 ps
CPU time 37.89 seconds
Started Feb 25 02:41:41 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 208012 kb
Host smart-0f915fb6-826e-4458-8a5c-abac66a99da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719066013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3719066013
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3910943134
Short name T178
Test name
Test status
Simulation time 1878584215 ps
CPU time 22.44 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 222492 kb
Host smart-46916249-8a11-4e13-b54d-f62799e6a369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910943134 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3910943134
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2380924591
Short name T295
Test name
Test status
Simulation time 1140590902 ps
CPU time 8.87 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:46 PM PST 24
Peak memory 218156 kb
Host smart-d9d0e29e-a13a-48b7-a729-d305c4cf2eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380924591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2380924591
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1009711506
Short name T114
Test name
Test status
Simulation time 222218476 ps
CPU time 1.59 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 209496 kb
Host smart-b6f09282-d500-4a0a-a598-be2209dc471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009711506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1009711506
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2478712156
Short name T667
Test name
Test status
Simulation time 44243838 ps
CPU time 0.78 seconds
Started Feb 25 02:41:38 PM PST 24
Finished Feb 25 02:41:39 PM PST 24
Peak memory 205856 kb
Host smart-da4136fb-8aae-4dc1-aa5e-2c5804b6848c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478712156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2478712156
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.212937792
Short name T223
Test name
Test status
Simulation time 180048555 ps
CPU time 9.7 seconds
Started Feb 25 02:41:42 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 214292 kb
Host smart-9d27db03-8f7a-49b6-8b4f-bd96c39fcfb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212937792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.212937792
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.531787407
Short name T458
Test name
Test status
Simulation time 50745575 ps
CPU time 2.44 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 209608 kb
Host smart-a1b1f3e3-4b68-4948-94a3-70b778a0e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531787407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.531787407
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2821286558
Short name T338
Test name
Test status
Simulation time 177216947 ps
CPU time 5.93 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 222092 kb
Host smart-2e856162-09bd-4e0d-b073-b167008ec32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821286558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2821286558
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1573335704
Short name T301
Test name
Test status
Simulation time 242687607 ps
CPU time 8.5 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:46 PM PST 24
Peak memory 222312 kb
Host smart-b9ad1021-6ddf-4694-860f-f287887e2187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573335704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1573335704
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1524327400
Short name T216
Test name
Test status
Simulation time 266400384 ps
CPU time 4.46 seconds
Started Feb 25 02:41:40 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 209764 kb
Host smart-ee7260eb-9b4f-4e65-b56e-088f0d963f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524327400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1524327400
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1688805725
Short name T322
Test name
Test status
Simulation time 318795636 ps
CPU time 2.95 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:41:37 PM PST 24
Peak memory 206768 kb
Host smart-f6ab856a-a8ad-49c9-a04e-88dfa3fce4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688805725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1688805725
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2306516865
Short name T133
Test name
Test status
Simulation time 197440919 ps
CPU time 5.34 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 208036 kb
Host smart-4cafa5df-2d4f-4448-878b-4edf3ef165a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306516865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2306516865
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.461032989
Short name T557
Test name
Test status
Simulation time 265714335 ps
CPU time 4.71 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 208184 kb
Host smart-3c25d4dc-b095-46bd-93e1-3ee3266c1c96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461032989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.461032989
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3423917947
Short name T897
Test name
Test status
Simulation time 242667210 ps
CPU time 4.93 seconds
Started Feb 25 02:41:33 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 207768 kb
Host smart-386b993f-bfb1-4546-82c9-fe89d4ddf044
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423917947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3423917947
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1167224113
Short name T722
Test name
Test status
Simulation time 187961449 ps
CPU time 2.08 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:47 PM PST 24
Peak memory 208556 kb
Host smart-38a65cb5-1c58-4574-82ee-52998147c5b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167224113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1167224113
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.338297783
Short name T253
Test name
Test status
Simulation time 4338718611 ps
CPU time 46.19 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 214156 kb
Host smart-e287f100-164d-48df-aa1b-a528cfddd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338297783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.338297783
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3550510805
Short name T484
Test name
Test status
Simulation time 6160580600 ps
CPU time 18.42 seconds
Started Feb 25 02:41:42 PM PST 24
Finished Feb 25 02:42:01 PM PST 24
Peak memory 208008 kb
Host smart-b7e31a77-ea12-425c-b05a-ebe837789a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550510805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3550510805
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3166233496
Short name T184
Test name
Test status
Simulation time 32996345779 ps
CPU time 173.05 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:44:30 PM PST 24
Peak memory 217036 kb
Host smart-3fde925d-f8b1-4e99-9250-6f3f025b72f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166233496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3166233496
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.439049604
Short name T666
Test name
Test status
Simulation time 337546877 ps
CPU time 4.05 seconds
Started Feb 25 02:41:34 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 209464 kb
Host smart-05b47154-feae-4fbe-8a8f-1c6b2e9f2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439049604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.439049604
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3927838835
Short name T529
Test name
Test status
Simulation time 176289675 ps
CPU time 2.31 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 210160 kb
Host smart-87a97988-bba0-44c8-9925-aad035c20a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927838835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3927838835
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1236445181
Short name T525
Test name
Test status
Simulation time 17891506 ps
CPU time 0.85 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 205892 kb
Host smart-b32e769e-4be0-4fab-8def-a26ac5e63ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236445181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1236445181
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.92565186
Short name T841
Test name
Test status
Simulation time 48499543 ps
CPU time 2.51 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:50 PM PST 24
Peak memory 209216 kb
Host smart-226056c8-cf60-488d-8ca6-7638375342b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92565186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.92565186
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2931260388
Short name T74
Test name
Test status
Simulation time 1221902257 ps
CPU time 25.17 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:42:08 PM PST 24
Peak memory 208492 kb
Host smart-7d8f2bae-5a44-4f1b-ba11-1bd4543c41cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931260388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2931260388
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.846956512
Short name T541
Test name
Test status
Simulation time 59923506 ps
CPU time 3.55 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 214220 kb
Host smart-7f224934-52be-4074-b401-361f0b7beea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846956512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.846956512
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4187826459
Short name T302
Test name
Test status
Simulation time 2460983291 ps
CPU time 6.27 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 211600 kb
Host smart-d005a2a5-033e-41f2-86d2-3b21c975f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187826459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4187826459
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.186014515
Short name T795
Test name
Test status
Simulation time 344158581 ps
CPU time 2.85 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 214476 kb
Host smart-31fba3ac-dc8d-4bfc-b8b7-6647ec0bc5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186014515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.186014515
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3556360610
Short name T598
Test name
Test status
Simulation time 327113230 ps
CPU time 4.31 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 208904 kb
Host smart-33d7bb44-176e-4349-a66b-86df932039c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556360610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3556360610
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.486548603
Short name T457
Test name
Test status
Simulation time 270472181 ps
CPU time 3.47 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 207532 kb
Host smart-0d98362d-546c-4295-a010-dbdeca0b2326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486548603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.486548603
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.672265585
Short name T881
Test name
Test status
Simulation time 76279750 ps
CPU time 2.95 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 208680 kb
Host smart-2acffb1f-a6c8-4117-be57-d0e7586c8a84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672265585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.672265585
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.12782700
Short name T417
Test name
Test status
Simulation time 214322385 ps
CPU time 7.49 seconds
Started Feb 25 02:41:35 PM PST 24
Finished Feb 25 02:41:43 PM PST 24
Peak memory 207796 kb
Host smart-a370ff98-f3d8-4d1e-8a6e-59b0f09e8ece
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12782700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.12782700
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.659697542
Short name T805
Test name
Test status
Simulation time 202140711 ps
CPU time 3.44 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:41 PM PST 24
Peak memory 208332 kb
Host smart-3f058206-82a6-4c24-b22b-b59968331c50
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659697542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.659697542
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.842777257
Short name T637
Test name
Test status
Simulation time 86363365 ps
CPU time 2.15 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 208388 kb
Host smart-3586244b-bd37-4121-89be-e03a85d56764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842777257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.842777257
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3161892266
Short name T423
Test name
Test status
Simulation time 534861798 ps
CPU time 5.84 seconds
Started Feb 25 02:41:43 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 208084 kb
Host smart-5216aea9-183c-4fa7-b496-d3876ebe3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161892266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3161892266
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.991185131
Short name T862
Test name
Test status
Simulation time 328232969 ps
CPU time 14.57 seconds
Started Feb 25 02:41:37 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 222612 kb
Host smart-c2820857-b08a-4dd2-a448-96f8b0e1c364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991185131 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.991185131
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1762350292
Short name T789
Test name
Test status
Simulation time 4206838649 ps
CPU time 55.97 seconds
Started Feb 25 02:41:38 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 222476 kb
Host smart-336edd11-381d-41a8-b458-c98b5d91efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762350292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1762350292
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1390711459
Short name T155
Test name
Test status
Simulation time 1353241738 ps
CPU time 3.82 seconds
Started Feb 25 02:41:41 PM PST 24
Finished Feb 25 02:41:45 PM PST 24
Peak memory 210044 kb
Host smart-728852e6-a4b0-41ee-83a8-50d7adae45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390711459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1390711459
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.590416351
Short name T627
Test name
Test status
Simulation time 32848738 ps
CPU time 0.84 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:24 PM PST 24
Peak memory 205820 kb
Host smart-4be9a254-1c6b-429d-8d12-ce0ba67fb5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590416351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.590416351
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.282494192
Short name T785
Test name
Test status
Simulation time 84637752 ps
CPU time 4.34 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 209376 kb
Host smart-5fba2e13-c764-41f1-a1da-0368f28c257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282494192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.282494192
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1650229028
Short name T751
Test name
Test status
Simulation time 37887315 ps
CPU time 2.73 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 207392 kb
Host smart-658cde10-fb73-46ae-bdcd-6cc20fb7b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650229028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1650229028
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4185022438
Short name T91
Test name
Test status
Simulation time 4988159967 ps
CPU time 44.84 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:41:07 PM PST 24
Peak memory 222416 kb
Host smart-c28f9ec4-b51f-4d45-ad2d-3723904e4817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185022438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4185022438
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2294373718
Short name T350
Test name
Test status
Simulation time 388234142 ps
CPU time 4.17 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 211164 kb
Host smart-98ad2e31-4a2c-417d-a2c9-d18a2ac5c496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294373718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2294373718
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1213039825
Short name T645
Test name
Test status
Simulation time 164167986 ps
CPU time 2.72 seconds
Started Feb 25 02:40:17 PM PST 24
Finished Feb 25 02:40:20 PM PST 24
Peak memory 218032 kb
Host smart-3221a313-2cfd-4908-943d-98b8f7de2bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213039825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1213039825
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.545120223
Short name T438
Test name
Test status
Simulation time 482595125 ps
CPU time 6.98 seconds
Started Feb 25 02:40:12 PM PST 24
Finished Feb 25 02:40:19 PM PST 24
Peak memory 208848 kb
Host smart-4593dcc7-3443-4074-9f19-13c5e5c69844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545120223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.545120223
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3980414533
Short name T102
Test name
Test status
Simulation time 4475267016 ps
CPU time 24.11 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 236212 kb
Host smart-ebbad3e7-a77d-4ce8-b999-5e6243347658
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980414533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3980414533
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4000833089
Short name T574
Test name
Test status
Simulation time 1724578974 ps
CPU time 6.04 seconds
Started Feb 25 02:40:10 PM PST 24
Finished Feb 25 02:40:17 PM PST 24
Peak memory 208156 kb
Host smart-7cf8701f-405e-4622-a085-9684cd2f63d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000833089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4000833089
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1558363914
Short name T697
Test name
Test status
Simulation time 47691325 ps
CPU time 2.57 seconds
Started Feb 25 02:40:15 PM PST 24
Finished Feb 25 02:40:18 PM PST 24
Peak memory 206528 kb
Host smart-b2db97f8-11e0-4794-977d-1320e1574cfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558363914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1558363914
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2818454999
Short name T759
Test name
Test status
Simulation time 323972928 ps
CPU time 4.29 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 208184 kb
Host smart-86cf8c25-1fe5-408a-807b-a8ea43450805
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818454999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2818454999
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1625130347
Short name T630
Test name
Test status
Simulation time 68321121 ps
CPU time 3.27 seconds
Started Feb 25 02:40:04 PM PST 24
Finished Feb 25 02:40:08 PM PST 24
Peak memory 208272 kb
Host smart-d0481837-2abd-4e53-8aa0-4d286d89d7a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625130347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1625130347
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3163390671
Short name T902
Test name
Test status
Simulation time 80465892 ps
CPU time 1.86 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 214312 kb
Host smart-27d7c475-e64a-4d7c-a316-8cf3fc6980fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163390671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3163390671
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4197439418
Short name T521
Test name
Test status
Simulation time 66256070 ps
CPU time 2.84 seconds
Started Feb 25 02:40:07 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 206540 kb
Host smart-dc9b474e-e602-44ca-bd66-c53e3671b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197439418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4197439418
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.439068691
Short name T793
Test name
Test status
Simulation time 45751771207 ps
CPU time 73.6 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:41:34 PM PST 24
Peak memory 222436 kb
Host smart-5c431f51-b1a9-4483-88ec-c8f4f1f59f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439068691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.439068691
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.140335641
Short name T601
Test name
Test status
Simulation time 548982254 ps
CPU time 10.96 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 222504 kb
Host smart-37a33bc3-be34-486a-b0fb-bf33f8321734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140335641 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.140335641
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.352231276
Short name T743
Test name
Test status
Simulation time 250406822 ps
CPU time 3.58 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 218220 kb
Host smart-67014a45-fdd4-4801-bbb5-e024e626b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352231276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.352231276
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3815743593
Short name T376
Test name
Test status
Simulation time 203337223 ps
CPU time 2.74 seconds
Started Feb 25 02:40:18 PM PST 24
Finished Feb 25 02:40:21 PM PST 24
Peak memory 209708 kb
Host smart-e33b8d8a-ea5b-4f70-9134-20451e5a5aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815743593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3815743593
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.565670355
Short name T813
Test name
Test status
Simulation time 152467514 ps
CPU time 0.77 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:50 PM PST 24
Peak memory 205888 kb
Host smart-7e2e502d-7e26-47d3-bc1e-2e65825555c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565670355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.565670355
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1180689826
Short name T854
Test name
Test status
Simulation time 146517367 ps
CPU time 1.67 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 207760 kb
Host smart-83b280c6-a383-4991-a644-4d7d493c7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180689826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1180689826
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2042983318
Short name T555
Test name
Test status
Simulation time 820496147 ps
CPU time 21.41 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 220180 kb
Host smart-98e246ef-c836-4878-a7ae-cd4ff9fcea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042983318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2042983318
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3106978225
Short name T363
Test name
Test status
Simulation time 247369876 ps
CPU time 2.06 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 209376 kb
Host smart-cd1feb88-2477-4cad-b17d-4f51a3a35074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106978225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3106978225
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4177719260
Short name T5
Test name
Test status
Simulation time 3245959727 ps
CPU time 26.85 seconds
Started Feb 25 02:41:44 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 222472 kb
Host smart-4abc8b70-aa16-4871-926a-6865027bb099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177719260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4177719260
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.998870706
Short name T606
Test name
Test status
Simulation time 824722051 ps
CPU time 4.81 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:50 PM PST 24
Peak memory 209696 kb
Host smart-9f5693f2-5a28-401e-beb1-7508906521bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998870706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.998870706
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.732308283
Short name T855
Test name
Test status
Simulation time 336116463 ps
CPU time 3.74 seconds
Started Feb 25 02:41:36 PM PST 24
Finished Feb 25 02:41:40 PM PST 24
Peak memory 208564 kb
Host smart-0ac14f26-c5c8-49bb-bd36-2c959b8a8148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732308283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.732308283
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.639388715
Short name T391
Test name
Test status
Simulation time 628720293 ps
CPU time 5.95 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:55 PM PST 24
Peak memory 208624 kb
Host smart-c7470d2a-b9dc-46c2-a5f5-29a6100887e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639388715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.639388715
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.999329812
Short name T129
Test name
Test status
Simulation time 44407430 ps
CPU time 1.97 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:47 PM PST 24
Peak memory 206536 kb
Host smart-4f3fd47c-bb21-4983-9ec6-3bf4fbc95c24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999329812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.999329812
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.4284291113
Short name T846
Test name
Test status
Simulation time 12617037928 ps
CPU time 17.98 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 207600 kb
Host smart-94163318-3542-42be-b479-c34049d9b7e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284291113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4284291113
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3918405738
Short name T196
Test name
Test status
Simulation time 453481605 ps
CPU time 2.89 seconds
Started Feb 25 02:41:50 PM PST 24
Finished Feb 25 02:41:53 PM PST 24
Peak memory 215100 kb
Host smart-393ddac9-e989-4985-9791-89bf5b9cab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918405738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3918405738
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1214211562
Short name T618
Test name
Test status
Simulation time 127656092 ps
CPU time 3.13 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 208100 kb
Host smart-1c733ced-f82a-4077-8e60-95b617af707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214211562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1214211562
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2378165753
Short name T804
Test name
Test status
Simulation time 35607154 ps
CPU time 2.72 seconds
Started Feb 25 02:41:51 PM PST 24
Finished Feb 25 02:41:54 PM PST 24
Peak memory 207204 kb
Host smart-cacfdd0d-c91d-477b-a3f0-4b2280f51d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378165753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2378165753
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1117953852
Short name T560
Test name
Test status
Simulation time 113692458 ps
CPU time 2.06 seconds
Started Feb 25 02:41:50 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 209648 kb
Host smart-13ebf1d8-f3e3-4584-9367-b0d008719f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117953852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1117953852
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4271338628
Short name T409
Test name
Test status
Simulation time 75684087 ps
CPU time 0.91 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:47 PM PST 24
Peak memory 205828 kb
Host smart-89e73d56-f04a-4380-afb8-1905ab870b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271338628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4271338628
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3754329731
Short name T778
Test name
Test status
Simulation time 364758968 ps
CPU time 2.77 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 207780 kb
Host smart-d6042988-bdb0-4bec-b9de-3d002439f593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754329731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3754329731
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.789064367
Short name T353
Test name
Test status
Simulation time 973450073 ps
CPU time 7.53 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:56 PM PST 24
Peak memory 208404 kb
Host smart-acaac454-9382-4dff-95cb-66aced42d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789064367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.789064367
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.970545613
Short name T729
Test name
Test status
Simulation time 199461780 ps
CPU time 3.15 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 207488 kb
Host smart-8d97cd50-3fc4-46ff-adc1-c42708a6d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970545613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.970545613
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.305072238
Short name T297
Test name
Test status
Simulation time 542351663 ps
CPU time 4.81 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:53 PM PST 24
Peak memory 209400 kb
Host smart-381be5df-7c80-4346-a8b0-9b8a9f2d7d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305072238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.305072238
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2417066844
Short name T194
Test name
Test status
Simulation time 48748373 ps
CPU time 2.72 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 206720 kb
Host smart-efcd16cb-b8ff-4cfd-aee7-3c869ede33eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417066844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2417066844
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2401807835
Short name T372
Test name
Test status
Simulation time 170679067 ps
CPU time 2.44 seconds
Started Feb 25 02:41:51 PM PST 24
Finished Feb 25 02:41:54 PM PST 24
Peak memory 206504 kb
Host smart-9e29112b-cac0-476d-be67-3b29174f7cef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401807835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2401807835
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.136244242
Short name T463
Test name
Test status
Simulation time 233733264 ps
CPU time 3.19 seconds
Started Feb 25 02:41:52 PM PST 24
Finished Feb 25 02:41:55 PM PST 24
Peak memory 208280 kb
Host smart-0366a051-51b8-46b5-a799-4669b72dbbb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136244242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.136244242
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.956650823
Short name T533
Test name
Test status
Simulation time 1153551901 ps
CPU time 3.66 seconds
Started Feb 25 02:41:44 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 208232 kb
Host smart-9ae7d16b-d58d-4dbe-8448-8c03b1d5ff7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956650823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.956650823
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3430236990
Short name T632
Test name
Test status
Simulation time 725625934 ps
CPU time 2.9 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 206836 kb
Host smart-32b8ceb5-dd92-4d39-9afd-3eb0bda08f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430236990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3430236990
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2270121981
Short name T389
Test name
Test status
Simulation time 100575385 ps
CPU time 2.67 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 206320 kb
Host smart-3e4feff7-0b14-4ec0-b80e-ddb832e7d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270121981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2270121981
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2147126104
Short name T191
Test name
Test status
Simulation time 3338221392 ps
CPU time 27.58 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:42:13 PM PST 24
Peak memory 216752 kb
Host smart-d5271471-040c-4295-8c7c-5d92fbb6c72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147126104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2147126104
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.169182716
Short name T767
Test name
Test status
Simulation time 1143120356 ps
CPU time 12.05 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 222432 kb
Host smart-7df12ee3-4c49-446c-a32a-4acc17d714ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169182716 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.169182716
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1933574249
Short name T318
Test name
Test status
Simulation time 139596905 ps
CPU time 3.03 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 207568 kb
Host smart-2d49b391-6f8a-46d7-a356-9d507be13b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933574249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1933574249
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.94848818
Short name T136
Test name
Test status
Simulation time 225166509 ps
CPU time 2.72 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:48 PM PST 24
Peak memory 210216 kb
Host smart-07bfd4b7-6f5e-4294-b75a-1c95829cd581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94848818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.94848818
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.931291508
Short name T871
Test name
Test status
Simulation time 48117815 ps
CPU time 0.77 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:02 PM PST 24
Peak memory 205828 kb
Host smart-65d98177-cab2-407a-9c47-0b2889a64ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931291508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.931291508
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.991038616
Short name T369
Test name
Test status
Simulation time 257024794 ps
CPU time 4.42 seconds
Started Feb 25 02:41:45 PM PST 24
Finished Feb 25 02:41:49 PM PST 24
Peak memory 214156 kb
Host smart-2e7f32dc-24fb-461d-bbb1-05a7ec210220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991038616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.991038616
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4130339192
Short name T55
Test name
Test status
Simulation time 351462250 ps
CPU time 4.56 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 209076 kb
Host smart-18f21242-9bdf-4ed0-a6ab-cb58afc66ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130339192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4130339192
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.434894264
Short name T87
Test name
Test status
Simulation time 169721221 ps
CPU time 5.85 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 214248 kb
Host smart-4865ba48-b0fc-409a-9669-ed87d7fb0907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434894264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.434894264
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.966601402
Short name T838
Test name
Test status
Simulation time 368826367 ps
CPU time 6.99 seconds
Started Feb 25 02:41:46 PM PST 24
Finished Feb 25 02:41:53 PM PST 24
Peak memory 211264 kb
Host smart-08e13a61-c192-40ae-8acc-2f258977d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966601402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.966601402
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.2610126100
Short name T663
Test name
Test status
Simulation time 1945239049 ps
CPU time 12.04 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 209036 kb
Host smart-42e3ca31-21d1-4fd5-aeca-34ba9b290ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610126100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2610126100
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4009322846
Short name T877
Test name
Test status
Simulation time 3392010473 ps
CPU time 65.01 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:42:52 PM PST 24
Peak memory 208232 kb
Host smart-3250220b-33d9-4ae2-ae7f-8308c7c329f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009322846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4009322846
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2327408645
Short name T534
Test name
Test status
Simulation time 977027413 ps
CPU time 14.54 seconds
Started Feb 25 02:41:51 PM PST 24
Finished Feb 25 02:42:06 PM PST 24
Peak memory 207740 kb
Host smart-82dbbd7f-9f34-4286-a8f5-962b8090a81c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327408645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2327408645
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3222647247
Short name T698
Test name
Test status
Simulation time 361644282 ps
CPU time 5.53 seconds
Started Feb 25 02:41:47 PM PST 24
Finished Feb 25 02:41:53 PM PST 24
Peak memory 208356 kb
Host smart-fe2e650e-94d2-4800-b07d-11a793323375
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222647247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3222647247
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.162681612
Short name T473
Test name
Test status
Simulation time 825066511 ps
CPU time 3.14 seconds
Started Feb 25 02:41:48 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 208536 kb
Host smart-7b2311d2-ec03-40cd-bf42-27e4a1ebcc9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162681612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.162681612
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4038055792
Short name T878
Test name
Test status
Simulation time 116113582 ps
CPU time 5.32 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 209964 kb
Host smart-e1c407a6-a0ff-4563-a38c-ecbf1b28bf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038055792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4038055792
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.450082774
Short name T766
Test name
Test status
Simulation time 59788160 ps
CPU time 2.72 seconds
Started Feb 25 02:41:49 PM PST 24
Finished Feb 25 02:41:52 PM PST 24
Peak memory 206456 kb
Host smart-0054d065-016d-4d49-8616-54e50ac04459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450082774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.450082774
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3153619380
Short name T620
Test name
Test status
Simulation time 78069348 ps
CPU time 4.07 seconds
Started Feb 25 02:41:51 PM PST 24
Finished Feb 25 02:41:55 PM PST 24
Peak memory 207140 kb
Host smart-4bdc4cd7-23f3-4b6b-ad24-d680eb5a127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153619380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3153619380
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.423751187
Short name T479
Test name
Test status
Simulation time 590024908 ps
CPU time 9.74 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:11 PM PST 24
Peak memory 210816 kb
Host smart-e5206a0a-00ed-47e4-8fc1-b416b2870199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423751187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.423751187
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.35894560
Short name T783
Test name
Test status
Simulation time 14449532 ps
CPU time 0.91 seconds
Started Feb 25 02:41:56 PM PST 24
Finished Feb 25 02:41:57 PM PST 24
Peak memory 206016 kb
Host smart-ca25f624-284d-4d0d-bd06-6fde0d920db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.35894560
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2500023405
Short name T787
Test name
Test status
Simulation time 236742984 ps
CPU time 5.59 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 221760 kb
Host smart-02ff5c09-8eb8-4466-ab03-288545e6c6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500023405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2500023405
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.222299628
Short name T633
Test name
Test status
Simulation time 257104341 ps
CPU time 2.19 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:56 PM PST 24
Peak memory 207028 kb
Host smart-b0d00ab4-6a22-47f8-bddc-0c83db9105cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222299628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.222299628
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.352565786
Short name T725
Test name
Test status
Simulation time 54054595 ps
CPU time 3.06 seconds
Started Feb 25 02:41:56 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 220232 kb
Host smart-79d0d003-0b36-4c28-83ee-f4d7e3bfbb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352565786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.352565786
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2341885000
Short name T187
Test name
Test status
Simulation time 491244260 ps
CPU time 5.33 seconds
Started Feb 25 02:41:55 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 214188 kb
Host smart-6ef5e13c-0408-47d8-899e-018a58b968ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341885000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2341885000
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1853570144
Short name T825
Test name
Test status
Simulation time 31887810 ps
CPU time 2.05 seconds
Started Feb 25 02:41:53 PM PST 24
Finished Feb 25 02:41:56 PM PST 24
Peak memory 214148 kb
Host smart-7b8ff4b7-45d6-44aa-b290-27c701ab02cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853570144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1853570144
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3419848522
Short name T387
Test name
Test status
Simulation time 157964245 ps
CPU time 4.09 seconds
Started Feb 25 02:41:58 PM PST 24
Finished Feb 25 02:42:02 PM PST 24
Peak memory 208640 kb
Host smart-9d4f51aa-16a0-48b3-bdab-9ee1ac93c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419848522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3419848522
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2413269660
Short name T246
Test name
Test status
Simulation time 751901001 ps
CPU time 2.87 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 208484 kb
Host smart-4408eaa0-b748-4df2-a6a2-798c259d5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413269660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2413269660
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3529471227
Short name T447
Test name
Test status
Simulation time 1494352949 ps
CPU time 8.23 seconds
Started Feb 25 02:41:52 PM PST 24
Finished Feb 25 02:42:01 PM PST 24
Peak memory 207668 kb
Host smart-d05f1f0f-c5f9-46ff-b3e5-9776c5b2b8c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529471227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3529471227
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2950710491
Short name T872
Test name
Test status
Simulation time 56724152 ps
CPU time 2.95 seconds
Started Feb 25 02:41:55 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 206520 kb
Host smart-93055e78-02e1-47d6-a8cc-659e6842f3a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950710491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2950710491
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1948774568
Short name T655
Test name
Test status
Simulation time 90043762 ps
CPU time 2.89 seconds
Started Feb 25 02:41:56 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 206412 kb
Host smart-f290a137-4323-4716-8b4b-d977753a8cb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948774568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1948774568
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.576491690
Short name T104
Test name
Test status
Simulation time 2603943139 ps
CPU time 10.53 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 208960 kb
Host smart-99250f0b-45a2-44b9-a37b-ddb2f9071f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576491690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.576491690
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3904372300
Short name T646
Test name
Test status
Simulation time 390507154 ps
CPU time 5.1 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:42:02 PM PST 24
Peak memory 206312 kb
Host smart-f8196a9e-aade-4050-a7ce-9d5fa6717dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904372300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3904372300
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1684793639
Short name T685
Test name
Test status
Simulation time 873270804 ps
CPU time 22.13 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:24 PM PST 24
Peak memory 222452 kb
Host smart-a168b96f-3975-4a49-b74d-d2172c14be3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684793639 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1684793639
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.650450102
Short name T721
Test name
Test status
Simulation time 102139989 ps
CPU time 4.81 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 209100 kb
Host smart-93ef6512-a721-42a4-902a-688ab0580911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650450102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.650450102
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.426149790
Short name T378
Test name
Test status
Simulation time 72381083 ps
CPU time 2.45 seconds
Started Feb 25 02:41:55 PM PST 24
Finished Feb 25 02:41:57 PM PST 24
Peak memory 210460 kb
Host smart-4a61f0fe-c0b2-405d-9282-d099c45e3448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426149790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.426149790
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.663731230
Short name T863
Test name
Test status
Simulation time 11613114 ps
CPU time 0.77 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:06 PM PST 24
Peak memory 205808 kb
Host smart-d1f2f9b3-d635-48d2-a80e-b0fbd336c0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663731230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.663731230
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4268320332
Short name T276
Test name
Test status
Simulation time 606841823 ps
CPU time 4.83 seconds
Started Feb 25 02:41:58 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 214160 kb
Host smart-066795cc-7c5d-4575-91f6-d240f5ec246b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268320332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4268320332
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2490716432
Short name T526
Test name
Test status
Simulation time 877788633 ps
CPU time 4.53 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 221832 kb
Host smart-b4602092-bf45-401e-988e-88c6ae551625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490716432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2490716432
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1619698034
Short name T797
Test name
Test status
Simulation time 46317622 ps
CPU time 1.8 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 206848 kb
Host smart-e3757c3a-4841-44be-8b11-693b427efdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619698034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1619698034
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4178877043
Short name T93
Test name
Test status
Simulation time 414639558 ps
CPU time 5.46 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 217404 kb
Host smart-6a978b23-22ab-42e5-8fdc-4d4f5f8f22bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178877043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4178877043
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3338925191
Short name T306
Test name
Test status
Simulation time 122321517 ps
CPU time 5.7 seconds
Started Feb 25 02:42:04 PM PST 24
Finished Feb 25 02:42:09 PM PST 24
Peak memory 214156 kb
Host smart-4f825931-e1b8-4d57-bfc9-364f2b8502b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338925191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3338925191
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2622105349
Short name T673
Test name
Test status
Simulation time 256526375 ps
CPU time 2.94 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 208956 kb
Host smart-9baa0caf-b1fb-453f-85c6-ce9d2f10e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622105349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2622105349
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2199489117
Short name T356
Test name
Test status
Simulation time 75454790 ps
CPU time 4.12 seconds
Started Feb 25 02:41:59 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 208432 kb
Host smart-8a4fbead-1faf-45c2-8762-0ee21d2ec11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199489117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2199489117
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3108712708
Short name T714
Test name
Test status
Simulation time 6787522261 ps
CPU time 50.2 seconds
Started Feb 25 02:41:58 PM PST 24
Finished Feb 25 02:42:49 PM PST 24
Peak memory 208288 kb
Host smart-18b8b60e-f5f8-428c-a3b3-8c65e9ad24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108712708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3108712708
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3560120366
Short name T247
Test name
Test status
Simulation time 247355031 ps
CPU time 3.35 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 206540 kb
Host smart-5c0f46cd-37d4-44a4-8404-e1d7c85596aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560120366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3560120366
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3305415253
Short name T709
Test name
Test status
Simulation time 537775634 ps
CPU time 7.88 seconds
Started Feb 25 02:42:08 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 208308 kb
Host smart-f89daa01-8e6e-46da-9b64-70af53f69518
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305415253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3305415253
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3530063487
Short name T730
Test name
Test status
Simulation time 52702181 ps
CPU time 1.83 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 209016 kb
Host smart-8988b94c-4823-4185-a9e2-7e788cb8d9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530063487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3530063487
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4275139146
Short name T894
Test name
Test status
Simulation time 295999022 ps
CPU time 3.16 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 207008 kb
Host smart-f523cf22-3ab3-4898-afda-3d88f1e24599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275139146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4275139146
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3571266784
Short name T807
Test name
Test status
Simulation time 203700204 ps
CPU time 4.7 seconds
Started Feb 25 02:41:55 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 207072 kb
Host smart-a783bb02-e93c-42f3-9450-ee796feda2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571266784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3571266784
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.245026239
Short name T380
Test name
Test status
Simulation time 54027400 ps
CPU time 2.38 seconds
Started Feb 25 02:41:56 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 209972 kb
Host smart-e7305378-9308-483e-8bd9-58ed4977f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245026239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.245026239
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3406257912
Short name T464
Test name
Test status
Simulation time 10539187 ps
CPU time 0.74 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 205812 kb
Host smart-3db5c661-c27d-47fe-9c24-7b48e37348ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406257912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3406257912
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3580688341
Short name T37
Test name
Test status
Simulation time 96514544 ps
CPU time 3.79 seconds
Started Feb 25 02:41:53 PM PST 24
Finished Feb 25 02:41:58 PM PST 24
Peak memory 218284 kb
Host smart-c7305741-f38c-4d5f-b860-e44cafc12bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580688341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3580688341
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4125456052
Short name T550
Test name
Test status
Simulation time 860104366 ps
CPU time 10.94 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:14 PM PST 24
Peak memory 218064 kb
Host smart-bdc853b9-692b-4c88-a7e3-42eef63721df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125456052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4125456052
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2633371723
Short name T784
Test name
Test status
Simulation time 109151764 ps
CPU time 3.61 seconds
Started Feb 25 02:41:56 PM PST 24
Finished Feb 25 02:42:00 PM PST 24
Peak memory 222300 kb
Host smart-6089737f-62c4-4438-b11f-c618a6a90e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633371723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2633371723
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4114357616
Short name T62
Test name
Test status
Simulation time 38285253 ps
CPU time 2.82 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:57 PM PST 24
Peak memory 220204 kb
Host smart-623b343f-899c-4567-bebe-c6eda47bce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114357616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4114357616
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4125181150
Short name T2
Test name
Test status
Simulation time 612905254 ps
CPU time 7.24 seconds
Started Feb 25 02:42:08 PM PST 24
Finished Feb 25 02:42:15 PM PST 24
Peak memory 207260 kb
Host smart-75cfa812-eb07-44a9-963a-386fcc80e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125181150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4125181150
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3267363124
Short name T272
Test name
Test status
Simulation time 276207581 ps
CPU time 4.18 seconds
Started Feb 25 02:42:09 PM PST 24
Finished Feb 25 02:42:13 PM PST 24
Peak memory 208352 kb
Host smart-87fe2241-98e0-40b3-b8da-0c191b2ddb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267363124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3267363124
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2504585015
Short name T233
Test name
Test status
Simulation time 139465055 ps
CPU time 5.22 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:42:02 PM PST 24
Peak memory 208396 kb
Host smart-a7aa5ef8-5e3b-4728-89b8-628d3e8ca262
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504585015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2504585015
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.339269941
Short name T790
Test name
Test status
Simulation time 277753245 ps
CPU time 3.51 seconds
Started Feb 25 02:41:59 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 208368 kb
Host smart-f706375c-7bd9-4325-a067-d50ba93176a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339269941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.339269941
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1177534280
Short name T518
Test name
Test status
Simulation time 166405145 ps
CPU time 3.71 seconds
Started Feb 25 02:41:59 PM PST 24
Finished Feb 25 02:42:03 PM PST 24
Peak memory 208248 kb
Host smart-a18877f9-647c-4274-ade6-a7f173d3e7c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177534280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1177534280
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2680823669
Short name T706
Test name
Test status
Simulation time 191863142 ps
CPU time 5.02 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:08 PM PST 24
Peak memory 208020 kb
Host smart-c836a0cb-0142-46cf-a29e-0f280b068a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680823669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2680823669
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3543065438
Short name T608
Test name
Test status
Simulation time 3072567555 ps
CPU time 5.75 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 208120 kb
Host smart-70afa2cd-a889-4c45-8a59-a9cea31b0ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543065438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3543065438
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4119077651
Short name T776
Test name
Test status
Simulation time 772009181 ps
CPU time 12.11 seconds
Started Feb 25 02:42:00 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 219752 kb
Host smart-9f3ca898-367f-4adc-8a4e-b3133bc05f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119077651 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4119077651
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2577733296
Short name T482
Test name
Test status
Simulation time 117678221 ps
CPU time 5.92 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 208772 kb
Host smart-bd8a42d8-48ed-4849-986c-7d7690704e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577733296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2577733296
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1001020537
Short name T168
Test name
Test status
Simulation time 330027480 ps
CPU time 2.75 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:20 PM PST 24
Peak memory 210152 kb
Host smart-bac4b1c7-e831-4ecf-a2a3-8f7a985485cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001020537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1001020537
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.835462081
Short name T679
Test name
Test status
Simulation time 34187929 ps
CPU time 0.74 seconds
Started Feb 25 02:42:00 PM PST 24
Finished Feb 25 02:42:01 PM PST 24
Peak memory 205660 kb
Host smart-9a5dfad1-182f-4a92-9fdf-232ecc48f48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835462081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.835462081
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1452754016
Short name T594
Test name
Test status
Simulation time 124323366 ps
CPU time 2.58 seconds
Started Feb 25 02:42:07 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 215956 kb
Host smart-0650bd3f-50eb-4c56-8347-82b3da31a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452754016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1452754016
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2350457566
Short name T537
Test name
Test status
Simulation time 91932302 ps
CPU time 3.37 seconds
Started Feb 25 02:42:10 PM PST 24
Finished Feb 25 02:42:13 PM PST 24
Peak memory 218156 kb
Host smart-5e82ade1-efcf-4e30-8570-c9c7080aa707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350457566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2350457566
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4003996748
Short name T849
Test name
Test status
Simulation time 544550950 ps
CPU time 6.68 seconds
Started Feb 25 02:42:04 PM PST 24
Finished Feb 25 02:42:11 PM PST 24
Peak memory 214096 kb
Host smart-220dcf4e-e889-47f2-8d28-ad275b0b433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003996748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4003996748
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2337148718
Short name T304
Test name
Test status
Simulation time 552894772 ps
CPU time 5.43 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 209180 kb
Host smart-c738db80-84fb-48e1-af23-7d1086012e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337148718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2337148718
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.626677519
Short name T829
Test name
Test status
Simulation time 59594853 ps
CPU time 2.37 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 209612 kb
Host smart-ef6bf829-0de6-4e39-9233-165ab677a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626677519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.626677519
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1689998887
Short name T317
Test name
Test status
Simulation time 58296166 ps
CPU time 3.77 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:08 PM PST 24
Peak memory 222336 kb
Host smart-28ef1d66-1040-4d5c-97cf-fa348127bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689998887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1689998887
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1219747199
Short name T768
Test name
Test status
Simulation time 130367694 ps
CPU time 3.29 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:14 PM PST 24
Peak memory 206540 kb
Host smart-583cd5da-28aa-46e4-a8fc-92f35664e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219747199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1219747199
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.171167850
Short name T830
Test name
Test status
Simulation time 68475511 ps
CPU time 2.94 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:18 PM PST 24
Peak memory 206436 kb
Host smart-cf986a4d-7a6d-41bd-9e9a-6ed57db72c40
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171167850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.171167850
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3367592791
Short name T802
Test name
Test status
Simulation time 81624879 ps
CPU time 3.89 seconds
Started Feb 25 02:41:54 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 208588 kb
Host smart-efcc2fa0-c2cc-4467-91fa-f08af89bec07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367592791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3367592791
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3971531023
Short name T800
Test name
Test status
Simulation time 71713221 ps
CPU time 3.39 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:18 PM PST 24
Peak memory 206552 kb
Host smart-4d07929b-76c9-4bba-bdee-7a95c8b5ce6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971531023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3971531023
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3903682447
Short name T664
Test name
Test status
Simulation time 1832381561 ps
CPU time 16.16 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 207868 kb
Host smart-c88f1ab3-92a3-4d88-876c-28fc2c7bdeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903682447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3903682447
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3375681892
Short name T413
Test name
Test status
Simulation time 85308681 ps
CPU time 1.94 seconds
Started Feb 25 02:41:57 PM PST 24
Finished Feb 25 02:41:59 PM PST 24
Peak memory 206544 kb
Host smart-92c98c97-3d00-4837-bcd9-425a6bcb33cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375681892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3375681892
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2613785927
Short name T676
Test name
Test status
Simulation time 125100269 ps
CPU time 5.39 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 209032 kb
Host smart-e2b89236-b363-4df3-a208-1a17db1c0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613785927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2613785927
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1169029827
Short name T573
Test name
Test status
Simulation time 72818471 ps
CPU time 2.79 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:20 PM PST 24
Peak memory 209528 kb
Host smart-e959927a-3a98-4c63-ba44-d751270580cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169029827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1169029827
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3316846546
Short name T809
Test name
Test status
Simulation time 13733939 ps
CPU time 0.88 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:18 PM PST 24
Peak memory 205888 kb
Host smart-d221f6b2-24d6-456b-9fba-cc6eb2d8b7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316846546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3316846546
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1527293667
Short name T360
Test name
Test status
Simulation time 292391192 ps
CPU time 3.36 seconds
Started Feb 25 02:42:06 PM PST 24
Finished Feb 25 02:42:09 PM PST 24
Peak memory 214860 kb
Host smart-b39b5b41-6d42-4acb-a2dc-b7228da50067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527293667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1527293667
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1003330358
Short name T499
Test name
Test status
Simulation time 143675715 ps
CPU time 2.55 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 218068 kb
Host smart-6f2c92f5-292e-4b39-9060-88e098db5142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003330358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1003330358
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1458074006
Short name T886
Test name
Test status
Simulation time 264627676 ps
CPU time 5.11 seconds
Started Feb 25 02:42:06 PM PST 24
Finished Feb 25 02:42:11 PM PST 24
Peak memory 209012 kb
Host smart-c3311908-363b-4395-a19e-98b2e40e898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458074006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1458074006
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3792852557
Short name T92
Test name
Test status
Simulation time 106173258 ps
CPU time 4.8 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 209500 kb
Host smart-62b2bb6a-1d1b-4815-88c6-abec82ed8561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792852557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3792852557
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3976192343
Short name T300
Test name
Test status
Simulation time 153239153 ps
CPU time 4.4 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 214140 kb
Host smart-312ee4df-5443-423c-aa06-2f3917cad8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976192343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3976192343
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2115113576
Short name T746
Test name
Test status
Simulation time 90228619 ps
CPU time 4 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 222456 kb
Host smart-2096550c-c621-4986-b130-65aac78485bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115113576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2115113576
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2927746201
Short name T190
Test name
Test status
Simulation time 57166131 ps
CPU time 3.76 seconds
Started Feb 25 02:42:00 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 214772 kb
Host smart-838475f1-5749-46ab-9745-e12f867460ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927746201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2927746201
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.766374047
Short name T559
Test name
Test status
Simulation time 117612586 ps
CPU time 2.48 seconds
Started Feb 25 02:42:17 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 207604 kb
Host smart-bfc8837f-b43c-4c28-beed-e90d3cbf8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766374047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.766374047
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1077217603
Short name T425
Test name
Test status
Simulation time 22717991 ps
CPU time 1.97 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:14 PM PST 24
Peak memory 207032 kb
Host smart-9f70ea1f-0141-44fe-9da3-c84dc2436db1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077217603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1077217603
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1519488103
Short name T850
Test name
Test status
Simulation time 857473171 ps
CPU time 7.45 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 208136 kb
Host smart-084043e7-eb67-4311-8d7b-20c0ae827df2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519488103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1519488103
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3758198574
Short name T619
Test name
Test status
Simulation time 156418129 ps
CPU time 2.26 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 206528 kb
Host smart-cdb4e84c-ced8-4e2b-b8ba-dc75cee8846b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758198574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3758198574
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.373600458
Short name T453
Test name
Test status
Simulation time 104489617 ps
CPU time 3.57 seconds
Started Feb 25 02:42:05 PM PST 24
Finished Feb 25 02:42:09 PM PST 24
Peak memory 208432 kb
Host smart-259b6814-8fe8-4cb4-b3ec-f8e50e8b26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373600458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.373600458
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1199479443
Short name T134
Test name
Test status
Simulation time 3082080320 ps
CPU time 31.85 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:48 PM PST 24
Peak memory 207648 kb
Host smart-09179eb0-8339-49c3-9f16-f9f89cb9544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199479443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1199479443
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3700484031
Short name T126
Test name
Test status
Simulation time 406131916 ps
CPU time 16.59 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 220288 kb
Host smart-097a41a1-a5ad-48ab-b473-cb7074f07f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700484031 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3700484031
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3066638135
Short name T819
Test name
Test status
Simulation time 82690932 ps
CPU time 4.18 seconds
Started Feb 25 02:42:08 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 207524 kb
Host smart-994f4f2f-e1b9-4149-b521-74c27b063ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066638135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3066638135
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.241446289
Short name T866
Test name
Test status
Simulation time 39209418 ps
CPU time 1.93 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 209352 kb
Host smart-3e45351c-e6c1-4612-9083-2e41e1df9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241446289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.241446289
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2961812479
Short name T675
Test name
Test status
Simulation time 16922947 ps
CPU time 0.9 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:15 PM PST 24
Peak memory 205948 kb
Host smart-9f679246-627d-4482-a231-66f4699f3ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961812479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2961812479
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1630332535
Short name T221
Test name
Test status
Simulation time 34151147 ps
CPU time 2.6 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 214128 kb
Host smart-b24fa19b-c580-469d-9cb5-cd3f15d366f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630332535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1630332535
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3829581371
Short name T211
Test name
Test status
Simulation time 393167351 ps
CPU time 2.96 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:14 PM PST 24
Peak memory 216628 kb
Host smart-ac36b017-4ac7-43d6-a2c7-e3f3a611a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829581371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3829581371
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1426766491
Short name T755
Test name
Test status
Simulation time 1112998091 ps
CPU time 3.62 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 206748 kb
Host smart-c794b718-7992-4917-970e-6ecb5b62698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426766491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1426766491
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.233690111
Short name T383
Test name
Test status
Simulation time 137824922 ps
CPU time 5.81 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 221404 kb
Host smart-2cc23b30-8ed0-42f0-b31b-c4da2515bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233690111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.233690111
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2772025073
Short name T672
Test name
Test status
Simulation time 53565349 ps
CPU time 3.37 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 208596 kb
Host smart-df932174-47f0-4103-93c5-0f683166cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772025073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2772025073
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2758434576
Short name T51
Test name
Test status
Simulation time 676531281 ps
CPU time 5.07 seconds
Started Feb 25 02:42:00 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 209764 kb
Host smart-469e7960-1035-40b0-94f1-4aafca5e2dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758434576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2758434576
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3352653933
Short name T275
Test name
Test status
Simulation time 104011325 ps
CPU time 3.8 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 214212 kb
Host smart-c43e8ce1-1b1e-4098-8578-1c4c092ccc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352653933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3352653933
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1898708647
Short name T294
Test name
Test status
Simulation time 960882011 ps
CPU time 29.7 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 208216 kb
Host smart-bb446f81-02ea-4f37-9517-bcd59944450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898708647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1898708647
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.357093946
Short name T629
Test name
Test status
Simulation time 224518634 ps
CPU time 6.54 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 207608 kb
Host smart-b1f8454b-b6c2-4dc9-acf0-4d0d3dd70352
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357093946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.357093946
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3851275581
Short name T131
Test name
Test status
Simulation time 294105157 ps
CPU time 3.77 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:20 PM PST 24
Peak memory 208088 kb
Host smart-b53bb293-f4a6-416d-9284-d42a974d504c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851275581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3851275581
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1522961766
Short name T264
Test name
Test status
Simulation time 103667898 ps
CPU time 3.96 seconds
Started Feb 25 02:42:09 PM PST 24
Finished Feb 25 02:42:13 PM PST 24
Peak memory 208476 kb
Host smart-ef657e11-62a8-4657-b55c-5390a624326f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522961766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1522961766
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2098475812
Short name T437
Test name
Test status
Simulation time 342095138 ps
CPU time 2.75 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:06 PM PST 24
Peak memory 214248 kb
Host smart-4a496067-e5b8-43fa-83f7-38b7f5c19683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098475812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2098475812
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.179496393
Short name T422
Test name
Test status
Simulation time 246259280 ps
CPU time 5.74 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:23 PM PST 24
Peak memory 207848 kb
Host smart-ec087497-c665-43ef-a743-ffc73e8a70ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179496393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.179496393
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.26199700
Short name T215
Test name
Test status
Simulation time 987564191 ps
CPU time 28.22 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:43 PM PST 24
Peak memory 215260 kb
Host smart-ac5f757f-44c4-40c4-b5f1-1587a8c77081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26199700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.26199700
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3461393353
Short name T760
Test name
Test status
Simulation time 186026913 ps
CPU time 10.92 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:23 PM PST 24
Peak memory 222380 kb
Host smart-7103c20f-6aed-4222-ab20-8179a4fd55be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461393353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3461393353
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.730602320
Short name T596
Test name
Test status
Simulation time 281709750 ps
CPU time 6.44 seconds
Started Feb 25 02:42:06 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 206772 kb
Host smart-455647d8-799e-4c2d-b4c9-6ba81ce4509c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730602320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.730602320
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2192157400
Short name T379
Test name
Test status
Simulation time 115064016 ps
CPU time 2.89 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 209772 kb
Host smart-e3ceea9e-de30-4e67-ad44-8d7650f7e5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192157400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2192157400
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1822932306
Short name T502
Test name
Test status
Simulation time 39229547 ps
CPU time 0.75 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:15 PM PST 24
Peak memory 205888 kb
Host smart-187cef8e-307e-49ba-a93c-d6e77a0f6a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822932306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1822932306
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1338416950
Short name T403
Test name
Test status
Simulation time 76776829 ps
CPU time 4.75 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 214740 kb
Host smart-499520ce-2948-4c42-a1b5-9d8cd596261a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338416950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1338416950
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.14068135
Short name T500
Test name
Test status
Simulation time 173229166 ps
CPU time 3.22 seconds
Started Feb 25 02:42:13 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 221576 kb
Host smart-68323af3-039d-43e1-888e-66e2d868b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14068135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.14068135
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2806786751
Short name T635
Test name
Test status
Simulation time 146652825 ps
CPU time 3.51 seconds
Started Feb 25 02:42:01 PM PST 24
Finished Feb 25 02:42:05 PM PST 24
Peak memory 214080 kb
Host smart-da8ab9cf-c0fa-4428-9b0d-dd45c7648d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806786751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2806786751
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3914581954
Short name T248
Test name
Test status
Simulation time 120901019 ps
CPU time 2.67 seconds
Started Feb 25 02:42:15 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 208812 kb
Host smart-76149f0b-5d51-4df7-a371-86e8cabb2642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914581954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3914581954
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.47075610
Short name T90
Test name
Test status
Simulation time 296320464 ps
CPU time 10.81 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:25 PM PST 24
Peak memory 222304 kb
Host smart-e0b39677-fc6a-49c3-ba03-eb025f2a2a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47075610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.47075610
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1871755995
Short name T668
Test name
Test status
Simulation time 155785180 ps
CPU time 6.32 seconds
Started Feb 25 02:42:10 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 220064 kb
Host smart-13c05f34-410c-4c7a-925d-8f8831db5f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871755995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1871755995
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3173875417
Short name T588
Test name
Test status
Simulation time 343050391 ps
CPU time 3.61 seconds
Started Feb 25 02:42:06 PM PST 24
Finished Feb 25 02:42:10 PM PST 24
Peak memory 218024 kb
Host smart-ee7b9598-a269-45a8-96b0-b8a3d41289cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173875417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3173875417
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.908704943
Short name T292
Test name
Test status
Simulation time 314668584 ps
CPU time 2.8 seconds
Started Feb 25 02:42:03 PM PST 24
Finished Feb 25 02:42:06 PM PST 24
Peak memory 206428 kb
Host smart-f3230e86-b2b8-48ff-8016-a7e122873b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908704943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.908704943
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1531869442
Short name T535
Test name
Test status
Simulation time 424429162 ps
CPU time 5.14 seconds
Started Feb 25 02:41:59 PM PST 24
Finished Feb 25 02:42:04 PM PST 24
Peak memory 208452 kb
Host smart-6dbf2ddc-2af6-404f-a9c2-462b41e2cf4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531869442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1531869442
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1049203783
Short name T873
Test name
Test status
Simulation time 390872797 ps
CPU time 3.91 seconds
Started Feb 25 02:42:12 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 206504 kb
Host smart-c231da71-0a7f-4fd3-bd91-de9fd2312478
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049203783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1049203783
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1029582171
Short name T677
Test name
Test status
Simulation time 6606266599 ps
CPU time 17.03 seconds
Started Feb 25 02:42:08 PM PST 24
Finished Feb 25 02:42:25 PM PST 24
Peak memory 208652 kb
Host smart-24bf745b-f3d0-4bf3-8130-775994f620cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029582171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1029582171
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2883394767
Short name T255
Test name
Test status
Simulation time 82238067 ps
CPU time 3.19 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:25 PM PST 24
Peak memory 214204 kb
Host smart-a8bcef0f-7af8-4cba-b088-dccd8f941137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883394767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2883394767
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1439169537
Short name T510
Test name
Test status
Simulation time 146419003 ps
CPU time 4.52 seconds
Started Feb 25 02:42:02 PM PST 24
Finished Feb 25 02:42:07 PM PST 24
Peak memory 207504 kb
Host smart-8110c49d-f626-4ec2-8ad8-cd0b4049ecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439169537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1439169537
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3065942809
Short name T480
Test name
Test status
Simulation time 646226461 ps
CPU time 5.42 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 207696 kb
Host smart-1fa25720-a080-4ab7-a1c2-73c9e036c2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065942809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3065942809
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1412840051
Short name T517
Test name
Test status
Simulation time 414259632 ps
CPU time 3.05 seconds
Started Feb 25 02:42:21 PM PST 24
Finished Feb 25 02:42:25 PM PST 24
Peak memory 210016 kb
Host smart-0829f641-91e3-4b49-9f19-079be19be90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412840051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1412840051
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1624003338
Short name T415
Test name
Test status
Simulation time 26625172 ps
CPU time 0.74 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 205904 kb
Host smart-3e7f7604-1cad-4557-94c2-3eb47dd5ad1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624003338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1624003338
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.556196585
Short name T138
Test name
Test status
Simulation time 429032149 ps
CPU time 3.97 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 214208 kb
Host smart-c258ebca-16f2-4a00-aa77-620c302f75c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556196585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.556196585
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3046403875
Short name T752
Test name
Test status
Simulation time 116418360 ps
CPU time 4.55 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 214300 kb
Host smart-db3b0253-5f40-4bfd-9969-c7d7449cde92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046403875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3046403875
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.922906041
Short name T772
Test name
Test status
Simulation time 196760432 ps
CPU time 4.24 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 208500 kb
Host smart-81b05024-0d42-4afd-aec8-126f1b0151cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922906041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.922906041
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.849017039
Short name T103
Test name
Test status
Simulation time 259898558 ps
CPU time 7.72 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:30 PM PST 24
Peak memory 214168 kb
Host smart-f775ceaa-68c1-4c4e-a211-1eecb11cb81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849017039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.849017039
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.627203565
Short name T212
Test name
Test status
Simulation time 72624685 ps
CPU time 2.91 seconds
Started Feb 25 02:40:19 PM PST 24
Finished Feb 25 02:40:22 PM PST 24
Peak memory 209288 kb
Host smart-3290a7e7-af88-4b27-8787-fcdcada4b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627203565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.627203565
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3861570467
Short name T638
Test name
Test status
Simulation time 291749999 ps
CPU time 4.1 seconds
Started Feb 25 02:40:21 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 206692 kb
Host smart-1b20734a-16bd-4adf-938a-167ea71b00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861570467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3861570467
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3916702947
Short name T495
Test name
Test status
Simulation time 126638477 ps
CPU time 4.02 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 208400 kb
Host smart-967302a2-7901-4874-aeb0-8cf20df011aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916702947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3916702947
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1622120914
Short name T99
Test name
Test status
Simulation time 50186593 ps
CPU time 2.67 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:25 PM PST 24
Peak memory 208488 kb
Host smart-3aea541f-6e5a-440d-a796-13574afe41de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622120914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1622120914
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3352930710
Short name T740
Test name
Test status
Simulation time 372309435 ps
CPU time 3.61 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 208632 kb
Host smart-1a8ec916-14fa-4023-be50-857ec9f537f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352930710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3352930710
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1083329429
Short name T823
Test name
Test status
Simulation time 8223018416 ps
CPU time 60.39 seconds
Started Feb 25 02:40:18 PM PST 24
Finished Feb 25 02:41:18 PM PST 24
Peak memory 207632 kb
Host smart-360662da-0719-4bf8-a4b9-190712bc33eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083329429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1083329429
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1315199298
Short name T599
Test name
Test status
Simulation time 300982515 ps
CPU time 3.72 seconds
Started Feb 25 02:40:26 PM PST 24
Finished Feb 25 02:40:29 PM PST 24
Peak memory 208932 kb
Host smart-9893c231-21e3-4e39-848e-6d2d2bdbcbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315199298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1315199298
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.772660269
Short name T386
Test name
Test status
Simulation time 56442498 ps
CPU time 2.91 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:25 PM PST 24
Peak memory 206804 kb
Host smart-2354d1ef-a090-4124-a667-994412f546eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772660269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.772660269
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1202830655
Short name T558
Test name
Test status
Simulation time 110887361386 ps
CPU time 659.91 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:51:24 PM PST 24
Peak memory 220564 kb
Host smart-d97041db-c4c2-4542-ac92-c8050eb733cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202830655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1202830655
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.523112565
Short name T747
Test name
Test status
Simulation time 334871221 ps
CPU time 5.98 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:29 PM PST 24
Peak memory 207072 kb
Host smart-3d1dddbd-0aac-48cf-856a-7cab84353041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523112565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.523112565
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1847561528
Short name T643
Test name
Test status
Simulation time 467308551 ps
CPU time 3.44 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 210200 kb
Host smart-d2372a0f-9232-4f11-9ac9-178f598ac1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847561528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1847561528
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.24043610
Short name T905
Test name
Test status
Simulation time 20664849 ps
CPU time 0.76 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:15 PM PST 24
Peak memory 205816 kb
Host smart-ebf17d72-64c5-44f5-baa8-743a12874fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.24043610
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3661675396
Short name T137
Test name
Test status
Simulation time 87959967 ps
CPU time 3.43 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:25 PM PST 24
Peak memory 214948 kb
Host smart-2f7d9f13-750b-4cf3-88a4-b5a1e74e4096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661675396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3661675396
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1754033212
Short name T63
Test name
Test status
Simulation time 94197598 ps
CPU time 2.69 seconds
Started Feb 25 02:42:17 PM PST 24
Finished Feb 25 02:42:20 PM PST 24
Peak memory 209856 kb
Host smart-23536fce-4a91-4a28-af32-18ef82f3e7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754033212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1754033212
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1288027991
Short name T515
Test name
Test status
Simulation time 184121789 ps
CPU time 5.32 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 216020 kb
Host smart-cd8ca7f3-9849-48fc-9731-830440e32aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288027991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1288027991
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3717202395
Short name T261
Test name
Test status
Simulation time 445703596 ps
CPU time 5.93 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 209596 kb
Host smart-22c24194-3a6d-459f-b5f5-ac67f0b126fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717202395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3717202395
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.156865551
Short name T446
Test name
Test status
Simulation time 279301300 ps
CPU time 3.55 seconds
Started Feb 25 02:42:17 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 215512 kb
Host smart-5e90e554-4dbf-4d2e-a2ce-271dbb99bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156865551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.156865551
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2789837233
Short name T597
Test name
Test status
Simulation time 231461272 ps
CPU time 9.77 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:21 PM PST 24
Peak memory 209452 kb
Host smart-c51122db-3728-418f-a5b8-2efadf3c2d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789837233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2789837233
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2749363804
Short name T84
Test name
Test status
Simulation time 684568643 ps
CPU time 22 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 207356 kb
Host smart-1f18624d-9fa3-4901-b7cf-e1a535ba3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749363804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2749363804
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.917214722
Short name T707
Test name
Test status
Simulation time 918448096 ps
CPU time 10.69 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 207452 kb
Host smart-763a575a-7d3e-4d37-87a1-e07301b32e1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917214722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.917214722
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.460648652
Short name T491
Test name
Test status
Simulation time 257658323 ps
CPU time 7 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:22 PM PST 24
Peak memory 208320 kb
Host smart-49cd321e-ddaa-4f10-ac57-5c442eee2bad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460648652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.460648652
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1778638265
Short name T451
Test name
Test status
Simulation time 2105849138 ps
CPU time 15.78 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 208368 kb
Host smart-d1542104-cc03-418b-8eba-d41e42be4835
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778638265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1778638265
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1073845782
Short name T426
Test name
Test status
Simulation time 706482623 ps
CPU time 15.57 seconds
Started Feb 25 02:42:13 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 209392 kb
Host smart-af892d2a-4848-4f46-93fc-8f3ecd51dea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073845782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1073845782
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.556882623
Short name T891
Test name
Test status
Simulation time 1530908008 ps
CPU time 3.81 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 208304 kb
Host smart-ddc89e7d-8ab2-4937-b2ff-dc3b0cf9d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556882623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.556882623
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2125718795
Short name T310
Test name
Test status
Simulation time 41425343733 ps
CPU time 740.05 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:54:42 PM PST 24
Peak memory 230652 kb
Host smart-01a59cea-4ec0-4c40-9c34-a591cbc29f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125718795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2125718795
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1843486410
Short name T125
Test name
Test status
Simulation time 311103377 ps
CPU time 11.7 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:35 PM PST 24
Peak memory 222200 kb
Host smart-5df485b0-90d3-4e80-9f13-9004257071a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843486410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1843486410
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3773801871
Short name T324
Test name
Test status
Simulation time 607604874 ps
CPU time 4.88 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 218308 kb
Host smart-8e3ac79a-3db4-4687-801b-e7619d6c2464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773801871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3773801871
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.918934433
Short name T848
Test name
Test status
Simulation time 171645658 ps
CPU time 4.36 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:19 PM PST 24
Peak memory 209832 kb
Host smart-104a3ba0-ecee-49a3-8f47-5a4b94cdfe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918934433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.918934433
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.633666431
Short name T692
Test name
Test status
Simulation time 106406080 ps
CPU time 0.8 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 205884 kb
Host smart-6654891a-2eae-4136-acd4-fd72b417d6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633666431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.633666431
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3636864219
Short name T402
Test name
Test status
Simulation time 67345610 ps
CPU time 4.5 seconds
Started Feb 25 02:42:16 PM PST 24
Finished Feb 25 02:42:20 PM PST 24
Peak memory 214216 kb
Host smart-3da86d18-b1ec-4a56-9d54-3bdcb03d09ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636864219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3636864219
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4030673945
Short name T880
Test name
Test status
Simulation time 649220038 ps
CPU time 2.98 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:26 PM PST 24
Peak memory 217932 kb
Host smart-64d385c8-cba3-4c0d-b780-454c44be269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030673945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4030673945
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1734520209
Short name T329
Test name
Test status
Simulation time 97189549 ps
CPU time 3.24 seconds
Started Feb 25 02:42:13 PM PST 24
Finished Feb 25 02:42:16 PM PST 24
Peak memory 209008 kb
Host smart-039b2aec-43bc-4fc3-a728-36dd460e5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734520209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1734520209
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3321749008
Short name T754
Test name
Test status
Simulation time 260536105 ps
CPU time 7.3 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:29 PM PST 24
Peak memory 214128 kb
Host smart-e6c58ee2-0575-4ff0-83e4-441a3cc1c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321749008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3321749008
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4151061055
Short name T43
Test name
Test status
Simulation time 483162203 ps
CPU time 3.65 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:18 PM PST 24
Peak memory 209720 kb
Host smart-57a8c6c9-d357-4ddc-9735-1e34a32d354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151061055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4151061055
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2031341737
Short name T78
Test name
Test status
Simulation time 219982577 ps
CPU time 5.93 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 209536 kb
Host smart-e98cb141-2668-47d4-98e9-5dc5ed88e9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031341737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2031341737
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3044913101
Short name T691
Test name
Test status
Simulation time 434383141 ps
CPU time 16.4 seconds
Started Feb 25 02:42:17 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 207944 kb
Host smart-d75c715b-1e18-4e50-8432-e4337c6755a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044913101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3044913101
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3061924417
Short name T552
Test name
Test status
Simulation time 277718159 ps
CPU time 3.61 seconds
Started Feb 25 02:42:13 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 208444 kb
Host smart-b2c251b9-1242-403b-907c-00ae0a0a5b70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061924417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3061924417
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.703476199
Short name T267
Test name
Test status
Simulation time 772925724 ps
CPU time 3.48 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:17 PM PST 24
Peak memory 208372 kb
Host smart-b3ed3f0e-d35d-4806-ab8b-fd5f9ac5002a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703476199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.703476199
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4294459295
Short name T770
Test name
Test status
Simulation time 1198260338 ps
CPU time 7.71 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 207592 kb
Host smart-67fc99ae-b126-4bd1-b81f-9ecb2f9ad46d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294459295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4294459295
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3896878429
Short name T309
Test name
Test status
Simulation time 115582057 ps
CPU time 4.79 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 215656 kb
Host smart-8f5957c2-490b-4e73-aa50-9f24e867968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896878429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3896878429
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2148903784
Short name T492
Test name
Test status
Simulation time 371647040 ps
CPU time 2.9 seconds
Started Feb 25 02:42:11 PM PST 24
Finished Feb 25 02:42:14 PM PST 24
Peak memory 206720 kb
Host smart-a1fb771d-e1d7-4d1e-9107-b3a3759ee819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148903784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2148903784
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.683753743
Short name T896
Test name
Test status
Simulation time 299962196 ps
CPU time 8.22 seconds
Started Feb 25 02:42:14 PM PST 24
Finished Feb 25 02:42:23 PM PST 24
Peak memory 207948 kb
Host smart-fc4ee2da-c546-48e7-9e3d-dcb71cb4db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683753743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.683753743
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4141572743
Short name T186
Test name
Test status
Simulation time 79360095 ps
CPU time 2.65 seconds
Started Feb 25 02:42:23 PM PST 24
Finished Feb 25 02:42:26 PM PST 24
Peak memory 209664 kb
Host smart-7c4cf98d-06b3-4af8-a431-2719425e4b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141572743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4141572743
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2767713401
Short name T523
Test name
Test status
Simulation time 9045414 ps
CPU time 0.83 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 205884 kb
Host smart-a7b02956-31c1-435c-9ac5-912609102278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767713401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2767713401
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2198788044
Short name T21
Test name
Test status
Simulation time 241461847 ps
CPU time 2.76 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:29 PM PST 24
Peak memory 218600 kb
Host smart-6e131497-459f-49aa-8316-a27a069e6dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198788044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2198788044
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2235333752
Short name T58
Test name
Test status
Simulation time 82551536 ps
CPU time 3.14 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 219500 kb
Host smart-d1dcff61-553b-4887-b644-8c271ac20e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235333752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2235333752
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.617744355
Short name T365
Test name
Test status
Simulation time 229531284 ps
CPU time 3.98 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 220480 kb
Host smart-69465734-56bd-42fe-b517-51a40efbdd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617744355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.617744355
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.918717020
Short name T263
Test name
Test status
Simulation time 533446766 ps
CPU time 3.54 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 211156 kb
Host smart-b5b0d8b0-72e2-4e22-81ae-3d7b9c7f71e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918717020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.918717020
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.203428876
Short name T644
Test name
Test status
Simulation time 414862007 ps
CPU time 4.04 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:29 PM PST 24
Peak memory 209372 kb
Host smart-c5333494-553e-4585-a1e5-d83d0939345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203428876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.203428876
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1302734213
Short name T913
Test name
Test status
Simulation time 86541917 ps
CPU time 4.51 seconds
Started Feb 25 02:42:28 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 209052 kb
Host smart-c302707f-81bd-4d1c-af01-7a1e2a0b19f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302734213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1302734213
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.116254286
Short name T647
Test name
Test status
Simulation time 1260217168 ps
CPU time 17.86 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:44 PM PST 24
Peak memory 208052 kb
Host smart-034e435f-f823-408b-bdd1-5cf1acf48289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116254286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.116254286
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2880651247
Short name T508
Test name
Test status
Simulation time 301405762 ps
CPU time 3.58 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 208544 kb
Host smart-0334a708-9cbc-4d97-bf17-54cbb45f4b4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880651247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2880651247
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4243495199
Short name T735
Test name
Test status
Simulation time 119677213 ps
CPU time 5.04 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 208224 kb
Host smart-9f69a93f-69b4-42d0-a3ab-883f266ee8f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243495199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4243495199
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2995137058
Short name T465
Test name
Test status
Simulation time 116811592 ps
CPU time 3.71 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 207040 kb
Host smart-d665d72b-602c-48ab-ae57-c0705d08c745
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995137058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2995137058
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1739508060
Short name T576
Test name
Test status
Simulation time 445988724 ps
CPU time 12.32 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 222308 kb
Host smart-bbc9d603-9f82-4b86-90b8-60c51f111884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739508060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1739508060
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2144796356
Short name T530
Test name
Test status
Simulation time 83807337 ps
CPU time 1.63 seconds
Started Feb 25 02:42:10 PM PST 24
Finished Feb 25 02:42:12 PM PST 24
Peak memory 206472 kb
Host smart-ad0200cc-89cb-49b2-bb0d-667ac09a3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144796356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2144796356
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1614902019
Short name T286
Test name
Test status
Simulation time 1108949322 ps
CPU time 23.23 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:48 PM PST 24
Peak memory 222288 kb
Host smart-ba79b180-ef83-4fb2-adc3-d3289068aa38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614902019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1614902019
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3538095097
Short name T268
Test name
Test status
Simulation time 237641005 ps
CPU time 3.98 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:42:37 PM PST 24
Peak memory 210004 kb
Host smart-2ab6c896-0a5b-456d-84e4-c4d93756e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538095097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3538095097
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1487880107
Short name T524
Test name
Test status
Simulation time 73663210 ps
CPU time 2.8 seconds
Started Feb 25 02:42:31 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 209800 kb
Host smart-2b3b2d69-b9b1-4764-b576-98fa12544e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487880107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1487880107
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3760288697
Short name T733
Test name
Test status
Simulation time 14798372 ps
CPU time 0.77 seconds
Started Feb 25 02:42:31 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 205816 kb
Host smart-8fc3d87e-4272-4398-a1b7-f7df87ac3d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760288697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3760288697
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.779734045
Short name T870
Test name
Test status
Simulation time 151138687 ps
CPU time 1.58 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 207964 kb
Host smart-70881489-5d08-4077-a436-907208174984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779734045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.779734045
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1346538879
Short name T748
Test name
Test status
Simulation time 72596563 ps
CPU time 2.75 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 209648 kb
Host smart-4fd9560a-d0f8-480e-9af5-6efe5e3073d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346538879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1346538879
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1162312847
Short name T779
Test name
Test status
Simulation time 307543796 ps
CPU time 9.59 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:36 PM PST 24
Peak memory 210324 kb
Host smart-49dd2052-3e18-4ca7-9838-24869ec19196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162312847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1162312847
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2976502258
Short name T384
Test name
Test status
Simulation time 254097489 ps
CPU time 2.7 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 208136 kb
Host smart-3c17f2fe-193a-4fb3-a9e4-7d09a15eb26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976502258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2976502258
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2565524994
Short name T269
Test name
Test status
Simulation time 665929661 ps
CPU time 6.89 seconds
Started Feb 25 02:42:34 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 207584 kb
Host smart-b9ad254b-0464-4cef-9601-e6f2b07a594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565524994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2565524994
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4148057955
Short name T690
Test name
Test status
Simulation time 350805312 ps
CPU time 4.45 seconds
Started Feb 25 02:42:24 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 206584 kb
Host smart-f49b079f-5e34-4aa1-9215-ff28688e6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148057955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4148057955
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.364867683
Short name T761
Test name
Test status
Simulation time 233451727 ps
CPU time 2.89 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 208288 kb
Host smart-d4e5d154-d420-4d04-9c97-8f6ae1dfec68
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364867683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.364867683
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2954445437
Short name T738
Test name
Test status
Simulation time 30099033 ps
CPU time 2.25 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:29 PM PST 24
Peak memory 208568 kb
Host smart-4ad95324-dc30-4ca9-a18e-75a0385325da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954445437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2954445437
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2344902476
Short name T516
Test name
Test status
Simulation time 112139324 ps
CPU time 2.77 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 207676 kb
Host smart-ab38db64-93a2-4d00-84fb-b13066387cfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344902476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2344902476
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.913620583
Short name T687
Test name
Test status
Simulation time 270719626 ps
CPU time 2.02 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 206932 kb
Host smart-9650c844-b96b-48e4-91f4-346f88ee7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913620583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.913620583
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1808283801
Short name T888
Test name
Test status
Simulation time 705496297 ps
CPU time 5.44 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 206228 kb
Host smart-e917c555-f88b-4b06-a262-c37055325b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808283801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1808283801
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.367557806
Short name T100
Test name
Test status
Simulation time 2247144520 ps
CPU time 26.43 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 215560 kb
Host smart-f981019d-d088-4e91-afde-85c977e99497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367557806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.367557806
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1965295888
Short name T803
Test name
Test status
Simulation time 197345140 ps
CPU time 8.01 seconds
Started Feb 25 02:42:32 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 222452 kb
Host smart-7cced6e2-b117-4982-a7a0-d1f736e04a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965295888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1965295888
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4167274927
Short name T293
Test name
Test status
Simulation time 637976599 ps
CPU time 3.26 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 207532 kb
Host smart-f02f742e-65d0-4b2a-83e0-04eddd3471eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167274927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4167274927
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1645551900
Short name T416
Test name
Test status
Simulation time 822209737 ps
CPU time 5.67 seconds
Started Feb 25 02:42:32 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 210048 kb
Host smart-bd3daa7c-56f3-4311-ace9-649592f8f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645551900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1645551900
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2516912650
Short name T79
Test name
Test status
Simulation time 33214812 ps
CPU time 0.93 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 206008 kb
Host smart-ee71b56f-9d74-4fcf-b401-9ecabf2a7b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516912650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2516912650
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1641293631
Short name T400
Test name
Test status
Simulation time 106338042 ps
CPU time 3.76 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 215012 kb
Host smart-9c6e392a-f882-42fe-889f-641fc5f74410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641293631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1641293631
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2607717641
Short name T19
Test name
Test status
Simulation time 346200973 ps
CPU time 3.74 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:42:26 PM PST 24
Peak memory 221188 kb
Host smart-a2d31d6d-99e0-4cef-bc8c-d14b2947f235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607717641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2607717641
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3819210944
Short name T762
Test name
Test status
Simulation time 377242726 ps
CPU time 3.57 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 208920 kb
Host smart-2544a47a-6b53-45ba-a522-a9ac9b556e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819210944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3819210944
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.910345946
Short name T86
Test name
Test status
Simulation time 266465845 ps
CPU time 6.26 seconds
Started Feb 25 02:42:32 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 218256 kb
Host smart-240366d3-911f-4d8f-ae2e-82d6ed7587f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910345946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.910345946
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2827568322
Short name T305
Test name
Test status
Simulation time 380807648 ps
CPU time 8.44 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:35 PM PST 24
Peak memory 214144 kb
Host smart-f6847275-24d7-40bf-8e54-94d068d01dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827568322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2827568322
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1169959576
Short name T339
Test name
Test status
Simulation time 397582387 ps
CPU time 2.97 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 220056 kb
Host smart-4e663eb2-9bce-4484-b6b2-270ea19cbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169959576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1169959576
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.105660655
Short name T731
Test name
Test status
Simulation time 176812302 ps
CPU time 6.82 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 209596 kb
Host smart-0139962b-c69e-490d-b92d-e839b3c6036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105660655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.105660655
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3824272969
Short name T617
Test name
Test status
Simulation time 115551827 ps
CPU time 4.26 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 206600 kb
Host smart-b81a2c96-ee2a-401c-bcde-28157df4159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824272969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3824272969
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1792570108
Short name T232
Test name
Test status
Simulation time 276728413 ps
CPU time 3.48 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 208368 kb
Host smart-0c5c003e-3368-4bb8-8bec-ab53bf8743de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792570108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1792570108
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1853203830
Short name T716
Test name
Test status
Simulation time 19650013 ps
CPU time 1.76 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 206520 kb
Host smart-392fdf8c-494a-4001-a950-343824e3f01f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853203830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1853203830
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2225162813
Short name T461
Test name
Test status
Simulation time 24930820 ps
CPU time 1.93 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:42:35 PM PST 24
Peak memory 206588 kb
Host smart-859b2c59-221f-4db9-bade-4e99a7c967e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225162813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2225162813
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.635775883
Short name T625
Test name
Test status
Simulation time 714799346 ps
CPU time 6.57 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 214164 kb
Host smart-6c563bdf-0ceb-46b5-9ae2-b988a9205e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635775883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.635775883
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.218898502
Short name T106
Test name
Test status
Simulation time 125868713 ps
CPU time 5.06 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 208276 kb
Host smart-d59bf1c7-db06-405e-bf86-32657ee521b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218898502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.218898502
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3530841640
Short name T702
Test name
Test status
Simulation time 6441160662 ps
CPU time 80.76 seconds
Started Feb 25 02:42:22 PM PST 24
Finished Feb 25 02:43:43 PM PST 24
Peak memory 216836 kb
Host smart-8c0f4a87-5e6c-4950-b650-e98ac5e5e2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530841640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3530841640
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.443795810
Short name T507
Test name
Test status
Simulation time 65791905 ps
CPU time 4.05 seconds
Started Feb 25 02:42:31 PM PST 24
Finished Feb 25 02:42:35 PM PST 24
Peak memory 207352 kb
Host smart-079ccacd-6322-4361-bf74-8b1e77721add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443795810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.443795810
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2719922059
Short name T48
Test name
Test status
Simulation time 102125600 ps
CPU time 3.95 seconds
Started Feb 25 02:42:24 PM PST 24
Finished Feb 25 02:42:28 PM PST 24
Peak memory 209832 kb
Host smart-a10f2518-94a3-4721-bb7b-b1068cb92b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719922059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2719922059
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4110372768
Short name T95
Test name
Test status
Simulation time 40441287 ps
CPU time 0.8 seconds
Started Feb 25 02:42:31 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 205896 kb
Host smart-985600e3-e36c-43f0-8f91-878d7eb3638d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110372768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4110372768
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1520584717
Short name T77
Test name
Test status
Simulation time 770575610 ps
CPU time 41.51 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:43:14 PM PST 24
Peak memory 214708 kb
Host smart-a492a898-b3b4-48be-a782-411bd41ff0bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520584717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1520584717
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1962295863
Short name T8
Test name
Test status
Simulation time 164431540 ps
CPU time 5.26 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 216720 kb
Host smart-68e8cbe1-6678-4c17-865a-67c4745069cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962295863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1962295863
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3555935215
Short name T662
Test name
Test status
Simulation time 32688404 ps
CPU time 1.61 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 209796 kb
Host smart-6a6689d5-f9b8-403b-81ee-43aa1f7cd311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555935215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3555935215
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3656028159
Short name T374
Test name
Test status
Simulation time 83324515 ps
CPU time 3.22 seconds
Started Feb 25 02:42:26 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 210044 kb
Host smart-b7917f81-b21a-482c-8a44-bf16ef3b5654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656028159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3656028159
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1320654273
Short name T609
Test name
Test status
Simulation time 227346982 ps
CPU time 4.7 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 208408 kb
Host smart-2e38eb9f-6239-49b9-a092-dd7f5c1c2317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320654273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1320654273
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.264251385
Short name T474
Test name
Test status
Simulation time 82963089 ps
CPU time 3.74 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 208324 kb
Host smart-0c0c3721-c30c-4733-83ec-75db8d165202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264251385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.264251385
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.573844832
Short name T441
Test name
Test status
Simulation time 3080133157 ps
CPU time 8.2 seconds
Started Feb 25 02:42:25 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 208720 kb
Host smart-aa8ea43b-84f3-4a96-810c-56d03aa9100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573844832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.573844832
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.818799957
Short name T420
Test name
Test status
Simulation time 220669816 ps
CPU time 2.46 seconds
Started Feb 25 02:42:28 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 206424 kb
Host smart-8b563ad4-3555-4f1d-952a-3db3caee5978
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818799957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.818799957
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.400175199
Short name T544
Test name
Test status
Simulation time 117775846 ps
CPU time 3.05 seconds
Started Feb 25 02:42:27 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 207772 kb
Host smart-0df9633a-d1b5-4240-a909-4b112a6768e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400175199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.400175199
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.403838507
Short name T536
Test name
Test status
Simulation time 50746864 ps
CPU time 2.72 seconds
Started Feb 25 02:42:24 PM PST 24
Finished Feb 25 02:42:27 PM PST 24
Peak memory 206652 kb
Host smart-54f52cde-42ca-4180-945e-9666fca789bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403838507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.403838507
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4081542984
Short name T399
Test name
Test status
Simulation time 315118967 ps
CPU time 2.7 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 208280 kb
Host smart-0040cdcc-0a2b-449b-b47f-8dc339a0afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081542984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4081542984
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1175934839
Short name T410
Test name
Test status
Simulation time 77117279 ps
CPU time 1.71 seconds
Started Feb 25 02:42:28 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 205936 kb
Host smart-369e7e19-c611-4cdf-bdf8-4427a036ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175934839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1175934839
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.267601225
Short name T392
Test name
Test status
Simulation time 791953264 ps
CPU time 12 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:42:50 PM PST 24
Peak memory 222528 kb
Host smart-6d8c78fa-6d65-4e04-89ed-caca9f137f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267601225 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.267601225
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2618659961
Short name T903
Test name
Test status
Simulation time 487983432 ps
CPU time 5.51 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:35 PM PST 24
Peak memory 214224 kb
Host smart-4ea65b4c-c8fb-4d75-8f92-dfd2de83bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618659961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2618659961
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1207122789
Short name T151
Test name
Test status
Simulation time 59027163 ps
CPU time 1.76 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 209284 kb
Host smart-998f1515-f557-4b97-9c63-dc55ff617bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207122789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1207122789
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1230101257
Short name T640
Test name
Test status
Simulation time 35509593 ps
CPU time 0.74 seconds
Started Feb 25 02:42:33 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 205860 kb
Host smart-25a6734e-f719-4350-a07b-9f1b553d485c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230101257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1230101257
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2963610194
Short name T26
Test name
Test status
Simulation time 104089784 ps
CPU time 3.93 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 222716 kb
Host smart-ef8d387a-c821-4ba9-9ae8-50bda73f74d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963610194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2963610194
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1310190332
Short name T607
Test name
Test status
Simulation time 74962628 ps
CPU time 2.07 seconds
Started Feb 25 02:42:40 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 209428 kb
Host smart-8e28bce4-8888-4cef-aba7-60ceb00d1c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310190332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1310190332
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.622922277
Short name T815
Test name
Test status
Simulation time 4660267090 ps
CPU time 66.01 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 214272 kb
Host smart-ff44bf3a-f7c2-489b-9b8a-21d4a34dcfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622922277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.622922277
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1529218965
Short name T565
Test name
Test status
Simulation time 53712541 ps
CPU time 1.83 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:31 PM PST 24
Peak memory 219488 kb
Host smart-c01d72fd-a951-4e97-9751-47f5a8651893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529218965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1529218965
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2096153503
Short name T694
Test name
Test status
Simulation time 455330588 ps
CPU time 5.74 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:42:44 PM PST 24
Peak memory 207080 kb
Host smart-138d78b5-de85-4d95-a42a-c2ca667620a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096153503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2096153503
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1199966157
Short name T201
Test name
Test status
Simulation time 47994598 ps
CPU time 2.71 seconds
Started Feb 25 02:42:29 PM PST 24
Finished Feb 25 02:42:32 PM PST 24
Peak memory 206356 kb
Host smart-4cab0088-8730-4715-8448-fb0f278e2041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199966157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1199966157
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.705175569
Short name T442
Test name
Test status
Simulation time 6450787935 ps
CPU time 27.25 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 208092 kb
Host smart-ea286e54-a343-4cb8-a010-8ba07863c2c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705175569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.705175569
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1806516534
Short name T648
Test name
Test status
Simulation time 202192392 ps
CPU time 6.14 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:43 PM PST 24
Peak memory 207592 kb
Host smart-c2b76827-2625-4e89-8701-3037f55b2d14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806516534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1806516534
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2621771230
Short name T511
Test name
Test status
Simulation time 366591848 ps
CPU time 3.41 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 208212 kb
Host smart-f0841064-6a38-4941-a79c-023f4e0720dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621771230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2621771230
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2549756455
Short name T653
Test name
Test status
Simulation time 128569755 ps
CPU time 3.27 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 207796 kb
Host smart-d84f6a92-4eb1-47a1-a3ff-c2a25ee0dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549756455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2549756455
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1763585359
Short name T130
Test name
Test status
Simulation time 105951554 ps
CPU time 2.83 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 207996 kb
Host smart-d7b82fec-bc82-480c-940d-2a2ce16fb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763585359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1763585359
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1690869049
Short name T340
Test name
Test status
Simulation time 3625516616 ps
CPU time 56.84 seconds
Started Feb 25 02:42:31 PM PST 24
Finished Feb 25 02:43:28 PM PST 24
Peak memory 222384 kb
Host smart-6ef5b3d9-6544-424d-803a-9a304ad05c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690869049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1690869049
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1655639434
Short name T227
Test name
Test status
Simulation time 433946971 ps
CPU time 4.08 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 209360 kb
Host smart-5c655241-64f4-4e89-98c7-ea9c527c8717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655639434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1655639434
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2800656012
Short name T407
Test name
Test status
Simulation time 25860158 ps
CPU time 0.83 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 205468 kb
Host smart-2c7f5c2f-214d-4356-8436-113ec9155b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800656012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2800656012
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1715670507
Short name T266
Test name
Test status
Simulation time 158850075 ps
CPU time 3.04 seconds
Started Feb 25 02:42:41 PM PST 24
Finished Feb 25 02:42:45 PM PST 24
Peak memory 214928 kb
Host smart-c0e22c12-2012-47ce-868f-4077b7a0d590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715670507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1715670507
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1874690020
Short name T54
Test name
Test status
Simulation time 116110334 ps
CPU time 2.8 seconds
Started Feb 25 02:42:40 PM PST 24
Finished Feb 25 02:42:43 PM PST 24
Peak memory 214204 kb
Host smart-0c50922a-1f55-44b3-9f46-5a6a0680a77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874690020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1874690020
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1129519096
Short name T834
Test name
Test status
Simulation time 730621770 ps
CPU time 12.7 seconds
Started Feb 25 02:42:40 PM PST 24
Finished Feb 25 02:42:58 PM PST 24
Peak memory 222152 kb
Host smart-be5e3dfa-6043-4566-b0bc-b56e7e271e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129519096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1129519096
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3769239197
Short name T649
Test name
Test status
Simulation time 39006145 ps
CPU time 2.65 seconds
Started Feb 25 02:42:34 PM PST 24
Finished Feb 25 02:42:37 PM PST 24
Peak memory 209304 kb
Host smart-08cba7cd-b129-4e28-94ec-88b6b28cac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769239197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3769239197
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2933820714
Short name T468
Test name
Test status
Simulation time 172839148 ps
CPU time 6.42 seconds
Started Feb 25 02:42:41 PM PST 24
Finished Feb 25 02:42:48 PM PST 24
Peak memory 207444 kb
Host smart-2685a829-38d3-4dda-8b14-d232f584abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933820714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2933820714
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1139386836
Short name T808
Test name
Test status
Simulation time 116104654 ps
CPU time 2.44 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 206476 kb
Host smart-cd4f35f4-7f2e-4c35-8026-dbd9b3e39fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139386836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1139386836
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.218548042
Short name T421
Test name
Test status
Simulation time 53022066 ps
CPU time 2.89 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:33 PM PST 24
Peak memory 207628 kb
Host smart-3cea33bf-b69a-48da-9a7f-b0268f239f4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218548042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.218548042
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.836608854
Short name T364
Test name
Test status
Simulation time 239215283 ps
CPU time 3.22 seconds
Started Feb 25 02:42:30 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 208148 kb
Host smart-cfa49cd4-c352-4681-bd71-bbdb2ed5ccf1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836608854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.836608854
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2997498945
Short name T899
Test name
Test status
Simulation time 8110406449 ps
CPU time 61.28 seconds
Started Feb 25 02:42:34 PM PST 24
Finished Feb 25 02:43:36 PM PST 24
Peak memory 208672 kb
Host smart-1c0cc497-da6f-493e-bde1-b37ced20d2d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997498945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2997498945
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1916543737
Short name T316
Test name
Test status
Simulation time 59364928 ps
CPU time 1.88 seconds
Started Feb 25 02:42:32 PM PST 24
Finished Feb 25 02:42:34 PM PST 24
Peak memory 207592 kb
Host smart-deb46d1f-ced8-46d4-8ce6-774342780a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916543737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1916543737
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3256693270
Short name T579
Test name
Test status
Simulation time 169635142 ps
CPU time 5.48 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:44 PM PST 24
Peak memory 207684 kb
Host smart-e546ad7a-b309-498b-995c-329117df0a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256693270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3256693270
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2968160390
Short name T756
Test name
Test status
Simulation time 1246228951 ps
CPU time 43.82 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:43:22 PM PST 24
Peak memory 214704 kb
Host smart-d657407a-b924-4a53-abd9-a481c1dd9038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968160390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2968160390
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.4123216111
Short name T176
Test name
Test status
Simulation time 518515824 ps
CPU time 18.32 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 220172 kb
Host smart-d7f713de-3ec4-4cbb-bf0a-fe9af3e70836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123216111 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.4123216111
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1800789104
Short name T674
Test name
Test status
Simulation time 1878032076 ps
CPU time 49.91 seconds
Started Feb 25 02:42:34 PM PST 24
Finished Feb 25 02:43:25 PM PST 24
Peak memory 214300 kb
Host smart-37398d68-3c0b-48e2-8861-34492b24ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800789104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1800789104
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.833067416
Short name T419
Test name
Test status
Simulation time 44554226 ps
CPU time 2.29 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 209592 kb
Host smart-615d326e-1c23-4e60-8bbc-57bce8b8d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833067416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.833067416
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3980831330
Short name T411
Test name
Test status
Simulation time 20990109 ps
CPU time 0.84 seconds
Started Feb 25 02:42:41 PM PST 24
Finished Feb 25 02:42:46 PM PST 24
Peak memory 205888 kb
Host smart-7629356f-8001-4122-b2c7-5cc3c12e5354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980831330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3980831330
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4167532738
Short name T225
Test name
Test status
Simulation time 90501493 ps
CPU time 4.65 seconds
Started Feb 25 02:42:41 PM PST 24
Finished Feb 25 02:42:46 PM PST 24
Peak memory 214880 kb
Host smart-fd825b5b-5966-4dc7-94a0-0c1b289c06a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167532738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4167532738
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3163654129
Short name T27
Test name
Test status
Simulation time 706763434 ps
CPU time 7.57 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:44 PM PST 24
Peak memory 214584 kb
Host smart-1f81a1ce-cad7-41be-92f2-cadeeeeed0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163654129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3163654129
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.339688072
Short name T520
Test name
Test status
Simulation time 166274386 ps
CPU time 3.02 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 209712 kb
Host smart-a3731e35-ba7a-43c2-b43d-41fc36370cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339688072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.339688072
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.101804670
Short name T572
Test name
Test status
Simulation time 617463686 ps
CPU time 3.61 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 222336 kb
Host smart-33de7b61-37e5-45d2-bc1c-fd4645eaea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101804670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.101804670
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.128710100
Short name T204
Test name
Test status
Simulation time 51037115 ps
CPU time 3.67 seconds
Started Feb 25 02:42:41 PM PST 24
Finished Feb 25 02:42:45 PM PST 24
Peak memory 209596 kb
Host smart-d91cf124-275e-4bb8-b417-19868b2115e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128710100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.128710100
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.477045088
Short name T343
Test name
Test status
Simulation time 149504594 ps
CPU time 7.09 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:46 PM PST 24
Peak memory 209840 kb
Host smart-807028b9-d7bb-46c4-b38b-fb58b00cb5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477045088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.477045088
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.762478938
Short name T822
Test name
Test status
Simulation time 527858324 ps
CPU time 4.47 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 208076 kb
Host smart-d287472c-6694-4ffc-8c9c-2ee331a4bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762478938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.762478938
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1711609459
Short name T910
Test name
Test status
Simulation time 147686208 ps
CPU time 3.15 seconds
Started Feb 25 02:42:34 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 208620 kb
Host smart-5af1be90-b5a8-43f7-9f1b-b513aac72964
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711609459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1711609459
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.45136376
Short name T737
Test name
Test status
Simulation time 503777873 ps
CPU time 7.76 seconds
Started Feb 25 02:42:32 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 207724 kb
Host smart-72436226-faf5-48d8-aca2-075c42c761d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45136376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.45136376
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4131972280
Short name T314
Test name
Test status
Simulation time 690897538 ps
CPU time 4.16 seconds
Started Feb 25 02:42:36 PM PST 24
Finished Feb 25 02:42:40 PM PST 24
Peak memory 208324 kb
Host smart-3c4c32a8-e6c8-4b09-ba53-b88435437211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131972280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4131972280
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2167829368
Short name T107
Test name
Test status
Simulation time 350737359 ps
CPU time 2.79 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 209676 kb
Host smart-b0cfef7b-865e-4755-bbaf-4a308e6791a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167829368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2167829368
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2066310938
Short name T433
Test name
Test status
Simulation time 229235910 ps
CPU time 3.24 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:38 PM PST 24
Peak memory 208144 kb
Host smart-a83b758e-b020-4f4e-b711-ca8ab06aad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066310938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2066310938
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3227306587
Short name T840
Test name
Test status
Simulation time 3087176943 ps
CPU time 21.17 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:58 PM PST 24
Peak memory 216396 kb
Host smart-66606553-0d0f-4918-84df-b8f4f9a63952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227306587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3227306587
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2061776281
Short name T175
Test name
Test status
Simulation time 1430693694 ps
CPU time 18.91 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:56 PM PST 24
Peak memory 219780 kb
Host smart-7c2a8397-a6fb-4935-8c9d-b34aa76f406d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061776281 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2061776281
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3525231585
Short name T571
Test name
Test status
Simulation time 57490106 ps
CPU time 3.93 seconds
Started Feb 25 02:42:35 PM PST 24
Finished Feb 25 02:42:39 PM PST 24
Peak memory 206588 kb
Host smart-679b9c73-e872-4e93-8762-eb5ad51dadd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525231585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3525231585
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.214113890
Short name T826
Test name
Test status
Simulation time 661002562 ps
CPU time 4.05 seconds
Started Feb 25 02:42:37 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 210148 kb
Host smart-bd953451-d3fc-4836-a280-dd90b8dd3064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214113890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.214113890
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3252255424
Short name T869
Test name
Test status
Simulation time 53115334 ps
CPU time 0.75 seconds
Started Feb 25 02:42:46 PM PST 24
Finished Feb 25 02:42:47 PM PST 24
Peak memory 205904 kb
Host smart-17159683-1734-4755-b3d2-b3d1c1d8eb13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252255424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3252255424
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1902578619
Short name T398
Test name
Test status
Simulation time 35730459 ps
CPU time 2.88 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:42:51 PM PST 24
Peak memory 214252 kb
Host smart-6141cb43-d843-488a-9c4f-e674cf00c7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902578619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1902578619
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4240639046
Short name T553
Test name
Test status
Simulation time 192402994 ps
CPU time 3.02 seconds
Started Feb 25 02:43:06 PM PST 24
Finished Feb 25 02:43:09 PM PST 24
Peak memory 221568 kb
Host smart-53e5d2e7-4923-4efa-b022-8d73a7bae1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240639046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4240639046
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1339935652
Short name T875
Test name
Test status
Simulation time 38065436 ps
CPU time 2.79 seconds
Started Feb 25 02:42:58 PM PST 24
Finished Feb 25 02:43:01 PM PST 24
Peak memory 209800 kb
Host smart-509c882e-2541-4487-8de2-c70d9d6df3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339935652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1339935652
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3572004242
Short name T23
Test name
Test status
Simulation time 765394447 ps
CPU time 5.64 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:55 PM PST 24
Peak memory 221832 kb
Host smart-fd699192-fa5f-47fb-b159-fc78990889d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572004242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3572004242
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.385391553
Short name T235
Test name
Test status
Simulation time 47273311 ps
CPU time 3.22 seconds
Started Feb 25 02:42:45 PM PST 24
Finished Feb 25 02:42:49 PM PST 24
Peak memory 214168 kb
Host smart-8a532d4d-10a8-4c69-868e-4eaeebc23006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385391553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.385391553
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2100261317
Short name T728
Test name
Test status
Simulation time 261089919 ps
CPU time 4.17 seconds
Started Feb 25 02:42:49 PM PST 24
Finished Feb 25 02:42:54 PM PST 24
Peak memory 214796 kb
Host smart-b451a982-08fc-4ca8-8d42-03816355e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100261317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2100261317
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3757722471
Short name T371
Test name
Test status
Simulation time 791368676 ps
CPU time 6.81 seconds
Started Feb 25 02:42:55 PM PST 24
Finished Feb 25 02:43:02 PM PST 24
Peak memory 208748 kb
Host smart-34fe044c-fbc0-433a-a8c2-e20687cc88a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757722471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3757722471
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3847697515
Short name T346
Test name
Test status
Simulation time 349744377 ps
CPU time 3.18 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 206420 kb
Host smart-722e05e8-fd8e-448f-8ce1-726279c0bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847697515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3847697515
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3251144791
Short name T487
Test name
Test status
Simulation time 285758877 ps
CPU time 3.8 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:42:57 PM PST 24
Peak memory 208188 kb
Host smart-9cda1b68-3ea1-4a6a-82de-eab36d9d28cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251144791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3251144791
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.891652837
Short name T418
Test name
Test status
Simulation time 199079670 ps
CPU time 2.96 seconds
Started Feb 25 02:42:38 PM PST 24
Finished Feb 25 02:42:41 PM PST 24
Peak memory 206568 kb
Host smart-fd51fdfa-06fa-4177-a3ae-9668072731b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891652837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.891652837
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4241289022
Short name T581
Test name
Test status
Simulation time 23481198666 ps
CPU time 35.85 seconds
Started Feb 25 02:42:54 PM PST 24
Finished Feb 25 02:43:30 PM PST 24
Peak memory 208612 kb
Host smart-89544330-d52d-4a1b-b5a8-89021bc77534
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241289022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4241289022
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1739933019
Short name T527
Test name
Test status
Simulation time 102364053 ps
CPU time 4.65 seconds
Started Feb 25 02:42:48 PM PST 24
Finished Feb 25 02:42:53 PM PST 24
Peak memory 210008 kb
Host smart-6265af9d-5aaa-4af6-80fa-5723221c895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739933019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1739933019
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3933613705
Short name T16
Test name
Test status
Simulation time 54011433 ps
CPU time 2.87 seconds
Started Feb 25 02:42:39 PM PST 24
Finished Feb 25 02:42:42 PM PST 24
Peak memory 207832 kb
Host smart-878196fb-3d04-4fa6-8d04-ae996dbd1755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933613705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3933613705
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3732346128
Short name T845
Test name
Test status
Simulation time 2330614155 ps
CPU time 22.38 seconds
Started Feb 25 02:42:55 PM PST 24
Finished Feb 25 02:43:18 PM PST 24
Peak memory 220752 kb
Host smart-a51083ac-41a6-4d35-9155-d7c2bd60bf52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732346128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3732346128
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3164096818
Short name T177
Test name
Test status
Simulation time 268533203 ps
CPU time 11.96 seconds
Started Feb 25 02:42:53 PM PST 24
Finished Feb 25 02:43:05 PM PST 24
Peak memory 218152 kb
Host smart-00ed4caf-bdf4-44c1-a44c-6fb1f0cb6c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164096818 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3164096818
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3395467757
Short name T243
Test name
Test status
Simulation time 263556941 ps
CPU time 4.79 seconds
Started Feb 25 02:43:05 PM PST 24
Finished Feb 25 02:43:10 PM PST 24
Peak memory 214120 kb
Host smart-65df5bf9-1442-45b7-abd4-a7d6fbb49ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395467757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3395467757
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3173374734
Short name T540
Test name
Test status
Simulation time 28122001 ps
CPU time 0.78 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 205892 kb
Host smart-51c6f5db-792c-4b70-bc28-46bfd6aaf3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173374734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3173374734
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.15432324
Short name T393
Test name
Test status
Simulation time 335996367 ps
CPU time 5.21 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:29 PM PST 24
Peak memory 214256 kb
Host smart-9c12fedf-d376-4720-acb5-96bab7f6c6ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15432324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.15432324
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.38153712
Short name T650
Test name
Test status
Simulation time 37275527 ps
CPU time 2.35 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 214240 kb
Host smart-8a203001-c4ef-43a5-8a82-8dab9f96f0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38153712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.38153712
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1574743868
Short name T17
Test name
Test status
Simulation time 217903430 ps
CPU time 2.64 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 207092 kb
Host smart-befc0481-2503-48e3-b50a-c8ff36ef8357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574743868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1574743868
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.594379891
Short name T25
Test name
Test status
Simulation time 175340537 ps
CPU time 4.09 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 208624 kb
Host smart-e51e926e-d651-4dbc-8e72-2ac31d690640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594379891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.594379891
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4217346404
Short name T900
Test name
Test status
Simulation time 243868217 ps
CPU time 3.37 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 208236 kb
Host smart-a658f35b-3557-4ac7-a6a7-41d955aa0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217346404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4217346404
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2081040459
Short name T488
Test name
Test status
Simulation time 62104192 ps
CPU time 3.06 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 208376 kb
Host smart-3068047d-8b33-4172-80f8-a4f31a85753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081040459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2081040459
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.700411921
Short name T291
Test name
Test status
Simulation time 37986923 ps
CPU time 2.11 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 208276 kb
Host smart-6ee3ed8c-e9cf-43c7-a80c-1a028d9f7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700411921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.700411921
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3252096755
Short name T501
Test name
Test status
Simulation time 65035071 ps
CPU time 2.96 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 206556 kb
Host smart-8821001b-3bf0-45c7-8e30-63b1c0802802
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252096755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3252096755
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.712483536
Short name T806
Test name
Test status
Simulation time 6116436794 ps
CPU time 42.57 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:41:06 PM PST 24
Peak memory 207988 kb
Host smart-13af4429-2c55-45e1-95fe-939e7c2985d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712483536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.712483536
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3703631476
Short name T820
Test name
Test status
Simulation time 469568001 ps
CPU time 5.3 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 206616 kb
Host smart-9db8f99f-6d67-4d8f-a0a5-272d09cde783
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703631476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3703631476
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3492154019
Short name T522
Test name
Test status
Simulation time 5104936542 ps
CPU time 16.81 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:39 PM PST 24
Peak memory 208740 kb
Host smart-7b9f5cab-d914-472c-9117-2e087f76715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492154019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3492154019
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.573644643
Short name T582
Test name
Test status
Simulation time 223993285 ps
CPU time 3.16 seconds
Started Feb 25 02:40:19 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 206520 kb
Host smart-f3adc87c-bbe4-47c1-9e46-156bd02b553d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573644643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.573644643
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2083740383
Short name T193
Test name
Test status
Simulation time 32929367878 ps
CPU time 419.72 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:47:23 PM PST 24
Peak memory 222484 kb
Host smart-bf47d073-69b4-4663-8644-b6b797b04322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083740383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2083740383
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2609478695
Short name T764
Test name
Test status
Simulation time 134881568 ps
CPU time 6.11 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:30 PM PST 24
Peak memory 222456 kb
Host smart-33b376f9-b3e6-4085-9c4a-3ff16cc703a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609478695 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2609478695
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.177016342
Short name T788
Test name
Test status
Simulation time 131121940 ps
CPU time 2.45 seconds
Started Feb 25 02:40:22 PM PST 24
Finished Feb 25 02:40:25 PM PST 24
Peak memory 207056 kb
Host smart-4103fb24-1fa4-41be-907a-f4afc9282832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177016342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.177016342
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.934415112
Short name T853
Test name
Test status
Simulation time 1311802301 ps
CPU time 2.55 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 210032 kb
Host smart-7ca5f867-e2b7-4a66-bb89-a787070d0ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934415112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.934415112
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3296936998
Short name T547
Test name
Test status
Simulation time 41879471 ps
CPU time 0.86 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 205808 kb
Host smart-ce419836-fe31-4c37-95fd-88bc1a610608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296936998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3296936998
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.382480405
Short name T358
Test name
Test status
Simulation time 61027931 ps
CPU time 4.47 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 215188 kb
Host smart-366dbc50-b418-4a77-ae37-b6f2ec12cf5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382480405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.382480405
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3268942688
Short name T203
Test name
Test status
Simulation time 17922028308 ps
CPU time 66.52 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:41:38 PM PST 24
Peak memory 222828 kb
Host smart-abaf8946-bb1f-4450-afb5-1f0b851342dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268942688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3268942688
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2161985847
Short name T884
Test name
Test status
Simulation time 3060475151 ps
CPU time 27.79 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:51 PM PST 24
Peak memory 208636 kb
Host smart-76ad004e-ae4e-4f6f-b76b-37bef0a0a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161985847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2161985847
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3365546084
Short name T331
Test name
Test status
Simulation time 212060456 ps
CPU time 4.82 seconds
Started Feb 25 02:40:27 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 222240 kb
Host smart-b1b1aebb-5286-4cde-ab75-1f464f762500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365546084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3365546084
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.78692258
Short name T210
Test name
Test status
Simulation time 96596142 ps
CPU time 3.06 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:32 PM PST 24
Peak memory 214248 kb
Host smart-e0af5a6a-404e-4da4-895e-b8157dd6f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78692258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.78692258
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.682346625
Short name T234
Test name
Test status
Simulation time 158219179 ps
CPU time 3.71 seconds
Started Feb 25 02:40:19 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 208364 kb
Host smart-a8cbe444-f1c7-4cdd-bf0f-d193010dc532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682346625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.682346625
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3055055397
Short name T856
Test name
Test status
Simulation time 2987698367 ps
CPU time 5.03 seconds
Started Feb 25 02:40:19 PM PST 24
Finished Feb 25 02:40:25 PM PST 24
Peak memory 207532 kb
Host smart-92dbebb0-f5bf-4a7e-8bf6-d72b63fb1c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055055397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3055055397
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2803671444
Short name T699
Test name
Test status
Simulation time 380440602 ps
CPU time 4.58 seconds
Started Feb 25 02:40:23 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 208308 kb
Host smart-742d9435-2c56-4ced-84a8-9737888bf415
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803671444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2803671444
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.481746895
Short name T466
Test name
Test status
Simulation time 209175046 ps
CPU time 5.39 seconds
Started Feb 25 02:40:20 PM PST 24
Finished Feb 25 02:40:26 PM PST 24
Peak memory 207772 kb
Host smart-8e8fce8d-644e-4661-a8d5-1d75e28a5e8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481746895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.481746895
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.693284958
Short name T429
Test name
Test status
Simulation time 50068098 ps
CPU time 2.81 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 206084 kb
Host smart-fee6af76-9f32-4c97-930e-a557321274fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693284958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.693284958
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3815149217
Short name T454
Test name
Test status
Simulation time 103391515 ps
CPU time 2.92 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 218164 kb
Host smart-e34b540e-36ba-44f7-9120-09e26d269660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815149217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3815149217
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3659854417
Short name T83
Test name
Test status
Simulation time 480879078 ps
CPU time 4.81 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 206336 kb
Host smart-c4a5c0c5-ba9f-4e93-8668-f2ee7bc26602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659854417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3659854417
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.439886449
Short name T503
Test name
Test status
Simulation time 69441996 ps
CPU time 2.93 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 208176 kb
Host smart-7e261642-182b-4b7c-879e-be6a6729582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439886449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.439886449
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1702428392
Short name T56
Test name
Test status
Simulation time 187075378 ps
CPU time 3.73 seconds
Started Feb 25 02:40:29 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 210064 kb
Host smart-42e6dac6-a487-42e0-a7ec-b4d900177b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702428392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1702428392
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1481844992
Short name T575
Test name
Test status
Simulation time 20101879 ps
CPU time 0.9 seconds
Started Feb 25 02:40:33 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 205880 kb
Host smart-6ec47c0c-faf7-47a4-916f-29306322fc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481844992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1481844992
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1802700069
Short name T325
Test name
Test status
Simulation time 476425492 ps
CPU time 13.16 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:42 PM PST 24
Peak memory 222312 kb
Host smart-011a1f91-3b09-4165-a8e2-be582cdf396d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802700069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1802700069
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4151430252
Short name T490
Test name
Test status
Simulation time 466760250 ps
CPU time 15.54 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:44 PM PST 24
Peak memory 214200 kb
Host smart-80b1f6e2-08db-440c-9a6f-c265bdb2e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151430252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4151430252
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3377524169
Short name T308
Test name
Test status
Simulation time 481939541 ps
CPU time 5.74 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 210328 kb
Host smart-97a7e009-0ae2-4cf2-a306-74f9d6387a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377524169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3377524169
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.722994947
Short name T459
Test name
Test status
Simulation time 171577669 ps
CPU time 4.56 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:41 PM PST 24
Peak memory 208196 kb
Host smart-30030abb-90ee-4092-8170-3458b2ebc333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722994947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.722994947
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3146384322
Short name T15
Test name
Test status
Simulation time 180990058 ps
CPU time 5.42 seconds
Started Feb 25 02:40:41 PM PST 24
Finished Feb 25 02:40:46 PM PST 24
Peak memory 208880 kb
Host smart-b36b7ed4-86a8-4d38-82df-f6301d279d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146384322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3146384322
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.522294807
Short name T839
Test name
Test status
Simulation time 67607554 ps
CPU time 3.08 seconds
Started Feb 25 02:40:26 PM PST 24
Finished Feb 25 02:40:30 PM PST 24
Peak memory 206412 kb
Host smart-65f33819-2bb3-4c7b-a865-17c730ced512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522294807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.522294807
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1382800204
Short name T703
Test name
Test status
Simulation time 1503490583 ps
CPU time 46.96 seconds
Started Feb 25 02:40:34 PM PST 24
Finished Feb 25 02:41:21 PM PST 24
Peak memory 207648 kb
Host smart-f9a5fac7-c630-4e6e-92bd-b7252bc6c452
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382800204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1382800204
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2985483765
Short name T242
Test name
Test status
Simulation time 1959521992 ps
CPU time 13.92 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:45 PM PST 24
Peak memory 208484 kb
Host smart-a916ee87-4d48-4147-9140-657c00232db5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985483765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2985483765
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.67056431
Short name T773
Test name
Test status
Simulation time 43454711 ps
CPU time 2.64 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 206580 kb
Host smart-11aab790-5561-4758-9076-b7c029188cc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67056431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.67056431
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.918212968
Short name T742
Test name
Test status
Simulation time 301012454 ps
CPU time 4.85 seconds
Started Feb 25 02:40:26 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 208672 kb
Host smart-5a1f1cb6-e870-437e-bb18-3ccfe8a9cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918212968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.918212968
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2608763184
Short name T478
Test name
Test status
Simulation time 81010936 ps
CPU time 2.62 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 208120 kb
Host smart-24d7b0cc-4cbc-49aa-ad97-5155f9ccb7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608763184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2608763184
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1262756720
Short name T321
Test name
Test status
Simulation time 5444867473 ps
CPU time 58.16 seconds
Started Feb 25 02:40:27 PM PST 24
Finished Feb 25 02:41:26 PM PST 24
Peak memory 222372 kb
Host smart-a4a9f35c-ddfa-497d-ba59-798c284a2280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262756720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1262756720
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1350376048
Short name T230
Test name
Test status
Simulation time 85039879 ps
CPU time 3.88 seconds
Started Feb 25 02:40:41 PM PST 24
Finished Feb 25 02:40:45 PM PST 24
Peak memory 208760 kb
Host smart-a762683b-bdfb-4281-a880-09c5a38cfbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350376048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1350376048
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1570036687
Short name T652
Test name
Test status
Simulation time 68511650 ps
CPU time 2.81 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 209936 kb
Host smart-31092f64-3d2b-4bfb-8d45-85ae8fea6fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570036687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1570036687
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.924346037
Short name T817
Test name
Test status
Simulation time 41220038 ps
CPU time 0.91 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:32 PM PST 24
Peak memory 205884 kb
Host smart-779498fb-6d2c-4534-a1ba-77cf3af7b1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924346037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.924346037
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1710914822
Short name T382
Test name
Test status
Simulation time 67608102 ps
CPU time 2.86 seconds
Started Feb 25 02:40:41 PM PST 24
Finished Feb 25 02:40:44 PM PST 24
Peak memory 214132 kb
Host smart-f6d3d214-e370-4748-81e0-f46b5ac2e549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710914822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1710914822
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.899000311
Short name T911
Test name
Test status
Simulation time 167208080 ps
CPU time 4.64 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 209404 kb
Host smart-1e87e2f2-6fef-4e24-ad80-4d0f1a8defb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899000311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.899000311
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4004572980
Short name T66
Test name
Test status
Simulation time 113441849 ps
CPU time 3.17 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 209676 kb
Host smart-180e67e0-fb4a-41be-b497-fb925111b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004572980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4004572980
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2096347265
Short name T24
Test name
Test status
Simulation time 56909089 ps
CPU time 2.1 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 207988 kb
Host smart-fb05cceb-de73-4ed2-879a-c5d65a80cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096347265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2096347265
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1957414131
Short name T861
Test name
Test status
Simulation time 257042253 ps
CPU time 6.22 seconds
Started Feb 25 02:40:41 PM PST 24
Finished Feb 25 02:40:47 PM PST 24
Peak memory 214152 kb
Host smart-c3bba284-24b8-4dff-946d-40f1c1bc834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957414131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1957414131
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1463539765
Short name T660
Test name
Test status
Simulation time 160551803 ps
CPU time 4.65 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 209144 kb
Host smart-76ea1b98-119c-4199-baa8-891843304b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463539765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1463539765
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2673515097
Short name T592
Test name
Test status
Simulation time 738755621 ps
CPU time 6.55 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:37 PM PST 24
Peak memory 207892 kb
Host smart-2cc5fa7e-2d7c-48d4-b92b-9ed764458f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673515097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2673515097
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1671873219
Short name T337
Test name
Test status
Simulation time 81662607 ps
CPU time 3.54 seconds
Started Feb 25 02:40:24 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 208536 kb
Host smart-c4955fb4-3343-4b0a-9954-fd57f2af3d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671873219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1671873219
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2095879632
Short name T671
Test name
Test status
Simulation time 41468077 ps
CPU time 1.9 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:27 PM PST 24
Peak memory 206480 kb
Host smart-5f2504e4-5f9f-4a15-a7b3-f2476e091239
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095879632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2095879632
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4191215414
Short name T701
Test name
Test status
Simulation time 317928995 ps
CPU time 4.46 seconds
Started Feb 25 02:40:27 PM PST 24
Finished Feb 25 02:40:32 PM PST 24
Peak memory 208624 kb
Host smart-e3a48a29-92de-4b08-958e-b6604f681f8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191215414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4191215414
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.172195100
Short name T562
Test name
Test status
Simulation time 27944795 ps
CPU time 2.29 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:33 PM PST 24
Peak memory 208328 kb
Host smart-10eca051-2e13-4a06-a31f-b897a4139ad6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172195100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.172195100
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3464363901
Short name T546
Test name
Test status
Simulation time 42314558 ps
CPU time 2.24 seconds
Started Feb 25 02:40:26 PM PST 24
Finished Feb 25 02:40:28 PM PST 24
Peak memory 208084 kb
Host smart-0cff14fa-fee8-427f-b941-d593c8e5bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464363901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3464363901
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3241301804
Short name T908
Test name
Test status
Simulation time 119951757 ps
CPU time 2.21 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:39 PM PST 24
Peak memory 206540 kb
Host smart-4ef44c32-338b-4ebd-8c84-2ccb04a35ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241301804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3241301804
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2498518839
Short name T610
Test name
Test status
Simulation time 182896476 ps
CPU time 12.05 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:50 PM PST 24
Peak memory 222432 kb
Host smart-375a5447-f9e9-4148-abe2-5292ac2d0d20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498518839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2498518839
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1796635879
Short name T909
Test name
Test status
Simulation time 209183329 ps
CPU time 7.86 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:36 PM PST 24
Peak memory 208564 kb
Host smart-60b8bfe1-a48c-4f87-84f5-e2d5e9c203bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796635879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1796635879
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.264653373
Short name T710
Test name
Test status
Simulation time 44938042 ps
CPU time 2.51 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 209492 kb
Host smart-972264fe-dddd-41bf-b387-6d63d8a6c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264653373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.264653373
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3732229808
Short name T844
Test name
Test status
Simulation time 47607476 ps
CPU time 0.81 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:31 PM PST 24
Peak memory 205892 kb
Host smart-e4162b88-3dd4-4958-aa57-fdbd19cc4d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732229808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3732229808
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.218553569
Short name T775
Test name
Test status
Simulation time 348249227 ps
CPU time 5.25 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:37 PM PST 24
Peak memory 221028 kb
Host smart-3cd83ad3-26ad-4198-9347-7cbf0bf59eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218553569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.218553569
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3832662822
Short name T73
Test name
Test status
Simulation time 260080399 ps
CPU time 3.57 seconds
Started Feb 25 02:40:29 PM PST 24
Finished Feb 25 02:40:32 PM PST 24
Peak memory 207900 kb
Host smart-58d56377-2819-4ce0-bd36-ef296f050a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832662822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3832662822
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2954187539
Short name T285
Test name
Test status
Simulation time 45022988 ps
CPU time 3.49 seconds
Started Feb 25 02:40:31 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 214116 kb
Host smart-abcc5cb2-76f7-43f8-807b-2c5a8c5d2284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954187539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2954187539
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.119590233
Short name T711
Test name
Test status
Simulation time 140434829 ps
CPU time 6.77 seconds
Started Feb 25 02:40:36 PM PST 24
Finished Feb 25 02:40:43 PM PST 24
Peak memory 214072 kb
Host smart-26340ec3-e334-4084-aeb7-dfb60880ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119590233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.119590233
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1678668885
Short name T583
Test name
Test status
Simulation time 178241023 ps
CPU time 4.67 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:37 PM PST 24
Peak memory 218692 kb
Host smart-09520d20-c96a-4fa2-8216-ee56c79bf0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678668885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1678668885
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2734775743
Short name T472
Test name
Test status
Simulation time 46095918 ps
CPU time 3 seconds
Started Feb 25 02:40:33 PM PST 24
Finished Feb 25 02:40:36 PM PST 24
Peak memory 214200 kb
Host smart-52153ed2-7530-4fe5-95ba-bf00de0248a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734775743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2734775743
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.324103414
Short name T456
Test name
Test status
Simulation time 5218400340 ps
CPU time 41.72 seconds
Started Feb 25 02:40:27 PM PST 24
Finished Feb 25 02:41:10 PM PST 24
Peak memory 208084 kb
Host smart-876b0f27-0b68-4c2a-8000-be89d9124791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324103414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.324103414
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1506767868
Short name T470
Test name
Test status
Simulation time 82761420 ps
CPU time 3.77 seconds
Started Feb 25 02:40:25 PM PST 24
Finished Feb 25 02:40:29 PM PST 24
Peak memory 208532 kb
Host smart-ffd36bc0-6039-4afa-85c6-a43dec799f19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506767868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1506767868
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1220787164
Short name T75
Test name
Test status
Simulation time 2354011020 ps
CPU time 7.03 seconds
Started Feb 25 02:40:41 PM PST 24
Finished Feb 25 02:40:48 PM PST 24
Peak memory 207708 kb
Host smart-c88f5962-d260-460c-9d7e-e8877ec9ef9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220787164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1220787164
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3972963744
Short name T347
Test name
Test status
Simulation time 214433470 ps
CPU time 3.04 seconds
Started Feb 25 02:40:27 PM PST 24
Finished Feb 25 02:40:30 PM PST 24
Peak memory 208468 kb
Host smart-d15e27d7-d2d0-45b9-b85d-2d4ecb684a10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972963744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3972963744
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1607666124
Short name T68
Test name
Test status
Simulation time 83717313 ps
CPU time 2.8 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:40:40 PM PST 24
Peak memory 208212 kb
Host smart-50b6a7dc-5dd1-4167-987f-eca157c0495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607666124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1607666124
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1462472639
Short name T605
Test name
Test status
Simulation time 263266460 ps
CPU time 3.95 seconds
Started Feb 25 02:40:30 PM PST 24
Finished Feb 25 02:40:34 PM PST 24
Peak memory 208252 kb
Host smart-e771da01-e11c-40b7-810f-9a14b8c322be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462472639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1462472639
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3257896758
Short name T885
Test name
Test status
Simulation time 14665681876 ps
CPU time 183.8 seconds
Started Feb 25 02:40:37 PM PST 24
Finished Feb 25 02:43:41 PM PST 24
Peak memory 216404 kb
Host smart-25a5556c-19fa-496a-b3a9-4ff511d03517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257896758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3257896758
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3797346992
Short name T704
Test name
Test status
Simulation time 393391598 ps
CPU time 21.16 seconds
Started Feb 25 02:40:28 PM PST 24
Finished Feb 25 02:40:49 PM PST 24
Peak memory 222444 kb
Host smart-7884bb97-0794-4a31-87ef-77bb87ca2c65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797346992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3797346992
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1698295455
Short name T455
Test name
Test status
Simulation time 92583867 ps
CPU time 4.4 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:37 PM PST 24
Peak memory 208460 kb
Host smart-baa27899-9a47-4a33-ac37-36c63bb4e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698295455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1698295455
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.249924064
Short name T33
Test name
Test status
Simulation time 251611197 ps
CPU time 2.97 seconds
Started Feb 25 02:40:32 PM PST 24
Finished Feb 25 02:40:35 PM PST 24
Peak memory 209848 kb
Host smart-6b366c90-a68f-4a94-995b-537216ea5d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249924064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.249924064
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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