Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4637

1

T2

11

T3

8

T4

6

auto[1]

552

1

T13

1

T17

1

T18

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4637

1

T2

11

T3

8

T4

6

auto[1]

552

1

T13

1

T17

1

T18

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4607

1

T2

11

T3

8

T4

5

auto[1]

582

1

T4

1

T18

1

T42

5

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4607

1

T2

11

T3

8

T4

5

auto[1]

582

1

T4

1

T18

1

T42

5

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T2	2		T13	3		T18	4
auto[OpGenId]	1075	1			T2	4		T4	2		T13	4
auto[OpGenSwOut]	1102	1			T2	3		T4	2		T13	3
auto[OpGenHwOut]	2522	1			T2	2		T3	8		T4	2
auto[OpDisable]	79	1			T18	1		T46	1		T59	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T2	2		T13	3		T18	4
auto[OpGenId]	1075	1			T2	4		T4	2		T13	4
auto[OpGenSwOut]	1102	1			T2	3		T4	2		T13	3
auto[OpGenHwOut]	2522	1			T2	2		T3	8		T4	2
auto[OpDisable]	79	1			T18	1		T46	1		T59	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4619

1

T2

11

T3

4

T4

6

auto[1]

570

1

T3

4

T15

5

T18

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4619

1

T2

11

T3

4

T4

6

auto[1]

570

1

T3

4

T15

5

T18

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4922

1

T2

11

T3

8

T4

6

auto[1]

267

1

T13

6

T36

8

T42

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1744	1			T2	5		T3	1		T4	2
auto[1]	712	1			T2	1		T3	3		T4	1
auto[2]	706	1			T2	2		T3	1		T13	2
auto[3]	699	1			T2	2		T3	2		T4	1
auto[4]	330	1			T4	1		T18	2		T231	1
auto[5]	330	1			T13	2		T15	1		T18	3
auto[6]	324	1			T2	1		T4	1		T18	1
auto[7]	344	1			T3	1		T13	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1328	1			T2	1		T3	1		T4	2
clear_one[1]	712	1			T2	1		T3	3		T4	1
clear_one[2]	706	1			T2	2		T3	1		T13	2
clear_one[3]	699	1			T2	2		T3	2		T4	1
clear_none	1744	1			T2	5		T3	1		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	946	1			T2	5		T4	2		T18	7
auto[StInit]	693	1			T3	1		T4	1		T13	2
auto[StCreatorRootKey]	549	1			T3	1		T13	2		T15	1
auto[StOwnerIntKey]	514	1			T3	1		T4	1		T13	1
auto[StOwnerKey]	464	1			T3	1		T15	1		T18	2
auto[StDisabled]	1870	1			T3	4		T4	2		T13	6
auto[StInvalid]	153	1			T2	6		T38	2		T224	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	946	1			T2	5		T4	2		T18	7
auto[StInit]	693	1			T3	1		T4	1		T13	2
auto[StCreatorRootKey]	549	1			T3	1		T13	2		T15	1
auto[StOwnerIntKey]	514	1			T3	1		T4	1		T13	1
auto[StOwnerKey]	464	1			T3	1		T15	1		T18	2
auto[StDisabled]	1870	1			T3	4		T4	2		T13	6
auto[StInvalid]	153	1			T2	6		T38	2		T224	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T255	2		T256	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	149	1			T18	1		T36	1		T28	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	145	1			T2	1		T18	3		T28	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	240	1			T2	1		T4	1		T18	1
auto[0]	auto[StInit]	auto[OpAdvance]	34	1			T18	1		T131	1		T224	1
auto[0]	auto[StInit]	auto[OpGenId]	107	1			T13	2		T18	2		T59	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	85	1			T130	1		T160	1		T26	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	182	1			T3	1		T15	1		T24	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T13	2		T144	1		T222	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	38	1			T28	1		T257	1		T39	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	52	1			T17	1		T147	1		T59	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	75	1			T42	1		T226	1		T59	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T131	1		T229	1		T144	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	25	1			T59	1		T63	1		T204	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	30	1			T13	1		T18	1		T42	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T90	1		T220	1		T59	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T141	1		T57	1		T258	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T18	1		T215	1		T96	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T144	1		T259	1		T260	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T42	1		T261	1		T140	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	27	1			T13	1		T219	1		T110	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T42	2		T130	2		T59	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T4	1		T90	1		T59	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	180	1			T15	1		T18	1		T42	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T262	1		T85	1		T263	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	6	1			T2	1		T105	1		T61	1
auto[0]	auto[StInvalid]	auto[OpGenId]	11	1			T2	1		T264	1		T265	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T2	1		T221	1		T228	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T224	1		T228	2		T266	1
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T267	1		T204	1		T268	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T4	1		T110	1		T204	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T18	1		T139	1		T269	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T133	1		T270	1		T271	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T24	1		T237	1		T146	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T104	1		T110	1		T64	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	30	1			T133	1		T272	1		T64	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T273	1		T88	2		T69	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T90	1		T258	1		T274	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T59	1		T76	1		T275	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T18	1		T140	1		T276	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T88	1		T270	1		T277	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T160	2		T88	1		T69	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T18	1		T59	1		T65	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T261	1		T278	1		T118	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T160	1		T57	1		T87	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T150	1		T82	1		T64	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T59	1		T279	1		T280	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T3	1		T15	1		T281	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T18	1		T36	4		T150	2
auto[1]	auto[StDisabled]	auto[OpGenId]	51	1			T28	1		T269	1		T66	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T36	1		T46	1		T59	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T3	2		T15	1		T47	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T18	1		T53	1		T57	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T2	1		T208	1		T264	1
auto[1]	auto[StInvalid]	auto[OpGenId]	5	1			T105	1		T228	1		T282	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T264	1		T283	1		T284	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T224	1		T285	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T36	1		T47	1		T287	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T2	1		T59	1		T63	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	33	1			T36	1		T218	1		T288	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T289	1		T290	1		T291	1
auto[2]	auto[StInit]	auto[OpGenId]	6	1			T220	1		T104	1		T151	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T18	1		T39	1		T87	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	35	1			T139	1		T30	1		T120	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T163	1		T43	1		T103	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T88	1		T64	1		T292	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T289	1		T268	1		T48	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T3	1		T15	1		T231	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T5	1		T110	1		T103	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T57	1		T43	1		T293	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T58	1		T277	1		T294	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T15	1		T276	1		T295	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T227	1		T296	1		T297	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	17	1			T66	1		T298	1		T299	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T28	1		T218	1		T204	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T18	1		T90	1		T231	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T59	1		T280	1		T57	1
auto[2]	auto[StDisabled]	auto[OpGenId]	63	1			T13	1		T18	1		T300	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T13	1		T160	2		T141	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T18	1		T25	1		T213	1
auto[2]	auto[StDisabled]	auto[OpDisable]	15	1			T50	1		T65	1		T73	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T224	1		T61	1		T266	1
auto[2]	auto[StInvalid]	auto[OpGenId]	2	1			T38	1		T301	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T61	1		T302	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T2	1		T264	1		T266	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T2	1		T57	2		T43	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	24	1			T18	1		T131	1		T220	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	44	1			T36	1		T303	2		T295	2
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T24	1		T304	1		T305	1
auto[3]	auto[StInit]	auto[OpGenId]	13	1			T36	1		T218	1		T54	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	18	1			T36	1		T26	1		T94	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	27	1			T4	1		T18	1		T24	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T161	1		T306	1		T290	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T307	1		T308	1		T210	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T53	1		T141	1		T57	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T18	1		T59	1		T150	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T57	1		T70	1		T309	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T163	1		T280	1		T310	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T161	1		T133	1		T7	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T3	1		T59	2		T214	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T311	1		T312	1		T253	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	20	1			T148	1		T313	1		T314	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T138	1		T222	1		T133	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T59	1		T139	1		T43	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	24	1			T18	1		T160	1		T220	1
auto[3]	auto[StDisabled]	auto[OpGenId]	49	1			T215	1		T223	1		T144	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T59	3		T215	1		T314	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T3	1		T147	1		T59	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T63	1		T133	1		T64	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T208	1		T265	1		T283	1
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T2	1		T228	1		T315	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T221	1		T264	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T228	1		T102	1		T265	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T59	1		T138	1		T57	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T316	1		T275	1		T210	2
auto[4]	auto[StReset]	auto[OpGenHwOut]	28	1			T46	1		T59	1		T303	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T110	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T317	1		T275	1		T318	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T94	1		T319	1		T304	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T161	1		T295	1		T320	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T150	1		T321	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T323	1		T324	1		T275	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T204	1		T325	1		T80	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T326	1		T281	1		T303	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T163	1		T210	1		T327	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T4	1		T150	1		T328	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T134	2		T240	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T231	1		T219	1		T57	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T163	1		T330	1		T331	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	14	1			T5	1		T332	1		T333	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T66	1		T306	1		T210	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T295	1		T115	1		T204	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T226	1		T59	1		T222	1
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T18	1		T163	1		T280	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T219	1		T162	1		T280	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	57	1			T18	1		T334	1		T261	1
auto[4]	auto[StDisabled]	auto[OpDisable]	12	1			T59	1		T54	1		T110	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T265	1		T335	1		T336	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T285	1		T337	1		T284	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T105	1		T338	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T224	1		T339	1		T286	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T30	1		T204	1		T310	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	15	1			T105	1		T61	1		T133	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	13	1			T59	1		T340	1		T290	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T133	1		T99	1		T341	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T342	1		T48	1		T343	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T253	1		T101	1		T344	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T26	1		T345	1		T346	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T18	1		T294	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T66	1		T70	1		T348	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T110	1		T349	1		T294	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T334	1		T110	1		T350	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T141	1		T296	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T205	1		T256	4		T351	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T204	1		T247	2		T352	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T288	1		T140	1		T353	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T57	1		T354	1		T78	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T57	1		T204	1		T100	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T59	1		T78	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T328	1		T356	1		T345	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T36	1		T96	1		T163	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T18	1		T226	1		T213	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T13	1		T138	1		T141	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T13	1		T15	1		T18	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T357	1		T358	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T38	1		T339	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T359	1		T286	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T109	1		T361	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T109	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T2	1		T47	1		T43	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T267	1		T146	1		T362	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	16	1			T137	1		T295	1		T363	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T291	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	9	1			T28	1		T364	1		T337	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	1	1			T365	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T105	1		T366	1		T77	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T280	1		T367	1		T368	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T148	1		T130	1		T51	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T36	2		T131	1		T117	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T271	1		T369	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T259	1		T370	1		T371	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T66	1		T133	1		T81	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T213	1		T281	1		T257	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T372	1		T81	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T147	1		T110	1		T204	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T130	1		T373	1		T70	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T25	1		T214	1		T276	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T161	2		T218	1		T374	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T4	1		T132	1		T152	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T18	1		T59	1		T161	3
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T326	1		T288	1		T139	2
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T55	1		T51	1		T77	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T375	1		T338	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T105	1		T102	1		T285	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T376	1		T377	1		T360	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T378	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T287	1		T82	1		T316	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T138	1		T57	1		T110	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	20	1			T139	1		T110	1		T379	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T151	1		T70	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	10	1			T104	1		T364	1		T380	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	9	1			T97	1		T95	2		T381	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	18	1			T137	1		T97	1		T340	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T57	1		T151	1		T306	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T133	1		T381	1		T382	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T252	1		T383	1		T79	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T143	1		T151	2		T356	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T273	1		T381	1		T384	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T36	1		T138	1		T206	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T73	1		T204	1		T133	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T130	1		T273	1		T151	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T317	1		T347	1		T81	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T300	1		T70	1		T45	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T213	1		T65	1		T274	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T385	1		T278	1		T363	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	16	1			T220	1		T59	1		T151	3
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T13	1		T130	1		T273	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T36	1		T162	1		T279	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T3	1		T15	1		T231	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T46	1		T275	1		T78	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T386	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T285	1		T264	1		T265	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T302	1		T361	2		T387	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T102	1		T388	1		T283	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1328

1

T2

1

T3

1

T4

2

clear_one[1]

auto[0]

auto[0]

auto[0]

378

1

T2

1

T4

1

T18

4

clear_one[1]

auto[0]

auto[0]

auto[1]

142

1

T3

3

T15

2

T36

1

clear_one[1]

auto[0]

auto[1]

auto[0]

144

1

T90

1

T59

1

T214

1

clear_one[1]

auto[0]

auto[1]

auto[1]

48

1

T18

1

T28

1

T59

2

clear_one[2]

auto[0]

auto[0]

auto[0]

418

1

T2

2

T13

1

T18

2

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T3

1

T15

2

T18

1

clear_one[2]

auto[1]

auto[0]

auto[0]

126

1

T13

1

T18

1

T213

1

clear_one[2]

auto[1]

auto[0]

auto[1]

35

1

T25

1

T218

1

T227

1

clear_one[3]

auto[0]

auto[0]

auto[0]

415

1

T2

2

T3

2

T4

1

clear_one[3]

auto[0]

auto[1]

auto[0]

120

1

T147

1

T59

5

T214

2

clear_one[3]

auto[1]

auto[0]

auto[0]

136

1

T18

1

T59

1

T161

1

clear_one[3]

auto[1]

auto[1]

auto[0]

28

1

T59

1

T222

1

T43

1

clear_none

auto[0]

auto[0]

auto[0]

1220

1

T2

5

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

117

1

T15

1

T231

1

T220

1

clear_none

auto[0]

auto[1]

auto[0]

140

1

T4

1

T148

1

T59

1

clear_none

auto[0]

auto[1]

auto[1]

40

1

T90

2

T226

1

T59

1

clear_none

auto[1]

auto[0]

auto[0]

131

1

T17

1

T42

1

T130

1

clear_none

auto[1]

auto[0]

auto[1]

34

1

T18

1

T57

1

T389

2

clear_none

auto[1]

auto[1]

auto[0]

35

1

T42

1

T59

1

T96

1

clear_none

auto[1]

auto[1]

auto[1]

27

1

T42

4

T144

3

T152

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1255	1			T2	1		T3	1		T4	2
clear_all	auto[1]	73	1			T13	1		T36	3		T150	1
clear_one[1]	auto[0]	657	1			T2	1		T3	3		T4	1
clear_one[1]	auto[1]	55	1			T36	4		T160	1		T150	2
clear_one[2]	auto[0]	661	1			T2	2		T3	1		T13	1
clear_one[2]	auto[1]	45	1			T13	1		T160	1		T306	1
clear_one[3]	auto[0]	666	1			T2	2		T3	2		T4	1
clear_one[3]	auto[1]	33	1			T36	1		T144	2		T314	1
clear_none	auto[0]	1683	1			T2	5		T3	1		T4	2
clear_none	auto[1]	61	1			T13	4		T42	4		T161	3