Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11179

1

T1

6

T2

31

T3

5

auto[Attestation]

8193

1

T1

3

T2

21

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2872	1			T1	2		T2	8		T4	4
auto[Aes]	3370	1			T1	1		T2	8		T4	4
auto[Kmac]	3498	1			T1	2		T2	6		T4	4
auto[Otbn]	3537	1			T1	1		T2	9		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7731	1			T1	1		T2	8		T3	8
auto[OpGenId]	6095	1			T1	3		T2	21		T4	9
auto[OpGenSwOut]	6123	1			T1	2		T2	10		T4	9
auto[OpGenHwOut]	7154	1			T1	4		T2	21		T3	8
auto[OpDisable]	138	1			T18	1		T46	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10197

1

T1

1

T2

1

T3

8

auto[OpDoneFail]

17044

1

T1

9

T2

59

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5945	1			T1	6		T2	30		T3	1
auto[StInit]	4332	1			T1	4		T2	1		T3	2
auto[StCreatorRootKey]	3138	1			T3	2		T4	3		T13	5
auto[StOwnerIntKey]	2680	1			T3	2		T4	2		T13	3
auto[StOwnerKey]	2317	1			T3	2		T4	3		T13	2
auto[StDisabled]	7803	1			T3	7		T4	15		T13	10
auto[StInvalid]	1026	1			T2	29		T38	24		T27	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	326	1			T2	3		T4	1		T18	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	115	1			T13	1		T18	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	93	1			T90	1		T46	1		T59	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T42	1		T59	1		T73	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	50	1			T149	1		T218	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T90	1		T148	1		T160	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	39	1			T2	1		T38	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T2	1		T14	2		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	135	1			T36	1		T46	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T13	1		T18	1		T148	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	52	1			T18	1		T147	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T215	1		T218	1		T67	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	201	1			T18	1		T36	2		T147	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T105	1		T108	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	277	1			T1	1		T14	1		T36	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	135	1			T4	1		T18	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T147	1		T160	1		T59	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T160	1		T220	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	69	1			T18	1		T59	2		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	210	1			T13	1		T36	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T108	1		T109	1		T221	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	296	1			T2	1		T4	2		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T13	1		T160	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T4	1		T25	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T13	2		T18	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T13	1		T59	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	238	1			T18	1		T36	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T38	2		T60	2		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T2	1		T18	3		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T1	1		T59	2		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T130	1		T226	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T226	1		T225	1		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T59	2		T162	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	227	1			T13	1		T18	2		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	38	1			T38	1		T27	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T18	2		T27	2		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T14	1		T24	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	85	1			T18	1		T36	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T18	1		T25	2		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	48	1			T42	1		T213	1		T215	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	220	1			T4	3		T42	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	29	1			T2	2		T38	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T18	3		T59	3		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	139	1			T24	2		T26	2		T59	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	73	1			T13	1		T226	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T17	1		T42	1		T59	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T28	1		T130	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	206	1			T36	1		T42	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T27	1		T60	1		T228	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T2	1		T18	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T42	1		T26	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T14	1		T17	2		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T18	1		T148	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	52	1			T18	1		T59	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	220	1			T4	1		T36	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T27	2		T224	2		T108	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	249	1			T1	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T4	1		T36	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T14	1		T38	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T28	1		T59	2		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T90	1		T226	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T18	1		T36	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T2	1		T38	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	399	1			T2	2		T4	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T1	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T17	1		T220	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	110	1			T36	1		T42	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	84	1			T18	1		T220	1		T59	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T18	2		T42	3		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	34	1			T2	2		T60	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	415	1			T1	1		T2	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	124	1			T18	1		T24	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T90	1		T46	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T90	1		T147	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	74	1			T18	1		T25	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T4	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	40	1			T2	2		T38	3		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	453	1			T2	3		T4	2		T36	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T3	1		T18	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T4	1		T15	1		T150	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T3	1		T15	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T3	1		T15	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T3	2		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T2	2		T224	1		T105	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	64	1			T2	1		T27	1		T105	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T26	1		T163	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T18	1		T25	2		T150	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T42	1		T226	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T42	1		T90	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	188	1			T4	1		T18	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T2	1		T38	2		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	39	1			T18	1		T59	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	139	1			T2	1		T24	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T18	1		T42	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T18	1		T130	1		T213	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T25	1		T147	1		T161	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	272	1			T13	1		T18	2		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T27	1		T60	3		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T2	1		T18	3		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	143	1			T17	1		T24	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T42	1		T59	4		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T36	1		T28	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T18	1		T213	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	295	1			T4	1		T18	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	22	1			T2	1		T38	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T2	1		T18	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	150	1			T1	1		T15	1		T24	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T3	1		T36	2		T231	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T231	1		T226	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T18	1		T28	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	311	1			T3	2		T15	2		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T2	1		T38	1		T27	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T42	1		T90	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	697	1			T2	4		T4	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	175	1			T13	1		T18	2		T147	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	662	1			T2	1		T14	2		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	218	1			T18	1		T147	1		T160	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	676	1			T1	1		T4	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T4	1		T13	3		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	700	1			T2	1		T4	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T130	1		T226	2		T59	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	452	1			T1	1		T2	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T18	2		T36	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	443	1			T2	2		T4	3		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	195	1			T13	1		T17	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	465	1			T18	3		T36	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	185	1			T14	1		T17	2		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	465	1			T2	1		T4	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	155	1			T14	1		T28	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	599	1			T1	1		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	270	1			T17	1		T18	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	856	1			T1	1		T2	4		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	254	1			T18	1		T25	1		T90	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	880	1			T1	1		T2	4		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	250	1			T3	2		T4	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	884	1			T2	5		T3	3		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	172	1			T18	1		T42	2		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	404	1			T2	2		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T18	2		T42	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	499	1			T2	1		T13	1		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T18	1		T36	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	536	1			T2	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	290	1			T3	1		T18	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	557	1			T1	1		T2	2		T3	2