Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31160

1

T1

10

T2

66

T3

19

auto[1]

233

1

T13

6

T36

2

T42

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31167	1			T1	10		T2	66		T3	19
auto[134217728:268435455]	10	1			T42	1		T150	1		T314	1
auto[268435456:402653183]	7	1			T163	1		T151	1		T88	1
auto[402653184:536870911]	6	1			T160	1		T413	1		T311	1
auto[536870912:671088639]	8	1			T163	1		T88	1		T292	1
auto[671088640:805306367]	9	1			T314	1		T414	1		T327	1
auto[805306368:939524095]	13	1			T147	2		T144	1		T314	1
auto[939524096:1073741823]	1	1			T150	1		-	-		-	-
auto[1073741824:1207959551]	6	1			T152	1		T413	1		T327	1
auto[1207959552:1342177279]	6	1			T292	2		T414	1		T256	1
auto[1342177280:1476395007]	7	1			T42	1		T292	1		T255	1
auto[1476395008:1610612735]	3	1			T13	1		T415	1		T416	1
auto[1610612736:1744830463]	8	1			T13	1		T147	1		T144	1
auto[1744830464:1879048191]	5	1			T13	1		T270	1		T256	1
auto[1879048192:2013265919]	10	1			T42	1		T160	1		T144	1
auto[2013265920:2147483647]	4	1			T144	1		T88	1		T417	1
auto[2147483648:2281701375]	9	1			T13	1		T150	1		T413	1
auto[2281701376:2415919103]	10	1			T150	1		T88	1		T413	1
auto[2415919104:2550136831]	5	1			T36	1		T270	1		T256	1
auto[2550136832:2684354559]	8	1			T13	1		T36	1		T400	1
auto[2684354560:2818572287]	11	1			T13	1		T42	1		T144	1
auto[2818572288:2952790015]	8	1			T42	1		T150	1		T273	1
auto[2952790016:3087007743]	12	1			T42	1		T144	1		T273	1
auto[3087007744:3221225471]	11	1			T163	2		T88	1		T400	1
auto[3221225472:3355443199]	5	1			T255	1		T309	1		T321	1
auto[3355443200:3489660927]	7	1			T400	1		T311	1		T330	2
auto[3489660928:3623878655]	5	1			T42	1		T144	1		T314	1
auto[3623878656:3758096383]	4	1			T163	1		T144	1		T255	1
auto[3758096384:3892314111]	6	1			T163	1		T88	1		T289	1
auto[3892314112:4026531839]	3	1			T144	1		T321	1		T330	1
auto[4026531840:4160749567]	8	1			T314	1		T289	1		T270	1
auto[4160749568:4294967295]	11	1			T42	1		T160	1		T150	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31160	1			T1	10		T2	66		T3	19
auto[0:134217727]	auto[1]	7	1			T88	1		T292	1		T311	1
auto[134217728:268435455]	auto[1]	10	1			T42	1		T150	1		T314	1
auto[268435456:402653183]	auto[1]	7	1			T163	1		T151	1		T88	1
auto[402653184:536870911]	auto[1]	6	1			T160	1		T413	1		T311	1
auto[536870912:671088639]	auto[1]	8	1			T163	1		T88	1		T292	1
auto[671088640:805306367]	auto[1]	9	1			T314	1		T414	1		T327	1
auto[805306368:939524095]	auto[1]	13	1			T147	2		T144	1		T314	1
auto[939524096:1073741823]	auto[1]	1	1			T150	1		-	-		-	-
auto[1073741824:1207959551]	auto[1]	6	1			T152	1		T413	1		T327	1
auto[1207959552:1342177279]	auto[1]	6	1			T292	2		T414	1		T256	1
auto[1342177280:1476395007]	auto[1]	7	1			T42	1		T292	1		T255	1
auto[1476395008:1610612735]	auto[1]	3	1			T13	1		T415	1		T416	1
auto[1610612736:1744830463]	auto[1]	8	1			T13	1		T147	1		T144	1
auto[1744830464:1879048191]	auto[1]	5	1			T13	1		T270	1		T256	1
auto[1879048192:2013265919]	auto[1]	10	1			T42	1		T160	1		T144	1
auto[2013265920:2147483647]	auto[1]	4	1			T144	1		T88	1		T417	1
auto[2147483648:2281701375]	auto[1]	9	1			T13	1		T150	1		T413	1
auto[2281701376:2415919103]	auto[1]	10	1			T150	1		T88	1		T413	1
auto[2415919104:2550136831]	auto[1]	5	1			T36	1		T270	1		T256	1
auto[2550136832:2684354559]	auto[1]	8	1			T13	1		T36	1		T400	1
auto[2684354560:2818572287]	auto[1]	11	1			T13	1		T42	1		T144	1
auto[2818572288:2952790015]	auto[1]	8	1			T42	1		T150	1		T273	1
auto[2952790016:3087007743]	auto[1]	12	1			T42	1		T144	1		T273	1
auto[3087007744:3221225471]	auto[1]	11	1			T163	2		T88	1		T400	1
auto[3221225472:3355443199]	auto[1]	5	1			T255	1		T309	1		T321	1
auto[3355443200:3489660927]	auto[1]	7	1			T400	1		T311	1		T330	2
auto[3489660928:3623878655]	auto[1]	5	1			T42	1		T144	1		T314	1
auto[3623878656:3758096383]	auto[1]	4	1			T163	1		T144	1		T255	1
auto[3758096384:3892314111]	auto[1]	6	1			T163	1		T88	1		T289	1
auto[3892314112:4026531839]	auto[1]	3	1			T144	1		T321	1		T330	1
auto[4026531840:4160749567]	auto[1]	8	1			T314	1		T289	1		T270	1
auto[4160749568:4294967295]	auto[1]	11	1			T42	1		T160	1		T150	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1412

1

T2

3

T4

2

T17

6

auto[1]

1678

1

T2

4

T4

2

T13

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T220	1		T59	1		T279	1
auto[134217728:268435455]	100	1			T4	1		T46	1		T47	1
auto[268435456:402653183]	91	1			T2	1		T28	1		T25	1
auto[402653184:536870911]	88	1			T2	1		T4	1		T17	1
auto[536870912:671088639]	88	1			T2	1		T13	1		T18	1
auto[671088640:805306367]	81	1			T90	1		T147	1		T131	1
auto[805306368:939524095]	94	1			T18	1		T36	1		T215	1
auto[939524096:1073741823]	104	1			T2	1		T18	1		T36	1
auto[1073741824:1207959551]	92	1			T59	1		T162	1		T96	1
auto[1207959552:1342177279]	103	1			T36	1		T131	1		T59	1
auto[1342177280:1476395007]	104	1			T4	1		T13	1		T18	1
auto[1476395008:1610612735]	94	1			T13	1		T59	4		T162	1
auto[1610612736:1744830463]	92	1			T17	1		T18	1		T36	1
auto[1744830464:1879048191]	85	1			T18	1		T90	1		T59	2
auto[1879048192:2013265919]	91	1			T18	1		T24	1		T226	1
auto[2013265920:2147483647]	100	1			T13	1		T17	1		T18	1
auto[2147483648:2281701375]	98	1			T13	1		T17	1		T18	1
auto[2281701376:2415919103]	87	1			T18	1		T46	1		T226	1
auto[2415919104:2550136831]	99	1			T18	1		T131	2		T5	1
auto[2550136832:2684354559]	105	1			T18	1		T28	1		T24	1
auto[2684354560:2818572287]	81	1			T4	1		T24	1		T46	1
auto[2818572288:2952790015]	83	1			T28	1		T59	2		T279	1
auto[2952790016:3087007743]	109	1			T36	1		T47	2		T220	1
auto[3087007744:3221225471]	114	1			T2	1		T18	1		T59	1
auto[3221225472:3355443199]	99	1			T25	1		T26	1		T230	1
auto[3355443200:3489660927]	111	1			T13	1		T18	2		T28	1
auto[3489660928:3623878655]	109	1			T18	3		T42	1		T59	1
auto[3623878656:3758096383]	99	1			T36	1		T147	1		T59	1
auto[3758096384:3892314111]	85	1			T18	3		T36	1		T42	1
auto[3892314112:4026531839]	106	1			T2	1		T17	1		T18	2
auto[4026531840:4160749567]	97	1			T2	1		T17	1		T18	1
auto[4160749568:4294967295]	109	1			T36	1		T59	2		T53	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T279	1		T222	1		T151	1
auto[0:134217727]	auto[1]	41	1			T220	1		T59	1		T109	1
auto[134217728:268435455]	auto[0]	48	1			T4	1		T26	1		T5	1
auto[134217728:268435455]	auto[1]	52	1			T46	1		T47	1		T26	1
auto[268435456:402653183]	auto[0]	39	1			T2	1		T25	1		T220	1
auto[268435456:402653183]	auto[1]	52	1			T28	1		T219	1		T27	1
auto[402653184:536870911]	auto[0]	41	1			T17	1		T24	1		T109	1
auto[402653184:536870911]	auto[1]	47	1			T2	1		T4	1		T141	1
auto[536870912:671088639]	auto[0]	31	1			T223	1		T138	1		T280	1
auto[536870912:671088639]	auto[1]	57	1			T2	1		T13	1		T18	1
auto[671088640:805306367]	auto[0]	37	1			T279	1		T30	1		T97	1
auto[671088640:805306367]	auto[1]	44	1			T90	1		T147	1		T131	1
auto[805306368:939524095]	auto[0]	50	1			T36	1		T142	1		T300	1
auto[805306368:939524095]	auto[1]	44	1			T18	1		T215	1		T38	2
auto[939524096:1073741823]	auto[0]	50	1			T2	1		T36	1		T24	1
auto[939524096:1073741823]	auto[1]	54	1			T18	1		T28	1		T59	1
auto[1073741824:1207959551]	auto[0]	37	1			T59	1		T162	1		T300	1
auto[1073741824:1207959551]	auto[1]	55	1			T96	1		T279	1		T222	1
auto[1207959552:1342177279]	auto[0]	44	1			T131	1		T215	1		T279	1
auto[1207959552:1342177279]	auto[1]	59	1			T36	1		T59	1		T163	1
auto[1342177280:1476395007]	auto[0]	44	1			T59	1		T163	2		T105	1
auto[1342177280:1476395007]	auto[1]	60	1			T4	1		T13	1		T18	1
auto[1476395008:1610612735]	auto[0]	44	1			T59	1		T224	1		T144	1
auto[1476395008:1610612735]	auto[1]	50	1			T13	1		T59	3		T162	1
auto[1610612736:1744830463]	auto[0]	55	1			T17	1		T18	1		T36	1
auto[1610612736:1744830463]	auto[1]	37	1			T27	1		T110	1		T43	1
auto[1744830464:1879048191]	auto[0]	47	1			T18	1		T59	2		T141	1
auto[1744830464:1879048191]	auto[1]	38	1			T90	1		T5	1		T150	1
auto[1879048192:2013265919]	auto[0]	39	1			T24	1		T215	1		T138	1
auto[1879048192:2013265919]	auto[1]	52	1			T18	1		T226	1		T220	1
auto[2013265920:2147483647]	auto[0]	48	1			T17	1		T18	1		T24	1
auto[2013265920:2147483647]	auto[1]	52	1			T13	1		T5	1		T215	1
auto[2147483648:2281701375]	auto[0]	45	1			T17	1		T162	1		T27	1
auto[2147483648:2281701375]	auto[1]	53	1			T13	1		T18	1		T226	1
auto[2281701376:2415919103]	auto[0]	32	1			T279	1		T144	1		T269	1
auto[2281701376:2415919103]	auto[1]	55	1			T18	1		T46	1		T226	1
auto[2415919104:2550136831]	auto[0]	44	1			T131	2		T97	1		T43	1
auto[2415919104:2550136831]	auto[1]	55	1			T18	1		T5	1		T38	1
auto[2550136832:2684354559]	auto[0]	40	1			T28	1		T24	1		T59	1
auto[2550136832:2684354559]	auto[1]	65	1			T18	1		T160	1		T59	1
auto[2684354560:2818572287]	auto[0]	33	1			T4	1		T24	1		T226	1
auto[2684354560:2818572287]	auto[1]	48	1			T46	1		T161	1		T110	2
auto[2818572288:2952790015]	auto[0]	43	1			T28	1		T279	1		T269	1
auto[2818572288:2952790015]	auto[1]	40	1			T59	2		T39	1		T314	1
auto[2952790016:3087007743]	auto[0]	46	1			T47	2		T59	2		T27	1
auto[2952790016:3087007743]	auto[1]	63	1			T36	1		T220	1		T59	2
auto[3087007744:3221225471]	auto[0]	50	1			T18	1		T59	1		T213	1
auto[3087007744:3221225471]	auto[1]	64	1			T2	1		T53	1		T162	1
auto[3221225472:3355443199]	auto[0]	52	1			T230	1		T218	1		T163	1
auto[3221225472:3355443199]	auto[1]	47	1			T25	1		T26	1		T222	1
auto[3355443200:3489660927]	auto[0]	52	1			T24	1		T147	1		T57	1
auto[3355443200:3489660927]	auto[1]	59	1			T13	1		T18	2		T28	1
auto[3489660928:3623878655]	auto[0]	37	1			T18	1		T110	1		T204	1
auto[3489660928:3623878655]	auto[1]	72	1			T18	2		T42	1		T59	1
auto[3623878656:3758096383]	auto[0]	55	1			T59	1		T218	1		T227	1
auto[3623878656:3758096383]	auto[1]	44	1			T36	1		T147	1		T5	1
auto[3758096384:3892314111]	auto[0]	47	1			T18	2		T213	1		T279	1
auto[3758096384:3892314111]	auto[1]	38	1			T18	1		T36	1		T42	1
auto[3892314112:4026531839]	auto[0]	35	1			T17	1		T418	1		T70	1
auto[3892314112:4026531839]	auto[1]	71	1			T2	1		T18	2		T28	1
auto[4026531840:4160749567]	auto[0]	48	1			T2	1		T17	1		T27	1
auto[4026531840:4160749567]	auto[1]	49	1			T18	1		T38	1		T96	1
auto[4160749568:4294967295]	auto[0]	48	1			T36	1		T221	1		T110	1
auto[4160749568:4294967295]	auto[1]	61	1			T59	2		T53	1		T279	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1414

1

T2

3

T4

3

T17

5

auto[1]

1676

1

T2

4

T4

1

T13

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	80	1			T18	2		T90	1		T5	1
auto[134217728:268435455]	96	1			T4	1		T42	1		T25	1
auto[268435456:402653183]	90	1			T2	1		T18	2		T131	1
auto[402653184:536870911]	99	1			T17	1		T18	1		T160	1
auto[536870912:671088639]	96	1			T17	1		T28	1		T59	1
auto[671088640:805306367]	92	1			T18	1		T36	1		T24	1
auto[805306368:939524095]	81	1			T2	1		T18	1		T226	1
auto[939524096:1073741823]	98	1			T2	1		T131	1		T59	2
auto[1073741824:1207959551]	127	1			T2	1		T18	1		T36	1
auto[1207959552:1342177279]	89	1			T2	1		T24	1		T59	1
auto[1342177280:1476395007]	102	1			T2	1		T36	1		T28	1
auto[1476395008:1610612735]	100	1			T18	1		T24	1		T59	2
auto[1610612736:1744830463]	88	1			T18	1		T218	1		T96	1
auto[1744830464:1879048191]	89	1			T4	1		T13	1		T42	1
auto[1879048192:2013265919]	107	1			T17	2		T18	1		T28	1
auto[2013265920:2147483647]	91	1			T28	1		T59	4		T27	1
auto[2147483648:2281701375]	87	1			T18	1		T59	2		T161	1
auto[2281701376:2415919103]	103	1			T18	1		T36	1		T47	1
auto[2415919104:2550136831]	104	1			T4	1		T36	1		T28	1
auto[2550136832:2684354559]	106	1			T18	3		T24	1		T213	1
auto[2684354560:2818572287]	91	1			T36	1		T24	1		T47	1
auto[2818572288:2952790015]	109	1			T13	1		T17	1		T18	1
auto[2952790016:3087007743]	96	1			T220	2		T215	1		T229	1
auto[3087007744:3221225471]	101	1			T13	1		T18	1		T24	1
auto[3221225472:3355443199]	102	1			T13	1		T17	1		T26	1
auto[3355443200:3489660927]	94	1			T18	2		T147	1		T150	1
auto[3489660928:3623878655]	110	1			T2	1		T24	1		T59	1
auto[3623878656:3758096383]	100	1			T13	1		T18	1		T25	1
auto[3758096384:3892314111]	93	1			T13	1		T47	1		T131	1
auto[3892314112:4026531839]	83	1			T18	2		T36	1		T59	1
auto[4026531840:4160749567]	102	1			T18	1		T36	1		T147	1
auto[4160749568:4294967295]	84	1			T4	1		T90	1		T220	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34	1			T38	1		T66	1		T30	1
auto[0:134217727]	auto[1]	46	1			T18	2		T90	1		T5	1
auto[134217728:268435455]	auto[0]	41	1			T4	1		T142	1		T300	1
auto[134217728:268435455]	auto[1]	55	1			T42	1		T25	1		T46	2
auto[268435456:402653183]	auto[0]	42	1			T162	1		T300	1		T57	1
auto[268435456:402653183]	auto[1]	48	1			T2	1		T18	2		T131	1
auto[402653184:536870911]	auto[0]	52	1			T17	1		T18	1		T131	1
auto[402653184:536870911]	auto[1]	47	1			T160	1		T27	1		T60	1
auto[536870912:671088639]	auto[0]	45	1			T17	1		T28	1		T59	1
auto[536870912:671088639]	auto[1]	51	1			T57	1		T119	1		T110	1
auto[671088640:805306367]	auto[0]	46	1			T36	1		T24	1		T279	1
auto[671088640:805306367]	auto[1]	46	1			T18	1		T59	1		T150	1
auto[805306368:939524095]	auto[0]	40	1			T220	1		T215	1		T208	1
auto[805306368:939524095]	auto[1]	41	1			T2	1		T18	1		T226	1
auto[939524096:1073741823]	auto[0]	45	1			T2	1		T131	1		T59	2
auto[939524096:1073741823]	auto[1]	53	1			T162	1		T96	1		T50	1
auto[1073741824:1207959551]	auto[0]	59	1			T2	1		T60	1		T224	1
auto[1073741824:1207959551]	auto[1]	68	1			T18	1		T36	1		T150	1
auto[1207959552:1342177279]	auto[0]	40	1			T2	1		T24	1		T59	1
auto[1207959552:1342177279]	auto[1]	49	1			T60	1		T73	1		T66	1
auto[1342177280:1476395007]	auto[0]	40	1			T28	1		T257	1		T224	1
auto[1342177280:1476395007]	auto[1]	62	1			T2	1		T36	1		T59	2
auto[1476395008:1610612735]	auto[0]	42	1			T18	1		T24	1		T279	1
auto[1476395008:1610612735]	auto[1]	58	1			T59	2		T287	1		T61	1
auto[1610612736:1744830463]	auto[0]	42	1			T218	1		T163	1		T141	1
auto[1610612736:1744830463]	auto[1]	46	1			T18	1		T96	1		T279	1
auto[1744830464:1879048191]	auto[0]	38	1			T5	1		T218	1		T279	1
auto[1744830464:1879048191]	auto[1]	51	1			T4	1		T13	1		T42	1
auto[1879048192:2013265919]	auto[0]	42	1			T17	2		T18	1		T59	1
auto[1879048192:2013265919]	auto[1]	65	1			T28	1		T59	1		T150	1
auto[2013265920:2147483647]	auto[0]	41	1			T59	1		T27	1		T142	1
auto[2013265920:2147483647]	auto[1]	50	1			T28	1		T59	3		T141	1
auto[2147483648:2281701375]	auto[0]	33	1			T18	1		T230	1		T222	1
auto[2147483648:2281701375]	auto[1]	54	1			T59	2		T161	1		T419	1
auto[2281701376:2415919103]	auto[0]	38	1			T36	1		T47	1		T26	1
auto[2281701376:2415919103]	auto[1]	65	1			T18	1		T59	2		T5	1
auto[2415919104:2550136831]	auto[0]	44	1			T4	1		T36	1		T28	1
auto[2415919104:2550136831]	auto[1]	60	1			T213	1		T218	1		T27	1
auto[2550136832:2684354559]	auto[0]	48	1			T24	1		T162	1		T27	1
auto[2550136832:2684354559]	auto[1]	58	1			T18	3		T213	1		T53	1
auto[2684354560:2818572287]	auto[0]	38	1			T24	1		T226	1		T59	2
auto[2684354560:2818572287]	auto[1]	53	1			T36	1		T47	1		T226	1
auto[2818572288:2952790015]	auto[0]	55	1			T213	1		T218	1		T269	2
auto[2818572288:2952790015]	auto[1]	54	1			T13	1		T17	1		T18	1
auto[2952790016:3087007743]	auto[0]	50	1			T105	1		T108	1		T104	1
auto[2952790016:3087007743]	auto[1]	46	1			T220	2		T215	1		T229	1
auto[3087007744:3221225471]	auto[0]	53	1			T18	1		T24	1		T59	1
auto[3087007744:3221225471]	auto[1]	48	1			T13	1		T147	1		T226	1
auto[3221225472:3355443199]	auto[0]	51	1			T17	1		T279	1		T280	1
auto[3221225472:3355443199]	auto[1]	51	1			T13	1		T26	1		T59	1
auto[3355443200:3489660927]	auto[0]	43	1			T223	1		T57	2		T43	2
auto[3355443200:3489660927]	auto[1]	51	1			T18	2		T147	1		T150	1
auto[3489660928:3623878655]	auto[0]	51	1			T24	1		T38	1		T108	1
auto[3489660928:3623878655]	auto[1]	59	1			T2	1		T59	1		T215	1
auto[3623878656:3758096383]	auto[0]	48	1			T18	1		T25	1		T57	2
auto[3623878656:3758096383]	auto[1]	52	1			T13	1		T59	1		T38	1
auto[3758096384:3892314111]	auto[0]	40	1			T47	1		T26	1		T163	2
auto[3758096384:3892314111]	auto[1]	53	1			T13	1		T131	1		T227	1
auto[3892314112:4026531839]	auto[0]	34	1			T18	1		T36	1		T218	1
auto[3892314112:4026531839]	auto[1]	49	1			T18	1		T59	1		T53	1
auto[4026531840:4160749567]	auto[0]	50	1			T215	1		T227	1		T105	1
auto[4026531840:4160749567]	auto[1]	52	1			T18	1		T36	1		T147	1
auto[4160749568:4294967295]	auto[0]	49	1			T4	1		T220	1		T59	2
auto[4160749568:4294967295]	auto[1]	35	1			T90	1		T5	1		T138	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1431

1

T2

4

T4

3

T13

1

auto[1]

1659

1

T2

3

T4

1

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T42	1		T25	1		T53	1
auto[134217728:268435455]	88	1			T2	1		T18	1		T131	1
auto[268435456:402653183]	75	1			T4	1		T131	1		T59	1
auto[402653184:536870911]	103	1			T4	1		T13	1		T28	1
auto[536870912:671088639]	108	1			T18	2		T90	1		T46	1
auto[671088640:805306367]	81	1			T42	1		T59	1		T213	1
auto[805306368:939524095]	95	1			T28	1		T131	1		T59	2
auto[939524096:1073741823]	116	1			T13	1		T90	1		T218	1
auto[1073741824:1207959551]	116	1			T5	1		T215	2		T27	1
auto[1207959552:1342177279]	90	1			T13	1		T18	1		T24	1
auto[1342177280:1476395007]	91	1			T5	1		T279	1		T222	1
auto[1476395008:1610612735]	113	1			T18	2		T46	1		T220	1
auto[1610612736:1744830463]	111	1			T28	1		T5	1		T161	1
auto[1744830464:1879048191]	98	1			T13	1		T18	2		T36	1
auto[1879048192:2013265919]	91	1			T28	1		T226	1		T220	1
auto[2013265920:2147483647]	113	1			T219	1		T27	1		T227	1
auto[2147483648:2281701375]	106	1			T13	1		T17	1		T18	2
auto[2281701376:2415919103]	102	1			T17	1		T18	1		T36	1
auto[2415919104:2550136831]	99	1			T18	1		T59	2		T150	1
auto[2550136832:2684354559]	86	1			T2	1		T13	1		T36	1
auto[2684354560:2818572287]	93	1			T2	1		T24	2		T59	1
auto[2818572288:2952790015]	91	1			T2	1		T18	2		T59	4
auto[2952790016:3087007743]	85	1			T2	1		T17	2		T36	1
auto[3087007744:3221225471]	92	1			T4	2		T24	1		T147	1
auto[3221225472:3355443199]	81	1			T17	2		T18	3		T59	1
auto[3355443200:3489660927]	95	1			T2	2		T24	1		T25	1
auto[3489660928:3623878655]	106	1			T18	1		T28	1		T24	1
auto[3623878656:3758096383]	93	1			T18	3		T28	1		T147	1
auto[3758096384:3892314111]	99	1			T59	4		T213	1		T218	1
auto[3892314112:4026531839]	94	1			T18	1		T47	1		T220	1
auto[4026531840:4160749567]	80	1			T18	2		T59	1		T163	1
auto[4160749568:4294967295]	97	1			T36	2		T24	1		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T230	1		T279	1		T105	1
auto[0:134217727]	auto[1]	55	1			T42	1		T25	1		T53	1
auto[134217728:268435455]	auto[0]	44	1			T2	1		T131	1		T104	1
auto[134217728:268435455]	auto[1]	44	1			T18	1		T138	1		T222	1
auto[268435456:402653183]	auto[0]	32	1			T4	1		T131	1		T162	1
auto[268435456:402653183]	auto[1]	43	1			T59	1		T38	1		T27	1
auto[402653184:536870911]	auto[0]	48	1			T13	1		T220	1		T138	1
auto[402653184:536870911]	auto[1]	55	1			T4	1		T28	1		T147	1
auto[536870912:671088639]	auto[0]	50	1			T18	2		T218	1		T224	1
auto[536870912:671088639]	auto[1]	58	1			T90	1		T46	1		T59	1
auto[671088640:805306367]	auto[0]	37	1			T109	1		T43	1		T132	1
auto[671088640:805306367]	auto[1]	44	1			T42	1		T59	1		T213	1
auto[805306368:939524095]	auto[0]	52	1			T28	1		T131	1		T59	1
auto[805306368:939524095]	auto[1]	43	1			T59	1		T27	1		T61	1
auto[939524096:1073741823]	auto[0]	57	1			T218	1		T142	1		T300	1
auto[939524096:1073741823]	auto[1]	59	1			T13	1		T90	1		T162	1
auto[1073741824:1207959551]	auto[0]	55	1			T215	2		T257	1		T222	1
auto[1073741824:1207959551]	auto[1]	61	1			T5	1		T27	1		T279	2
auto[1207959552:1342177279]	auto[0]	40	1			T18	1		T24	1		T215	1
auto[1207959552:1342177279]	auto[1]	50	1			T13	1		T47	1		T226	1
auto[1342177280:1476395007]	auto[0]	42	1			T228	1		T57	2		T58	2
auto[1342177280:1476395007]	auto[1]	49	1			T5	1		T279	1		T222	1
auto[1476395008:1610612735]	auto[0]	63	1			T59	1		T5	1		T63	1
auto[1476395008:1610612735]	auto[1]	50	1			T18	2		T46	1		T220	1
auto[1610612736:1744830463]	auto[0]	43	1			T28	1		T5	1		T218	1
auto[1610612736:1744830463]	auto[1]	68	1			T161	1		T300	1		T29	1
auto[1744830464:1879048191]	auto[0]	42	1			T18	1		T36	1		T59	1
auto[1744830464:1879048191]	auto[1]	56	1			T13	1		T18	1		T160	1
auto[1879048192:2013265919]	auto[0]	43	1			T226	1		T221	1		T280	1
auto[1879048192:2013265919]	auto[1]	48	1			T28	1		T220	1		T287	1
auto[2013265920:2147483647]	auto[0]	51	1			T219	1		T27	1		T227	1
auto[2013265920:2147483647]	auto[1]	62	1			T141	1		T65	1		T61	1
auto[2147483648:2281701375]	auto[0]	44	1			T17	1		T18	1		T59	1
auto[2147483648:2281701375]	auto[1]	62	1			T13	1		T18	1		T36	2
auto[2281701376:2415919103]	auto[0]	45	1			T17	1		T36	1		T218	1
auto[2281701376:2415919103]	auto[1]	57	1			T18	1		T131	1		T215	1
auto[2415919104:2550136831]	auto[0]	42	1			T18	1		T138	1		T57	1
auto[2415919104:2550136831]	auto[1]	57	1			T59	2		T150	1		T96	2
auto[2550136832:2684354559]	auto[0]	31	1			T2	1		T36	1		T26	1
auto[2550136832:2684354559]	auto[1]	55	1			T13	1		T59	1		T150	1
auto[2684354560:2818572287]	auto[0]	48	1			T24	2		T59	1		T57	2
auto[2684354560:2818572287]	auto[1]	45	1			T2	1		T280	1		T66	1
auto[2818572288:2952790015]	auto[0]	41	1			T2	1		T18	1		T59	1
auto[2818572288:2952790015]	auto[1]	50	1			T18	1		T59	3		T162	1
auto[2952790016:3087007743]	auto[0]	42	1			T2	1		T17	1		T24	1
auto[2952790016:3087007743]	auto[1]	43	1			T17	1		T36	1		T26	1
auto[3087007744:3221225471]	auto[0]	47	1			T4	2		T24	1		T47	1
auto[3087007744:3221225471]	auto[1]	45	1			T147	1		T226	1		T59	1
auto[3221225472:3355443199]	auto[0]	38	1			T17	2		T18	2		T59	1
auto[3221225472:3355443199]	auto[1]	43	1			T18	1		T150	1		T53	1
auto[3355443200:3489660927]	auto[0]	50	1			T24	1		T25	1		T226	1
auto[3355443200:3489660927]	auto[1]	45	1			T2	2		T220	1		T59	2
auto[3489660928:3623878655]	auto[0]	48	1			T24	1		T26	1		T59	1
auto[3489660928:3623878655]	auto[1]	58	1			T18	1		T28	1		T213	1
auto[3623878656:3758096383]	auto[0]	36	1			T18	1		T59	1		T27	1
auto[3623878656:3758096383]	auto[1]	57	1			T18	2		T28	1		T147	1
auto[3758096384:3892314111]	auto[0]	53	1			T59	4		T213	1		T218	1
auto[3758096384:3892314111]	auto[1]	46	1			T96	2		T141	1		T39	1
auto[3892314112:4026531839]	auto[0]	36	1			T47	1		T220	1		T108	1
auto[3892314112:4026531839]	auto[1]	58	1			T18	1		T59	2		T314	1
auto[4026531840:4160749567]	auto[0]	39	1			T163	1		T273	1		T43	1
auto[4026531840:4160749567]	auto[1]	41	1			T18	2		T59	1		T141	1
auto[4160749568:4294967295]	auto[0]	45	1			T36	1		T24	1		T38	1
auto[4160749568:4294967295]	auto[1]	52	1			T36	1		T257	1		T314	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1432

1

T2

4

T4

3

T13

1

auto[1]

1658

1

T2

3

T4

1

T13

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T18	2		T25	1		T59	1
auto[134217728:268435455]	111	1			T18	2		T226	1		T162	1
auto[268435456:402653183]	101	1			T2	1		T13	1		T131	1
auto[402653184:536870911]	119	1			T4	1		T17	1		T24	1
auto[536870912:671088639]	96	1			T17	2		T220	1		T59	1
auto[671088640:805306367]	97	1			T26	1		T59	2		T150	1
auto[805306368:939524095]	95	1			T17	1		T18	1		T24	1
auto[939524096:1073741823]	104	1			T2	2		T36	1		T147	1
auto[1073741824:1207959551]	88	1			T18	3		T36	1		T59	1
auto[1207959552:1342177279]	100	1			T59	3		T96	1		T60	1
auto[1342177280:1476395007]	83	1			T2	1		T24	1		T226	1
auto[1476395008:1610612735]	98	1			T59	1		T215	2		T279	2
auto[1610612736:1744830463]	114	1			T13	1		T17	1		T18	1
auto[1744830464:1879048191]	95	1			T18	1		T90	1		T47	1
auto[1879048192:2013265919]	92	1			T18	1		T42	1		T28	1
auto[2013265920:2147483647]	96	1			T59	2		T269	1		T66	1
auto[2147483648:2281701375]	98	1			T18	1		T131	1		T26	1
auto[2281701376:2415919103]	89	1			T18	1		T28	1		T24	1
auto[2415919104:2550136831]	99	1			T2	1		T18	1		T24	1
auto[2550136832:2684354559]	82	1			T2	1		T26	1		T5	1
auto[2684354560:2818572287]	101	1			T13	2		T42	1		T90	1
auto[2818572288:2952790015]	102	1			T4	1		T59	2		T163	1
auto[2952790016:3087007743]	87	1			T17	1		T36	2		T28	1
auto[3087007744:3221225471]	109	1			T4	1		T13	1		T18	2
auto[3221225472:3355443199]	95	1			T4	1		T13	1		T18	2
auto[3355443200:3489660927]	93	1			T18	2		T28	1		T25	1
auto[3489660928:3623878655]	86	1			T18	2		T28	1		T218	1
auto[3623878656:3758096383]	97	1			T36	1		T226	1		T59	1
auto[3758096384:3892314111]	85	1			T28	1		T59	1		T108	1
auto[3892314112:4026531839]	89	1			T18	1		T47	1		T59	2
auto[4026531840:4160749567]	100	1			T2	1		T18	1		T36	1
auto[4160749568:4294967295]	94	1			T36	1		T160	1		T46	1