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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4176 1 T2 12 T4 8 T13 10
auto[1] 2004 1 T2 2 T13 2 T17 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 188 1 T18 2 T59 2 T5 2
auto[134217728:268435455] 192 1 T36 2 T24 4 T5 4
auto[268435456:402653183] 188 1 T13 2 T18 4 T42 2
auto[402653184:536870911] 186 1 T24 2 T147 2 T131 2
auto[536870912:671088639] 210 1 T26 2 T59 2 T213 2
auto[671088640:805306367] 222 1 T2 2 T131 2 T220 2
auto[805306368:939524095] 194 1 T13 2 T24 2 T226 2
auto[939524096:1073741823] 194 1 T59 2 T279 2 T221 2
auto[1073741824:1207959551] 212 1 T13 2 T18 2 T46 2
auto[1207959552:1342177279] 146 1 T2 2 T18 2 T219 2
auto[1342177280:1476395007] 244 1 T17 2 T18 2 T160 2
auto[1476395008:1610612735] 222 1 T4 2 T17 2 T18 2
auto[1610612736:1744830463] 224 1 T2 2 T18 2 T36 2
auto[1744830464:1879048191] 156 1 T4 2 T18 2 T28 2
auto[1879048192:2013265919] 180 1 T17 2 T18 4 T36 4
auto[2013265920:2147483647] 198 1 T18 2 T226 2 T59 4
auto[2147483648:2281701375] 206 1 T18 2 T36 2 T226 2
auto[2281701376:2415919103] 196 1 T47 2 T59 6 T161 2
auto[2415919104:2550136831] 182 1 T25 2 T220 2 T138 2
auto[2550136832:2684354559] 200 1 T18 2 T28 2 T26 2
auto[2684354560:2818572287] 176 1 T17 2 T28 2 T38 4
auto[2818572288:2952790015] 190 1 T2 2 T18 2 T59 2
auto[2952790016:3087007743] 208 1 T4 2 T13 2 T18 2
auto[3087007744:3221225471] 166 1 T2 2 T36 2 T59 2
auto[3221225472:3355443199] 204 1 T18 2 T36 2 T90 2
auto[3355443200:3489660927] 184 1 T13 2 T28 4 T131 2
auto[3489660928:3623878655] 196 1 T4 2 T13 2 T18 4
auto[3623878656:3758096383] 196 1 T17 2 T18 4 T47 2
auto[3758096384:3892314111] 170 1 T24 4 T220 2 T59 4
auto[3892314112:4026531839] 212 1 T2 2 T18 2 T46 2
auto[4026531840:4160749567] 178 1 T18 2 T59 6 T27 2
auto[4160749568:4294967295] 160 1 T2 2 T17 2 T18 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 120 1 T18 2 T59 2 T5 2
auto[0:134217727] auto[1] 68 1 T27 2 T229 2 T142 2
auto[134217728:268435455] auto[0] 134 1 T24 2 T5 4 T218 2
auto[134217728:268435455] auto[1] 58 1 T36 2 T24 2 T38 2
auto[268435456:402653183] auto[0] 122 1 T18 4 T42 2 T59 2
auto[268435456:402653183] auto[1] 66 1 T13 2 T24 2 T222 2
auto[402653184:536870911] auto[0] 132 1 T24 2 T147 2 T131 2
auto[402653184:536870911] auto[1] 54 1 T287 2 T64 2 T76 2
auto[536870912:671088639] auto[0] 146 1 T26 2 T59 2 T53 2
auto[536870912:671088639] auto[1] 64 1 T213 2 T223 2 T109 2
auto[671088640:805306367] auto[0] 142 1 T2 2 T131 2 T220 2
auto[671088640:805306367] auto[1] 80 1 T105 2 T273 2 T306 2
auto[805306368:939524095] auto[0] 132 1 T13 2 T24 2 T226 2
auto[805306368:939524095] auto[1] 62 1 T314 2 T29 2 T61 2
auto[939524096:1073741823] auto[0] 132 1 T221 2 T66 2 T30 2
auto[939524096:1073741823] auto[1] 62 1 T59 2 T279 2 T273 2
auto[1073741824:1207959551] auto[0] 138 1 T13 2 T46 2 T213 2
auto[1073741824:1207959551] auto[1] 74 1 T18 2 T138 2 T419 2
auto[1207959552:1342177279] auto[0] 94 1 T2 2 T18 2 T162 2
auto[1207959552:1342177279] auto[1] 52 1 T219 2 T108 2 T110 2
auto[1342177280:1476395007] auto[0] 162 1 T17 2 T46 2 T59 4
auto[1342177280:1476395007] auto[1] 82 1 T18 2 T160 2 T47 2
auto[1476395008:1610612735] auto[0] 152 1 T4 2 T17 2 T59 2
auto[1476395008:1610612735] auto[1] 70 1 T18 2 T25 2 T147 4
auto[1610612736:1744830463] auto[0] 148 1 T2 2 T36 2 T24 2
auto[1610612736:1744830463] auto[1] 76 1 T18 2 T144 2 T273 2
auto[1744830464:1879048191] auto[0] 100 1 T4 2 T18 2 T28 2
auto[1744830464:1879048191] auto[1] 56 1 T257 2 T54 2 T57 2
auto[1879048192:2013265919] auto[0] 124 1 T17 2 T18 2 T36 4
auto[1879048192:2013265919] auto[1] 56 1 T18 2 T42 2 T218 2
auto[2013265920:2147483647] auto[0] 142 1 T18 2 T226 2 T59 4
auto[2013265920:2147483647] auto[1] 56 1 T53 2 T419 2 T132 2
auto[2147483648:2281701375] auto[0] 132 1 T36 2 T226 2 T5 2
auto[2147483648:2281701375] auto[1] 74 1 T18 2 T426 2 T110 2
auto[2281701376:2415919103] auto[0] 124 1 T47 2 T59 6 T161 2
auto[2281701376:2415919103] auto[1] 72 1 T27 2 T104 2 T221 2
auto[2415919104:2550136831] auto[0] 124 1 T220 2 T138 2 T61 2
auto[2415919104:2550136831] auto[1] 58 1 T25 2 T105 2 T63 2
auto[2550136832:2684354559] auto[0] 120 1 T18 2 T28 2 T218 2
auto[2550136832:2684354559] auto[1] 80 1 T26 2 T215 2 T54 2
auto[2684354560:2818572287] auto[0] 128 1 T17 2 T38 4 T141 2
auto[2684354560:2818572287] auto[1] 48 1 T28 2 T222 2 T269 2
auto[2818572288:2952790015] auto[0] 130 1 T2 2 T18 2 T59 2
auto[2818572288:2952790015] auto[1] 60 1 T132 4 T58 2 T99 2
auto[2952790016:3087007743] auto[0] 146 1 T4 2 T13 2 T18 2
auto[2952790016:3087007743] auto[1] 62 1 T287 2 T306 2 T51 2
auto[3087007744:3221225471] auto[0] 114 1 T2 2 T36 2 T59 2
auto[3087007744:3221225471] auto[1] 52 1 T267 2 T58 2 T152 2
auto[3221225472:3355443199] auto[0] 130 1 T36 2 T27 2 T279 2
auto[3221225472:3355443199] auto[1] 74 1 T18 2 T90 2 T162 2
auto[3355443200:3489660927] auto[0] 120 1 T13 2 T28 4 T131 2
auto[3355443200:3489660927] auto[1] 64 1 T59 2 T163 2 T73 2
auto[3489660928:3623878655] auto[0] 128 1 T4 2 T13 2 T18 2
auto[3489660928:3623878655] auto[1] 68 1 T18 2 T223 2 T273 2
auto[3623878656:3758096383] auto[0] 136 1 T18 2 T5 2 T230 2
auto[3623878656:3758096383] auto[1] 60 1 T17 2 T18 2 T47 2
auto[3758096384:3892314111] auto[0] 124 1 T220 2 T59 4 T224 2
auto[3758096384:3892314111] auto[1] 46 1 T24 4 T63 2 T51 2
auto[3892314112:4026531839] auto[0] 154 1 T46 2 T59 2 T138 2
auto[3892314112:4026531839] auto[1] 58 1 T2 2 T18 2 T38 2
auto[4026531840:4160749567] auto[0] 134 1 T18 2 T59 4 T27 2
auto[4026531840:4160749567] auto[1] 44 1 T59 2 T144 2 T314 2
auto[4160749568:4294967295] auto[0] 112 1 T2 2 T17 2 T18 2
auto[4160749568:4294967295] auto[1] 48 1 T98 2 T204 2 T74 2

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