Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T2

7

T4

4

T13

6

auto[1]

261

1

T13

8

T36

5

T42

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	74	1			T13	1		T24	1		T25	1
auto[134217728:268435455]	99	1			T36	1		T226	1		T150	1
auto[268435456:402653183]	96	1			T18	1		T42	1		T131	1
auto[402653184:536870911]	92	1			T13	1		T28	1		T24	1
auto[536870912:671088639]	103	1			T17	1		T18	1		T36	1
auto[671088640:805306367]	83	1			T18	1		T59	1		T218	1
auto[805306368:939524095]	88	1			T4	1		T36	1		T42	2
auto[939524096:1073741823]	91	1			T2	1		T47	1		T226	1
auto[1073741824:1207959551]	105	1			T42	1		T28	1		T59	1
auto[1207959552:1342177279]	96	1			T13	1		T18	1		T24	1
auto[1342177280:1476395007]	106	1			T2	1		T13	1		T36	1
auto[1476395008:1610612735]	91	1			T2	1		T18	1		T226	1
auto[1610612736:1744830463]	97	1			T42	1		T131	1		T5	1
auto[1744830464:1879048191]	94	1			T4	2		T13	1		T17	1
auto[1879048192:2013265919]	98	1			T28	1		T147	1		T131	1
auto[2013265920:2147483647]	88	1			T18	3		T36	2		T28	1
auto[2147483648:2281701375]	98	1			T2	1		T4	1		T13	3
auto[2281701376:2415919103]	83	1			T18	1		T46	1		T59	1
auto[2415919104:2550136831]	93	1			T18	2		T24	1		T150	1
auto[2550136832:2684354559]	101	1			T18	1		T36	1		T59	2
auto[2684354560:2818572287]	99	1			T2	1		T13	1		T36	1
auto[2818572288:2952790015]	100	1			T18	3		T147	1		T220	1
auto[2952790016:3087007743]	92	1			T13	1		T36	3		T28	1
auto[3087007744:3221225471]	106	1			T18	1		T46	1		T59	4
auto[3221225472:3355443199]	84	1			T2	1		T13	1		T42	2
auto[3355443200:3489660927]	91	1			T36	1		T28	1		T24	1
auto[3489660928:3623878655]	110	1			T47	1		T59	2		T213	1
auto[3623878656:3758096383]	89	1			T18	1		T226	1		T287	1
auto[3758096384:3892314111]	92	1			T13	2		T42	1		T59	3
auto[3892314112:4026531839]	102	1			T17	1		T42	4		T160	1
auto[4026531840:4160749567]	90	1			T2	1		T13	1		T18	1
auto[4160749568:4294967295]	110	1			T18	1		T131	1		T220	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	66	1			T24	1		T25	1		T27	1
auto[0:134217727]	auto[1]	8	1			T13	1		T163	1		T151	2
auto[134217728:268435455]	auto[0]	92	1			T226	1		T230	1		T219	1
auto[134217728:268435455]	auto[1]	7	1			T36	1		T150	1		T151	1
auto[268435456:402653183]	auto[0]	84	1			T18	1		T131	1		T218	2
auto[268435456:402653183]	auto[1]	12	1			T42	1		T150	1		T88	1
auto[402653184:536870911]	auto[0]	83	1			T28	1		T24	1		T90	1
auto[402653184:536870911]	auto[1]	9	1			T13	1		T147	1		T150	1
auto[536870912:671088639]	auto[0]	96	1			T17	1		T18	1		T36	1
auto[536870912:671088639]	auto[1]	7	1			T163	1		T151	1		T289	1
auto[671088640:805306367]	auto[0]	78	1			T18	1		T59	1		T218	1
auto[671088640:805306367]	auto[1]	5	1			T151	1		T413	1		T255	1
auto[805306368:939524095]	auto[0]	76	1			T4	1		T42	1		T220	1
auto[805306368:939524095]	auto[1]	12	1			T36	1		T42	1		T163	1
auto[939524096:1073741823]	auto[0]	82	1			T2	1		T47	1		T226	1
auto[939524096:1073741823]	auto[1]	9	1			T163	1		T314	1		T311	1
auto[1073741824:1207959551]	auto[0]	98	1			T28	1		T59	1		T279	1
auto[1073741824:1207959551]	auto[1]	7	1			T42	1		T161	1		T292	1
auto[1207959552:1342177279]	auto[0]	86	1			T13	1		T18	1		T24	1
auto[1207959552:1342177279]	auto[1]	10	1			T273	1		T88	1		T413	1
auto[1342177280:1476395007]	auto[0]	96	1			T2	1		T36	1		T24	1
auto[1342177280:1476395007]	auto[1]	10	1			T13	1		T88	1		T400	1
auto[1476395008:1610612735]	auto[0]	84	1			T2	1		T18	1		T226	1
auto[1476395008:1610612735]	auto[1]	7	1			T150	1		T144	1		T151	1
auto[1610612736:1744830463]	auto[0]	90	1			T131	1		T5	1		T215	1
auto[1610612736:1744830463]	auto[1]	7	1			T42	1		T161	1		T144	1
auto[1744830464:1879048191]	auto[0]	86	1			T4	2		T13	1		T17	1
auto[1744830464:1879048191]	auto[1]	8	1			T160	1		T163	1		T144	1
auto[1879048192:2013265919]	auto[0]	90	1			T28	1		T147	1		T131	1
auto[1879048192:2013265919]	auto[1]	8	1			T150	1		T292	1		T422	1
auto[2013265920:2147483647]	auto[0]	83	1			T18	3		T36	2		T28	1
auto[2013265920:2147483647]	auto[1]	5	1			T88	1		T413	1		T329	1
auto[2147483648:2281701375]	auto[0]	86	1			T2	1		T4	1		T13	1
auto[2147483648:2281701375]	auto[1]	12	1			T13	2		T147	1		T422	1
auto[2281701376:2415919103]	auto[0]	79	1			T18	1		T46	1		T59	1
auto[2281701376:2415919103]	auto[1]	4	1			T400	1		T427	1		T311	1
auto[2415919104:2550136831]	auto[0]	85	1			T18	2		T24	1		T150	1
auto[2415919104:2550136831]	auto[1]	8	1			T88	2		T311	2		T428	1
auto[2550136832:2684354559]	auto[0]	95	1			T18	1		T36	1		T59	2
auto[2550136832:2684354559]	auto[1]	6	1			T163	1		T289	1		T256	1
auto[2684354560:2818572287]	auto[0]	90	1			T2	1		T13	1		T36	1
auto[2684354560:2818572287]	auto[1]	9	1			T151	1		T88	1		T292	1
auto[2818572288:2952790015]	auto[0]	91	1			T18	3		T147	1		T220	1
auto[2818572288:2952790015]	auto[1]	9	1			T151	1		T427	1		T311	1
auto[2952790016:3087007743]	auto[0]	86	1			T36	1		T28	1		T59	1
auto[2952790016:3087007743]	auto[1]	6	1			T13	1		T36	2		T273	1
auto[3087007744:3221225471]	auto[0]	95	1			T18	1		T46	1		T59	4
auto[3087007744:3221225471]	auto[1]	11	1			T144	1		T354	1		T277	2
auto[3221225472:3355443199]	auto[0]	75	1			T2	1		T42	1		T46	1
auto[3221225472:3355443199]	auto[1]	9	1			T13	1		T42	1		T147	1
auto[3355443200:3489660927]	auto[0]	83	1			T28	1		T24	1		T26	1
auto[3355443200:3489660927]	auto[1]	8	1			T36	1		T273	1		T152	1
auto[3489660928:3623878655]	auto[0]	101	1			T47	1		T59	2		T213	1
auto[3489660928:3623878655]	auto[1]	9	1			T273	2		T270	1		T312	1
auto[3623878656:3758096383]	auto[0]	84	1			T18	1		T226	1		T287	1
auto[3623878656:3758096383]	auto[1]	5	1			T163	1		T277	1		T414	1
auto[3758096384:3892314111]	auto[0]	82	1			T13	1		T59	3		T218	1
auto[3758096384:3892314111]	auto[1]	10	1			T13	1		T42	1		T163	1
auto[3892314112:4026531839]	auto[0]	89	1			T17	1		T160	1		T59	1
auto[3892314112:4026531839]	auto[1]	13	1			T42	4		T152	1		T292	1
auto[4026531840:4160749567]	auto[0]	87	1			T2	1		T13	1		T18	1
auto[4026531840:4160749567]	auto[1]	3	1			T255	1		T311	1		T421	1
auto[4160749568:4294967295]	auto[0]	102	1			T18	1		T131	1		T220	1
auto[4160749568:4294967295]	auto[1]	8	1			T161	2		T163	1		T422	1