Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6707

1

T2

24

T4

8

T13

11

auto[1]

304

1

T13

7

T36

9

T42

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2796	1			T2	11		T4	4		T13	4
auto[134217728:268435455]	162	1			T13	1		T18	2		T36	2
auto[268435456:402653183]	149	1			T18	1		T25	2		T131	2
auto[402653184:536870911]	155	1			T2	1		T13	1		T18	2
auto[536870912:671088639]	147	1			T36	1		T59	2		T213	1
auto[671088640:805306367]	135	1			T13	1		T36	1		T59	2
auto[805306368:939524095]	113	1			T13	2		T18	1		T42	1
auto[939524096:1073741823]	120	1			T17	1		T28	2		T59	3
auto[1073741824:1207959551]	150	1			T4	1		T18	1		T36	1
auto[1207959552:1342177279]	145	1			T2	1		T13	1		T36	1
auto[1342177280:1476395007]	132	1			T36	1		T42	2		T28	1
auto[1476395008:1610612735]	135	1			T18	3		T36	1		T28	1
auto[1610612736:1744830463]	142	1			T13	1		T36	1		T28	1
auto[1744830464:1879048191]	128	1			T13	1		T17	1		T42	1
auto[1879048192:2013265919]	134	1			T160	1		T46	1		T59	2
auto[2013265920:2147483647]	119	1			T4	1		T24	1		T147	1
auto[2147483648:2281701375]	135	1			T2	2		T24	1		T47	1
auto[2281701376:2415919103]	119	1			T24	1		T59	1		T142	1
auto[2415919104:2550136831]	137	1			T18	2		T36	1		T42	1
auto[2550136832:2684354559]	116	1			T13	1		T59	1		T213	1
auto[2684354560:2818572287]	119	1			T18	1		T42	1		T28	2
auto[2818572288:2952790015]	115	1			T2	1		T36	2		T25	1
auto[2952790016:3087007743]	152	1			T59	4		T38	1		T223	2
auto[3087007744:3221225471]	129	1			T2	1		T13	2		T18	2
auto[3221225472:3355443199]	123	1			T2	1		T13	1		T18	2
auto[3355443200:3489660927]	116	1			T36	1		T160	2		T26	1
auto[3489660928:3623878655]	151	1			T2	1		T13	1		T18	1
auto[3623878656:3758096383]	156	1			T2	1		T18	2		T42	1
auto[3758096384:3892314111]	146	1			T18	2		T24	1		T147	1
auto[3892314112:4026531839]	160	1			T2	1		T4	1		T13	1
auto[4026531840:4160749567]	138	1			T18	1		T131	1		T59	3
auto[4160749568:4294967295]	137	1			T2	3		T4	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2792	1			T2	11		T4	4		T13	4
auto[0:134217727]	auto[1]	4	1			T256	2		T417	1		T420	1
auto[134217728:268435455]	auto[0]	150	1			T13	1		T18	2		T36	2
auto[134217728:268435455]	auto[1]	12	1			T144	1		T400	1		T292	1
auto[268435456:402653183]	auto[0]	139	1			T18	1		T25	2		T131	2
auto[268435456:402653183]	auto[1]	10	1			T161	1		T88	2		T292	1
auto[402653184:536870911]	auto[0]	146	1			T2	1		T18	2		T147	1
auto[402653184:536870911]	auto[1]	9	1			T13	1		T151	1		T88	1
auto[536870912:671088639]	auto[0]	141	1			T36	1		T59	2		T213	1
auto[536870912:671088639]	auto[1]	6	1			T144	1		T413	1		T421	1
auto[671088640:805306367]	auto[0]	126	1			T59	2		T215	1		T279	1
auto[671088640:805306367]	auto[1]	9	1			T13	1		T36	1		T150	1
auto[805306368:939524095]	auto[0]	105	1			T13	2		T18	1		T24	1
auto[805306368:939524095]	auto[1]	8	1			T42	1		T150	1		T292	1
auto[939524096:1073741823]	auto[0]	107	1			T17	1		T28	2		T59	3
auto[939524096:1073741823]	auto[1]	13	1			T161	1		T314	1		T273	1
auto[1073741824:1207959551]	auto[0]	136	1			T4	1		T18	1		T90	2
auto[1073741824:1207959551]	auto[1]	14	1			T36	1		T42	1		T161	1
auto[1207959552:1342177279]	auto[0]	138	1			T2	1		T13	1		T36	1
auto[1207959552:1342177279]	auto[1]	7	1			T273	1		T292	1		T312	1
auto[1342177280:1476395007]	auto[0]	118	1			T36	1		T28	1		T213	2
auto[1342177280:1476395007]	auto[1]	14	1			T42	2		T160	1		T314	1
auto[1476395008:1610612735]	auto[0]	127	1			T18	3		T28	1		T24	1
auto[1476395008:1610612735]	auto[1]	8	1			T36	1		T160	1		T144	1
auto[1610612736:1744830463]	auto[0]	131	1			T28	1		T226	1		T59	2
auto[1610612736:1744830463]	auto[1]	11	1			T13	1		T36	1		T150	1
auto[1744830464:1879048191]	auto[0]	125	1			T13	1		T17	1		T28	1
auto[1744830464:1879048191]	auto[1]	3	1			T42	1		T400	1		T343	1
auto[1879048192:2013265919]	auto[0]	124	1			T46	1		T59	2		T162	1
auto[1879048192:2013265919]	auto[1]	10	1			T160	1		T163	1		T88	1
auto[2013265920:2147483647]	auto[0]	111	1			T4	1		T24	1		T147	1
auto[2013265920:2147483647]	auto[1]	8	1			T88	1		T289	1		T255	1
auto[2147483648:2281701375]	auto[0]	124	1			T2	2		T24	1		T47	1
auto[2147483648:2281701375]	auto[1]	11	1			T150	1		T144	1		T273	1
auto[2281701376:2415919103]	auto[0]	108	1			T24	1		T59	1		T142	1
auto[2281701376:2415919103]	auto[1]	11	1			T306	1		T152	1		T422	1
auto[2415919104:2550136831]	auto[0]	126	1			T18	2		T36	1		T24	1
auto[2415919104:2550136831]	auto[1]	11	1			T42	1		T160	1		T150	1
auto[2550136832:2684354559]	auto[0]	105	1			T59	1		T213	1		T215	1
auto[2550136832:2684354559]	auto[1]	11	1			T13	1		T161	1		T144	2
auto[2684354560:2818572287]	auto[0]	107	1			T18	1		T28	2		T25	1
auto[2684354560:2818572287]	auto[1]	12	1			T42	1		T161	1		T144	1
auto[2818572288:2952790015]	auto[0]	103	1			T2	1		T25	1		T90	1
auto[2818572288:2952790015]	auto[1]	12	1			T36	2		T150	1		T88	1
auto[2952790016:3087007743]	auto[0]	144	1			T59	4		T38	1		T223	2
auto[2952790016:3087007743]	auto[1]	8	1			T400	1		T422	2		T423	1
auto[3087007744:3221225471]	auto[0]	116	1			T2	1		T13	1		T18	2
auto[3087007744:3221225471]	auto[1]	13	1			T13	1		T36	1		T42	2
auto[3221225472:3355443199]	auto[0]	117	1			T2	1		T18	2		T36	1
auto[3221225472:3355443199]	auto[1]	6	1			T13	1		T163	1		T151	2
auto[3355443200:3489660927]	auto[0]	111	1			T36	1		T160	1		T26	1
auto[3355443200:3489660927]	auto[1]	5	1			T160	1		T311	1		T256	1
auto[3489660928:3623878655]	auto[0]	141	1			T2	1		T18	1		T36	1
auto[3489660928:3623878655]	auto[1]	10	1			T13	1		T36	2		T400	1
auto[3623878656:3758096383]	auto[0]	145	1			T2	1		T18	2		T28	1
auto[3623878656:3758096383]	auto[1]	11	1			T42	1		T144	3		T273	1
auto[3758096384:3892314111]	auto[0]	135	1			T18	2		T24	1		T59	1
auto[3758096384:3892314111]	auto[1]	11	1			T147	1		T314	1		T88	2
auto[3892314112:4026531839]	auto[0]	152	1			T2	1		T4	1		T13	1
auto[3892314112:4026531839]	auto[1]	8	1			T42	1		T160	1		T144	1
auto[4026531840:4160749567]	auto[0]	131	1			T18	1		T131	1		T59	3
auto[4026531840:4160749567]	auto[1]	7	1			T151	1		T88	1		T270	1
auto[4160749568:4294967295]	auto[0]	126	1			T2	3		T4	1		T25	1
auto[4160749568:4294967295]	auto[1]	11	1			T160	1		T422	1		T362	1