Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4198

1

T2

10

T4

4

T13

12

auto[1]

1982

1

T2

4

T4

4

T17

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	176	1			T2	2		T13	2		T17	2
auto[134217728:268435455]	156	1			T160	2		T59	2		T150	2
auto[268435456:402653183]	198	1			T18	4		T36	2		T28	2
auto[402653184:536870911]	180	1			T18	2		T59	2		T162	2
auto[536870912:671088639]	156	1			T17	2		T18	6		T28	2
auto[671088640:805306367]	222	1			T18	4		T226	2		T59	6
auto[805306368:939524095]	186	1			T18	2		T59	2		T215	2
auto[939524096:1073741823]	232	1			T18	4		T24	4		T38	2
auto[1073741824:1207959551]	224	1			T18	2		T42	2		T28	4
auto[1207959552:1342177279]	180	1			T18	2		T59	2		T162	2
auto[1342177280:1476395007]	162	1			T24	2		T59	4		T30	2
auto[1476395008:1610612735]	194	1			T4	2		T18	2		T42	2
auto[1610612736:1744830463]	172	1			T36	2		T24	2		T26	2
auto[1744830464:1879048191]	234	1			T2	2		T36	2		T24	4
auto[1879048192:2013265919]	170	1			T59	2		T230	2		T218	2
auto[2013265920:2147483647]	204	1			T18	2		T36	2		T224	2
auto[2147483648:2281701375]	192	1			T13	2		T17	2		T18	2
auto[2281701376:2415919103]	214	1			T18	4		T25	2		T47	2
auto[2415919104:2550136831]	200	1			T13	2		T131	2		T59	4
auto[2550136832:2684354559]	166	1			T17	2		T18	2		T36	2
auto[2684354560:2818572287]	196	1			T215	2		T219	2		T162	2
auto[2818572288:2952790015]	194	1			T2	2		T4	2		T226	2
auto[2952790016:3087007743]	212	1			T17	2		T28	2		T24	2
auto[3087007744:3221225471]	208	1			T2	2		T17	2		T18	2
auto[3221225472:3355443199]	212	1			T18	4		T163	2		T50	2
auto[3355443200:3489660927]	160	1			T47	2		T215	2		T223	2
auto[3489660928:3623878655]	224	1			T13	4		T46	2		T226	2
auto[3623878656:3758096383]	210	1			T4	2		T18	2		T46	2
auto[3758096384:3892314111]	208	1			T2	2		T36	2		T147	2
auto[3892314112:4026531839]	190	1			T2	2		T36	2		T59	2
auto[4026531840:4160749567]	182	1			T2	2		T18	2		T36	2
auto[4160749568:4294967295]	166	1			T4	2		T13	2		T131	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	116	1			T2	2		T13	2		T17	2
auto[0:134217727]	auto[1]	60	1			T59	2		T105	4		T73	2
auto[134217728:268435455]	auto[0]	114	1			T59	2		T150	2		T162	2
auto[134217728:268435455]	auto[1]	42	1			T160	2		T218	2		T96	2
auto[268435456:402653183]	auto[0]	122	1			T36	2		T28	2		T24	2
auto[268435456:402653183]	auto[1]	76	1			T18	4		T27	2		T60	2
auto[402653184:536870911]	auto[0]	122	1			T18	2		T162	2		T144	2
auto[402653184:536870911]	auto[1]	58	1			T59	2		T142	2		T133	2
auto[536870912:671088639]	auto[0]	106	1			T17	2		T18	4		T28	2
auto[536870912:671088639]	auto[1]	50	1			T18	2		T26	2		T213	2
auto[671088640:805306367]	auto[0]	146	1			T18	2		T226	2		T59	2
auto[671088640:805306367]	auto[1]	76	1			T18	2		T59	4		T57	4
auto[805306368:939524095]	auto[0]	136	1			T18	2		T59	2		T215	2
auto[805306368:939524095]	auto[1]	50	1			T50	2		T204	2		T88	2
auto[939524096:1073741823]	auto[0]	154	1			T18	2		T24	4		T38	2
auto[939524096:1073741823]	auto[1]	78	1			T18	2		T141	2		T63	2
auto[1073741824:1207959551]	auto[0]	170	1			T18	2		T28	2		T219	2
auto[1073741824:1207959551]	auto[1]	54	1			T42	2		T28	2		T142	2
auto[1207959552:1342177279]	auto[0]	132	1			T18	2		T162	2		T38	4
auto[1207959552:1342177279]	auto[1]	48	1			T59	2		T65	2		T221	2
auto[1342177280:1476395007]	auto[0]	114	1			T24	2		T59	4		T30	2
auto[1342177280:1476395007]	auto[1]	48	1			T58	2		T424	2		T64	2
auto[1476395008:1610612735]	auto[0]	134	1			T4	2		T220	2		T162	2
auto[1476395008:1610612735]	auto[1]	60	1			T18	2		T42	2		T90	4
auto[1610612736:1744830463]	auto[0]	114	1			T24	2		T59	2		T163	2
auto[1610612736:1744830463]	auto[1]	58	1			T36	2		T26	2		T59	2
auto[1744830464:1879048191]	auto[0]	156	1			T2	2		T24	4		T220	2
auto[1744830464:1879048191]	auto[1]	78	1			T36	2		T38	2		T300	2
auto[1879048192:2013265919]	auto[0]	112	1			T230	2		T96	2		T280	2
auto[1879048192:2013265919]	auto[1]	58	1			T59	2		T218	2		T96	2
auto[2013265920:2147483647]	auto[0]	148	1			T18	2		T36	2		T224	2
auto[2013265920:2147483647]	auto[1]	56	1			T222	2		T65	2		T317	2
auto[2147483648:2281701375]	auto[0]	126	1			T13	2		T17	2		T18	2
auto[2147483648:2281701375]	auto[1]	66	1			T66	2		T30	2		T102	2
auto[2281701376:2415919103]	auto[0]	158	1			T18	4		T25	2		T47	2
auto[2281701376:2415919103]	auto[1]	56	1			T59	4		T218	2		T38	2
auto[2415919104:2550136831]	auto[0]	148	1			T13	2		T59	4		T287	2
auto[2415919104:2550136831]	auto[1]	52	1			T131	2		T73	2		T273	2
auto[2550136832:2684354559]	auto[0]	100	1			T17	2		T18	2		T138	2
auto[2550136832:2684354559]	auto[1]	66	1			T36	2		T59	2		T279	2
auto[2684354560:2818572287]	auto[0]	134	1			T215	2		T219	2		T162	2
auto[2684354560:2818572287]	auto[1]	62	1			T104	2		T97	2		T43	2
auto[2818572288:2952790015]	auto[0]	128	1			T226	2		T59	4		T5	4
auto[2818572288:2952790015]	auto[1]	66	1			T2	2		T4	2		T131	2
auto[2952790016:3087007743]	auto[0]	140	1			T17	2		T28	2		T59	8
auto[2952790016:3087007743]	auto[1]	72	1			T24	2		T96	2		T300	2
auto[3087007744:3221225471]	auto[0]	118	1			T2	2		T18	2		T28	2
auto[3087007744:3221225471]	auto[1]	90	1			T17	2		T104	2		T55	2
auto[3221225472:3355443199]	auto[0]	128	1			T18	2		T138	2		T280	2
auto[3221225472:3355443199]	auto[1]	84	1			T18	2		T163	2		T50	2
auto[3355443200:3489660927]	auto[0]	92	1			T57	2		T110	2		T306	2
auto[3355443200:3489660927]	auto[1]	68	1			T47	2		T215	2		T223	2
auto[3489660928:3623878655]	auto[0]	164	1			T13	4		T46	2		T226	2
auto[3489660928:3623878655]	auto[1]	60	1			T161	2		T218	2		T27	2
auto[3623878656:3758096383]	auto[0]	142	1			T220	4		T59	2		T53	2
auto[3623878656:3758096383]	auto[1]	68	1			T4	2		T18	2		T46	2
auto[3758096384:3892314111]	auto[0]	142	1			T36	2		T147	2		T227	2
auto[3758096384:3892314111]	auto[1]	66	1			T2	2		T46	2		T59	2
auto[3892314112:4026531839]	auto[0]	134	1			T2	2		T36	2		T59	2
auto[3892314112:4026531839]	auto[1]	56	1			T38	2		T229	2		T108	2
auto[4026531840:4160749567]	auto[0]	132	1			T2	2		T147	2		T47	2
auto[4026531840:4160749567]	auto[1]	50	1			T18	2		T36	2		T111	2
auto[4160749568:4294967295]	auto[0]	116	1			T4	2		T13	2		T59	4
auto[4160749568:4294967295]	auto[1]	50	1			T131	4		T215	2		T60	2