Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.07 98.14 98.62 100.00 99.11 98.41 91.61


Total test records in report: 1072
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T1002 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2299783927 Feb 28 05:47:12 PM PST 24 Feb 28 05:47:17 PM PST 24 53439997 ps
T1003 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.172140479 Feb 28 05:47:00 PM PST 24 Feb 28 05:47:03 PM PST 24 97136350 ps
T1004 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.443972927 Feb 28 05:47:21 PM PST 24 Feb 28 05:47:25 PM PST 24 575601019 ps
T1005 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.827366684 Feb 28 05:47:11 PM PST 24 Feb 28 05:47:13 PM PST 24 12979195 ps
T1006 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3547846234 Feb 28 05:47:30 PM PST 24 Feb 28 05:47:32 PM PST 24 18351359 ps
T1007 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.801431418 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:17 PM PST 24 51242228 ps
T1008 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2210875113 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:23 PM PST 24 992051450 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3158151156 Feb 28 05:46:56 PM PST 24 Feb 28 05:46:57 PM PST 24 39989231 ps
T1010 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3943505630 Feb 28 05:47:44 PM PST 24 Feb 28 05:47:45 PM PST 24 12010344 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.134195729 Feb 28 05:47:01 PM PST 24 Feb 28 05:47:11 PM PST 24 257535898 ps
T1012 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3057548015 Feb 28 05:47:05 PM PST 24 Feb 28 05:47:08 PM PST 24 160855848 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2981711850 Feb 28 05:46:57 PM PST 24 Feb 28 05:47:00 PM PST 24 151246926 ps
T1014 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2586568783 Feb 28 05:47:12 PM PST 24 Feb 28 05:47:17 PM PST 24 1927458817 ps
T1015 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1007932206 Feb 28 05:47:31 PM PST 24 Feb 28 05:47:32 PM PST 24 39585757 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2892051834 Feb 28 05:47:25 PM PST 24 Feb 28 05:47:26 PM PST 24 13035184 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2511764599 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:22 PM PST 24 1345715605 ps
T1018 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.63538959 Feb 28 05:47:16 PM PST 24 Feb 28 05:47:18 PM PST 24 37073842 ps
T1019 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.817308424 Feb 28 05:46:56 PM PST 24 Feb 28 05:46:58 PM PST 24 29817133 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3817878849 Feb 28 05:47:04 PM PST 24 Feb 28 05:47:12 PM PST 24 513934135 ps
T1021 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2517200381 Feb 28 05:47:19 PM PST 24 Feb 28 05:47:20 PM PST 24 31186287 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3075707013 Feb 28 05:47:18 PM PST 24 Feb 28 05:47:20 PM PST 24 43246682 ps
T1023 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4012160097 Feb 28 05:46:54 PM PST 24 Feb 28 05:46:55 PM PST 24 54365089 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.105936344 Feb 28 05:47:15 PM PST 24 Feb 28 05:47:18 PM PST 24 125562773 ps
T1025 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1661229170 Feb 28 05:46:52 PM PST 24 Feb 28 05:46:57 PM PST 24 140636042 ps
T1026 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1810111080 Feb 28 05:47:31 PM PST 24 Feb 28 05:47:32 PM PST 24 17014815 ps
T1027 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1306026504 Feb 28 05:47:02 PM PST 24 Feb 28 05:47:07 PM PST 24 278039526 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2547560159 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:17 PM PST 24 120373521 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3520866154 Feb 28 05:47:05 PM PST 24 Feb 28 05:47:10 PM PST 24 243346522 ps
T175 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1484823345 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:22 PM PST 24 1125362859 ps
T1030 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3381841829 Feb 28 05:47:30 PM PST 24 Feb 28 05:47:31 PM PST 24 32399711 ps
T1031 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1896153907 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:23 PM PST 24 2170500108 ps
T1032 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3854422286 Feb 28 05:47:30 PM PST 24 Feb 28 05:47:39 PM PST 24 850051448 ps
T1033 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3822843528 Feb 28 05:47:29 PM PST 24 Feb 28 05:47:33 PM PST 24 149426024 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2668033334 Feb 28 05:47:01 PM PST 24 Feb 28 05:47:17 PM PST 24 257350240 ps
T1035 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1217196526 Feb 28 05:47:31 PM PST 24 Feb 28 05:47:32 PM PST 24 11232753 ps
T1036 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2100760101 Feb 28 05:46:55 PM PST 24 Feb 28 05:47:09 PM PST 24 889021731 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1160843781 Feb 28 05:47:16 PM PST 24 Feb 28 05:47:18 PM PST 24 94196895 ps
T1038 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1212972094 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:16 PM PST 24 47780514 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3802597914 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:17 PM PST 24 429226347 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2555950989 Feb 28 05:47:19 PM PST 24 Feb 28 05:47:23 PM PST 24 403589809 ps
T1041 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4131577463 Feb 28 05:47:17 PM PST 24 Feb 28 05:47:20 PM PST 24 420424679 ps
T1042 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4251584914 Feb 28 05:47:26 PM PST 24 Feb 28 05:47:29 PM PST 24 172586056 ps
T1043 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1520958965 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:18 PM PST 24 694605317 ps
T1044 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3145739207 Feb 28 05:47:38 PM PST 24 Feb 28 05:47:40 PM PST 24 65582110 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1104820169 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:26 PM PST 24 1687953519 ps
T1046 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3092447680 Feb 28 05:46:55 PM PST 24 Feb 28 05:46:57 PM PST 24 68876962 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3162427666 Feb 28 05:47:12 PM PST 24 Feb 28 05:47:18 PM PST 24 174529576 ps
T1048 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.19752908 Feb 28 05:47:32 PM PST 24 Feb 28 05:47:33 PM PST 24 10328305 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3403358863 Feb 28 05:47:05 PM PST 24 Feb 28 05:47:06 PM PST 24 52868583 ps
T1050 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2712069579 Feb 28 05:47:16 PM PST 24 Feb 28 05:47:17 PM PST 24 40640217 ps
T1051 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3999282962 Feb 28 05:46:55 PM PST 24 Feb 28 05:46:58 PM PST 24 184940046 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3562873508 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:15 PM PST 24 25168480 ps
T1053 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3386743172 Feb 28 05:47:22 PM PST 24 Feb 28 05:47:26 PM PST 24 1088472854 ps
T1054 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3294275416 Feb 28 05:47:31 PM PST 24 Feb 28 05:47:32 PM PST 24 32583050 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1387848348 Feb 28 05:47:16 PM PST 24 Feb 28 05:47:17 PM PST 24 36419849 ps
T1056 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3239096691 Feb 28 05:47:23 PM PST 24 Feb 28 05:47:25 PM PST 24 373701995 ps
T1057 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1415233102 Feb 28 05:47:25 PM PST 24 Feb 28 05:47:26 PM PST 24 11286294 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1293795163 Feb 28 05:46:54 PM PST 24 Feb 28 05:47:01 PM PST 24 311148202 ps
T1059 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2027447574 Feb 28 05:47:29 PM PST 24 Feb 28 05:47:30 PM PST 24 9299216 ps
T1060 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.92148367 Feb 28 05:47:44 PM PST 24 Feb 28 05:47:45 PM PST 24 7988713 ps
T1061 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.452291244 Feb 28 05:46:57 PM PST 24 Feb 28 05:47:04 PM PST 24 131505483 ps
T1062 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2519274622 Feb 28 05:47:07 PM PST 24 Feb 28 05:47:08 PM PST 24 58632086 ps
T1063 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3379959441 Feb 28 05:47:13 PM PST 24 Feb 28 05:47:18 PM PST 24 999163644 ps
T1064 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.796350716 Feb 28 05:47:31 PM PST 24 Feb 28 05:47:32 PM PST 24 9201883 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1970372834 Feb 28 05:46:54 PM PST 24 Feb 28 05:46:56 PM PST 24 31387831 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3250169011 Feb 28 05:47:17 PM PST 24 Feb 28 05:47:21 PM PST 24 43655465 ps
T1067 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.956829418 Feb 28 05:47:17 PM PST 24 Feb 28 05:47:21 PM PST 24 177737747 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4071392160 Feb 28 05:47:27 PM PST 24 Feb 28 05:47:31 PM PST 24 568780605 ps
T1069 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2638913614 Feb 28 05:47:18 PM PST 24 Feb 28 05:47:22 PM PST 24 123596301 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1372039534 Feb 28 05:47:14 PM PST 24 Feb 28 05:47:17 PM PST 24 103096316 ps
T1071 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3755302774 Feb 28 05:47:15 PM PST 24 Feb 28 05:47:16 PM PST 24 18765418 ps
T1072 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1615899292 Feb 28 05:47:21 PM PST 24 Feb 28 05:47:27 PM PST 24 219925549 ps

Test location /workspace/coverage/default/38.keymgr_stress_all.1424839856
Short name T18
Test name
Test status
Simulation time 1010692906 ps
CPU time 13.42 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 221776 kb
Host smart-b390dd11-9e3b-4959-815b-8aad6039d764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424839856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1424839856
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.727575031
Short name T59
Test name
Test status
Simulation time 1757486900 ps
CPU time 35.86 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 215796 kb
Host smart-3f7bfb24-9191-4d76-a95b-6adc3071744f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727575031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.727575031
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2780894237
Short name T6
Test name
Test status
Simulation time 4773766094 ps
CPU time 26.34 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:53 PM PST 24
Peak memory 235880 kb
Host smart-9203ea9d-f72b-418d-9ed5-6c562d3f1326
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780894237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2780894237
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3821146470
Short name T132
Test name
Test status
Simulation time 2535586025 ps
CPU time 14.93 seconds
Started Feb 28 06:33:16 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 221980 kb
Host smart-5e2fa6c2-1b45-49c0-8c1d-76b72fda9021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821146470 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3821146470
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3933152983
Short name T36
Test name
Test status
Simulation time 335135340 ps
CPU time 5.69 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:21 PM PST 24
Peak memory 214524 kb
Host smart-fe460bd7-435e-4fb4-a1cb-8c300429cf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933152983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3933152983
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1987856262
Short name T57
Test name
Test status
Simulation time 504913919 ps
CPU time 20.57 seconds
Started Feb 28 06:31:33 PM PST 24
Finished Feb 28 06:31:54 PM PST 24
Peak memory 214800 kb
Host smart-34655bbc-2bc8-41e9-924f-053e1b46982e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987856262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1987856262
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1751222801
Short name T64
Test name
Test status
Simulation time 403220385 ps
CPU time 21.26 seconds
Started Feb 28 06:33:03 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 215164 kb
Host smart-7662d6c5-3eeb-4760-b76e-192f776d5247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751222801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1751222801
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1754055404
Short name T124
Test name
Test status
Simulation time 1526151847 ps
CPU time 7.23 seconds
Started Feb 28 05:47:04 PM PST 24
Finished Feb 28 05:47:11 PM PST 24
Peak memory 214072 kb
Host smart-434f4d11-cb7e-4653-aaa8-c5623a3d0de5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754055404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1754055404
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4089878807
Short name T27
Test name
Test status
Simulation time 559882294 ps
CPU time 5.94 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 213636 kb
Host smart-6336c386-2406-4ad1-a536-7be0f6beb164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089878807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4089878807
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2784832414
Short name T20
Test name
Test status
Simulation time 245997668 ps
CPU time 3.52 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 214032 kb
Host smart-4cb756a2-fa9d-450b-8b18-8a1247df6d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784832414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2784832414
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2502109889
Short name T49
Test name
Test status
Simulation time 455209010 ps
CPU time 16.96 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:46 PM PST 24
Peak memory 221988 kb
Host smart-b9c76b90-9dab-44a1-835b-2caede64f476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502109889 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2502109889
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4255016066
Short name T10
Test name
Test status
Simulation time 406007979 ps
CPU time 5.09 seconds
Started Feb 28 06:33:31 PM PST 24
Finished Feb 28 06:33:37 PM PST 24
Peak memory 213924 kb
Host smart-07bd6039-b162-434a-9182-af833061390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255016066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4255016066
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1703438250
Short name T88
Test name
Test status
Simulation time 1002033466 ps
CPU time 13.91 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:37 PM PST 24
Peak memory 214360 kb
Host smart-69189b9f-43b0-4048-b14a-25bf05f4925a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703438250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1703438250
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3388945549
Short name T66
Test name
Test status
Simulation time 676412075 ps
CPU time 11.51 seconds
Started Feb 28 06:32:34 PM PST 24
Finished Feb 28 06:32:46 PM PST 24
Peak memory 221972 kb
Host smart-b415e856-6106-4fbd-9e3d-e7959e1bbc47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388945549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3388945549
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3733723458
Short name T144
Test name
Test status
Simulation time 375379846 ps
CPU time 10.65 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:33 PM PST 24
Peak memory 214036 kb
Host smart-e0c3f7c6-9c0a-4d07-b2b7-d3d8de83fa6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733723458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3733723458
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1694516815
Short name T256
Test name
Test status
Simulation time 652607790 ps
CPU time 18.36 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 214296 kb
Host smart-dd502792-edf8-43bb-abe9-4d65e1ec38b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694516815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1694516815
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.376142916
Short name T24
Test name
Test status
Simulation time 1891661751 ps
CPU time 5.12 seconds
Started Feb 28 06:32:40 PM PST 24
Finished Feb 28 06:32:46 PM PST 24
Peak memory 208692 kb
Host smart-9663effa-7d5d-4859-80f7-f2f9a6540abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376142916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.376142916
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2596518938
Short name T110
Test name
Test status
Simulation time 1928003522 ps
CPU time 21.65 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:32:04 PM PST 24
Peak memory 215720 kb
Host smart-b20cf1b7-7d5b-46c3-a26c-67d25b143c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596518938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2596518938
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4140238822
Short name T311
Test name
Test status
Simulation time 560315825 ps
CPU time 15.21 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 213664 kb
Host smart-2aed1044-c5bd-4807-bead-0f4504f23bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140238822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4140238822
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.378349741
Short name T163
Test name
Test status
Simulation time 57849707 ps
CPU time 4.26 seconds
Started Feb 28 06:31:51 PM PST 24
Finished Feb 28 06:31:55 PM PST 24
Peak memory 213588 kb
Host smart-eb435f97-6e6f-41dd-bfa3-40c9e9b1e47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378349741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.378349741
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.708263005
Short name T58
Test name
Test status
Simulation time 564408699 ps
CPU time 17.14 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:24 PM PST 24
Peak memory 222064 kb
Host smart-ba00060f-b0b3-469c-9704-ed2cf6cc5434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708263005 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.708263005
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3796739282
Short name T39
Test name
Test status
Simulation time 253176133 ps
CPU time 3.17 seconds
Started Feb 28 06:30:30 PM PST 24
Finished Feb 28 06:30:33 PM PST 24
Peak memory 208220 kb
Host smart-0a804eba-f58d-482e-b334-190dcf0cdc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796739282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3796739282
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3034552980
Short name T94
Test name
Test status
Simulation time 301373267 ps
CPU time 8.9 seconds
Started Feb 28 06:31:40 PM PST 24
Finished Feb 28 06:31:49 PM PST 24
Peak memory 213692 kb
Host smart-6802af96-1d89-48ec-b3fb-0a6c64bdcef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034552980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3034552980
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.889072337
Short name T343
Test name
Test status
Simulation time 470051958 ps
CPU time 18.28 seconds
Started Feb 28 06:31:56 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 214540 kb
Host smart-51da23b1-372d-4749-bc8b-991b01d9d920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889072337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.889072337
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2169576013
Short name T2
Test name
Test status
Simulation time 516017768 ps
CPU time 8.93 seconds
Started Feb 28 06:31:52 PM PST 24
Finished Feb 28 06:32:01 PM PST 24
Peak memory 221644 kb
Host smart-ffbb2980-3187-49f7-b176-cd6b41ff3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169576013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2169576013
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3101805036
Short name T240
Test name
Test status
Simulation time 1499921486 ps
CPU time 53.69 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 214660 kb
Host smart-0d5093cf-9292-441c-a2b9-c17012b95eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101805036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3101805036
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1588264715
Short name T954
Test name
Test status
Simulation time 454845409 ps
CPU time 7.1 seconds
Started Feb 28 05:47:24 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 213936 kb
Host smart-91a2e9cd-eca0-4357-80bc-618a2551fb21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588264715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1588264715
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1296108392
Short name T150
Test name
Test status
Simulation time 63363763 ps
CPU time 4.22 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 214440 kb
Host smart-e4ec2170-d393-4706-b2b7-4203b42dc677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296108392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1296108392
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2988718490
Short name T33
Test name
Test status
Simulation time 189460768 ps
CPU time 4.19 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 213688 kb
Host smart-f1820bae-3a9e-4ace-ba87-9130566ad185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988718490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2988718490
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1647423204
Short name T416
Test name
Test status
Simulation time 543106586 ps
CPU time 13.53 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 213664 kb
Host smart-b5f76ed2-607d-4bdc-ad42-ea9e781bc54c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647423204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1647423204
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2958474697
Short name T204
Test name
Test status
Simulation time 1822608741 ps
CPU time 42.66 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:33:49 PM PST 24
Peak memory 215532 kb
Host smart-8c1cd3b9-4203-441d-adf4-a9e5b75d483a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958474697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2958474697
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2851730570
Short name T21
Test name
Test status
Simulation time 808983307 ps
CPU time 8.58 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:32:06 PM PST 24
Peak memory 213652 kb
Host smart-9897f0f4-fdab-4de3-8e98-fcadb646436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851730570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2851730570
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3085820449
Short name T119
Test name
Test status
Simulation time 164423989 ps
CPU time 6.25 seconds
Started Feb 28 06:31:14 PM PST 24
Finished Feb 28 06:31:21 PM PST 24
Peak memory 216276 kb
Host smart-ea5bfb27-88c0-4117-89f6-4df7109b58a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085820449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3085820449
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.596724027
Short name T275
Test name
Test status
Simulation time 4206756389 ps
CPU time 68.06 seconds
Started Feb 28 06:32:20 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 221808 kb
Host smart-1bc9e9b9-5cc1-4aff-97c4-67037617b409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596724027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.596724027
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.502759213
Short name T70
Test name
Test status
Simulation time 1139038544 ps
CPU time 23.65 seconds
Started Feb 28 06:31:20 PM PST 24
Finished Feb 28 06:31:44 PM PST 24
Peak memory 219760 kb
Host smart-09fdcec9-9871-4e05-8419-868652706ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502759213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.502759213
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1963220611
Short name T182
Test name
Test status
Simulation time 248047797 ps
CPU time 8.49 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:47:04 PM PST 24
Peak memory 208988 kb
Host smart-508f0210-e586-412a-90f2-15f86cb4c513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963220611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1963220611
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.743286929
Short name T122
Test name
Test status
Simulation time 230444256 ps
CPU time 2.36 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 208688 kb
Host smart-5bc76591-1f11-4467-a6ca-5ea9b2174c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743286929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.743286929
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3102328261
Short name T337
Test name
Test status
Simulation time 5434521884 ps
CPU time 114.68 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 227964 kb
Host smart-7fa2b477-f871-4edd-8d03-8b41e8e80eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102328261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3102328261
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3034440767
Short name T437
Test name
Test status
Simulation time 87558612 ps
CPU time 0.86 seconds
Started Feb 28 06:31:32 PM PST 24
Finished Feb 28 06:31:33 PM PST 24
Peak memory 205328 kb
Host smart-640448e5-5e6b-412c-8bb9-2aa54a39d5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034440767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3034440767
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1951164842
Short name T329
Test name
Test status
Simulation time 1370431739 ps
CPU time 11.3 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 214896 kb
Host smart-aabd2a9e-d0bd-40e3-8eac-8072c852970b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951164842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1951164842
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2032953091
Short name T105
Test name
Test status
Simulation time 263542759 ps
CPU time 8.06 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:14 PM PST 24
Peak memory 213740 kb
Host smart-447398ab-2f18-4afa-8170-efe41adf713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032953091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2032953091
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3581464357
Short name T292
Test name
Test status
Simulation time 239527952 ps
CPU time 7.11 seconds
Started Feb 28 06:32:22 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 214596 kb
Host smart-68432a31-a21a-4612-96d7-5df8d775ae5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581464357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3581464357
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.113082992
Short name T191
Test name
Test status
Simulation time 814867018 ps
CPU time 5.67 seconds
Started Feb 28 06:32:41 PM PST 24
Finished Feb 28 06:32:47 PM PST 24
Peak memory 221948 kb
Host smart-24ffd86c-b984-4deb-ac6c-cd7135fdea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113082992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.113082992
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1724585476
Short name T347
Test name
Test status
Simulation time 11959806129 ps
CPU time 292.47 seconds
Started Feb 28 06:31:45 PM PST 24
Finished Feb 28 06:36:38 PM PST 24
Peak memory 221912 kb
Host smart-02e4c756-0610-4f08-918e-0ec5723813da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724585476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1724585476
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2164253823
Short name T109
Test name
Test status
Simulation time 956386690 ps
CPU time 10.74 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 221708 kb
Host smart-90b61c33-bbfd-4b42-8836-b668d8858106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164253823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2164253823
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2045483814
Short name T166
Test name
Test status
Simulation time 122387435 ps
CPU time 6.79 seconds
Started Feb 28 05:47:01 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 213840 kb
Host smart-57fe80ba-669e-41d8-9c79-1504c47ff758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045483814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2045483814
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2443056766
Short name T360
Test name
Test status
Simulation time 387719504 ps
CPU time 4.76 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 213592 kb
Host smart-f0a58ef8-163a-4547-afae-59377ba0a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443056766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2443056766
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3762893438
Short name T197
Test name
Test status
Simulation time 234244531 ps
CPU time 5.43 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:54 PM PST 24
Peak memory 217496 kb
Host smart-5fc97e5b-9d1e-48c8-8641-2f4459dbeb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762893438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3762893438
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3381000982
Short name T151
Test name
Test status
Simulation time 413371877 ps
CPU time 10.71 seconds
Started Feb 28 06:32:33 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 214868 kb
Host smart-216cb3da-1305-4b99-a4a7-6cc7f8b511d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381000982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3381000982
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2199513233
Short name T5
Test name
Test status
Simulation time 137514533 ps
CPU time 3.55 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 213704 kb
Host smart-f60a3622-8d40-4715-bbd7-037d568978d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199513233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2199513233
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.90740778
Short name T79
Test name
Test status
Simulation time 1499013648 ps
CPU time 50.96 seconds
Started Feb 28 06:31:05 PM PST 24
Finished Feb 28 06:31:56 PM PST 24
Peak memory 214764 kb
Host smart-4b62fb65-2c5e-49c6-aef9-cea4b4b69f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90740778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.90740778
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1484823345
Short name T175
Test name
Test status
Simulation time 1125362859 ps
CPU time 7.68 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:22 PM PST 24
Peak memory 208600 kb
Host smart-63bf3700-5323-42d9-9d07-64d63c163985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484823345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1484823345
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4205099418
Short name T111
Test name
Test status
Simulation time 115440488 ps
CPU time 2.49 seconds
Started Feb 28 06:31:45 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 216764 kb
Host smart-6fa5147e-205b-47ad-a04e-186520f1c1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205099418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4205099418
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1289090769
Short name T192
Test name
Test status
Simulation time 564294306 ps
CPU time 5.39 seconds
Started Feb 28 06:30:44 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 216752 kb
Host smart-88facacf-315f-4c78-9895-acd85592514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289090769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1289090769
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.4008011803
Short name T265
Test name
Test status
Simulation time 194496994 ps
CPU time 2.16 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 208304 kb
Host smart-0569fd15-f261-408b-bb75-9dae8cabc598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008011803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4008011803
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3630707592
Short name T381
Test name
Test status
Simulation time 3873576394 ps
CPU time 25.08 seconds
Started Feb 28 06:32:31 PM PST 24
Finished Feb 28 06:32:56 PM PST 24
Peak memory 219908 kb
Host smart-22965378-a767-483e-b370-74f812371599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630707592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3630707592
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2937938019
Short name T176
Test name
Test status
Simulation time 154780873 ps
CPU time 6.3 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 208948 kb
Host smart-70e16946-3488-444a-b039-2735f066aa66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937938019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2937938019
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2089219342
Short name T170
Test name
Test status
Simulation time 623587940 ps
CPU time 9.24 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:14 PM PST 24
Peak memory 209356 kb
Host smart-57f79c68-4d4c-46c2-89ea-c6598c1a4c12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089219342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2089219342
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1643696803
Short name T81
Test name
Test status
Simulation time 14856210755 ps
CPU time 355.65 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:37:32 PM PST 24
Peak memory 216316 kb
Host smart-6f942bd2-f740-42be-b217-c512b9c06565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643696803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1643696803
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.167570324
Short name T247
Test name
Test status
Simulation time 583513528 ps
CPU time 21.44 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:26 PM PST 24
Peak memory 221992 kb
Host smart-9343e850-d04e-4af8-8d05-9cbb4a2f252c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167570324 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.167570324
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.870242391
Short name T257
Test name
Test status
Simulation time 2624105954 ps
CPU time 26.57 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 208504 kb
Host smart-fbd3616c-4890-4022-a815-988ce5f112cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870242391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.870242391
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3933216311
Short name T255
Test name
Test status
Simulation time 207046535 ps
CPU time 5.33 seconds
Started Feb 28 06:30:40 PM PST 24
Finished Feb 28 06:30:45 PM PST 24
Peak memory 213576 kb
Host smart-a03a10f3-de31-47f5-8c59-0752bc8e1324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933216311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3933216311
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3021676074
Short name T69
Test name
Test status
Simulation time 159835365 ps
CPU time 8.04 seconds
Started Feb 28 06:32:30 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 208984 kb
Host smart-d405a0d3-305b-4580-8d44-b76c5842d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021676074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3021676074
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.561735059
Short name T296
Test name
Test status
Simulation time 96071921 ps
CPU time 4.58 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 217608 kb
Host smart-fd99431d-b4ce-4d7b-9f50-908c90447a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561735059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.561735059
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4193784581
Short name T253
Test name
Test status
Simulation time 19289952611 ps
CPU time 55.79 seconds
Started Feb 28 06:30:54 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 215156 kb
Host smart-be7935d9-252d-451b-bef0-d3c013e9fcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193784581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4193784581
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.495754739
Short name T302
Test name
Test status
Simulation time 113559185 ps
CPU time 5.53 seconds
Started Feb 28 06:31:01 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 213572 kb
Host smart-22c9cca3-40c3-4a5d-afe9-b8e39da71bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495754739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.495754739
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.365579779
Short name T91
Test name
Test status
Simulation time 93602188 ps
CPU time 4.08 seconds
Started Feb 28 06:32:18 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 213736 kb
Host smart-507a6ab9-0cf0-4a68-a7ed-6f429bb8a518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365579779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.365579779
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2126278182
Short name T190
Test name
Test status
Simulation time 173883208 ps
CPU time 4.95 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:18 PM PST 24
Peak memory 217352 kb
Host smart-a4118102-c4d1-4060-a561-5ddcaa85f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126278182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2126278182
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2713039619
Short name T363
Test name
Test status
Simulation time 59443966 ps
CPU time 3.05 seconds
Started Feb 28 06:31:22 PM PST 24
Finished Feb 28 06:31:25 PM PST 24
Peak memory 207888 kb
Host smart-05b6c57e-d9e0-4c10-bc43-58f4149e3c13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713039619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2713039619
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.525546283
Short name T398
Test name
Test status
Simulation time 174354994 ps
CPU time 2.09 seconds
Started Feb 28 06:31:25 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 209420 kb
Host smart-fd9bb1e1-5339-42c8-b662-ef00779a5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525546283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.525546283
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2581792521
Short name T38
Test name
Test status
Simulation time 50245198 ps
CPU time 3.75 seconds
Started Feb 28 06:32:20 PM PST 24
Finished Feb 28 06:32:24 PM PST 24
Peak memory 210768 kb
Host smart-f54a61f9-0b51-4265-83b8-99d15c3532bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581792521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2581792521
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4101557115
Short name T390
Test name
Test status
Simulation time 151070830 ps
CPU time 5.53 seconds
Started Feb 28 06:32:45 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 221576 kb
Host smart-127b78e5-dd66-4ef8-91cb-b6bdaaf779f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101557115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4101557115
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2804897882
Short name T338
Test name
Test status
Simulation time 6579105209 ps
CPU time 43.7 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:34:06 PM PST 24
Peak memory 221804 kb
Host smart-0e4b96ec-66dc-404e-b199-12f70b0a0734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804897882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2804897882
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3618795437
Short name T171
Test name
Test status
Simulation time 1170567530 ps
CPU time 11.61 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 208500 kb
Host smart-9b0e3fc6-4fba-416e-8a35-751b3897288e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618795437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3618795437
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1087365037
Short name T179
Test name
Test status
Simulation time 188271301 ps
CPU time 5.14 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:19 PM PST 24
Peak memory 209292 kb
Host smart-f348a47a-a4d3-4bda-828c-4aebb91642b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087365037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1087365037
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.869269182
Short name T165
Test name
Test status
Simulation time 234017557 ps
CPU time 6.13 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 209204 kb
Host smart-2e3dba84-ba2d-45d4-b6a5-0c7f7be6245b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869269182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.869269182
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1911467214
Short name T181
Test name
Test status
Simulation time 218535000 ps
CPU time 9.94 seconds
Started Feb 28 05:47:24 PM PST 24
Finished Feb 28 05:47:34 PM PST 24
Peak memory 208896 kb
Host smart-60bef7d0-4a8c-45c3-b99f-6366c3335a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911467214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1911467214
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.959394586
Short name T180
Test name
Test status
Simulation time 276319091 ps
CPU time 6.3 seconds
Started Feb 28 05:47:04 PM PST 24
Finished Feb 28 05:47:11 PM PST 24
Peak memory 208900 kb
Host smart-32f621fc-b82f-4f31-a915-e6e07c69ea4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959394586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
959394586
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.903724451
Short name T184
Test name
Test status
Simulation time 1927289678 ps
CPU time 5.35 seconds
Started Feb 28 05:47:11 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 209324 kb
Host smart-e45a3408-0ee0-4ae8-8668-ac15fd1825e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903724451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
903724451
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3637235156
Short name T167
Test name
Test status
Simulation time 48759624 ps
CPU time 2 seconds
Started Feb 28 06:32:30 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 209632 kb
Host smart-ab6b4876-e115-4864-af75-bfe4c89dda92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637235156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3637235156
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.939065012
Short name T185
Test name
Test status
Simulation time 207408674 ps
CPU time 2.49 seconds
Started Feb 28 06:33:01 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 209192 kb
Host smart-331ea1b5-5882-47be-a69c-7313c4d94357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939065012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.939065012
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2602383366
Short name T199
Test name
Test status
Simulation time 211034086 ps
CPU time 3.02 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 221968 kb
Host smart-b71a2f18-6451-46a9-9ff0-d8193629fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602383366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2602383366
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.398959434
Short name T195
Test name
Test status
Simulation time 101386085 ps
CPU time 3.19 seconds
Started Feb 28 06:31:35 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 216264 kb
Host smart-be35253b-4c85-4589-9896-ef543b083de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398959434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.398959434
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.306670218
Short name T194
Test name
Test status
Simulation time 34492487 ps
CPU time 2.46 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 222072 kb
Host smart-3d156542-8c86-4b7a-8200-817de597e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306670218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.306670218
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.382668055
Short name T193
Test name
Test status
Simulation time 97031249 ps
CPU time 4.44 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:21 PM PST 24
Peak memory 217512 kb
Host smart-47cdb0fe-8c16-4714-a4dd-8e568f9c6de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382668055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.382668055
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2403837378
Short name T198
Test name
Test status
Simulation time 70006633 ps
CPU time 3.22 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 216360 kb
Host smart-d2a04b2d-e191-418c-8e18-82a5c92234c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403837378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2403837378
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1435063295
Short name T254
Test name
Test status
Simulation time 1665990167 ps
CPU time 25.65 seconds
Started Feb 28 06:30:27 PM PST 24
Finished Feb 28 06:30:53 PM PST 24
Peak memory 208952 kb
Host smart-0715a9bf-9ba8-4e8d-9314-7cc6235ba12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435063295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1435063295
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.14490262
Short name T596
Test name
Test status
Simulation time 434609570 ps
CPU time 3.42 seconds
Started Feb 28 06:30:31 PM PST 24
Finished Feb 28 06:30:35 PM PST 24
Peak memory 209476 kb
Host smart-6c841fff-71d9-4e91-be55-809bded83d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14490262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.14490262
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.715943297
Short name T26
Test name
Test status
Simulation time 292808885 ps
CPU time 9.99 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:31:29 PM PST 24
Peak memory 207928 kb
Host smart-5bc2b091-e2ce-4766-aabb-3aaaacfa0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715943297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.715943297
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1381944978
Short name T291
Test name
Test status
Simulation time 4216768467 ps
CPU time 60.39 seconds
Started Feb 28 06:31:37 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 221980 kb
Host smart-a5984f77-f5af-481f-9616-c55d3f4ecded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381944978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1381944978
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1488929288
Short name T423
Test name
Test status
Simulation time 428958175 ps
CPU time 6.29 seconds
Started Feb 28 06:31:33 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 221804 kb
Host smart-c2f732e7-5741-431e-8db0-46da90a3868c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488929288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1488929288
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1124026140
Short name T235
Test name
Test status
Simulation time 398007845 ps
CPU time 4.2 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:44 PM PST 24
Peak memory 219728 kb
Host smart-828e5593-2760-45f9-a087-36cdcc4b0d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124026140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1124026140
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4035718225
Short name T314
Test name
Test status
Simulation time 54713899 ps
CPU time 3.79 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:49 PM PST 24
Peak memory 213668 kb
Host smart-7c3eeeb3-0392-4915-a3f5-4a60f26668fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035718225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4035718225
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.100106991
Short name T391
Test name
Test status
Simulation time 276019463 ps
CPU time 9.71 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:53 PM PST 24
Peak memory 208192 kb
Host smart-7b35e008-b393-4570-9221-8c7329174fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100106991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.100106991
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.419224093
Short name T221
Test name
Test status
Simulation time 7831164709 ps
CPU time 33.66 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:32:18 PM PST 24
Peak memory 209956 kb
Host smart-ef4566b0-6978-4843-a755-7cf1e50a61bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419224093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.419224093
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.1773404059
Short name T901
Test name
Test status
Simulation time 650356871 ps
CPU time 12.34 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:56 PM PST 24
Peak memory 207164 kb
Host smart-906285c4-84e5-4d6d-be8e-01d07641e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773404059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1773404059
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2852186071
Short name T99
Test name
Test status
Simulation time 1546345490 ps
CPU time 19.76 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 221652 kb
Host smart-e4e6bdb3-b38d-4ea6-aad6-ab14d812f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852186071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2852186071
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1298734908
Short name T251
Test name
Test status
Simulation time 2741613533 ps
CPU time 22.57 seconds
Started Feb 28 06:30:38 PM PST 24
Finished Feb 28 06:31:00 PM PST 24
Peak memory 221876 kb
Host smart-8d3a3886-131f-406c-8435-b2b030103a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298734908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1298734908
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_random.907815505
Short name T4
Test name
Test status
Simulation time 271262899 ps
CPU time 4.01 seconds
Started Feb 28 06:31:53 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 208600 kb
Host smart-178a8f42-5bb9-46b7-bbb1-19763f88c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907815505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.907815505
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.996000955
Short name T244
Test name
Test status
Simulation time 205856625 ps
CPU time 5.89 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 208764 kb
Host smart-eaecdd6a-a0ce-433a-9617-67571e9517b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996000955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.996000955
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2818724788
Short name T386
Test name
Test status
Simulation time 158370607 ps
CPU time 4.12 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 209116 kb
Host smart-7c498a58-7c57-44f5-85fd-537ad012c1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818724788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2818724788
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3186942415
Short name T243
Test name
Test status
Simulation time 1609082698 ps
CPU time 38.89 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 221780 kb
Host smart-de5bc829-0604-47e2-8389-9d759e6429a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186942415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3186942415
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3387352418
Short name T357
Test name
Test status
Simulation time 71444860 ps
CPU time 2.45 seconds
Started Feb 28 06:32:14 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 206692 kb
Host smart-c4183ff6-c907-48b9-9422-4fe1cf12cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387352418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3387352418
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1519832860
Short name T365
Test name
Test status
Simulation time 113160306 ps
CPU time 4.91 seconds
Started Feb 28 06:32:20 PM PST 24
Finished Feb 28 06:32:24 PM PST 24
Peak memory 220304 kb
Host smart-45fc1c6f-d811-4596-b4dd-a31783a94f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519832860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1519832860
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2793347679
Short name T310
Test name
Test status
Simulation time 737649122 ps
CPU time 8.2 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 220516 kb
Host smart-019dbe61-50b0-4958-897d-a4ad934f02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793347679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2793347679
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1998632860
Short name T102
Test name
Test status
Simulation time 636682755 ps
CPU time 9.4 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:56 PM PST 24
Peak memory 213556 kb
Host smart-d6791e36-b88d-48e1-a9fc-6e3a50d011f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998632860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1998632860
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3746641789
Short name T236
Test name
Test status
Simulation time 144057920 ps
CPU time 4.55 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 222172 kb
Host smart-642e874e-441d-48e1-9e8c-3c308c0a7e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746641789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3746641789
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.122028852
Short name T271
Test name
Test status
Simulation time 385432174 ps
CPU time 4.77 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:32:57 PM PST 24
Peak memory 213948 kb
Host smart-26b2301c-bb8f-4e80-a94c-544872593a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122028852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.122028852
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2800780872
Short name T378
Test name
Test status
Simulation time 120619584 ps
CPU time 5.31 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 213656 kb
Host smart-131b645d-a78b-4903-8761-edb4e0fcf57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800780872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2800780872
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1918675669
Short name T196
Test name
Test status
Simulation time 98832241 ps
CPU time 4.42 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 217000 kb
Host smart-a5398988-9712-42c7-8c97-44df5bbf6bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918675669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1918675669
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1857671550
Short name T200
Test name
Test status
Simulation time 74997202 ps
CPU time 2.48 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 215992 kb
Host smart-3da8e3dc-4344-48e8-9239-38a161f7f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857671550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1857671550
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1661229170
Short name T1025
Test name
Test status
Simulation time 140636042 ps
CPU time 4.84 seconds
Started Feb 28 05:46:52 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 205544 kb
Host smart-b2841279-7b46-4dd8-b794-bbbfef086f5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661229170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
661229170
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2100760101
Short name T1036
Test name
Test status
Simulation time 889021731 ps
CPU time 14.26 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:47:09 PM PST 24
Peak memory 205592 kb
Host smart-c7c5932f-e4c6-4154-ad29-9b80eb38bcf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100760101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
100760101
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3153108956
Short name T932
Test name
Test status
Simulation time 105969836 ps
CPU time 1.38 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 205564 kb
Host smart-a8691f6e-f07f-4e58-98e4-f202b4b324f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153108956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
153108956
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1970372834
Short name T1065
Test name
Test status
Simulation time 31387831 ps
CPU time 1.33 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:46:56 PM PST 24
Peak memory 205624 kb
Host smart-3c7c3417-774c-4908-9593-8260a8eaa728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970372834 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1970372834
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3092447680
Short name T1046
Test name
Test status
Simulation time 68876962 ps
CPU time 1.53 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 205492 kb
Host smart-6207c231-34d0-4a29-a668-a8752a42cee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092447680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3092447680
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2093212389
Short name T917
Test name
Test status
Simulation time 11207791 ps
CPU time 0.85 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:46:56 PM PST 24
Peak memory 205360 kb
Host smart-0e2cb0d3-7873-4346-a888-d523a679f017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093212389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2093212389
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4012160097
Short name T1023
Test name
Test status
Simulation time 54365089 ps
CPU time 1.68 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:46:55 PM PST 24
Peak memory 205572 kb
Host smart-822e814e-f7b6-47e8-afbf-c857b86503ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012160097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4012160097
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.952255764
Short name T976
Test name
Test status
Simulation time 1119020327 ps
CPU time 3.59 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 213872 kb
Host smart-82e34c0a-b476-49ed-ba39-568e0d9f9f01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952255764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.952255764
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2392461118
Short name T980
Test name
Test status
Simulation time 204807167 ps
CPU time 7.86 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:47:02 PM PST 24
Peak memory 213980 kb
Host smart-cc95579b-9b48-41ad-86ce-e0ae4379a96a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392461118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2392461118
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3999282962
Short name T1051
Test name
Test status
Simulation time 184940046 ps
CPU time 2.95 seconds
Started Feb 28 05:46:55 PM PST 24
Finished Feb 28 05:46:58 PM PST 24
Peak memory 216924 kb
Host smart-d80ef83e-eafd-43d0-989a-cab3f1fdc508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999282962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3999282962
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1225397920
Short name T984
Test name
Test status
Simulation time 132207019 ps
CPU time 7.61 seconds
Started Feb 28 05:46:58 PM PST 24
Finished Feb 28 05:47:05 PM PST 24
Peak memory 205540 kb
Host smart-f51ebab4-d6bb-496b-a94c-5da36fd2e5c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225397920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
225397920
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.733613327
Short name T164
Test name
Test status
Simulation time 865845951 ps
CPU time 23.83 seconds
Started Feb 28 05:47:00 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 205516 kb
Host smart-8cff1016-8a07-4a96-a8c0-92edc952559e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733613327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.733613327
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3158151156
Short name T1009
Test name
Test status
Simulation time 39989231 ps
CPU time 0.86 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 205356 kb
Host smart-3409a9e1-567e-46e9-b5f0-041617472499
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158151156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
158151156
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3435043947
Short name T928
Test name
Test status
Simulation time 53316418 ps
CPU time 1.12 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:46:57 PM PST 24
Peak memory 205612 kb
Host smart-1892e4fc-859f-40b4-be21-c4b061eead9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435043947 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3435043947
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3646740752
Short name T998
Test name
Test status
Simulation time 50778258 ps
CPU time 1.24 seconds
Started Feb 28 05:46:59 PM PST 24
Finished Feb 28 05:47:00 PM PST 24
Peak memory 205592 kb
Host smart-dd78239f-5331-49ea-9b6a-d5f7b3a4dbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646740752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3646740752
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2733898820
Short name T992
Test name
Test status
Simulation time 10135065 ps
CPU time 0.73 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:46:58 PM PST 24
Peak memory 205412 kb
Host smart-69ce5c97-f4e3-4086-bad9-06a47ecac7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733898820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2733898820
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1139372875
Short name T949
Test name
Test status
Simulation time 45716804 ps
CPU time 2.03 seconds
Started Feb 28 05:46:58 PM PST 24
Finished Feb 28 05:47:00 PM PST 24
Peak memory 205584 kb
Host smart-ffccaba6-d140-4c7d-bea2-eaf89acb4211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139372875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1139372875
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3446750306
Short name T994
Test name
Test status
Simulation time 237646984 ps
CPU time 2.28 seconds
Started Feb 28 05:46:52 PM PST 24
Finished Feb 28 05:46:54 PM PST 24
Peak memory 214020 kb
Host smart-4368d848-79ca-4d30-90af-e9d244f765f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446750306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3446750306
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1293795163
Short name T1058
Test name
Test status
Simulation time 311148202 ps
CPU time 6.73 seconds
Started Feb 28 05:46:54 PM PST 24
Finished Feb 28 05:47:01 PM PST 24
Peak memory 214004 kb
Host smart-99f3bf40-0bd7-4056-9c3d-ff9208c29913
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293795163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1293795163
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4047589217
Short name T981
Test name
Test status
Simulation time 137266130 ps
CPU time 3.01 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:47:00 PM PST 24
Peak memory 216304 kb
Host smart-514ca9da-1e1e-4e93-abec-23fa073d9198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047589217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4047589217
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2195554158
Short name T990
Test name
Test status
Simulation time 55302548 ps
CPU time 2.22 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 213896 kb
Host smart-114ded39-e9e5-4afc-87c4-6a99d5b6d172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195554158 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2195554158
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3075707013
Short name T1022
Test name
Test status
Simulation time 43246682 ps
CPU time 1.45 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 205464 kb
Host smart-f4e94e01-3191-46d1-a1a9-d144df8a4e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075707013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3075707013
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3755302774
Short name T1071
Test name
Test status
Simulation time 18765418 ps
CPU time 0.82 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 205440 kb
Host smart-5b0422ce-91ac-4779-bf38-12e3c1eefaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755302774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3755302774
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1160843781
Short name T1037
Test name
Test status
Simulation time 94196895 ps
CPU time 1.74 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 205456 kb
Host smart-372bf0fd-578b-41f9-b0de-693eac4f103b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160843781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1160843781
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1520958965
Short name T1043
Test name
Test status
Simulation time 694605317 ps
CPU time 4.2 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 222076 kb
Host smart-38d3a845-8dd0-470d-b520-609e5b5ead78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520958965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1520958965
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2361229617
Short name T982
Test name
Test status
Simulation time 864860343 ps
CPU time 8.65 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 214004 kb
Host smart-4223ba9a-2718-4c66-a0be-e69745f76984
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361229617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2361229617
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1233044151
Short name T203
Test name
Test status
Simulation time 1514095165 ps
CPU time 3.83 seconds
Started Feb 28 05:47:11 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 214948 kb
Host smart-62d352a9-5041-45e3-bf8c-5b4d22bbe9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233044151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1233044151
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3162427666
Short name T1047
Test name
Test status
Simulation time 174529576 ps
CPU time 5.23 seconds
Started Feb 28 05:47:12 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 208780 kb
Host smart-b1f1e25a-d974-49e7-b669-d83f1c922384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162427666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3162427666
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.978821265
Short name T912
Test name
Test status
Simulation time 437405190 ps
CPU time 1.59 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 213944 kb
Host smart-d9cd9e42-7ef9-442f-a95d-4b20fe1aa20c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978821265 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.978821265
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.812240863
Short name T1001
Test name
Test status
Simulation time 58736376 ps
CPU time 1.34 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 205540 kb
Host smart-f58d63dc-eafe-456b-9a2a-76324a972a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812240863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.812240863
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.800459309
Short name T916
Test name
Test status
Simulation time 20956007 ps
CPU time 0.73 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205348 kb
Host smart-81eb40db-a722-46d2-8e24-c08df749375c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800459309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.800459309
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.105936344
Short name T1024
Test name
Test status
Simulation time 125562773 ps
CPU time 2.42 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 205696 kb
Host smart-e0040c97-83bf-4500-a6b5-c8a8131998b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105936344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.105936344
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1009656501
Short name T920
Test name
Test status
Simulation time 299907326 ps
CPU time 7.78 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 214024 kb
Host smart-ea1d4059-e6bf-4079-90a0-888c2771b1c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009656501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1009656501
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1104820169
Short name T1045
Test name
Test status
Simulation time 1687953519 ps
CPU time 11.93 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 214028 kb
Host smart-e8f16100-43fd-44d2-be52-4a5548146ad0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104820169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1104820169
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.801431418
Short name T1007
Test name
Test status
Simulation time 51242228 ps
CPU time 3.19 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 215964 kb
Host smart-e0c305bd-90ba-4589-ac56-9ccde7cce2a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801431418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.801431418
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3776674479
Short name T941
Test name
Test status
Simulation time 70104803 ps
CPU time 1.71 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 213920 kb
Host smart-3a9bc6d6-bdcb-48ce-9202-2650184b91f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776674479 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3776674479
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4047377956
Short name T973
Test name
Test status
Simulation time 29941588 ps
CPU time 1.19 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:19 PM PST 24
Peak memory 205516 kb
Host smart-0f58de11-470f-4bc3-94ec-0c2291cb7d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047377956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4047377956
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2712069579
Short name T1050
Test name
Test status
Simulation time 40640217 ps
CPU time 0.84 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205464 kb
Host smart-c3f9d989-06d3-4db5-8b67-c94e75e7780c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712069579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2712069579
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1780239084
Short name T997
Test name
Test status
Simulation time 103832814 ps
CPU time 1.73 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 205644 kb
Host smart-3470a93e-c008-4968-b578-1b2bdfda23d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780239084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1780239084
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1337126992
Short name T985
Test name
Test status
Simulation time 73047461 ps
CPU time 2.45 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 213996 kb
Host smart-6197acad-fd6a-4330-8f4d-cbe42c1203e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337126992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1337126992
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2305126484
Short name T935
Test name
Test status
Simulation time 184981161 ps
CPU time 4.21 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 213988 kb
Host smart-2d7e8908-5d5a-47c9-8de1-82fb8707aef0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305126484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2305126484
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3250169011
Short name T1066
Test name
Test status
Simulation time 43655465 ps
CPU time 2.93 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 213876 kb
Host smart-2d2a0f34-b280-4619-95a8-89066f2b7e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250169011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3250169011
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1870682316
Short name T939
Test name
Test status
Simulation time 110500524 ps
CPU time 1.72 seconds
Started Feb 28 05:47:20 PM PST 24
Finished Feb 28 05:47:22 PM PST 24
Peak memory 213872 kb
Host smart-8475677b-9196-43e9-9528-a2b9760112fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870682316 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1870682316
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1958411871
Short name T972
Test name
Test status
Simulation time 17535469 ps
CPU time 0.96 seconds
Started Feb 28 05:47:20 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 205508 kb
Host smart-435c3aa0-4126-4a6e-a820-f4e6921082c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958411871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1958411871
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2145686500
Short name T974
Test name
Test status
Simulation time 11039453 ps
CPU time 0.9 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205460 kb
Host smart-ded57f52-d317-4efa-a08c-fea2eea910ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145686500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2145686500
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3352728450
Short name T159
Test name
Test status
Simulation time 440220908 ps
CPU time 3.04 seconds
Started Feb 28 05:47:21 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 205636 kb
Host smart-540c1f8a-7c0e-476c-8475-f1d8bb0ff10a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352728450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3352728450
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1148160988
Short name T129
Test name
Test status
Simulation time 169510779 ps
CPU time 2.14 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 213944 kb
Host smart-8990d96a-6977-466c-9b9e-b8c68eef5642
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148160988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1148160988
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1615899292
Short name T1072
Test name
Test status
Simulation time 219925549 ps
CPU time 5.55 seconds
Started Feb 28 05:47:21 PM PST 24
Finished Feb 28 05:47:27 PM PST 24
Peak memory 214020 kb
Host smart-436eb23e-2a51-4e1b-8816-1509166f90b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615899292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1615899292
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.956829418
Short name T1067
Test name
Test status
Simulation time 177737747 ps
CPU time 2.75 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 215832 kb
Host smart-3b9db19c-a796-4bbf-8b44-e998134140b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956829418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.956829418
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1590857083
Short name T934
Test name
Test status
Simulation time 19104295 ps
CPU time 1.6 seconds
Started Feb 28 05:47:22 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 213852 kb
Host smart-d279b301-907f-449c-bcde-7c1f7c889ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590857083 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1590857083
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3301497403
Short name T153
Test name
Test status
Simulation time 27218234 ps
CPU time 1.31 seconds
Started Feb 28 05:47:22 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 205752 kb
Host smart-212d3b7e-f448-4ce6-87ad-1195706ca7d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301497403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3301497403
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3089325987
Short name T963
Test name
Test status
Simulation time 12778364 ps
CPU time 0.85 seconds
Started Feb 28 05:47:21 PM PST 24
Finished Feb 28 05:47:22 PM PST 24
Peak memory 205292 kb
Host smart-fb8eb8e4-b5ca-4ebc-acf0-de1cdd7dedaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089325987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3089325987
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3023595632
Short name T989
Test name
Test status
Simulation time 24934620 ps
CPU time 1.69 seconds
Started Feb 28 05:47:23 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 205656 kb
Host smart-6888f42d-618e-4014-921b-81761407db5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023595632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3023595632
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2638913614
Short name T1069
Test name
Test status
Simulation time 123596301 ps
CPU time 3.69 seconds
Started Feb 28 05:47:18 PM PST 24
Finished Feb 28 05:47:22 PM PST 24
Peak memory 214024 kb
Host smart-80db70f4-84ad-4815-9e0a-ad36fcddb969
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638913614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2638913614
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2415894746
Short name T960
Test name
Test status
Simulation time 1231794405 ps
CPU time 5.59 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 213876 kb
Host smart-13cedd80-6e83-4d43-8720-227fdc704442
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415894746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2415894746
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4131577463
Short name T1041
Test name
Test status
Simulation time 420424679 ps
CPU time 2.85 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 215972 kb
Host smart-38bbcdc9-3165-413e-8353-31ea084ab419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131577463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4131577463
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.814053417
Short name T186
Test name
Test status
Simulation time 221991615 ps
CPU time 4.94 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 208852 kb
Host smart-9135b27e-7c95-4446-81ca-d6570b4af9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814053417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.814053417
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1777105974
Short name T957
Test name
Test status
Simulation time 41965719 ps
CPU time 1.49 seconds
Started Feb 28 05:47:19 PM PST 24
Finished Feb 28 05:47:21 PM PST 24
Peak memory 213880 kb
Host smart-e98ad63b-1f2d-462f-9c39-6948e1b21318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777105974 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1777105974
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2517200381
Short name T1021
Test name
Test status
Simulation time 31186287 ps
CPU time 1.26 seconds
Started Feb 28 05:47:19 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 205540 kb
Host smart-abf9f95d-0e06-4c24-8003-00e64e93b71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517200381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2517200381
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1415233102
Short name T1057
Test name
Test status
Simulation time 11286294 ps
CPU time 0.86 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 205444 kb
Host smart-bc0be68e-3762-453e-8dd5-a169f2b29a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415233102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1415233102
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2071885858
Short name T154
Test name
Test status
Simulation time 358042206 ps
CPU time 2.21 seconds
Started Feb 28 05:47:17 PM PST 24
Finished Feb 28 05:47:20 PM PST 24
Peak memory 205724 kb
Host smart-4a3f8b10-6d2e-4d72-afbe-12c893b19743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071885858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2071885858
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3386743172
Short name T1053
Test name
Test status
Simulation time 1088472854 ps
CPU time 4.12 seconds
Started Feb 28 05:47:22 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 214016 kb
Host smart-30545e1f-937b-4d9e-9079-5ed907c5ec95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386743172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3386743172
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1168377919
Short name T937
Test name
Test status
Simulation time 3202182195 ps
CPU time 8.36 seconds
Started Feb 28 05:47:20 PM PST 24
Finished Feb 28 05:47:29 PM PST 24
Peak memory 214048 kb
Host smart-97bf8b12-5da5-4e4e-9fab-99760a7ab72c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168377919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1168377919
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.443972927
Short name T1004
Test name
Test status
Simulation time 575601019 ps
CPU time 4.23 seconds
Started Feb 28 05:47:21 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 213748 kb
Host smart-a5548d21-1173-4e93-b452-d54c156e988e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443972927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.443972927
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3239096691
Short name T1056
Test name
Test status
Simulation time 373701995 ps
CPU time 1.41 seconds
Started Feb 28 05:47:23 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 213812 kb
Host smart-125631c4-ae49-44df-94e7-f5afee821781
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239096691 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3239096691
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2417562214
Short name T953
Test name
Test status
Simulation time 17966199 ps
CPU time 1.34 seconds
Started Feb 28 05:47:22 PM PST 24
Finished Feb 28 05:47:24 PM PST 24
Peak memory 205580 kb
Host smart-e1337f7f-e088-4bb4-816b-bf6579ea0305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417562214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2417562214
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1329606361
Short name T958
Test name
Test status
Simulation time 10667852 ps
CPU time 0.77 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 205424 kb
Host smart-42bc3b50-bc9f-4de5-9e98-3bf2f44a2813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329606361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1329606361
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3908509051
Short name T926
Test name
Test status
Simulation time 519753149 ps
CPU time 2.79 seconds
Started Feb 28 05:47:23 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 205696 kb
Host smart-e8fc7421-6acf-4a6f-b653-a7dd3dfd6c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908509051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3908509051
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2555950989
Short name T1040
Test name
Test status
Simulation time 403589809 ps
CPU time 3.74 seconds
Started Feb 28 05:47:19 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 214152 kb
Host smart-3005dcf4-2800-4520-89ba-754642c842a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555950989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2555950989
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1442947034
Short name T123
Test name
Test status
Simulation time 324399512 ps
CPU time 7.12 seconds
Started Feb 28 05:47:19 PM PST 24
Finished Feb 28 05:47:27 PM PST 24
Peak memory 219744 kb
Host smart-3c89b2b1-9922-403d-a5e1-099b51ecd5e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442947034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1442947034
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2834825157
Short name T217
Test name
Test status
Simulation time 538558757 ps
CPU time 4.94 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 216088 kb
Host smart-3bf6fc15-15c2-41a8-84a6-2523d0d89b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834825157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2834825157
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3002346684
Short name T187
Test name
Test status
Simulation time 607136447 ps
CPU time 7.57 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 209004 kb
Host smart-0aeb537a-e4c3-4009-a4fb-3d09485021fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002346684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3002346684
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3058809291
Short name T966
Test name
Test status
Simulation time 54372080 ps
CPU time 1.64 seconds
Started Feb 28 05:47:26 PM PST 24
Finished Feb 28 05:47:28 PM PST 24
Peak memory 213744 kb
Host smart-9e5f67ab-4afc-4ec2-b275-0e3f213cf473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058809291 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3058809291
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1041842241
Short name T948
Test name
Test status
Simulation time 59952017 ps
CPU time 1.58 seconds
Started Feb 28 05:47:27 PM PST 24
Finished Feb 28 05:47:29 PM PST 24
Peak memory 205476 kb
Host smart-8cd6832c-aa4e-4fa3-9a67-6093872a4c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041842241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1041842241
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2974666194
Short name T909
Test name
Test status
Simulation time 9912893 ps
CPU time 0.7 seconds
Started Feb 28 05:47:24 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 205328 kb
Host smart-2bf61c98-083f-4492-8024-55654385910f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974666194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2974666194
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1773662820
Short name T944
Test name
Test status
Simulation time 267748548 ps
CPU time 2.66 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:27 PM PST 24
Peak memory 205644 kb
Host smart-f6e812d3-acad-4a73-a789-79237c975b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773662820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1773662820
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3995574806
Short name T927
Test name
Test status
Simulation time 3346413850 ps
CPU time 6.37 seconds
Started Feb 28 05:47:23 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 220856 kb
Host smart-fd66751c-29f8-4c9c-89be-044d2ff0f705
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995574806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3995574806
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1004467421
Short name T952
Test name
Test status
Simulation time 37108953 ps
CPU time 2.75 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:28 PM PST 24
Peak memory 213856 kb
Host smart-9acb6f3e-51ea-4b2c-95b7-184d3c92a449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004467421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1004467421
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2356840539
Short name T178
Test name
Test status
Simulation time 443537203 ps
CPU time 6.24 seconds
Started Feb 28 05:47:26 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 208432 kb
Host smart-f3f644f6-e300-40a1-8800-f7b170b35bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356840539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2356840539
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4015350274
Short name T399
Test name
Test status
Simulation time 89834201 ps
CPU time 2.28 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:27 PM PST 24
Peak memory 213876 kb
Host smart-a1925822-feba-4d8c-bdbe-d766fdbbaebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015350274 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4015350274
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2323908746
Short name T943
Test name
Test status
Simulation time 15931803 ps
CPU time 1.18 seconds
Started Feb 28 05:47:24 PM PST 24
Finished Feb 28 05:47:25 PM PST 24
Peak memory 205496 kb
Host smart-44cac387-370d-451e-8b42-503e5a557efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323908746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2323908746
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2892051834
Short name T1016
Test name
Test status
Simulation time 13035184 ps
CPU time 0.85 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:26 PM PST 24
Peak memory 205440 kb
Host smart-d6668434-3eb2-4267-8d7a-83cae96f35fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892051834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2892051834
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.490719012
Short name T951
Test name
Test status
Simulation time 86363466 ps
CPU time 2.62 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:28 PM PST 24
Peak memory 205564 kb
Host smart-55a3af72-af52-4253-9eca-737e6ef68d5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490719012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.490719012
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3384534749
Short name T988
Test name
Test status
Simulation time 190894478 ps
CPU time 5.77 seconds
Started Feb 28 05:47:25 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 214140 kb
Host smart-4700c53b-612d-4006-9428-6ecb477f9308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384534749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3384534749
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1622907282
Short name T125
Test name
Test status
Simulation time 294203934 ps
CPU time 6.96 seconds
Started Feb 28 05:47:24 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 213932 kb
Host smart-b7ab22d5-236a-4dba-a2ea-165f61eaa79c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622907282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1622907282
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4251584914
Short name T1042
Test name
Test status
Simulation time 172586056 ps
CPU time 2.52 seconds
Started Feb 28 05:47:26 PM PST 24
Finished Feb 28 05:47:29 PM PST 24
Peak memory 213868 kb
Host smart-8276054e-77f7-4e12-ae6b-389d284d3c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251584914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4251584914
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2895445373
Short name T986
Test name
Test status
Simulation time 181322735 ps
CPU time 1.58 seconds
Started Feb 28 05:47:28 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 213968 kb
Host smart-0367dfc4-12aa-4241-8bff-2d8be5c891ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895445373 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2895445373
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3547846234
Short name T1006
Test name
Test status
Simulation time 18351359 ps
CPU time 1 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205500 kb
Host smart-8bc819d9-2980-486d-9162-10d3b623c757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547846234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3547846234
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3704979251
Short name T921
Test name
Test status
Simulation time 34865775 ps
CPU time 0.79 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:29 PM PST 24
Peak memory 205320 kb
Host smart-270388c2-813f-4e1b-974d-1dc3334bd975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704979251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3704979251
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.170335882
Short name T157
Test name
Test status
Simulation time 58466388 ps
CPU time 2.53 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:33 PM PST 24
Peak memory 205660 kb
Host smart-f74f9fb1-6fd7-4337-98ac-80c7053ded61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170335882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.170335882
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4071392160
Short name T1068
Test name
Test status
Simulation time 568780605 ps
CPU time 3.21 seconds
Started Feb 28 05:47:27 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 214120 kb
Host smart-1f2bdf97-7c9e-49d6-ae31-0511745a6874
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071392160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4071392160
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3854422286
Short name T1032
Test name
Test status
Simulation time 850051448 ps
CPU time 8.66 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:39 PM PST 24
Peak memory 213956 kb
Host smart-31492279-13d9-4835-bfcd-9137a7f98118
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854422286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3854422286
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3822843528
Short name T1033
Test name
Test status
Simulation time 149426024 ps
CPU time 3.38 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:33 PM PST 24
Peak memory 213956 kb
Host smart-0a300ffa-1a80-4162-892b-ab05ec5f449e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822843528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3822843528
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3505658226
Short name T183
Test name
Test status
Simulation time 1662525399 ps
CPU time 20.09 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:51 PM PST 24
Peak memory 209236 kb
Host smart-fc1ce66b-4b39-44bb-8cbc-9c281dae6866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505658226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3505658226
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1151791228
Short name T925
Test name
Test status
Simulation time 859411125 ps
CPU time 14.45 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 204912 kb
Host smart-d75653d3-3e1a-436a-9040-1138d6c529f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151791228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
151791228
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.452291244
Short name T1061
Test name
Test status
Simulation time 131505483 ps
CPU time 6.92 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:47:04 PM PST 24
Peak memory 205396 kb
Host smart-840695b0-299f-4c17-b81b-ab12f3cf9266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452291244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.452291244
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.817308424
Short name T1019
Test name
Test status
Simulation time 29817133 ps
CPU time 1.38 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:46:58 PM PST 24
Peak memory 205516 kb
Host smart-353917fd-ec64-4eb7-bdb2-26e41ab006a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817308424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.817308424
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.825293274
Short name T979
Test name
Test status
Simulation time 197854100 ps
CPU time 1.86 seconds
Started Feb 28 05:46:58 PM PST 24
Finished Feb 28 05:47:00 PM PST 24
Peak memory 213876 kb
Host smart-247cf9f9-07ad-4286-91ae-b5876f217a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825293274 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.825293274
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3578343552
Short name T156
Test name
Test status
Simulation time 13923738 ps
CPU time 1.08 seconds
Started Feb 28 05:46:58 PM PST 24
Finished Feb 28 05:46:59 PM PST 24
Peak memory 205452 kb
Host smart-800fdcdc-017d-474d-904a-fee6e18689f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578343552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3578343552
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4051739385
Short name T929
Test name
Test status
Simulation time 87493525 ps
CPU time 0.71 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:46:58 PM PST 24
Peak memory 205360 kb
Host smart-4c35a868-4c2c-4dd2-8136-0a675f47163f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051739385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4051739385
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3476845748
Short name T945
Test name
Test status
Simulation time 130243625 ps
CPU time 2.22 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:46:58 PM PST 24
Peak memory 205552 kb
Host smart-eb6914d0-5a57-436b-ae71-ff237f75b620
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476845748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3476845748
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1079648380
Short name T956
Test name
Test status
Simulation time 264978540 ps
CPU time 5.86 seconds
Started Feb 28 05:46:58 PM PST 24
Finished Feb 28 05:47:04 PM PST 24
Peak memory 214084 kb
Host smart-1af392df-ffa2-4d14-8c71-fc93f68c5148
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079648380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1079648380
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2821738377
Short name T987
Test name
Test status
Simulation time 626364235 ps
CPU time 11.57 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 214012 kb
Host smart-782d446c-ab4c-40f5-8458-60db8b3551f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821738377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2821738377
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2981711850
Short name T1013
Test name
Test status
Simulation time 151246926 ps
CPU time 2.74 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:47:00 PM PST 24
Peak memory 213800 kb
Host smart-d9ee5801-06af-4666-875e-c4e857564304
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981711850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2981711850
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2231826927
Short name T177
Test name
Test status
Simulation time 1098200055 ps
CPU time 10.77 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 209140 kb
Host smart-8c122f4c-cef7-46e9-afbf-c921ec9fabec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231826927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2231826927
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3255760696
Short name T968
Test name
Test status
Simulation time 9984596 ps
CPU time 0.81 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 205260 kb
Host smart-39e02b84-3b71-40de-afe4-a495682af506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255760696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3255760696
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1007932206
Short name T1015
Test name
Test status
Simulation time 39585757 ps
CPU time 0.73 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205448 kb
Host smart-20db5ccd-68d5-4e71-af3d-dfa3999bc38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007932206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1007932206
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1810111080
Short name T1026
Test name
Test status
Simulation time 17014815 ps
CPU time 0.78 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205452 kb
Host smart-cb0aa582-44b0-427e-9aa4-861f6a0356de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810111080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1810111080
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2027447574
Short name T1059
Test name
Test status
Simulation time 9299216 ps
CPU time 0.71 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 205408 kb
Host smart-234667cd-6474-4c3a-8aad-569a302d949d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027447574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2027447574
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2643872153
Short name T978
Test name
Test status
Simulation time 150181345 ps
CPU time 0.72 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 205440 kb
Host smart-45df771d-ddce-4ad4-a6d6-cc04b46d6c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643872153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2643872153
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2153469797
Short name T924
Test name
Test status
Simulation time 21059203 ps
CPU time 0.77 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:29 PM PST 24
Peak memory 205424 kb
Host smart-663b217e-e304-4ef8-a769-ed5a0985caa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153469797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2153469797
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3381841829
Short name T1030
Test name
Test status
Simulation time 32399711 ps
CPU time 0.81 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 205384 kb
Host smart-ed93204f-d977-4f30-a993-4dfcf2f95d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381841829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3381841829
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2160800403
Short name T922
Test name
Test status
Simulation time 28543305 ps
CPU time 0.88 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 205436 kb
Host smart-39b222a0-a9b1-47bb-842f-22596b67b458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160800403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2160800403
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1105501373
Short name T938
Test name
Test status
Simulation time 10311471 ps
CPU time 0.7 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 205436 kb
Host smart-23c04973-3f8a-4591-9087-f35b8a6ce0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105501373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1105501373
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3025677405
Short name T946
Test name
Test status
Simulation time 29728066 ps
CPU time 0.69 seconds
Started Feb 28 05:47:28 PM PST 24
Finished Feb 28 05:47:28 PM PST 24
Peak memory 205292 kb
Host smart-72fa7f5a-0c22-4727-ac20-c1429e3173e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025677405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3025677405
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.134195729
Short name T1011
Test name
Test status
Simulation time 257535898 ps
CPU time 9.23 seconds
Started Feb 28 05:47:01 PM PST 24
Finished Feb 28 05:47:11 PM PST 24
Peak memory 205560 kb
Host smart-c5d9211f-4966-4b73-95ac-bad92d6cc5e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134195729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.134195729
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2668033334
Short name T1034
Test name
Test status
Simulation time 257350240 ps
CPU time 15.6 seconds
Started Feb 28 05:47:01 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205584 kb
Host smart-229f0b5f-4a37-4b09-9bfd-091623475b6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668033334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
668033334
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.88397514
Short name T923
Test name
Test status
Simulation time 25536179 ps
CPU time 1.31 seconds
Started Feb 28 05:47:00 PM PST 24
Finished Feb 28 05:47:02 PM PST 24
Peak memory 205396 kb
Host smart-0a3ca851-6209-4db8-81e2-dcafe7204200
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88397514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.88397514
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.172140479
Short name T1003
Test name
Test status
Simulation time 97136350 ps
CPU time 2.13 seconds
Started Feb 28 05:47:00 PM PST 24
Finished Feb 28 05:47:03 PM PST 24
Peak memory 213956 kb
Host smart-c6f4f029-512e-4be6-906b-43fa5aa3b03b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172140479 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.172140479
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3464693844
Short name T999
Test name
Test status
Simulation time 83551124 ps
CPU time 0.87 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:03 PM PST 24
Peak memory 205428 kb
Host smart-fa5b4165-6bde-4fdb-aa19-cb614ede1be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464693844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3464693844
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.427092926
Short name T964
Test name
Test status
Simulation time 16449093 ps
CPU time 0.76 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:02 PM PST 24
Peak memory 205304 kb
Host smart-6203515f-c4ab-42e8-93d3-7dfb8a77d60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427092926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.427092926
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1021803738
Short name T975
Test name
Test status
Simulation time 212817589 ps
CPU time 2.63 seconds
Started Feb 28 05:47:01 PM PST 24
Finished Feb 28 05:47:04 PM PST 24
Peak memory 205684 kb
Host smart-a595287c-57e9-4448-af8a-af85d4ae991e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021803738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1021803738
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3526247889
Short name T128
Test name
Test status
Simulation time 484302701 ps
CPU time 9.94 seconds
Started Feb 28 05:46:57 PM PST 24
Finished Feb 28 05:47:07 PM PST 24
Peak memory 214016 kb
Host smart-8594e6a7-2971-4d19-b4f2-2e5d8d4fed68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526247889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3526247889
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1299839034
Short name T977
Test name
Test status
Simulation time 557827948 ps
CPU time 7.08 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:09 PM PST 24
Peak memory 213352 kb
Host smart-f577a9a7-ae5b-4aca-85f3-92314a786795
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299839034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1299839034
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2759884911
Short name T906
Test name
Test status
Simulation time 133629674 ps
CPU time 3.67 seconds
Started Feb 28 05:46:56 PM PST 24
Finished Feb 28 05:47:01 PM PST 24
Peak memory 216120 kb
Host smart-fbc31159-b037-44b9-a0cf-e8d6d9594f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759884911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2759884911
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1835874904
Short name T950
Test name
Test status
Simulation time 9164584 ps
CPU time 0.8 seconds
Started Feb 28 05:47:29 PM PST 24
Finished Feb 28 05:47:30 PM PST 24
Peak memory 205436 kb
Host smart-931243c1-0a49-45a2-aef1-112a2137369c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835874904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1835874904
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3145739207
Short name T1044
Test name
Test status
Simulation time 65582110 ps
CPU time 0.74 seconds
Started Feb 28 05:47:38 PM PST 24
Finished Feb 28 05:47:40 PM PST 24
Peak memory 205404 kb
Host smart-fddde962-8720-405a-8b87-9b5040d72e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145739207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3145739207
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.796350716
Short name T1064
Test name
Test status
Simulation time 9201883 ps
CPU time 0.83 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205448 kb
Host smart-1cfb2cb4-c46b-439a-8602-b832cfba3e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796350716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.796350716
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.92148367
Short name T1060
Test name
Test status
Simulation time 7988713 ps
CPU time 0.8 seconds
Started Feb 28 05:47:44 PM PST 24
Finished Feb 28 05:47:45 PM PST 24
Peak memory 205436 kb
Host smart-190a4469-cd60-4323-b841-5743f3ff54be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92148367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.92148367
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1953516417
Short name T991
Test name
Test status
Simulation time 26588008 ps
CPU time 0.87 seconds
Started Feb 28 05:47:34 PM PST 24
Finished Feb 28 05:47:35 PM PST 24
Peak memory 205472 kb
Host smart-a7d83256-5fa3-4fec-b99f-dc8989aaca36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953516417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1953516417
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2985648382
Short name T911
Test name
Test status
Simulation time 25686665 ps
CPU time 0.7 seconds
Started Feb 28 05:47:33 PM PST 24
Finished Feb 28 05:47:34 PM PST 24
Peak memory 205332 kb
Host smart-75447f36-0018-4f0c-93fd-1c8e99f7d843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985648382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2985648382
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2383679904
Short name T993
Test name
Test status
Simulation time 61076412 ps
CPU time 0.7 seconds
Started Feb 28 05:47:30 PM PST 24
Finished Feb 28 05:47:31 PM PST 24
Peak memory 205396 kb
Host smart-a1726068-4f3a-4b07-8546-474bb97c4896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383679904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2383679904
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.19752908
Short name T1048
Test name
Test status
Simulation time 10328305 ps
CPU time 0.86 seconds
Started Feb 28 05:47:32 PM PST 24
Finished Feb 28 05:47:33 PM PST 24
Peak memory 205488 kb
Host smart-40d4ac93-129d-402b-ae76-97117ec840de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19752908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.19752908
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2322619792
Short name T915
Test name
Test status
Simulation time 135647676 ps
CPU time 0.77 seconds
Started Feb 28 05:47:32 PM PST 24
Finished Feb 28 05:47:33 PM PST 24
Peak memory 205300 kb
Host smart-cf60db87-0b07-478b-9b93-621629f85772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322619792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2322619792
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3055016111
Short name T970
Test name
Test status
Simulation time 58859035 ps
CPU time 0.79 seconds
Started Feb 28 05:47:36 PM PST 24
Finished Feb 28 05:47:37 PM PST 24
Peak memory 205436 kb
Host smart-3a204f03-b7e2-47b5-8eb8-21f4e107cdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055016111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3055016111
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3817878849
Short name T1020
Test name
Test status
Simulation time 513934135 ps
CPU time 6.96 seconds
Started Feb 28 05:47:04 PM PST 24
Finished Feb 28 05:47:12 PM PST 24
Peak memory 205608 kb
Host smart-c363fa2e-1c08-49f9-99e5-da3c4c63d422
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817878849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
817878849
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.596026185
Short name T908
Test name
Test status
Simulation time 584542314 ps
CPU time 8.17 seconds
Started Feb 28 05:47:03 PM PST 24
Finished Feb 28 05:47:11 PM PST 24
Peak memory 205632 kb
Host smart-e5486083-7e61-4f83-9ca9-6fb19815cfa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596026185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.596026185
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.752619584
Short name T168
Test name
Test status
Simulation time 199714775 ps
CPU time 0.97 seconds
Started Feb 28 05:47:04 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 205528 kb
Host smart-0119f725-9f2a-4dfd-8df4-54cccf4c71ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752619584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.752619584
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1370052784
Short name T931
Test name
Test status
Simulation time 97329049 ps
CPU time 2.23 seconds
Started Feb 28 05:47:10 PM PST 24
Finished Feb 28 05:47:13 PM PST 24
Peak memory 213900 kb
Host smart-79e1c008-2a51-45db-bfee-beb8c4081649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370052784 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1370052784
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1884561167
Short name T155
Test name
Test status
Simulation time 49632797 ps
CPU time 1.51 seconds
Started Feb 28 05:47:06 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 205512 kb
Host smart-246667af-60fb-43f0-adcb-c343f143ee31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884561167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1884561167
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2078851226
Short name T955
Test name
Test status
Simulation time 23276385 ps
CPU time 0.75 seconds
Started Feb 28 05:47:03 PM PST 24
Finished Feb 28 05:47:04 PM PST 24
Peak memory 205452 kb
Host smart-e8993f90-fc1a-4fef-9590-72d1bb71fa54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078851226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2078851226
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2010264771
Short name T961
Test name
Test status
Simulation time 81116453 ps
CPU time 1.43 seconds
Started Feb 28 05:47:04 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 205600 kb
Host smart-f23f06ae-9f10-4eb1-8c52-39aac5d33d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010264771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2010264771
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2259247846
Short name T126
Test name
Test status
Simulation time 45746955 ps
CPU time 1.67 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:07 PM PST 24
Peak memory 214020 kb
Host smart-2f0f9b53-3f58-4e04-a013-c8aff83a299f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259247846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2259247846
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1004525044
Short name T1000
Test name
Test status
Simulation time 1609017705 ps
CPU time 5.42 seconds
Started Feb 28 05:46:59 PM PST 24
Finished Feb 28 05:47:05 PM PST 24
Peak memory 214040 kb
Host smart-b553d612-a530-4d0f-b356-7977d1ce3942
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004525044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1004525044
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.851198401
Short name T907
Test name
Test status
Simulation time 213377970 ps
CPU time 4.11 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 213856 kb
Host smart-0ab51c8f-504d-4efe-b1f6-2497a7c2e547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851198401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.851198401
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3116988866
Short name T971
Test name
Test status
Simulation time 13779900 ps
CPU time 0.87 seconds
Started Feb 28 05:47:44 PM PST 24
Finished Feb 28 05:47:45 PM PST 24
Peak memory 205428 kb
Host smart-9e042ebf-45c8-4f6f-9f97-76eab4785c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116988866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3116988866
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3294275416
Short name T1054
Test name
Test status
Simulation time 32583050 ps
CPU time 0.76 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205448 kb
Host smart-1889da15-e23e-4c9a-b711-a6edecf45dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294275416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3294275416
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.719547347
Short name T983
Test name
Test status
Simulation time 9451100 ps
CPU time 0.81 seconds
Started Feb 28 05:47:43 PM PST 24
Finished Feb 28 05:47:44 PM PST 24
Peak memory 205424 kb
Host smart-f1eb955e-cb4b-454d-8327-9353c989154b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719547347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.719547347
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3943505630
Short name T1010
Test name
Test status
Simulation time 12010344 ps
CPU time 0.72 seconds
Started Feb 28 05:47:44 PM PST 24
Finished Feb 28 05:47:45 PM PST 24
Peak memory 205436 kb
Host smart-36a38a85-3696-4ff3-9ada-a173bae4f1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943505630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3943505630
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1953909869
Short name T933
Test name
Test status
Simulation time 58844331 ps
CPU time 0.92 seconds
Started Feb 28 05:47:44 PM PST 24
Finished Feb 28 05:47:45 PM PST 24
Peak memory 205432 kb
Host smart-b7029d59-7050-4d90-9d97-0de62dfff15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953909869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1953909869
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1852130906
Short name T918
Test name
Test status
Simulation time 9165982 ps
CPU time 0.83 seconds
Started Feb 28 05:47:33 PM PST 24
Finished Feb 28 05:47:34 PM PST 24
Peak memory 205356 kb
Host smart-57f9365a-0a52-43bf-85d0-691b10d43fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852130906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1852130906
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1217196526
Short name T1035
Test name
Test status
Simulation time 11232753 ps
CPU time 0.8 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205380 kb
Host smart-d8d47251-a2ff-4d54-b3e8-04ce67ffb567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217196526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1217196526
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1893555529
Short name T910
Test name
Test status
Simulation time 61283333 ps
CPU time 0.82 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205408 kb
Host smart-f9b849d2-e648-45f7-b6fa-66590a45503a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893555529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1893555529
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3564853005
Short name T962
Test name
Test status
Simulation time 42555685 ps
CPU time 0.82 seconds
Started Feb 28 05:47:38 PM PST 24
Finished Feb 28 05:47:40 PM PST 24
Peak memory 205440 kb
Host smart-fe48ab89-944a-4bca-87e5-7f3530275528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564853005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3564853005
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2387843784
Short name T913
Test name
Test status
Simulation time 10687711 ps
CPU time 0.69 seconds
Started Feb 28 05:47:31 PM PST 24
Finished Feb 28 05:47:32 PM PST 24
Peak memory 205396 kb
Host smart-a78361d0-df1b-427f-b2b9-1cea7ba50408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387843784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2387843784
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1363910618
Short name T919
Test name
Test status
Simulation time 69692807 ps
CPU time 1.3 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:07 PM PST 24
Peak memory 213856 kb
Host smart-4a64022a-8027-45ba-a5b5-eed7663c7734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363910618 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1363910618
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2519274622
Short name T1062
Test name
Test status
Simulation time 58632086 ps
CPU time 1.05 seconds
Started Feb 28 05:47:07 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 205484 kb
Host smart-a58b137f-bc5d-47c6-9253-a781ce814c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519274622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2519274622
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.330543304
Short name T936
Test name
Test status
Simulation time 13267662 ps
CPU time 0.73 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 205440 kb
Host smart-01152c64-2552-48df-8d47-78c7fc8418ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330543304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.330543304
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.914541125
Short name T940
Test name
Test status
Simulation time 46057452 ps
CPU time 1.53 seconds
Started Feb 28 05:47:03 PM PST 24
Finished Feb 28 05:47:05 PM PST 24
Peak memory 205676 kb
Host smart-4d9ab04b-fe85-4d08-a07f-774132da51b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914541125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.914541125
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1306026504
Short name T1027
Test name
Test status
Simulation time 278039526 ps
CPU time 4.45 seconds
Started Feb 28 05:47:02 PM PST 24
Finished Feb 28 05:47:07 PM PST 24
Peak memory 214032 kb
Host smart-81fec163-40e9-42a1-a0c5-f25ad51f917c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306026504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1306026504
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3403358863
Short name T1049
Test name
Test status
Simulation time 52868583 ps
CPU time 1.71 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:06 PM PST 24
Peak memory 222048 kb
Host smart-cf439107-6b9b-4ae2-8d8e-89b6ac0aac48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403358863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3403358863
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1372039534
Short name T1070
Test name
Test status
Simulation time 103096316 ps
CPU time 2.36 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 214072 kb
Host smart-1660f086-5f1d-4184-a529-e47e6762bf2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372039534 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1372039534
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3562873508
Short name T1052
Test name
Test status
Simulation time 25168480 ps
CPU time 1.15 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205556 kb
Host smart-3befca32-595a-413d-9db5-6a1c64053804
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562873508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3562873508
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3098920084
Short name T947
Test name
Test status
Simulation time 8069287 ps
CPU time 0.83 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205432 kb
Host smart-86c33289-b75f-46b4-bad3-ad5160515414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098920084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3098920084
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1387848348
Short name T1055
Test name
Test status
Simulation time 36419849 ps
CPU time 1.48 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205704 kb
Host smart-3fffeb5a-5187-47a8-ad4b-e638c67f3748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387848348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1387848348
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3617380456
Short name T127
Test name
Test status
Simulation time 99362056 ps
CPU time 3.13 seconds
Started Feb 28 05:47:08 PM PST 24
Finished Feb 28 05:47:12 PM PST 24
Peak memory 214028 kb
Host smart-2a43354f-ffc6-4a7e-aa01-91a2a75e8474
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617380456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3617380456
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3520866154
Short name T1029
Test name
Test status
Simulation time 243346522 ps
CPU time 4.4 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:10 PM PST 24
Peak memory 219508 kb
Host smart-792439c8-ffcd-405d-9ec2-49d0116dbbc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520866154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3520866154
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3057548015
Short name T1012
Test name
Test status
Simulation time 160855848 ps
CPU time 2.65 seconds
Started Feb 28 05:47:05 PM PST 24
Finished Feb 28 05:47:08 PM PST 24
Peak memory 213780 kb
Host smart-e0de03c2-63e8-4778-9efb-b8c50f69b18f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057548015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3057548015
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3022477622
Short name T395
Test name
Test status
Simulation time 91877540 ps
CPU time 3.85 seconds
Started Feb 28 05:47:12 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 209176 kb
Host smart-6358cd98-1bef-40e5-b130-c54bc3680261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022477622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3022477622
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2716756023
Short name T942
Test name
Test status
Simulation time 61910010 ps
CPU time 2.67 seconds
Started Feb 28 05:47:15 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 213900 kb
Host smart-9ab64e0c-74dd-4f84-a581-82309e8cf522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716756023 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2716756023
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1952094446
Short name T995
Test name
Test status
Simulation time 80178107 ps
CPU time 0.94 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 205320 kb
Host smart-6d492057-226a-4293-a694-c4a9659d75fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952094446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1952094446
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1147028611
Short name T996
Test name
Test status
Simulation time 16518687 ps
CPU time 0.81 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205328 kb
Host smart-0a36ad98-91cf-43ca-8389-2ee9502d6247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147028611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1147028611
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2226184408
Short name T158
Test name
Test status
Simulation time 38907884 ps
CPU time 1.47 seconds
Started Feb 28 05:47:10 PM PST 24
Finished Feb 28 05:47:13 PM PST 24
Peak memory 205604 kb
Host smart-43b59b7c-4a39-400b-88d9-02d7180477f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226184408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2226184408
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2547560159
Short name T1028
Test name
Test status
Simulation time 120373521 ps
CPU time 2.6 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 222088 kb
Host smart-99972451-14ac-4d62-b25b-a24ac90a4afd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547560159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2547560159
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3903361689
Short name T969
Test name
Test status
Simulation time 8486889642 ps
CPU time 12.94 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:28 PM PST 24
Peak memory 220308 kb
Host smart-e1a295e8-90d5-4af3-8607-c24dec0d674c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903361689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3903361689
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2586568783
Short name T1014
Test name
Test status
Simulation time 1927458817 ps
CPU time 2.96 seconds
Started Feb 28 05:47:12 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 221936 kb
Host smart-3a20ff04-66a4-4862-ba5b-f73b13cceab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586568783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2586568783
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.361624695
Short name T174
Test name
Test status
Simulation time 852718551 ps
CPU time 8.17 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 209060 kb
Host smart-6c35e244-7df3-4949-aa52-dbe57f774350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361624695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
361624695
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3454266178
Short name T965
Test name
Test status
Simulation time 89033823 ps
CPU time 1.13 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205616 kb
Host smart-3de86d59-ba90-4350-8a18-23558a14f404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454266178 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3454266178
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.827366684
Short name T1005
Test name
Test status
Simulation time 12979195 ps
CPU time 1.07 seconds
Started Feb 28 05:47:11 PM PST 24
Finished Feb 28 05:47:13 PM PST 24
Peak memory 205424 kb
Host smart-022e31cb-3576-4991-9809-d8a559940a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827366684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.827366684
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.526444384
Short name T914
Test name
Test status
Simulation time 12968573 ps
CPU time 0.8 seconds
Started Feb 28 05:47:10 PM PST 24
Finished Feb 28 05:47:12 PM PST 24
Peak memory 205436 kb
Host smart-b519c73e-917b-4939-bcc3-341160cc0940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526444384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.526444384
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1212972094
Short name T1038
Test name
Test status
Simulation time 47780514 ps
CPU time 1.73 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 205656 kb
Host smart-29b40ed5-ba48-4734-b704-856ab37f58fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212972094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1212972094
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2342945217
Short name T930
Test name
Test status
Simulation time 1152023082 ps
CPU time 7.21 seconds
Started Feb 28 05:47:11 PM PST 24
Finished Feb 28 05:47:19 PM PST 24
Peak memory 214016 kb
Host smart-86db19ce-a56d-4651-bc08-cce1faf95c59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342945217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2342945217
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2210875113
Short name T1008
Test name
Test status
Simulation time 992051450 ps
CPU time 8.66 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 214012 kb
Host smart-3e0eb8f2-bab5-43a0-a46a-18a7bff0b4c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210875113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2210875113
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2299783927
Short name T1002
Test name
Test status
Simulation time 53439997 ps
CPU time 3.32 seconds
Started Feb 28 05:47:12 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 213856 kb
Host smart-0932f7f7-90e0-46f1-9f7b-771b778758a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299783927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2299783927
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.63538959
Short name T1018
Test name
Test status
Simulation time 37073842 ps
CPU time 1.99 seconds
Started Feb 28 05:47:16 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 213972 kb
Host smart-c13d0b4a-bf72-40d5-bd39-9b9964da908c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63538959 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.63538959
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3021550135
Short name T169
Test name
Test status
Simulation time 53587903 ps
CPU time 1.21 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205564 kb
Host smart-b88ff4b0-073a-4bfa-beba-211fbadb8350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021550135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3021550135
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2531614935
Short name T959
Test name
Test status
Simulation time 8934689 ps
CPU time 0.78 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:15 PM PST 24
Peak memory 205472 kb
Host smart-25f14875-a3fa-4d92-9c26-025f6b4c2697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531614935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2531614935
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3802597914
Short name T1039
Test name
Test status
Simulation time 429226347 ps
CPU time 2.77 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:17 PM PST 24
Peak memory 205532 kb
Host smart-2beea125-c947-43f0-841d-e92b3974c40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802597914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3802597914
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3379959441
Short name T1063
Test name
Test status
Simulation time 999163644 ps
CPU time 4.2 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:18 PM PST 24
Peak memory 222208 kb
Host smart-175c9b87-98fb-4962-9303-9d3d43cf1dd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379959441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3379959441
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1896153907
Short name T1031
Test name
Test status
Simulation time 2170500108 ps
CPU time 8.48 seconds
Started Feb 28 05:47:13 PM PST 24
Finished Feb 28 05:47:23 PM PST 24
Peak memory 214060 kb
Host smart-3696ae72-a739-4e82-bbe2-194d475fa402
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896153907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1896153907
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2471479022
Short name T967
Test name
Test status
Simulation time 78132836 ps
CPU time 1.52 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:16 PM PST 24
Peak memory 213716 kb
Host smart-e7cfd5c8-c2a5-4d5e-a673-f3b63b1d0e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471479022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2471479022
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2511764599
Short name T1017
Test name
Test status
Simulation time 1345715605 ps
CPU time 7.38 seconds
Started Feb 28 05:47:14 PM PST 24
Finished Feb 28 05:47:22 PM PST 24
Peak memory 208832 kb
Host smart-5736daf8-d155-4e2c-ae76-dcb7c6da237c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511764599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2511764599
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.432250657
Short name T481
Test name
Test status
Simulation time 13051515 ps
CPU time 0.76 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:27 PM PST 24
Peak memory 205220 kb
Host smart-adbf9705-7de0-47bd-b244-0dc196a1142a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432250657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.432250657
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2591717328
Short name T433
Test name
Test status
Simulation time 274629779 ps
CPU time 15.99 seconds
Started Feb 28 06:30:20 PM PST 24
Finished Feb 28 06:30:36 PM PST 24
Peak memory 213668 kb
Host smart-0b426978-ab17-4b0b-b12c-a312ab888390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591717328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2591717328
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2592639362
Short name T31
Test name
Test status
Simulation time 72314981 ps
CPU time 2.75 seconds
Started Feb 28 06:30:23 PM PST 24
Finished Feb 28 06:30:26 PM PST 24
Peak memory 208920 kb
Host smart-01e7d025-6559-401e-bed8-2a073b2e43b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592639362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2592639362
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3043152478
Short name T626
Test name
Test status
Simulation time 147585672 ps
CPU time 3.46 seconds
Started Feb 28 06:30:19 PM PST 24
Finished Feb 28 06:30:23 PM PST 24
Peak memory 206520 kb
Host smart-3fa9db5c-6a10-4d0f-a642-c404ff79d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043152478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3043152478
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1461624039
Short name T97
Test name
Test status
Simulation time 3545805648 ps
CPU time 12.5 seconds
Started Feb 28 06:30:22 PM PST 24
Finished Feb 28 06:30:34 PM PST 24
Peak memory 220412 kb
Host smart-f625c34c-532c-45e3-99dc-de3949a6ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461624039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1461624039
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2120584811
Short name T817
Test name
Test status
Simulation time 3292040102 ps
CPU time 34.71 seconds
Started Feb 28 06:30:21 PM PST 24
Finished Feb 28 06:30:56 PM PST 24
Peak memory 221652 kb
Host smart-e940201c-e6b6-4fae-8de1-e61cc63fdec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120584811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2120584811
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3545945256
Short name T233
Test name
Test status
Simulation time 399794978 ps
CPU time 3.92 seconds
Started Feb 28 06:30:21 PM PST 24
Finished Feb 28 06:30:25 PM PST 24
Peak memory 218804 kb
Host smart-af3351f7-9eb7-4a24-8b8a-c778747a592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545945256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3545945256
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1663754896
Short name T222
Test name
Test status
Simulation time 412390910 ps
CPU time 4.9 seconds
Started Feb 28 06:30:20 PM PST 24
Finished Feb 28 06:30:25 PM PST 24
Peak memory 206544 kb
Host smart-32dc7c11-6f5f-4d91-9e14-a82a27cb1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663754896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1663754896
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2692620039
Short name T749
Test name
Test status
Simulation time 22202175 ps
CPU time 2.12 seconds
Started Feb 28 06:30:24 PM PST 24
Finished Feb 28 06:30:26 PM PST 24
Peak memory 205904 kb
Host smart-58f2a2ba-cf46-41d0-9cda-827ef711761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692620039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2692620039
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.715782805
Short name T866
Test name
Test status
Simulation time 4090926890 ps
CPU time 41.9 seconds
Started Feb 28 06:30:18 PM PST 24
Finished Feb 28 06:31:00 PM PST 24
Peak memory 207780 kb
Host smart-3c080bf6-7348-4e7b-9540-60ba1177a7b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715782805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.715782805
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2866894323
Short name T288
Test name
Test status
Simulation time 78488291 ps
CPU time 3.01 seconds
Started Feb 28 06:30:17 PM PST 24
Finished Feb 28 06:30:20 PM PST 24
Peak memory 208056 kb
Host smart-c8e62dbf-f254-4cda-a2bb-baa464389d0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866894323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2866894323
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1132549866
Short name T522
Test name
Test status
Simulation time 820995648 ps
CPU time 6.74 seconds
Started Feb 28 06:30:24 PM PST 24
Finished Feb 28 06:30:31 PM PST 24
Peak memory 207792 kb
Host smart-935cbc3b-edf9-45c6-b721-d9f85959f3c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132549866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1132549866
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.423040207
Short name T739
Test name
Test status
Simulation time 94265311 ps
CPU time 2.69 seconds
Started Feb 28 06:30:24 PM PST 24
Finished Feb 28 06:30:27 PM PST 24
Peak memory 208092 kb
Host smart-4e3b032f-9174-41d4-a2ca-a81378760edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423040207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.423040207
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.748914888
Short name T446
Test name
Test status
Simulation time 41046089 ps
CPU time 2.35 seconds
Started Feb 28 06:30:18 PM PST 24
Finished Feb 28 06:30:20 PM PST 24
Peak memory 206004 kb
Host smart-3e36ae67-caf9-4b84-89b1-4cdd6bba7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748914888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.748914888
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.305634119
Short name T667
Test name
Test status
Simulation time 294243727 ps
CPU time 11.71 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:38 PM PST 24
Peak memory 221848 kb
Host smart-90d012e2-1e0e-4dab-9b76-abc6466f32c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305634119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.305634119
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1652799365
Short name T239
Test name
Test status
Simulation time 618747905 ps
CPU time 19.47 seconds
Started Feb 28 06:30:25 PM PST 24
Finished Feb 28 06:30:45 PM PST 24
Peak memory 221956 kb
Host smart-cf41d4e0-4c76-415e-9df1-81331838362a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652799365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1652799365
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1795231813
Short name T819
Test name
Test status
Simulation time 201881565 ps
CPU time 3.34 seconds
Started Feb 28 06:30:21 PM PST 24
Finished Feb 28 06:30:25 PM PST 24
Peak memory 207500 kb
Host smart-667d914e-e1e5-4160-87e1-560f07a6ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795231813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1795231813
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.527916168
Short name T473
Test name
Test status
Simulation time 94137274 ps
CPU time 2.02 seconds
Started Feb 28 06:30:24 PM PST 24
Finished Feb 28 06:30:26 PM PST 24
Peak memory 209556 kb
Host smart-7c6e8356-dee6-468f-9a31-34f7b85af3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527916168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.527916168
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3945299432
Short name T590
Test name
Test status
Simulation time 13187081 ps
CPU time 0.7 seconds
Started Feb 28 06:30:39 PM PST 24
Finished Feb 28 06:30:40 PM PST 24
Peak memory 205320 kb
Host smart-30febfdd-3c1a-4a88-a5cf-d684fcfd3a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945299432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3945299432
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2709593408
Short name T273
Test name
Test status
Simulation time 236954821 ps
CPU time 4.29 seconds
Started Feb 28 06:30:27 PM PST 24
Finished Feb 28 06:30:31 PM PST 24
Peak memory 214612 kb
Host smart-d33f382e-a73a-44ce-83b7-7f452726ec92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709593408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2709593408
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1595796959
Short name T496
Test name
Test status
Simulation time 135258763 ps
CPU time 4.96 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:31 PM PST 24
Peak memory 209084 kb
Host smart-2ac2b91b-70fc-4bb5-821d-4bfbd1ddd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595796959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1595796959
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3413616959
Short name T28
Test name
Test status
Simulation time 1094871263 ps
CPU time 36.48 seconds
Started Feb 28 06:30:28 PM PST 24
Finished Feb 28 06:31:05 PM PST 24
Peak memory 213544 kb
Host smart-427576d9-b719-40bd-85e7-d9ac9bbf0546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413616959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3413616959
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.203951910
Short name T861
Test name
Test status
Simulation time 428651415 ps
CPU time 10.84 seconds
Started Feb 28 06:30:31 PM PST 24
Finished Feb 28 06:30:42 PM PST 24
Peak memory 213524 kb
Host smart-7db9a9dd-307f-4089-a280-2fda003a9057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203951910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.203951910
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.916446827
Short name T87
Test name
Test status
Simulation time 357751093 ps
CPU time 10.09 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:36 PM PST 24
Peak memory 209184 kb
Host smart-8ffbd751-73b6-4bc2-b3c4-8c3e2c9508d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916446827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.916446827
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2711401262
Short name T112
Test name
Test status
Simulation time 1289076449 ps
CPU time 22.27 seconds
Started Feb 28 06:30:32 PM PST 24
Finished Feb 28 06:30:55 PM PST 24
Peak memory 232444 kb
Host smart-3f648e09-2d9c-4266-b4f0-63c00efa1ec8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711401262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2711401262
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1171827310
Short name T211
Test name
Test status
Simulation time 199969276 ps
CPU time 2.62 seconds
Started Feb 28 06:30:23 PM PST 24
Finished Feb 28 06:30:26 PM PST 24
Peak memory 205840 kb
Host smart-9708db49-86e8-4971-a9d1-bb6423031013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171827310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1171827310
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3857434529
Short name T818
Test name
Test status
Simulation time 40622867 ps
CPU time 1.96 seconds
Started Feb 28 06:30:28 PM PST 24
Finished Feb 28 06:30:30 PM PST 24
Peak memory 207716 kb
Host smart-d011a628-39a3-41b8-8795-3eea4e41ba41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857434529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3857434529
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2083920823
Short name T891
Test name
Test status
Simulation time 189834834 ps
CPU time 2.72 seconds
Started Feb 28 06:30:28 PM PST 24
Finished Feb 28 06:30:31 PM PST 24
Peak memory 205912 kb
Host smart-ba57ba41-62f0-4ba5-88bf-6e64559fdc28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083920823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2083920823
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.837284459
Short name T526
Test name
Test status
Simulation time 156597595 ps
CPU time 2.66 seconds
Started Feb 28 06:30:27 PM PST 24
Finished Feb 28 06:30:30 PM PST 24
Peak memory 206084 kb
Host smart-28e067b6-6452-49b5-9536-e1f096311fbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837284459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.837284459
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.748941828
Short name T227
Test name
Test status
Simulation time 178002064 ps
CPU time 2.59 seconds
Started Feb 28 06:30:32 PM PST 24
Finished Feb 28 06:30:35 PM PST 24
Peak memory 215212 kb
Host smart-5e5da93a-972c-4c53-9c6b-8427374b3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748941828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.748941828
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.89063976
Short name T443
Test name
Test status
Simulation time 723306052 ps
CPU time 4.3 seconds
Started Feb 28 06:30:26 PM PST 24
Finished Feb 28 06:30:30 PM PST 24
Peak memory 205840 kb
Host smart-0adf3d53-e6fe-40f1-b143-ad95f638df96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89063976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.89063976
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.122210198
Short name T900
Test name
Test status
Simulation time 92224648 ps
CPU time 2.74 seconds
Started Feb 28 06:30:33 PM PST 24
Finished Feb 28 06:30:37 PM PST 24
Peak memory 206016 kb
Host smart-3db86bbc-36c8-4fe3-b7e4-32f8132a5bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122210198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.122210198
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.445560188
Short name T733
Test name
Test status
Simulation time 94258908 ps
CPU time 3.36 seconds
Started Feb 28 06:30:30 PM PST 24
Finished Feb 28 06:30:34 PM PST 24
Peak memory 207484 kb
Host smart-adb1c69b-c071-4d90-abe0-848756651605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445560188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.445560188
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.421976234
Short name T592
Test name
Test status
Simulation time 82943177 ps
CPU time 0.93 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:31:20 PM PST 24
Peak memory 205480 kb
Host smart-d2a86873-168d-458b-8d2a-f3b935fd5b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421976234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.421976234
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.175555800
Short name T42
Test name
Test status
Simulation time 325394542 ps
CPU time 4.9 seconds
Started Feb 28 06:31:16 PM PST 24
Finished Feb 28 06:31:21 PM PST 24
Peak memory 213540 kb
Host smart-370341da-41e1-4baf-a120-4569cd252209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175555800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.175555800
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.335695268
Short name T881
Test name
Test status
Simulation time 461977227 ps
CPU time 2.62 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:31:22 PM PST 24
Peak memory 208736 kb
Host smart-0f4f3a15-d695-4155-bdfd-2b6c955d514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335695268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.335695268
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2950276028
Short name T519
Test name
Test status
Simulation time 123819873 ps
CPU time 2.51 seconds
Started Feb 28 06:31:20 PM PST 24
Finished Feb 28 06:31:23 PM PST 24
Peak memory 206296 kb
Host smart-fa61f89d-4b05-4a6c-b64c-9f66e8cf7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950276028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2950276028
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4041705097
Short name T282
Test name
Test status
Simulation time 4116998515 ps
CPU time 54.66 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 221888 kb
Host smart-73cf3781-7f84-4050-9c4a-64a3cc3947e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041705097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4041705097
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1690306993
Short name T709
Test name
Test status
Simulation time 278486481 ps
CPU time 3.55 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:25 PM PST 24
Peak memory 218372 kb
Host smart-0e02b72d-7fe3-4cd8-b99a-4a879ef32087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690306993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1690306993
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1880767134
Short name T457
Test name
Test status
Simulation time 1673061865 ps
CPU time 10.75 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:31:26 PM PST 24
Peak memory 208200 kb
Host smart-6bc1403c-e67d-40fb-ac4a-40be1913ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880767134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1880767134
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2349343053
Short name T572
Test name
Test status
Simulation time 247539826 ps
CPU time 2.99 seconds
Started Feb 28 06:31:16 PM PST 24
Finished Feb 28 06:31:19 PM PST 24
Peak memory 205932 kb
Host smart-c9931c7c-078a-41c0-8c8c-a20ddcb31948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349343053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2349343053
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.677014490
Short name T655
Test name
Test status
Simulation time 906368812 ps
CPU time 6.66 seconds
Started Feb 28 06:31:20 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 207904 kb
Host smart-d66f20a3-2a47-4d19-80a6-c590d7fc126c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677014490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.677014490
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2407878651
Short name T320
Test name
Test status
Simulation time 662136883 ps
CPU time 18.48 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:31:34 PM PST 24
Peak memory 207416 kb
Host smart-d2560064-bc68-403c-bfef-96affa92ae23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407878651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2407878651
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4043949623
Short name T545
Test name
Test status
Simulation time 8282666198 ps
CPU time 62.8 seconds
Started Feb 28 06:31:17 PM PST 24
Finished Feb 28 06:32:20 PM PST 24
Peak memory 207516 kb
Host smart-5ced668b-fc6b-4f6a-a5bb-7bcfbc159b4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043949623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4043949623
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3557852795
Short name T830
Test name
Test status
Simulation time 2076838171 ps
CPU time 20.37 seconds
Started Feb 28 06:31:18 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 207872 kb
Host smart-d0f0307f-efe1-43c5-9e42-459f6b8a97d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557852795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3557852795
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2746896784
Short name T538
Test name
Test status
Simulation time 141865427 ps
CPU time 2.41 seconds
Started Feb 28 06:31:16 PM PST 24
Finished Feb 28 06:31:19 PM PST 24
Peak memory 206052 kb
Host smart-7e9b3322-da89-4622-b41c-493ff9fbf95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746896784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2746896784
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4268266952
Short name T51
Test name
Test status
Simulation time 314746861 ps
CPU time 7.27 seconds
Started Feb 28 06:31:20 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 221940 kb
Host smart-51f43f2d-c3a8-4582-8ac3-0b768d3a9b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268266952 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4268266952
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.666402455
Short name T672
Test name
Test status
Simulation time 113837346 ps
CPU time 4.91 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:26 PM PST 24
Peak memory 207880 kb
Host smart-f3902909-f942-473b-bd9d-c66c98f0983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666402455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.666402455
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4072306003
Short name T488
Test name
Test status
Simulation time 299545734 ps
CPU time 3.59 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:31:23 PM PST 24
Peak memory 209772 kb
Host smart-0e9f9218-b0b9-4669-8eeb-0e3a08a0010c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072306003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4072306003
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2327307669
Short name T732
Test name
Test status
Simulation time 21020601 ps
CPU time 0.69 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:22 PM PST 24
Peak memory 205288 kb
Host smart-11d5e259-c6aa-4400-a22e-14f0ca15c8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327307669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2327307669
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3831774948
Short name T161
Test name
Test status
Simulation time 194493452 ps
CPU time 4.14 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 213624 kb
Host smart-a5ff6318-fb94-46c3-902b-1d4194898735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831774948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3831774948
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2683666291
Short name T631
Test name
Test status
Simulation time 54936834 ps
CPU time 2.26 seconds
Started Feb 28 06:31:22 PM PST 24
Finished Feb 28 06:31:24 PM PST 24
Peak memory 207632 kb
Host smart-0e9db724-7217-4a36-bb05-d6359d6063e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683666291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2683666291
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2690639565
Short name T75
Test name
Test status
Simulation time 19931161 ps
CPU time 1.68 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:23 PM PST 24
Peak memory 207240 kb
Host smart-bd02457f-70be-4e92-ac72-a4663453c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690639565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2690639565
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2076696703
Short name T104
Test name
Test status
Simulation time 182992721 ps
CPU time 4.34 seconds
Started Feb 28 06:31:22 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 207780 kb
Host smart-765b39a7-4d19-4240-a91c-bdff98c94415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076696703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2076696703
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1094991970
Short name T335
Test name
Test status
Simulation time 709178718 ps
CPU time 10.71 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:34 PM PST 24
Peak memory 213636 kb
Host smart-ebd92628-2947-4660-a779-d494c7f48a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094991970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1094991970
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3911597115
Short name T665
Test name
Test status
Simulation time 847164829 ps
CPU time 4.79 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:28 PM PST 24
Peak memory 208972 kb
Host smart-082b7102-e276-47da-8ffb-6b0439171d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911597115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3911597115
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.366135423
Short name T653
Test name
Test status
Simulation time 756962916 ps
CPU time 6.56 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 213628 kb
Host smart-476e47d4-00f1-4282-8351-4b7f91c5a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366135423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.366135423
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1816954121
Short name T628
Test name
Test status
Simulation time 37472841 ps
CPU time 2.44 seconds
Started Feb 28 06:31:24 PM PST 24
Finished Feb 28 06:31:26 PM PST 24
Peak memory 206008 kb
Host smart-dedc7774-6e20-48c0-b842-f0cd64b71017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816954121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1816954121
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2046623434
Short name T544
Test name
Test status
Simulation time 207974160 ps
CPU time 5.85 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 206996 kb
Host smart-5b130c5a-ac15-4a89-b521-3b6883535413
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046623434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2046623434
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4055941567
Short name T704
Test name
Test status
Simulation time 34847590 ps
CPU time 2.25 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:25 PM PST 24
Peak memory 206176 kb
Host smart-7baf0100-e503-4f6a-9933-69c13f783f20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055941567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4055941567
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4228411581
Short name T903
Test name
Test status
Simulation time 179397486 ps
CPU time 2.18 seconds
Started Feb 28 06:31:22 PM PST 24
Finished Feb 28 06:31:24 PM PST 24
Peak memory 206652 kb
Host smart-afc16ac9-e79b-420f-a29f-e4e1b9a9f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228411581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4228411581
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4142075709
Short name T833
Test name
Test status
Simulation time 981095755 ps
CPU time 7.15 seconds
Started Feb 28 06:31:21 PM PST 24
Finished Feb 28 06:31:29 PM PST 24
Peak memory 207600 kb
Host smart-128f157c-adc4-4f9a-9bef-1edc72c93029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142075709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4142075709
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.543214879
Short name T575
Test name
Test status
Simulation time 343169544 ps
CPU time 5.59 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:29 PM PST 24
Peak memory 217652 kb
Host smart-70557953-ed0b-44e4-9a25-342057c65fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543214879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.543214879
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.691516498
Short name T791
Test name
Test status
Simulation time 709611986 ps
CPU time 6.22 seconds
Started Feb 28 06:31:23 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 217484 kb
Host smart-ca1f126e-3491-4931-a587-280abc95b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691516498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.691516498
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3285174433
Short name T695
Test name
Test status
Simulation time 14921976 ps
CPU time 0.87 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:31 PM PST 24
Peak memory 205336 kb
Host smart-6dd1c21c-86b7-4583-b41a-832e15bde641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285174433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3285174433
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.888979057
Short name T306
Test name
Test status
Simulation time 171697359 ps
CPU time 3.57 seconds
Started Feb 28 06:31:25 PM PST 24
Finished Feb 28 06:31:29 PM PST 24
Peak memory 214508 kb
Host smart-12c5b34d-7f02-447d-b1d7-86fb1a17a9ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888979057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.888979057
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2585386695
Short name T40
Test name
Test status
Simulation time 2032665656 ps
CPU time 12.66 seconds
Started Feb 28 06:31:26 PM PST 24
Finished Feb 28 06:31:40 PM PST 24
Peak memory 217488 kb
Host smart-8e13351e-e8d2-40b1-be54-3420f8de4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585386695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2585386695
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2730650089
Short name T734
Test name
Test status
Simulation time 136818842 ps
CPU time 3.79 seconds
Started Feb 28 06:31:26 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 217260 kb
Host smart-77633cdb-50c3-4dee-ba2d-df390fb34a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730650089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2730650089
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2288806052
Short name T92
Test name
Test status
Simulation time 291543807 ps
CPU time 6.93 seconds
Started Feb 28 06:31:26 PM PST 24
Finished Feb 28 06:31:34 PM PST 24
Peak memory 213652 kb
Host smart-7b08fc29-e6e8-40b6-af3a-f20bc75c9b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288806052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2288806052
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.151560142
Short name T603
Test name
Test status
Simulation time 67235068 ps
CPU time 2.87 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:31:31 PM PST 24
Peak memory 209312 kb
Host smart-654e152d-2d1b-49fc-a18c-7e288c2cffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151560142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.151560142
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.249541444
Short name T585
Test name
Test status
Simulation time 109662439 ps
CPU time 3.71 seconds
Started Feb 28 06:31:27 PM PST 24
Finished Feb 28 06:31:31 PM PST 24
Peak memory 207312 kb
Host smart-75c8a381-cba3-4c25-b181-14baadea1e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249541444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.249541444
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1343943272
Short name T137
Test name
Test status
Simulation time 240849930 ps
CPU time 3 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:31:31 PM PST 24
Peak memory 207544 kb
Host smart-e1777348-a1f1-4b17-b58c-8f6a2dcbed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343943272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1343943272
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1133430476
Short name T511
Test name
Test status
Simulation time 292148972 ps
CPU time 3.3 seconds
Started Feb 28 06:31:25 PM PST 24
Finished Feb 28 06:31:28 PM PST 24
Peak memory 207300 kb
Host smart-7178081c-4045-40f0-8b56-2ae836683bf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133430476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1133430476
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1618807834
Short name T879
Test name
Test status
Simulation time 498910928 ps
CPU time 7.15 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:31:36 PM PST 24
Peak memory 207712 kb
Host smart-ebae3dbd-7e0c-4c7f-bd44-42a940ae42a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618807834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1618807834
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4220944805
Short name T523
Test name
Test status
Simulation time 53934375 ps
CPU time 2.9 seconds
Started Feb 28 06:31:26 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 206052 kb
Host smart-39270e43-bfa7-4481-a9c7-5e70f7f83da1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220944805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4220944805
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2485036449
Short name T418
Test name
Test status
Simulation time 17217148 ps
CPU time 1.56 seconds
Started Feb 28 06:31:25 PM PST 24
Finished Feb 28 06:31:27 PM PST 24
Peak memory 207472 kb
Host smart-0e2b6794-9899-4dac-b8ca-4128002e8a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485036449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2485036449
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2692168261
Short name T880
Test name
Test status
Simulation time 339918060 ps
CPU time 3.03 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:31:31 PM PST 24
Peak memory 205836 kb
Host smart-202fc0d6-70de-480c-b0e4-246a1defb8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692168261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2692168261
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2083234802
Short name T248
Test name
Test status
Simulation time 1035474937 ps
CPU time 14.56 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 222024 kb
Host smart-5c1835b2-6b21-4b4b-995c-36d0a9bcd11c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083234802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2083234802
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1262611031
Short name T82
Test name
Test status
Simulation time 210823918 ps
CPU time 3.83 seconds
Started Feb 28 06:31:24 PM PST 24
Finished Feb 28 06:31:28 PM PST 24
Peak memory 213592 kb
Host smart-8691fa92-0e85-4359-b9b6-4d9bd2438409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262611031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1262611031
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3579625629
Short name T408
Test name
Test status
Simulation time 112789069 ps
CPU time 4.1 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:34 PM PST 24
Peak memory 209644 kb
Host smart-30a797be-c94c-4a4b-887f-dba0125ffbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579625629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3579625629
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3157318993
Short name T414
Test name
Test status
Simulation time 274391788 ps
CPU time 15.11 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 213760 kb
Host smart-1f8a6169-6a6c-4a10-8f0d-4d8740872746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157318993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3157318993
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.170745232
Short name T857
Test name
Test status
Simulation time 237307856 ps
CPU time 3.82 seconds
Started Feb 28 06:31:31 PM PST 24
Finished Feb 28 06:31:35 PM PST 24
Peak memory 218596 kb
Host smart-9f3e6af1-c7be-4b75-9ea9-1fe97bfca1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170745232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.170745232
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.444428009
Short name T76
Test name
Test status
Simulation time 128281297 ps
CPU time 5.18 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 206720 kb
Host smart-a9156aac-f7f9-4421-9f14-de58deafe3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444428009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.444428009
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.325717990
Short name T797
Test name
Test status
Simulation time 316873873 ps
CPU time 8.34 seconds
Started Feb 28 06:31:33 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 213572 kb
Host smart-ffb6dd2c-7662-46a7-8a24-0b53e2d32102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325717990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.325717990
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1096355413
Short name T285
Test name
Test status
Simulation time 73975234 ps
CPU time 4.52 seconds
Started Feb 28 06:31:33 PM PST 24
Finished Feb 28 06:31:38 PM PST 24
Peak memory 219436 kb
Host smart-700a1185-34dd-4ded-b4ca-faaca48fcf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096355413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1096355413
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2191655115
Short name T541
Test name
Test status
Simulation time 106232854 ps
CPU time 5.04 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:35 PM PST 24
Peak memory 209400 kb
Host smart-dba7f30a-ce27-4cbb-b099-d3219b5b6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191655115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2191655115
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1092164067
Short name T219
Test name
Test status
Simulation time 61456646 ps
CPU time 2.46 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:32 PM PST 24
Peak memory 206528 kb
Host smart-191fa22b-22a9-4bee-a975-f80a317c53be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092164067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1092164067
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2105916150
Short name T445
Test name
Test status
Simulation time 1491303076 ps
CPU time 6.48 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:37 PM PST 24
Peak memory 206076 kb
Host smart-74ebc5a1-b3f4-4b4c-81b9-becbd1690ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105916150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2105916150
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3604012022
Short name T543
Test name
Test status
Simulation time 1438602008 ps
CPU time 9.66 seconds
Started Feb 28 06:31:30 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 207272 kb
Host smart-27fbb5ab-54b9-401f-878c-dbc9cd4f4511
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604012022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3604012022
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2498368627
Short name T602
Test name
Test status
Simulation time 19760509562 ps
CPU time 40.73 seconds
Started Feb 28 06:31:29 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 208364 kb
Host smart-83799968-9ed2-4f9b-9ca8-ead99714a0d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498368627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2498368627
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.95231092
Short name T710
Test name
Test status
Simulation time 4162208563 ps
CPU time 42.72 seconds
Started Feb 28 06:31:28 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 207708 kb
Host smart-c14b35e5-cf27-451d-8952-af83354da594
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95231092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.95231092
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2107991105
Short name T804
Test name
Test status
Simulation time 46780405 ps
CPU time 3.2 seconds
Started Feb 28 06:31:31 PM PST 24
Finished Feb 28 06:31:35 PM PST 24
Peak memory 213680 kb
Host smart-a200bd7b-268e-4497-a26a-7d04a5282921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107991105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2107991105
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3418375514
Short name T83
Test name
Test status
Simulation time 51330364 ps
CPU time 2.72 seconds
Started Feb 28 06:31:32 PM PST 24
Finished Feb 28 06:31:35 PM PST 24
Peak memory 207392 kb
Host smart-44777613-dbb9-401a-abd3-72fdf8ec0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418375514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3418375514
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2315683907
Short name T700
Test name
Test status
Simulation time 608584554 ps
CPU time 6.99 seconds
Started Feb 28 06:31:32 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 209032 kb
Host smart-ce1bc07d-b4f4-459d-be04-e91d87fcc27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315683907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2315683907
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3076347210
Short name T1
Test name
Test status
Simulation time 90896783 ps
CPU time 2.21 seconds
Started Feb 28 06:31:32 PM PST 24
Finished Feb 28 06:31:34 PM PST 24
Peak memory 209460 kb
Host smart-aaed45a5-692f-4b1a-b10d-8e29ee8cb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076347210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3076347210
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1222906367
Short name T453
Test name
Test status
Simulation time 19476056 ps
CPU time 0.99 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:37 PM PST 24
Peak memory 205428 kb
Host smart-01b02d3f-14b5-46ea-8237-836384d924b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222906367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1222906367
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3087997542
Short name T746
Test name
Test status
Simulation time 361581510 ps
CPU time 10.45 seconds
Started Feb 28 06:31:35 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 207480 kb
Host smart-7d1d0693-59f7-4eca-bd1e-e81abcdc5ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087997542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3087997542
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1363236757
Short name T392
Test name
Test status
Simulation time 113545538 ps
CPU time 4.93 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 221800 kb
Host smart-5b69d956-b1c4-4074-baf6-f0d4c72fff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363236757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1363236757
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3210958350
Short name T301
Test name
Test status
Simulation time 1019906624 ps
CPU time 35.04 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:32:12 PM PST 24
Peak memory 210144 kb
Host smart-f9b56853-cf00-44ab-bf5e-0bd775cac026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210958350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3210958350
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2172985872
Short name T299
Test name
Test status
Simulation time 114887468 ps
CPU time 5.78 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 213652 kb
Host smart-83492249-2d98-4fdf-80bb-4274afcaec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172985872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2172985872
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4099555674
Short name T634
Test name
Test status
Simulation time 1231630276 ps
CPU time 8.99 seconds
Started Feb 28 06:31:35 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 213620 kb
Host smart-e47cb4ba-d336-4a94-92b8-d61ccd1517c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099555674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4099555674
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1017755791
Short name T579
Test name
Test status
Simulation time 41865945 ps
CPU time 2.98 seconds
Started Feb 28 06:31:31 PM PST 24
Finished Feb 28 06:31:35 PM PST 24
Peak memory 207840 kb
Host smart-70ed41c7-74b1-4014-94f6-228b911868cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017755791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1017755791
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3034181552
Short name T758
Test name
Test status
Simulation time 576693387 ps
CPU time 2.61 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 206028 kb
Host smart-52d04d6b-b772-4baa-bd80-e9432287d053
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034181552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3034181552
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1083614995
Short name T483
Test name
Test status
Simulation time 1388208673 ps
CPU time 42.53 seconds
Started Feb 28 06:31:34 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 207164 kb
Host smart-70715928-1809-4c65-9a33-c18d7b397061
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083614995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1083614995
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1469008861
Short name T870
Test name
Test status
Simulation time 692130486 ps
CPU time 6.06 seconds
Started Feb 28 06:31:35 PM PST 24
Finished Feb 28 06:31:41 PM PST 24
Peak memory 207496 kb
Host smart-8e98aa0e-a011-4f7e-a8a9-cb678078c743
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469008861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1469008861
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2500788881
Short name T604
Test name
Test status
Simulation time 128314510 ps
CPU time 2.23 seconds
Started Feb 28 06:31:33 PM PST 24
Finished Feb 28 06:31:36 PM PST 24
Peak memory 206836 kb
Host smart-6100e1de-b05d-4138-80b8-402dff90b9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500788881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2500788881
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4090058945
Short name T834
Test name
Test status
Simulation time 2410400471 ps
CPU time 22.68 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 222032 kb
Host smart-fdb93c42-ae6f-43c9-a845-2e567785afff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090058945 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4090058945
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.957464413
Short name T551
Test name
Test status
Simulation time 389702038 ps
CPU time 6.52 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:43 PM PST 24
Peak memory 217736 kb
Host smart-148f9a4f-e0e2-450f-8f70-718c86c61e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957464413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.957464413
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.303989306
Short name T743
Test name
Test status
Simulation time 50620070 ps
CPU time 2.84 seconds
Started Feb 28 06:31:37 PM PST 24
Finished Feb 28 06:31:40 PM PST 24
Peak memory 209020 kb
Host smart-2d6a0968-ae82-41af-9946-0d5e24a55bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303989306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.303989306
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1032960186
Short name T644
Test name
Test status
Simulation time 10675450 ps
CPU time 0.73 seconds
Started Feb 28 06:31:38 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 205368 kb
Host smart-15c8fced-373e-4df3-8e0d-1932ecd384c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032960186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1032960186
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2100349982
Short name T312
Test name
Test status
Simulation time 281439219 ps
CPU time 8.14 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 214592 kb
Host smart-4ffab9cc-c770-49da-9965-2b6203c8f6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100349982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2100349982
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3159974101
Short name T454
Test name
Test status
Simulation time 29412364 ps
CPU time 2.02 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:44 PM PST 24
Peak memory 206844 kb
Host smart-f444cfce-2bf8-48f9-bb96-576109b6ec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159974101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3159974101
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1704626840
Short name T284
Test name
Test status
Simulation time 1173336326 ps
CPU time 6.55 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 213596 kb
Host smart-b16f14b9-2acb-47de-965f-73a0df1d78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704626840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1704626840
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.3705331002
Short name T528
Test name
Test status
Simulation time 474729430 ps
CPU time 9.51 seconds
Started Feb 28 06:31:38 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 207436 kb
Host smart-48a9cbe7-f94d-4da4-a820-1f10d5a35942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705331002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3705331002
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2921369340
Short name T858
Test name
Test status
Simulation time 1880280497 ps
CPU time 20.07 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 207404 kb
Host smart-3b4e8042-ea38-490c-9aa9-3762f4dca35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921369340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2921369340
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3230579893
Short name T489
Test name
Test status
Simulation time 441978330 ps
CPU time 5.57 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:47 PM PST 24
Peak memory 207924 kb
Host smart-44e79a66-e52e-451b-a178-e7921383a962
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230579893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3230579893
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2566277971
Short name T491
Test name
Test status
Simulation time 53484445 ps
CPU time 2.3 seconds
Started Feb 28 06:31:37 PM PST 24
Finished Feb 28 06:31:40 PM PST 24
Peak memory 207844 kb
Host smart-d422f5c2-d2b8-4193-ae13-4b576024b720
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566277971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2566277971
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1201906017
Short name T666
Test name
Test status
Simulation time 1327075876 ps
CPU time 32.1 seconds
Started Feb 28 06:31:38 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 207988 kb
Host smart-840c7735-da9d-4574-bc5f-97ec3ad9898d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201906017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1201906017
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2079339453
Short name T325
Test name
Test status
Simulation time 24556362 ps
CPU time 1.76 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 208152 kb
Host smart-013aa9e8-1fe3-410a-98ff-89d6a531b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079339453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2079339453
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.64642396
Short name T554
Test name
Test status
Simulation time 96506072 ps
CPU time 2.09 seconds
Started Feb 28 06:31:37 PM PST 24
Finished Feb 28 06:31:40 PM PST 24
Peak memory 207760 kb
Host smart-120929e6-842b-462b-92e3-99cb0a367705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64642396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.64642396
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.389431494
Short name T134
Test name
Test status
Simulation time 237650132 ps
CPU time 9.88 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:52 PM PST 24
Peak memory 222000 kb
Host smart-e9980fdf-1a56-449d-9d46-e94e4514b6df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389431494 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.389431494
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.268910112
Short name T657
Test name
Test status
Simulation time 111444290 ps
CPU time 4.68 seconds
Started Feb 28 06:31:40 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 206848 kb
Host smart-2e8d926d-07d1-45e6-a538-97d91a4ad1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268910112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.268910112
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2930975515
Short name T173
Test name
Test status
Simulation time 66077984 ps
CPU time 2.53 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 209432 kb
Host smart-bd92fe4e-6fc5-49f5-9057-44fefd500b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930975515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2930975515
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2369800780
Short name T106
Test name
Test status
Simulation time 33253688 ps
CPU time 0.86 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 205320 kb
Host smart-58d36064-d479-4903-8373-e8843f2ceb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369800780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2369800780
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2566756790
Short name T823
Test name
Test status
Simulation time 125816987 ps
CPU time 2.79 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 214080 kb
Host smart-c3a9c36e-a564-4566-a5e7-4b78022c0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566756790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2566756790
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.870965901
Short name T761
Test name
Test status
Simulation time 135492163 ps
CPU time 3.3 seconds
Started Feb 28 06:31:37 PM PST 24
Finished Feb 28 06:31:41 PM PST 24
Peak memory 208616 kb
Host smart-783a96c0-bf82-470c-a30b-1f5456b66ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870965901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.870965901
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1617700696
Short name T660
Test name
Test status
Simulation time 513446632 ps
CPU time 4.58 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:44 PM PST 24
Peak memory 209124 kb
Host smart-a08ba704-f8f3-4fd3-bc15-73089097d361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617700696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1617700696
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1240290519
Short name T521
Test name
Test status
Simulation time 474284062 ps
CPU time 5.64 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 205896 kb
Host smart-1e6f77bb-5e0f-4224-87f1-9d78bf42201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240290519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1240290519
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.402902279
Short name T622
Test name
Test status
Simulation time 49588050 ps
CPU time 2.9 seconds
Started Feb 28 06:31:40 PM PST 24
Finished Feb 28 06:31:44 PM PST 24
Peak memory 207832 kb
Host smart-fa24e147-a7f7-4ed4-85cc-d94b71d8ec5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402902279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.402902279
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.238151160
Short name T569
Test name
Test status
Simulation time 234281123 ps
CPU time 2.59 seconds
Started Feb 28 06:31:39 PM PST 24
Finished Feb 28 06:31:42 PM PST 24
Peak memory 205988 kb
Host smart-fd28ffcf-a8e4-49eb-8f81-191d7969d6d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238151160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.238151160
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1485369257
Short name T651
Test name
Test status
Simulation time 39959339 ps
CPU time 2.5 seconds
Started Feb 28 06:31:36 PM PST 24
Finished Feb 28 06:31:39 PM PST 24
Peak memory 205836 kb
Host smart-b4032015-8810-4c3c-a014-24375c796919
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485369257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1485369257
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3506685992
Short name T598
Test name
Test status
Simulation time 94702520 ps
CPU time 1.82 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 206200 kb
Host smart-c2d6ce12-4d68-4ef7-9a94-1b4492896fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506685992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3506685992
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1313617603
Short name T444
Test name
Test status
Simulation time 55415692 ps
CPU time 2.69 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:47 PM PST 24
Peak memory 207708 kb
Host smart-86f2a004-427d-4120-8f03-37ac5ac03df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313617603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1313617603
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2383002178
Short name T250
Test name
Test status
Simulation time 4911031282 ps
CPU time 65.97 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 214944 kb
Host smart-52b2dded-aee7-4edb-b04f-45ce4938ea8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383002178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2383002178
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4192216999
Short name T322
Test name
Test status
Simulation time 591113043 ps
CPU time 5.05 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 213672 kb
Host smart-3537a419-8786-4908-a381-fd4ae7740c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192216999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4192216999
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1546862307
Short name T646
Test name
Test status
Simulation time 228468840 ps
CPU time 2.12 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 209344 kb
Host smart-edcb40af-a2ba-40f8-95b5-9ceb10839827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546862307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1546862307
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3184761983
Short name T872
Test name
Test status
Simulation time 32084537 ps
CPU time 0.97 seconds
Started Feb 28 06:31:47 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 205456 kb
Host smart-a8b93e5e-2d75-4bda-80bb-9f23b4eefc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184761983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3184761983
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1291312984
Short name T152
Test name
Test status
Simulation time 265632550 ps
CPU time 3.15 seconds
Started Feb 28 06:31:43 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 213596 kb
Host smart-0b2733f5-e5cf-4b4e-b6e2-47007467fe74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291312984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1291312984
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.22443862
Short name T350
Test name
Test status
Simulation time 46042146 ps
CPU time 2.6 seconds
Started Feb 28 06:31:46 PM PST 24
Finished Feb 28 06:31:49 PM PST 24
Peak memory 208484 kb
Host smart-a468e28a-b689-4b7e-952a-25461cd6a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22443862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.22443862
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.644743810
Short name T612
Test name
Test status
Simulation time 121450317 ps
CPU time 4.91 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 213612 kb
Host smart-8bfd522a-f3ad-4ec3-834d-803d6f57faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644743810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.644743810
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3124814528
Short name T568
Test name
Test status
Simulation time 608521563 ps
CPU time 7.51 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:55 PM PST 24
Peak memory 210036 kb
Host smart-34dd91df-0f3b-45f1-b149-d347fba661a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124814528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3124814528
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2903413264
Short name T624
Test name
Test status
Simulation time 106392429 ps
CPU time 3.23 seconds
Started Feb 28 06:31:46 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 208456 kb
Host smart-ac236984-c5ba-427b-bd56-db1c6d745567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903413264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2903413264
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2894799463
Short name T516
Test name
Test status
Simulation time 595843991 ps
CPU time 9.17 seconds
Started Feb 28 06:31:40 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 207552 kb
Host smart-ab8ba57a-186a-407b-b12c-8f0a20f05855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894799463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2894799463
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2522507526
Short name T790
Test name
Test status
Simulation time 76151547 ps
CPU time 3.47 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:31:46 PM PST 24
Peak memory 207860 kb
Host smart-4284bf2c-9e56-4203-9fa0-3f41d4295242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522507526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2522507526
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.967379377
Short name T714
Test name
Test status
Simulation time 115107149 ps
CPU time 3.15 seconds
Started Feb 28 06:31:41 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 206008 kb
Host smart-aa2370c4-685e-4f62-a8bb-fa11b0015c80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967379377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.967379377
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.323848904
Short name T504
Test name
Test status
Simulation time 45956626 ps
CPU time 2.73 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 207724 kb
Host smart-cb44a42d-d90f-4e29-8109-d4919993933a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323848904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.323848904
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2106205352
Short name T508
Test name
Test status
Simulation time 938078049 ps
CPU time 10.97 seconds
Started Feb 28 06:31:42 PM PST 24
Finished Feb 28 06:31:53 PM PST 24
Peak memory 207344 kb
Host smart-28e7846e-4bf0-4bef-b865-698a83481429
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106205352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2106205352
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3326605556
Short name T763
Test name
Test status
Simulation time 293684479 ps
CPU time 2.26 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:50 PM PST 24
Peak memory 213528 kb
Host smart-01f347fd-2a44-4e5d-8672-609ad3544d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326605556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3326605556
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1158675008
Short name T547
Test name
Test status
Simulation time 241417430 ps
CPU time 3.04 seconds
Started Feb 28 06:31:40 PM PST 24
Finished Feb 28 06:31:43 PM PST 24
Peak memory 207564 kb
Host smart-18f29ed5-6e35-4404-9e08-229a022a5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158675008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1158675008
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.339490785
Short name T581
Test name
Test status
Simulation time 237394301 ps
CPU time 3.8 seconds
Started Feb 28 06:31:45 PM PST 24
Finished Feb 28 06:31:49 PM PST 24
Peak memory 206380 kb
Host smart-f161a803-56af-4ba2-b20c-36f2520ce3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339490785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.339490785
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1685285769
Short name T493
Test name
Test status
Simulation time 41403177 ps
CPU time 0.85 seconds
Started Feb 28 06:31:52 PM PST 24
Finished Feb 28 06:31:54 PM PST 24
Peak memory 205240 kb
Host smart-fcf3ea39-3c77-4755-9917-c85222c86c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685285769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1685285769
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1936496760
Short name T321
Test name
Test status
Simulation time 303983392 ps
CPU time 8.82 seconds
Started Feb 28 06:31:52 PM PST 24
Finished Feb 28 06:32:01 PM PST 24
Peak memory 214772 kb
Host smart-b970831e-6568-4914-bac1-9eb8199c050e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936496760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1936496760
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4182266077
Short name T73
Test name
Test status
Simulation time 77318335 ps
CPU time 3.46 seconds
Started Feb 28 06:31:49 PM PST 24
Finished Feb 28 06:31:53 PM PST 24
Peak memory 208972 kb
Host smart-71e33b2a-f921-4d2c-8d22-d5132bab5a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182266077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4182266077
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2819786897
Short name T594
Test name
Test status
Simulation time 579251382 ps
CPU time 4.5 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:53 PM PST 24
Peak memory 210704 kb
Host smart-ea2a8e33-0166-4f3e-871e-db378f030b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819786897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2819786897
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.13207865
Short name T890
Test name
Test status
Simulation time 156982439 ps
CPU time 1.74 seconds
Started Feb 28 06:31:49 PM PST 24
Finished Feb 28 06:31:51 PM PST 24
Peak memory 205612 kb
Host smart-6dc2ebe3-668c-4584-90dc-feed221b665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13207865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.13207865
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1293073669
Short name T722
Test name
Test status
Simulation time 4675728817 ps
CPU time 84.85 seconds
Started Feb 28 06:31:46 PM PST 24
Finished Feb 28 06:33:12 PM PST 24
Peak memory 208228 kb
Host smart-5fe12669-8c3c-4abd-88a0-7cf7f86cbf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293073669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1293073669
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1571597637
Short name T205
Test name
Test status
Simulation time 148815181 ps
CPU time 3.1 seconds
Started Feb 28 06:31:47 PM PST 24
Finished Feb 28 06:31:51 PM PST 24
Peak memory 205976 kb
Host smart-5588045e-d648-4379-83e7-dfeb066bcb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571597637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1571597637
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2596450532
Short name T366
Test name
Test status
Simulation time 138990516 ps
CPU time 4.38 seconds
Started Feb 28 06:31:48 PM PST 24
Finished Feb 28 06:31:52 PM PST 24
Peak memory 207852 kb
Host smart-6397741f-bba8-433d-a51c-079476c8c735
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596450532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2596450532
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2013790655
Short name T692
Test name
Test status
Simulation time 111146656 ps
CPU time 2.28 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:47 PM PST 24
Peak memory 206008 kb
Host smart-247bdbb3-257d-40db-9da9-bb4d57ba23e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013790655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2013790655
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.628048476
Short name T120
Test name
Test status
Simulation time 208682722 ps
CPU time 5.57 seconds
Started Feb 28 06:31:46 PM PST 24
Finished Feb 28 06:31:52 PM PST 24
Peak memory 207656 kb
Host smart-b7066efd-49de-4bbd-95f7-5af0bc9cd804
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628048476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.628048476
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.348738008
Short name T307
Test name
Test status
Simulation time 2406083369 ps
CPU time 13.79 seconds
Started Feb 28 06:31:50 PM PST 24
Finished Feb 28 06:32:04 PM PST 24
Peak memory 208788 kb
Host smart-b6e2a625-4239-4056-a055-2659322f8d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348738008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.348738008
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1027864853
Short name T531
Test name
Test status
Simulation time 280438950 ps
CPU time 2.44 seconds
Started Feb 28 06:31:44 PM PST 24
Finished Feb 28 06:31:48 PM PST 24
Peak memory 206380 kb
Host smart-b10d1604-0f6c-43b5-aa82-da302cb74188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027864853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1027864853
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.510161679
Short name T213
Test name
Test status
Simulation time 240286083 ps
CPU time 4.23 seconds
Started Feb 28 06:31:49 PM PST 24
Finished Feb 28 06:31:53 PM PST 24
Peak memory 209128 kb
Host smart-a2326f56-650b-43a2-a868-9b5119a97af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510161679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.510161679
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1199702479
Short name T121
Test name
Test status
Simulation time 71180541 ps
CPU time 2.78 seconds
Started Feb 28 06:31:49 PM PST 24
Finished Feb 28 06:31:52 PM PST 24
Peak memory 209488 kb
Host smart-86a66662-6311-4b67-8c65-0a3a719ece28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199702479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1199702479
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1783402312
Short name T775
Test name
Test status
Simulation time 16344415 ps
CPU time 0.92 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:31:58 PM PST 24
Peak memory 205380 kb
Host smart-f249543d-0480-4c13-8037-06b6c82e3cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783402312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1783402312
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2155068831
Short name T65
Test name
Test status
Simulation time 291825296 ps
CPU time 3.44 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:31:58 PM PST 24
Peak memory 217628 kb
Host smart-1b239979-da9d-4d8e-9a78-bf9209f94eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155068831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2155068831
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3347389280
Short name T741
Test name
Test status
Simulation time 112184079 ps
CPU time 5.27 seconds
Started Feb 28 06:31:51 PM PST 24
Finished Feb 28 06:31:56 PM PST 24
Peak memory 207572 kb
Host smart-e95927cf-c8d9-43e2-a811-a1f6e9b0c348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347389280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3347389280
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.342121991
Short name T756
Test name
Test status
Simulation time 52651508 ps
CPU time 3.36 seconds
Started Feb 28 06:31:52 PM PST 24
Finished Feb 28 06:31:56 PM PST 24
Peak memory 208624 kb
Host smart-225247d1-254e-4dfc-899f-4a79159e6f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342121991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.342121991
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3827102188
Short name T550
Test name
Test status
Simulation time 214833683 ps
CPU time 3.73 seconds
Started Feb 28 06:31:52 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 208840 kb
Host smart-176872b1-5e2a-4c22-9452-354638676530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827102188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3827102188
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2669706289
Short name T148
Test name
Test status
Simulation time 29441491 ps
CPU time 2.34 seconds
Started Feb 28 06:31:55 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 205996 kb
Host smart-86535f95-d93d-425a-bac4-d1619038e21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669706289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2669706289
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.935253687
Short name T855
Test name
Test status
Simulation time 984439215 ps
CPU time 6.92 seconds
Started Feb 28 06:31:53 PM PST 24
Finished Feb 28 06:32:00 PM PST 24
Peak memory 207936 kb
Host smart-3842eb44-5126-421f-9507-439ab1740487
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935253687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.935253687
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3015654594
Short name T807
Test name
Test status
Simulation time 263491384 ps
CPU time 3.49 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:31:58 PM PST 24
Peak memory 205960 kb
Host smart-a2dc5b2a-c780-40f3-8b31-faca550102df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015654594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3015654594
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3706763812
Short name T345
Test name
Test status
Simulation time 827349258 ps
CPU time 3.81 seconds
Started Feb 28 06:31:53 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 207544 kb
Host smart-9888669d-a2c4-4ba2-9c48-64b44a90026f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706763812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3706763812
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2045252258
Short name T786
Test name
Test status
Simulation time 237769151 ps
CPU time 5.19 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:32:00 PM PST 24
Peak memory 209316 kb
Host smart-5e65bf11-9900-48d9-9413-88baee728618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045252258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2045252258
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1458786694
Short name T799
Test name
Test status
Simulation time 127502075 ps
CPU time 4.95 seconds
Started Feb 28 06:31:50 PM PST 24
Finished Feb 28 06:31:56 PM PST 24
Peak memory 205856 kb
Host smart-306f8fd7-b7ab-4192-8019-36a2b4b95be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458786694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1458786694
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2802048040
Short name T595
Test name
Test status
Simulation time 2235499921 ps
CPU time 18.24 seconds
Started Feb 28 06:31:56 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 214448 kb
Host smart-0d00b1e8-88af-40d5-b908-8ed7a1d71a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802048040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2802048040
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3644253388
Short name T821
Test name
Test status
Simulation time 78998456 ps
CPU time 2.16 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:31:59 PM PST 24
Peak memory 209184 kb
Host smart-e136ec4a-1489-4d9d-a8f1-8b88c671a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644253388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3644253388
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1933282966
Short name T487
Test name
Test status
Simulation time 52725745 ps
CPU time 0.72 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:37 PM PST 24
Peak memory 205260 kb
Host smart-25f70d83-ba53-472d-958a-d5ca5aee50a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933282966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1933282966
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.332136583
Short name T430
Test name
Test status
Simulation time 91054723 ps
CPU time 2.83 seconds
Started Feb 28 06:30:32 PM PST 24
Finished Feb 28 06:30:35 PM PST 24
Peak memory 214768 kb
Host smart-9e2dc617-6248-448f-adb6-c90b6c4185d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332136583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.332136583
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2226692720
Short name T19
Test name
Test status
Simulation time 223547781 ps
CPU time 4.47 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:41 PM PST 24
Peak memory 209972 kb
Host smart-b9ff0baa-5760-4f3c-860f-65092416d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226692720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2226692720
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.939849581
Short name T771
Test name
Test status
Simulation time 575971163 ps
CPU time 2.11 seconds
Started Feb 28 06:30:33 PM PST 24
Finished Feb 28 06:30:36 PM PST 24
Peak memory 206296 kb
Host smart-ca834fc6-7a85-4b63-9d66-7eeafcfbe3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939849581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.939849581
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2767220981
Short name T96
Test name
Test status
Simulation time 46626578 ps
CPU time 3.03 seconds
Started Feb 28 06:30:38 PM PST 24
Finished Feb 28 06:30:41 PM PST 24
Peak memory 208216 kb
Host smart-4bfec9df-b84f-4526-87fc-8d913b465bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767220981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2767220981
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3104043877
Short name T664
Test name
Test status
Simulation time 103530035 ps
CPU time 3.18 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:40 PM PST 24
Peak memory 209128 kb
Host smart-358d640a-1503-4c1e-83e0-a63db387692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104043877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3104043877
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3650336442
Short name T328
Test name
Test status
Simulation time 2390220719 ps
CPU time 55.63 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:31:37 PM PST 24
Peak memory 207588 kb
Host smart-ae20d009-39c5-4355-a6f9-ace3cd39dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650336442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3650336442
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1383871792
Short name T11
Test name
Test status
Simulation time 5659877520 ps
CPU time 23.65 seconds
Started Feb 28 06:30:37 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 231308 kb
Host smart-617949ef-99ce-4ee6-9121-2da26d1eb7cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383871792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1383871792
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2169680097
Short name T512
Test name
Test status
Simulation time 897171583 ps
CPU time 21.07 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:31:02 PM PST 24
Peak memory 206944 kb
Host smart-b54e6d99-d268-4137-ab3c-e8fa99ebde02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169680097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2169680097
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.688055887
Short name T303
Test name
Test status
Simulation time 274435297 ps
CPU time 4.32 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:30:45 PM PST 24
Peak memory 207692 kb
Host smart-8a678c79-e2d6-4b46-a487-b8b364e81002
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688055887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.688055887
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1714634386
Short name T637
Test name
Test status
Simulation time 29455626 ps
CPU time 2.11 seconds
Started Feb 28 06:30:40 PM PST 24
Finished Feb 28 06:30:42 PM PST 24
Peak memory 207748 kb
Host smart-396bb2e6-9233-4248-99ee-1bde0f7ba54c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714634386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1714634386
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2071479454
Short name T261
Test name
Test status
Simulation time 6251918643 ps
CPU time 63.8 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 207496 kb
Host smart-ad2b3c28-751b-4a3d-a2d1-e796412da7ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071479454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2071479454
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.740318416
Short name T409
Test name
Test status
Simulation time 77884486 ps
CPU time 3.79 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:40 PM PST 24
Peak memory 209092 kb
Host smart-0808c827-918a-44bd-9e71-570c441cd01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740318416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.740318416
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1764775816
Short name T874
Test name
Test status
Simulation time 2616759115 ps
CPU time 27.56 seconds
Started Feb 28 06:30:30 PM PST 24
Finished Feb 28 06:30:57 PM PST 24
Peak memory 207604 kb
Host smart-a599f878-acfb-4559-9195-2693543974c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764775816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1764775816
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2431163783
Short name T202
Test name
Test status
Simulation time 299210692 ps
CPU time 5.8 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:42 PM PST 24
Peak memory 216540 kb
Host smart-bb2c4e3b-f4b4-4068-997a-2c263c8df890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431163783 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2431163783
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.117927045
Short name T220
Test name
Test status
Simulation time 486359702 ps
CPU time 9.71 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:46 PM PST 24
Peak memory 217720 kb
Host smart-e921d20a-57da-48ff-9a0b-7619caf5d750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117927045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.117927045
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1280209083
Short name T201
Test name
Test status
Simulation time 42542202 ps
CPU time 2.02 seconds
Started Feb 28 06:30:36 PM PST 24
Finished Feb 28 06:30:39 PM PST 24
Peak memory 208860 kb
Host smart-9aa66cb4-a8fb-4cfe-901d-f8806851cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280209083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1280209083
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2329770760
Short name T639
Test name
Test status
Simulation time 39969647 ps
CPU time 0.75 seconds
Started Feb 28 06:31:58 PM PST 24
Finished Feb 28 06:31:59 PM PST 24
Peak memory 205336 kb
Host smart-739bdbe3-9e86-4e01-977b-ef9d0073f896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329770760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2329770760
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.260191630
Short name T22
Test name
Test status
Simulation time 106195598 ps
CPU time 2.53 seconds
Started Feb 28 06:31:58 PM PST 24
Finished Feb 28 06:32:01 PM PST 24
Peak memory 216580 kb
Host smart-6497b46f-4562-4413-8601-816b7c9387c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260191630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.260191630
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3931771932
Short name T54
Test name
Test status
Simulation time 146433736 ps
CPU time 4.31 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:31:59 PM PST 24
Peak memory 213544 kb
Host smart-b3703dfd-71b4-4991-9730-744009c3c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931771932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3931771932
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3776612823
Short name T738
Test name
Test status
Simulation time 103785997 ps
CPU time 3.6 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:32:01 PM PST 24
Peak memory 214568 kb
Host smart-d7a4b67c-31f8-41cb-bc2a-a0b2cb7d5738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776612823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3776612823
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2219877350
Short name T333
Test name
Test status
Simulation time 256774986 ps
CPU time 5.75 seconds
Started Feb 28 06:31:55 PM PST 24
Finished Feb 28 06:32:01 PM PST 24
Peak memory 207664 kb
Host smart-d67ab992-aadb-4230-a7a5-7599f73373e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219877350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2219877350
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3155248573
Short name T633
Test name
Test status
Simulation time 84639006 ps
CPU time 3.92 seconds
Started Feb 28 06:31:56 PM PST 24
Finished Feb 28 06:32:00 PM PST 24
Peak memory 208132 kb
Host smart-4f353305-4c1f-4666-9a0c-1ced6277720f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155248573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3155248573
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2572799440
Short name T751
Test name
Test status
Simulation time 125632090 ps
CPU time 1.75 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:31:59 PM PST 24
Peak memory 205924 kb
Host smart-4aef1f0a-e3ee-4b8d-afaa-64933e13b6ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572799440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2572799440
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3110142930
Short name T694
Test name
Test status
Simulation time 241797235 ps
CPU time 3.07 seconds
Started Feb 28 06:31:54 PM PST 24
Finished Feb 28 06:31:57 PM PST 24
Peak memory 206128 kb
Host smart-6a69ff3c-891e-48a0-99ab-a034217321fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110142930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3110142930
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2474575348
Short name T411
Test name
Test status
Simulation time 78337865 ps
CPU time 2.54 seconds
Started Feb 28 06:32:00 PM PST 24
Finished Feb 28 06:32:03 PM PST 24
Peak memory 214096 kb
Host smart-0146cf45-ea8b-4157-ba07-f28241f8853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474575348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2474575348
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.849400949
Short name T778
Test name
Test status
Simulation time 79391227 ps
CPU time 1.93 seconds
Started Feb 28 06:31:56 PM PST 24
Finished Feb 28 06:31:58 PM PST 24
Peak memory 205996 kb
Host smart-f287b0d9-668d-4f08-bd88-7efb257636bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849400949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.849400949
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4186283657
Short name T820
Test name
Test status
Simulation time 302118815 ps
CPU time 9.49 seconds
Started Feb 28 06:31:58 PM PST 24
Finished Feb 28 06:32:07 PM PST 24
Peak memory 209224 kb
Host smart-2a0e01c8-92be-4a91-8cf6-d19fc2d4ceaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186283657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4186283657
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2335304173
Short name T578
Test name
Test status
Simulation time 254601125 ps
CPU time 7.09 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 208944 kb
Host smart-fb79f8a3-29cf-4e61-94a1-9f63545f1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335304173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2335304173
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1237951382
Short name T533
Test name
Test status
Simulation time 97189593 ps
CPU time 1.87 seconds
Started Feb 28 06:31:58 PM PST 24
Finished Feb 28 06:32:00 PM PST 24
Peak memory 209076 kb
Host smart-864400f2-3a26-4e48-8e04-2286eaf979fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237951382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1237951382
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2866783195
Short name T593
Test name
Test status
Simulation time 235606577 ps
CPU time 0.93 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:04 PM PST 24
Peak memory 205428 kb
Host smart-aac3d980-bd0a-46dc-afb1-080f7824dd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866783195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2866783195
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1593442299
Short name T330
Test name
Test status
Simulation time 201037095 ps
CPU time 6.23 seconds
Started Feb 28 06:32:01 PM PST 24
Finished Feb 28 06:32:07 PM PST 24
Peak memory 213832 kb
Host smart-0a47f0d3-641e-4b60-8890-067eb7fa23f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593442299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1593442299
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.835001131
Short name T902
Test name
Test status
Simulation time 646006091 ps
CPU time 5.06 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 208576 kb
Host smart-a3e84de8-d2af-45f4-9776-89a10f113677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835001131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.835001131
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1915262733
Short name T53
Test name
Test status
Simulation time 351461012 ps
CPU time 10.66 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 208284 kb
Host smart-0bb6e06f-dfd6-409b-852e-a45d990e634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915262733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1915262733
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1875564593
Short name T424
Test name
Test status
Simulation time 1001928994 ps
CPU time 5.37 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 213560 kb
Host smart-45dddc36-a8e6-47da-a2d6-6aa8c6c02bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875564593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1875564593
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2937856152
Short name T377
Test name
Test status
Simulation time 3174289980 ps
CPU time 37.02 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:44 PM PST 24
Peak memory 221844 kb
Host smart-54153ae8-b38c-4bb7-b294-d4743bfaf311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937856152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2937856152
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.451765113
Short name T779
Test name
Test status
Simulation time 409185669 ps
CPU time 5.09 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 206980 kb
Host smart-2c538875-5207-4865-9a72-9cf39b354108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451765113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.451765113
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.347327151
Short name T678
Test name
Test status
Simulation time 194469563 ps
CPU time 4.99 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 206896 kb
Host smart-67cb2b30-e9c9-4a63-87ed-16bdf2d00a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347327151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.347327151
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2668348418
Short name T696
Test name
Test status
Simulation time 1359201779 ps
CPU time 17.13 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:32:15 PM PST 24
Peak memory 207136 kb
Host smart-82a1f3bb-37e0-46c3-bd6d-adb842b2879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668348418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2668348418
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4262023119
Short name T139
Test name
Test status
Simulation time 674379247 ps
CPU time 17.38 seconds
Started Feb 28 06:31:56 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 207936 kb
Host smart-e6d76abb-d511-48ab-afda-f0a211e3523b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262023119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4262023119
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3213784924
Short name T326
Test name
Test status
Simulation time 68890989 ps
CPU time 2.92 seconds
Started Feb 28 06:31:59 PM PST 24
Finished Feb 28 06:32:02 PM PST 24
Peak memory 206020 kb
Host smart-14bd7e2f-069c-404c-8860-7b1be7483769
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213784924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3213784924
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1099774349
Short name T546
Test name
Test status
Simulation time 136609947 ps
CPU time 1.98 seconds
Started Feb 28 06:31:57 PM PST 24
Finished Feb 28 06:31:59 PM PST 24
Peak memory 206724 kb
Host smart-5c6386be-2f72-4a26-bdb1-bc6edf884378
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099774349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1099774349
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2577136010
Short name T534
Test name
Test status
Simulation time 184700985 ps
CPU time 3.28 seconds
Started Feb 28 06:32:00 PM PST 24
Finished Feb 28 06:32:03 PM PST 24
Peak memory 215112 kb
Host smart-1e6686bb-aba7-42e9-be7d-6662387d182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577136010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2577136010
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.914500592
Short name T684
Test name
Test status
Simulation time 490002856 ps
CPU time 6.3 seconds
Started Feb 28 06:32:01 PM PST 24
Finished Feb 28 06:32:07 PM PST 24
Peak memory 205924 kb
Host smart-8aa7127d-9374-40bb-8cea-045aa60b89fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914500592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.914500592
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.209687795
Short name T897
Test name
Test status
Simulation time 2989301382 ps
CPU time 10.65 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 214680 kb
Host smart-54268e91-9dbf-4c56-9a6a-2079217327da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209687795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.209687795
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1510448212
Short name T267
Test name
Test status
Simulation time 106318300 ps
CPU time 5.13 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 209184 kb
Host smart-200ccdc7-d3ba-42f0-a879-755479e57df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510448212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1510448212
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1594320716
Short name T676
Test name
Test status
Simulation time 69080851 ps
CPU time 2.05 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 208904 kb
Host smart-8f557256-5845-4583-82a3-2f26f429a371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594320716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1594320716
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1096469866
Short name T482
Test name
Test status
Simulation time 18203954 ps
CPU time 0.82 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:06 PM PST 24
Peak memory 205292 kb
Host smart-0c188b52-225e-4bec-b896-2b392aa76ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096469866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1096469866
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2175084250
Short name T142
Test name
Test status
Simulation time 43961933 ps
CPU time 2.05 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:04 PM PST 24
Peak memory 207964 kb
Host smart-e74b26df-1bad-4b61-93cb-1220c621bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175084250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2175084250
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2654338489
Short name T711
Test name
Test status
Simulation time 217204047 ps
CPU time 4.02 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 208236 kb
Host smart-c869f14c-34b7-4aeb-a964-6f505cdc5a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654338489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2654338489
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3440961783
Short name T232
Test name
Test status
Simulation time 141389853 ps
CPU time 3.36 seconds
Started Feb 28 06:32:05 PM PST 24
Finished Feb 28 06:32:09 PM PST 24
Peak memory 213692 kb
Host smart-8de16c53-c9a8-4663-81c3-75f392c2bfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440961783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3440961783
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2785132827
Short name T859
Test name
Test status
Simulation time 1649010778 ps
CPU time 10.51 seconds
Started Feb 28 06:32:01 PM PST 24
Finished Feb 28 06:32:12 PM PST 24
Peak memory 217684 kb
Host smart-795d9cf7-155d-4a0b-81aa-e3bc35a2d4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785132827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2785132827
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1413255587
Short name T506
Test name
Test status
Simulation time 238798365 ps
CPU time 6.12 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 205892 kb
Host smart-90eeeea0-ddd6-4c2e-8db0-b03595862a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413255587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1413255587
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.31145720
Short name T801
Test name
Test status
Simulation time 896689009 ps
CPU time 4.19 seconds
Started Feb 28 06:32:00 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 207820 kb
Host smart-ed8d6434-b3d2-4da5-9075-6a7b92c7041a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.31145720
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.673073892
Short name T829
Test name
Test status
Simulation time 247990502 ps
CPU time 3.44 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 205960 kb
Host smart-2ab44424-ece4-484f-8a42-90e1cd412b39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673073892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.673073892
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1114949699
Short name T587
Test name
Test status
Simulation time 60468964 ps
CPU time 3.2 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 207716 kb
Host smart-b86f2c08-c678-45fb-816c-581b3af59945
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114949699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1114949699
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4005564718
Short name T854
Test name
Test status
Simulation time 242821289 ps
CPU time 2.33 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 206756 kb
Host smart-28b0245c-aa33-4010-9aa2-337aa96eb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005564718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4005564718
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3355081955
Short name T507
Test name
Test status
Simulation time 1467017369 ps
CPU time 10.3 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 207576 kb
Host smart-830a9c34-f976-4a85-948c-c7c8b4c84502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355081955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3355081955
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1938163430
Short name T316
Test name
Test status
Simulation time 760916717 ps
CPU time 14.07 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:18 PM PST 24
Peak memory 215980 kb
Host smart-674a3a9e-503b-4520-9098-100c9116a146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938163430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1938163430
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2497209342
Short name T509
Test name
Test status
Simulation time 404520882 ps
CPU time 6.59 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 209264 kb
Host smart-3fa3795e-1242-4969-8d4c-e5ce04d83209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497209342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2497209342
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1932955424
Short name T37
Test name
Test status
Simulation time 50788853 ps
CPU time 2.41 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:09 PM PST 24
Peak memory 208928 kb
Host smart-cd7993cd-4360-4027-ac49-6c7153cfdbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932955424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1932955424
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1614535549
Short name T705
Test name
Test status
Simulation time 47907107 ps
CPU time 0.75 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:12 PM PST 24
Peak memory 205268 kb
Host smart-75e80eb0-a78e-4b49-83af-9557a1e78545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614535549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1614535549
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1940099121
Short name T13
Test name
Test status
Simulation time 694010654 ps
CPU time 8.04 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 221864 kb
Host smart-ad35ee24-2cfe-40b9-a269-12c1f0d95d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940099121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1940099121
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.277923826
Short name T498
Test name
Test status
Simulation time 153981812 ps
CPU time 1.76 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 206972 kb
Host smart-e8b026c2-c7f2-457f-b074-f2f455bd235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277923826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.277923826
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.408256533
Short name T364
Test name
Test status
Simulation time 71775781 ps
CPU time 3.84 seconds
Started Feb 28 06:32:08 PM PST 24
Finished Feb 28 06:32:12 PM PST 24
Peak memory 209536 kb
Host smart-798bb451-880b-49ca-a1a5-3f54d49a7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408256533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.408256533
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3664099325
Short name T402
Test name
Test status
Simulation time 149325442 ps
CPU time 5.26 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:15 PM PST 24
Peak memory 210760 kb
Host smart-624d7273-0006-48b2-8025-52697c6b9613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664099325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3664099325
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2698048626
Short name T564
Test name
Test status
Simulation time 250691651 ps
CPU time 3.15 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 208176 kb
Host smart-246f268e-b876-4701-a4c1-0748a819cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698048626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2698048626
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3470677633
Short name T780
Test name
Test status
Simulation time 301153511 ps
CPU time 10.49 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 209444 kb
Host smart-452e9f47-71f3-4e53-a2aa-e453528dbb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470677633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3470677633
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1875494676
Short name T848
Test name
Test status
Simulation time 860480938 ps
CPU time 3.66 seconds
Started Feb 28 06:32:03 PM PST 24
Finished Feb 28 06:32:07 PM PST 24
Peak memory 207432 kb
Host smart-1ffd73a5-f680-4736-9049-1389832de186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875494676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1875494676
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1829735652
Short name T767
Test name
Test status
Simulation time 169144037 ps
CPU time 3.4 seconds
Started Feb 28 06:32:02 PM PST 24
Finished Feb 28 06:32:05 PM PST 24
Peak memory 207536 kb
Host smart-c674f4c4-2291-4caf-ab8e-24465d1d5467
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829735652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1829735652
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3136530935
Short name T143
Test name
Test status
Simulation time 1619838294 ps
CPU time 23.19 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:30 PM PST 24
Peak memory 207308 kb
Host smart-4096715c-9714-4bcc-9f97-d92e30a8656d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136530935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3136530935
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1044879208
Short name T503
Test name
Test status
Simulation time 92089001 ps
CPU time 3.15 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 206468 kb
Host smart-0371dd52-de76-42b8-be5b-43901bcea932
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044879208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1044879208
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.88684403
Short name T789
Test name
Test status
Simulation time 44750848 ps
CPU time 2.36 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 214840 kb
Host smart-420772c2-c3b2-4d35-84f5-71c63bef4b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88684403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.88684403
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1249121105
Short name T441
Test name
Test status
Simulation time 210422648 ps
CPU time 5.31 seconds
Started Feb 28 06:32:04 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 207684 kb
Host smart-e13191c8-f605-4e8b-a69c-7f074c081b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249121105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1249121105
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3032425373
Short name T279
Test name
Test status
Simulation time 218627455 ps
CPU time 3.95 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 208708 kb
Host smart-9c6ce961-24dd-4ecb-9a7c-8f6d1b3ea8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032425373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3032425373
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2165936735
Short name T899
Test name
Test status
Simulation time 105768767 ps
CPU time 3.51 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:12 PM PST 24
Peak memory 209468 kb
Host smart-a605451a-e426-4153-8c8c-ee2a50ba56aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165936735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2165936735
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3811498415
Short name T469
Test name
Test status
Simulation time 24476209 ps
CPU time 1 seconds
Started Feb 28 06:32:12 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 205484 kb
Host smart-58c67497-bbc8-461f-9d52-0a1b39239254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811498415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3811498415
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3306293980
Short name T147
Test name
Test status
Simulation time 38686533 ps
CPU time 3.28 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:15 PM PST 24
Peak memory 213660 kb
Host smart-7a2194de-1d56-451c-ad8d-be8b2d58eeb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306293980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3306293980
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2947210901
Short name T241
Test name
Test status
Simulation time 4929254098 ps
CPU time 24.41 seconds
Started Feb 28 06:32:12 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 218344 kb
Host smart-dd4d4fdc-f624-4bef-aea8-1b9d5e411c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947210901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2947210901
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.791403949
Short name T765
Test name
Test status
Simulation time 777230982 ps
CPU time 4.5 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:15 PM PST 24
Peak memory 207900 kb
Host smart-84d66209-7abc-41f0-bb6a-f7878abf5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791403949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.791403949
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3835568794
Short name T661
Test name
Test status
Simulation time 215526949 ps
CPU time 2.94 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 208480 kb
Host smart-9b8e4cda-463f-4f64-bfea-f748df6a468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835568794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3835568794
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4138703846
Short name T460
Test name
Test status
Simulation time 92170814 ps
CPU time 4.26 seconds
Started Feb 28 06:32:06 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 206632 kb
Host smart-04921d05-761b-45c8-a46a-f1530184d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138703846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4138703846
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1886091208
Short name T662
Test name
Test status
Simulation time 35463371 ps
CPU time 2.49 seconds
Started Feb 28 06:32:07 PM PST 24
Finished Feb 28 06:32:10 PM PST 24
Peak memory 207564 kb
Host smart-9ce0c162-3eba-4291-af4f-a43da940fe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886091208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1886091208
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.86976339
Short name T532
Test name
Test status
Simulation time 137712436 ps
CPU time 4 seconds
Started Feb 28 06:32:07 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 207868 kb
Host smart-42bf3fd1-2078-4611-9a8e-11144a9b4654
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86976339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.86976339
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3495111759
Short name T502
Test name
Test status
Simulation time 136090333 ps
CPU time 2.23 seconds
Started Feb 28 06:32:09 PM PST 24
Finished Feb 28 06:32:11 PM PST 24
Peak memory 206036 kb
Host smart-3e21e587-a71f-4bb5-931e-525dd93ad98e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495111759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3495111759
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1387760754
Short name T776
Test name
Test status
Simulation time 182866590 ps
CPU time 2.69 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 205988 kb
Host smart-1e535f1b-1a7f-4380-a950-a4afcbdb521d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387760754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1387760754
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1826446273
Short name T658
Test name
Test status
Simulation time 378996154 ps
CPU time 4.25 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:14 PM PST 24
Peak memory 213608 kb
Host smart-03556b3f-af50-43f7-8b13-85ecb1696576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826446273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1826446273
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.58077847
Short name T517
Test name
Test status
Simulation time 20295274 ps
CPU time 1.75 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 205860 kb
Host smart-b026122b-7326-4ac2-8b8c-8dffa7fc411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58077847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.58077847
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4145266413
Short name T470
Test name
Test status
Simulation time 19838308878 ps
CPU time 97.9 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:33:48 PM PST 24
Peak memory 208080 kb
Host smart-ef841087-4b78-4986-88c6-95091451534f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145266413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4145266413
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2852720174
Short name T844
Test name
Test status
Simulation time 407135397 ps
CPU time 5.21 seconds
Started Feb 28 06:32:11 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 206732 kb
Host smart-a68512d7-de83-48a6-ad83-57542831055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852720174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2852720174
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.641606522
Short name T837
Test name
Test status
Simulation time 78302831 ps
CPU time 2.72 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 209020 kb
Host smart-dc50b72a-4524-4d52-b0ec-53d19b5b6f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641606522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.641606522
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3696422216
Short name T623
Test name
Test status
Simulation time 17958269 ps
CPU time 0.86 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 205308 kb
Host smart-c144c9c7-61e7-47cc-a6b5-634543dc5951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696422216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3696422216
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.401376806
Short name T415
Test name
Test status
Simulation time 142155949 ps
CPU time 6.59 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 213912 kb
Host smart-2e7347e4-0308-418e-b4c9-846746c9786e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401376806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.401376806
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1529848818
Short name T263
Test name
Test status
Simulation time 93659423 ps
CPU time 2.1 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:18 PM PST 24
Peak memory 207156 kb
Host smart-439f08a0-2a0f-41c3-8f21-d9603ef5ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529848818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1529848818
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.614591028
Short name T103
Test name
Test status
Simulation time 111988357 ps
CPU time 4.95 seconds
Started Feb 28 06:32:14 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 213604 kb
Host smart-57287f13-2da0-47d1-bdc6-2eefb9378857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614591028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.614591028
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3366718534
Short name T60
Test name
Test status
Simulation time 62008918 ps
CPU time 4.09 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 210464 kb
Host smart-c3dfdb8b-c994-4ea1-b80f-e4233da365f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366718534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3366718534
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1679059077
Short name T729
Test name
Test status
Simulation time 51043756 ps
CPU time 2.69 seconds
Started Feb 28 06:32:13 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 218948 kb
Host smart-86fd6195-ebe4-445f-b06e-3f5785fbabee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679059077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1679059077
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1045634612
Short name T608
Test name
Test status
Simulation time 366112835 ps
CPU time 5.85 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:21 PM PST 24
Peak memory 206644 kb
Host smart-a809c6cb-f848-4e2c-b708-a955f6080569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045634612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1045634612
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2251018042
Short name T455
Test name
Test status
Simulation time 494313348 ps
CPU time 13.41 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:23 PM PST 24
Peak memory 207288 kb
Host smart-eba968f5-b1ec-4178-b3b6-27e8200c2707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251018042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2251018042
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.160341407
Short name T501
Test name
Test status
Simulation time 227482654 ps
CPU time 3.02 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 207724 kb
Host smart-4e6da710-4749-4cad-b15d-e96e830d0a6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160341407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.160341407
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1243234045
Short name T878
Test name
Test status
Simulation time 499380365 ps
CPU time 6.19 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 207952 kb
Host smart-72d8e341-60d1-4c2c-a43e-48e43c63482c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243234045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1243234045
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3534381533
Short name T650
Test name
Test status
Simulation time 828745232 ps
CPU time 5.23 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 208100 kb
Host smart-2258e9fe-de0c-4b33-9a31-e2ff46cb4c54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534381533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3534381533
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3325957781
Short name T116
Test name
Test status
Simulation time 256979747 ps
CPU time 4.49 seconds
Started Feb 28 06:32:12 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 208296 kb
Host smart-785ae1f7-1a18-4c04-9dd1-5f9d0dcd01f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325957781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3325957781
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4085485626
Short name T149
Test name
Test status
Simulation time 128432689 ps
CPU time 3.2 seconds
Started Feb 28 06:32:10 PM PST 24
Finished Feb 28 06:32:13 PM PST 24
Peak memory 207796 kb
Host smart-4c66b20e-8ebe-465f-bbcf-327a120c6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085485626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4085485626
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2906739537
Short name T358
Test name
Test status
Simulation time 604606791 ps
CPU time 6.65 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 215556 kb
Host smart-358b94f9-0f52-4c8d-8868-9ff0d602c03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906739537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2906739537
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.125827317
Short name T787
Test name
Test status
Simulation time 670324557 ps
CPU time 7.43 seconds
Started Feb 28 06:32:13 PM PST 24
Finished Feb 28 06:32:21 PM PST 24
Peak memory 217352 kb
Host smart-1a82cd88-f556-4e3d-9b15-34ea4170589c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125827317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.125827317
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1825098041
Short name T745
Test name
Test status
Simulation time 2790387128 ps
CPU time 7.73 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:23 PM PST 24
Peak memory 209484 kb
Host smart-82ada8e4-092e-4922-8dab-92c3cdca37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825098041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1825098041
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1756066305
Short name T693
Test name
Test status
Simulation time 95007634 ps
CPU time 1.85 seconds
Started Feb 28 06:32:13 PM PST 24
Finished Feb 28 06:32:15 PM PST 24
Peak memory 209472 kb
Host smart-a4bd181f-ffe3-43bc-8bf0-80da5da917d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756066305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1756066305
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.731418641
Short name T461
Test name
Test status
Simulation time 27830270 ps
CPU time 0.93 seconds
Started Feb 28 06:32:17 PM PST 24
Finished Feb 28 06:32:18 PM PST 24
Peak memory 205520 kb
Host smart-acb96638-a033-4819-bd4a-70a78fa4841a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731418641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.731418641
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2128643080
Short name T160
Test name
Test status
Simulation time 46631976 ps
CPU time 3.49 seconds
Started Feb 28 06:32:14 PM PST 24
Finished Feb 28 06:32:18 PM PST 24
Peak memory 213844 kb
Host smart-2ccd62ba-8506-41fb-b9a1-63116d1904c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128643080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2128643080
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.611979376
Short name T549
Test name
Test status
Simulation time 79409802 ps
CPU time 3.28 seconds
Started Feb 28 06:32:13 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 208288 kb
Host smart-6b1e9bef-3a94-4925-9498-8e3222dbbd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611979376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.611979376
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2512812254
Short name T597
Test name
Test status
Simulation time 530910494 ps
CPU time 4.35 seconds
Started Feb 28 06:32:17 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 209072 kb
Host smart-229baad2-4bfe-4acd-8983-e5746ee91c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512812254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2512812254
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2277936327
Short name T699
Test name
Test status
Simulation time 1026776442 ps
CPU time 26.68 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:41 PM PST 24
Peak memory 208668 kb
Host smart-ed82f5de-a780-4a83-b9d5-ef560cfb0a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277936327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2277936327
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1148178862
Short name T609
Test name
Test status
Simulation time 87522994 ps
CPU time 1.81 seconds
Started Feb 28 06:32:14 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 206320 kb
Host smart-4aff2a6d-1969-47ac-a588-2d3012dfaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148178862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1148178862
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2250338828
Short name T836
Test name
Test status
Simulation time 128644988 ps
CPU time 2.49 seconds
Started Feb 28 06:32:13 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 206080 kb
Host smart-4737eb1a-d282-468e-9876-b7e73868a007
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250338828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2250338828
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2551455968
Short name T405
Test name
Test status
Simulation time 422452837 ps
CPU time 11.22 seconds
Started Feb 28 06:32:12 PM PST 24
Finished Feb 28 06:32:23 PM PST 24
Peak memory 207736 kb
Host smart-1adf3dfd-8078-41a5-9c37-9d77f1af22b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551455968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2551455968
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1607146037
Short name T757
Test name
Test status
Simulation time 86468497 ps
CPU time 3.93 seconds
Started Feb 28 06:32:15 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 208200 kb
Host smart-52fb7b7d-297c-48b2-acb5-85fae5f0336f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607146037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1607146037
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2118468706
Short name T260
Test name
Test status
Simulation time 1248109860 ps
CPU time 12.28 seconds
Started Feb 28 06:32:17 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 207796 kb
Host smart-827c5814-c1e5-433e-a8d6-a49edd3e172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118468706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2118468706
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.937227265
Short name T465
Test name
Test status
Simulation time 51897471 ps
CPU time 2.77 seconds
Started Feb 28 06:32:14 PM PST 24
Finished Feb 28 06:32:16 PM PST 24
Peak memory 205916 kb
Host smart-0f475e07-53d8-4f0c-b265-fa3278f36e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937227265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.937227265
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1350412682
Short name T772
Test name
Test status
Simulation time 358973606 ps
CPU time 14.42 seconds
Started Feb 28 06:32:17 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 215868 kb
Host smart-761bb4ef-2b4b-4d05-bb9f-9d9ca035fda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350412682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1350412682
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2221420042
Short name T505
Test name
Test status
Simulation time 188300392 ps
CPU time 6.19 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:26 PM PST 24
Peak memory 208820 kb
Host smart-217e662d-884c-4b0d-a587-8628defc5d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221420042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2221420042
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4074957616
Short name T136
Test name
Test status
Simulation time 74408978 ps
CPU time 3.27 seconds
Started Feb 28 06:32:16 PM PST 24
Finished Feb 28 06:32:19 PM PST 24
Peak memory 209408 kb
Host smart-80c8ecbd-9366-4966-b225-fb298ed7da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074957616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4074957616
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3575512582
Short name T636
Test name
Test status
Simulation time 35118617 ps
CPU time 0.86 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:27 PM PST 24
Peak memory 205176 kb
Host smart-6b928506-e674-4ec6-9eab-606c55f5a4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575512582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3575512582
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1601245138
Short name T530
Test name
Test status
Simulation time 41459023 ps
CPU time 2.37 seconds
Started Feb 28 06:32:20 PM PST 24
Finished Feb 28 06:32:22 PM PST 24
Peak memory 208512 kb
Host smart-c879bfd4-6efd-4d3a-9c9f-a8dacfab91be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601245138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1601245138
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4169418834
Short name T17
Test name
Test status
Simulation time 62401504 ps
CPU time 3.27 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 213624 kb
Host smart-27f91b75-9e18-4b3f-b325-fc15f472df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169418834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4169418834
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3383226820
Short name T701
Test name
Test status
Simulation time 110437551 ps
CPU time 5.22 seconds
Started Feb 28 06:32:18 PM PST 24
Finished Feb 28 06:32:23 PM PST 24
Peak memory 209480 kb
Host smart-87434511-08f0-4794-b41b-6ff767f84cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383226820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3383226820
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4210923201
Short name T452
Test name
Test status
Simulation time 1379144214 ps
CPU time 45.02 seconds
Started Feb 28 06:32:18 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 207344 kb
Host smart-1162b04c-95c9-4c64-bc88-070c3477fbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210923201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4210923201
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1919329677
Short name T840
Test name
Test status
Simulation time 741471122 ps
CPU time 6.18 seconds
Started Feb 28 06:32:18 PM PST 24
Finished Feb 28 06:32:24 PM PST 24
Peak memory 207124 kb
Host smart-215317a6-dbee-4439-88b8-984b833795d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919329677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1919329677
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3668869397
Short name T140
Test name
Test status
Simulation time 363298563 ps
CPU time 6.32 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:25 PM PST 24
Peak memory 207108 kb
Host smart-9bb94f68-dc32-4747-a329-3ba501a33dc6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668869397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3668869397
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1930720471
Short name T563
Test name
Test status
Simulation time 218972679 ps
CPU time 6.53 seconds
Started Feb 28 06:32:17 PM PST 24
Finished Feb 28 06:32:24 PM PST 24
Peak memory 207916 kb
Host smart-902f4c3a-2b4b-49e8-8b12-106279de4587
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930720471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1930720471
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1264732048
Short name T403
Test name
Test status
Simulation time 22465663 ps
CPU time 1.88 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:28 PM PST 24
Peak memory 205864 kb
Host smart-26c3e1ad-09df-42d3-b804-5f1eb42fc5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264732048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1264732048
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3987398291
Short name T555
Test name
Test status
Simulation time 2112800201 ps
CPU time 22.26 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 207032 kb
Host smart-2b4f8cbe-a10f-4c86-bb35-db4ab1c46e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987398291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3987398291
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2996467804
Short name T706
Test name
Test status
Simulation time 1890659477 ps
CPU time 15.86 seconds
Started Feb 28 06:32:20 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 215492 kb
Host smart-64d66ecd-2206-4d24-9659-b3daf7f84dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996467804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2996467804
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2092088090
Short name T559
Test name
Test status
Simulation time 1487693232 ps
CPU time 15.74 seconds
Started Feb 28 06:32:21 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 219972 kb
Host smart-a1519042-67b9-412a-b029-75ce448337bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092088090 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2092088090
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1696106648
Short name T831
Test name
Test status
Simulation time 1913140354 ps
CPU time 48.32 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:33:14 PM PST 24
Peak memory 217816 kb
Host smart-b8bf5a47-7df6-41dd-83d5-8ea6809e7665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696106648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1696106648
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.564616673
Short name T396
Test name
Test status
Simulation time 437205586 ps
CPU time 11.04 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 210164 kb
Host smart-1f721a35-5fb5-4bac-a425-22e775f6fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564616673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.564616673
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3570771760
Short name T524
Test name
Test status
Simulation time 20835399 ps
CPU time 0.71 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 205340 kb
Host smart-3253b617-670e-4d5b-81ab-6f2ef25f0df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570771760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3570771760
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4250156061
Short name T47
Test name
Test status
Simulation time 130578420 ps
CPU time 2.93 seconds
Started Feb 28 06:32:22 PM PST 24
Finished Feb 28 06:32:25 PM PST 24
Peak memory 213648 kb
Host smart-eec942e9-4979-44b8-b548-f7a291535ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250156061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4250156061
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.992161771
Short name T788
Test name
Test status
Simulation time 151151320 ps
CPU time 2.71 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:28 PM PST 24
Peak memory 208460 kb
Host smart-225a1f0c-d3a0-4076-af14-539577bd78ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992161771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.992161771
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.677474388
Short name T224
Test name
Test status
Simulation time 36147610 ps
CPU time 2.7 seconds
Started Feb 28 06:32:22 PM PST 24
Finished Feb 28 06:32:25 PM PST 24
Peak memory 207860 kb
Host smart-e98c70cc-4e94-440f-8da4-194cfacef6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677474388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.677474388
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.663363915
Short name T234
Test name
Test status
Simulation time 189869219 ps
CPU time 6.2 seconds
Started Feb 28 06:32:21 PM PST 24
Finished Feb 28 06:32:27 PM PST 24
Peak memory 209104 kb
Host smart-1d62d3f4-0e97-4e87-b47b-53eb58256726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663363915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.663363915
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.427485895
Short name T614
Test name
Test status
Simulation time 9493039802 ps
CPU time 92.54 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:33:52 PM PST 24
Peak memory 208228 kb
Host smart-31f17ea2-f0e1-4152-bddf-59a2de73f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427485895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.427485895
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3982742779
Short name T274
Test name
Test status
Simulation time 169165868 ps
CPU time 4.55 seconds
Started Feb 28 06:32:24 PM PST 24
Finished Feb 28 06:32:28 PM PST 24
Peak memory 207584 kb
Host smart-aee0dba2-ac1b-4e2f-9d1a-389779f8eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982742779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3982742779
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2892710938
Short name T459
Test name
Test status
Simulation time 13958676964 ps
CPU time 26.91 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:46 PM PST 24
Peak memory 207976 kb
Host smart-425d7bcb-608f-4404-8e4e-549801867109
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892710938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2892710938
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1835031217
Short name T278
Test name
Test status
Simulation time 3232730362 ps
CPU time 31.79 seconds
Started Feb 28 06:32:21 PM PST 24
Finished Feb 28 06:32:53 PM PST 24
Peak memory 207568 kb
Host smart-63ebb88f-603b-4887-b9de-1bdd06e9e76f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835031217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1835031217
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3059285191
Short name T755
Test name
Test status
Simulation time 75016925 ps
CPU time 3.54 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 208360 kb
Host smart-8142cc4d-a1cc-4d8b-9480-191800157f7f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059285191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3059285191
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2844681843
Short name T439
Test name
Test status
Simulation time 51649554 ps
CPU time 2.63 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 207124 kb
Host smart-c07f5826-23a1-4b12-aa73-af2bcce5261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844681843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2844681843
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2347992683
Short name T682
Test name
Test status
Simulation time 239989307 ps
CPU time 12.28 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 222036 kb
Host smart-56f95cd5-3f55-49a8-a25a-b84a48d2b2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347992683 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2347992683
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1264007989
Short name T351
Test name
Test status
Simulation time 95569336 ps
CPU time 4.12 seconds
Started Feb 28 06:32:19 PM PST 24
Finished Feb 28 06:32:23 PM PST 24
Peak memory 208576 kb
Host smart-4d6b5dcf-fdf7-4c28-ae5a-3982dba244ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264007989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1264007989
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3796059440
Short name T56
Test name
Test status
Simulation time 194674176 ps
CPU time 1.97 seconds
Started Feb 28 06:32:22 PM PST 24
Finished Feb 28 06:32:24 PM PST 24
Peak memory 209444 kb
Host smart-92c55105-d04a-444f-97ac-54424fcb3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796059440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3796059440
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2306223824
Short name T680
Test name
Test status
Simulation time 23933627 ps
CPU time 0.86 seconds
Started Feb 28 06:32:24 PM PST 24
Finished Feb 28 06:32:25 PM PST 24
Peak memory 205288 kb
Host smart-1e9ea065-588a-4565-9193-5042ec30c40c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306223824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2306223824
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3386628593
Short name T887
Test name
Test status
Simulation time 210829832 ps
CPU time 5.41 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 218680 kb
Host smart-55679066-eebc-4259-8c5f-e1cb818d20b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386628593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3386628593
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2230517019
Short name T548
Test name
Test status
Simulation time 59801539 ps
CPU time 1.97 seconds
Started Feb 28 06:32:24 PM PST 24
Finished Feb 28 06:32:26 PM PST 24
Peak memory 213644 kb
Host smart-1ce07a14-b883-456d-8c58-70357466c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230517019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2230517019
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3669482148
Short name T561
Test name
Test status
Simulation time 280009754 ps
CPU time 3.6 seconds
Started Feb 28 06:32:23 PM PST 24
Finished Feb 28 06:32:27 PM PST 24
Peak memory 207632 kb
Host smart-3d82638c-e066-43b0-97ad-d7f7cda5b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669482148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3669482148
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1346202480
Short name T361
Test name
Test status
Simulation time 265969662 ps
CPU time 6.13 seconds
Started Feb 28 06:32:23 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 213708 kb
Host smart-f47455a1-4a40-4f22-8731-c07eb410a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346202480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1346202480
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.174796467
Short name T610
Test name
Test status
Simulation time 54292204 ps
CPU time 3.99 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 209944 kb
Host smart-112cad33-8c48-4b99-81cb-f7253cbbc5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174796467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.174796467
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3905631035
Short name T875
Test name
Test status
Simulation time 196614660 ps
CPU time 6.01 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:33 PM PST 24
Peak memory 208200 kb
Host smart-8317ae77-9cd5-4090-b76f-1e28b675d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905631035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3905631035
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1289029975
Short name T822
Test name
Test status
Simulation time 48865618 ps
CPU time 2.68 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 205784 kb
Host smart-91affc02-4929-4157-9a2a-0623d6d80cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289029975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1289029975
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3589556408
Short name T863
Test name
Test status
Simulation time 115195182 ps
CPU time 3.75 seconds
Started Feb 28 06:32:22 PM PST 24
Finished Feb 28 06:32:26 PM PST 24
Peak memory 206088 kb
Host smart-8a2c7d0e-91b3-46b8-84ba-30243bd30829
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589556408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3589556408
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2918995197
Short name T214
Test name
Test status
Simulation time 79300745 ps
CPU time 3.29 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 207192 kb
Host smart-f8b53882-9de1-43b6-8159-b1fe1a79f9c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918995197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2918995197
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2703795018
Short name T905
Test name
Test status
Simulation time 66884714 ps
CPU time 2.32 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 205976 kb
Host smart-a34ea585-91bd-467f-8011-5a7ad8759a0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703795018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2703795018
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2116455637
Short name T419
Test name
Test status
Simulation time 97698047 ps
CPU time 3.25 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:28 PM PST 24
Peak memory 208008 kb
Host smart-4ff8e6d7-7072-4a6c-8314-625d56784075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116455637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2116455637
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3343770302
Short name T862
Test name
Test status
Simulation time 138409259 ps
CPU time 3.78 seconds
Started Feb 28 06:32:24 PM PST 24
Finished Feb 28 06:32:28 PM PST 24
Peak memory 205908 kb
Host smart-f37f4f91-e7e0-4d51-be5e-707794a91d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343770302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3343770302
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2966533980
Short name T332
Test name
Test status
Simulation time 2575777118 ps
CPU time 18.6 seconds
Started Feb 28 06:32:23 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 208480 kb
Host smart-6b1b60ba-d500-4927-b223-d2facb52aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966533980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2966533980
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.931296202
Short name T726
Test name
Test status
Simulation time 414022449 ps
CPU time 6.96 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 210220 kb
Host smart-a15322f4-247d-430c-b0ef-cdaeea636c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931296202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.931296202
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2854666774
Short name T697
Test name
Test status
Simulation time 16475206 ps
CPU time 1 seconds
Started Feb 28 06:30:48 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 205440 kb
Host smart-7c8cd68c-8491-4207-b53a-d63c40310dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854666774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2854666774
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4137742574
Short name T85
Test name
Test status
Simulation time 52398192 ps
CPU time 2.43 seconds
Started Feb 28 06:30:43 PM PST 24
Finished Feb 28 06:30:46 PM PST 24
Peak memory 213644 kb
Host smart-fa5bcbb8-e1cf-4d3c-8661-6594e01670b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137742574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4137742574
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3061405248
Short name T23
Test name
Test status
Simulation time 103686596 ps
CPU time 4.63 seconds
Started Feb 28 06:30:44 PM PST 24
Finished Feb 28 06:30:49 PM PST 24
Peak memory 219348 kb
Host smart-dbd0572e-afe7-4854-ba8b-84f492f1d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061405248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3061405248
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2682140598
Short name T359
Test name
Test status
Simulation time 421224595 ps
CPU time 4.63 seconds
Started Feb 28 06:30:42 PM PST 24
Finished Feb 28 06:30:47 PM PST 24
Peak memory 209972 kb
Host smart-d6355158-1d10-4eb8-9958-2d286c7d39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682140598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2682140598
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.521084051
Short name T462
Test name
Test status
Simulation time 331711036 ps
CPU time 3.76 seconds
Started Feb 28 06:30:44 PM PST 24
Finished Feb 28 06:30:48 PM PST 24
Peak memory 208716 kb
Host smart-aaf23fcb-b5f5-465a-b598-854d422c5020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521084051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.521084051
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2224500971
Short name T552
Test name
Test status
Simulation time 57234499 ps
CPU time 3.47 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:30:45 PM PST 24
Peak memory 206056 kb
Host smart-2b7dc9f7-4e81-475f-be54-949d920b7fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224500971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2224500971
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.832819973
Short name T12
Test name
Test status
Simulation time 1108435075 ps
CPU time 18.75 seconds
Started Feb 28 06:30:46 PM PST 24
Finished Feb 28 06:31:05 PM PST 24
Peak memory 232068 kb
Host smart-37701535-e356-4c02-9a96-97c1649582e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832819973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.832819973
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3348442899
Short name T613
Test name
Test status
Simulation time 1774611859 ps
CPU time 22.87 seconds
Started Feb 28 06:30:40 PM PST 24
Finished Feb 28 06:31:03 PM PST 24
Peak memory 207936 kb
Host smart-82e27e8b-2f41-4b04-a41a-752def6c6b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348442899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3348442899
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1276030829
Short name T740
Test name
Test status
Simulation time 265854163 ps
CPU time 3.12 seconds
Started Feb 28 06:30:39 PM PST 24
Finished Feb 28 06:30:42 PM PST 24
Peak memory 207556 kb
Host smart-2778335a-0a81-44a7-80b7-d30442d96c1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276030829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1276030829
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2908868488
Short name T379
Test name
Test status
Simulation time 266274766 ps
CPU time 3.42 seconds
Started Feb 28 06:30:39 PM PST 24
Finished Feb 28 06:30:43 PM PST 24
Peak memory 208132 kb
Host smart-c79b089d-0460-4a90-b8dd-3bd7af0ed3dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908868488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2908868488
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.298215340
Short name T808
Test name
Test status
Simulation time 3488183402 ps
CPU time 35.88 seconds
Started Feb 28 06:30:41 PM PST 24
Finished Feb 28 06:31:17 PM PST 24
Peak memory 208040 kb
Host smart-ce7de2ce-a37b-4ac4-b3f2-1e2f64db7d6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298215340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.298215340
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3456783896
Short name T629
Test name
Test status
Simulation time 152438893 ps
CPU time 3.66 seconds
Started Feb 28 06:30:47 PM PST 24
Finished Feb 28 06:30:51 PM PST 24
Peak memory 213760 kb
Host smart-30b4538b-cbda-4c85-9fb9-51d895c2cf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456783896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3456783896
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3362493163
Short name T721
Test name
Test status
Simulation time 160843119 ps
CPU time 2.23 seconds
Started Feb 28 06:30:37 PM PST 24
Finished Feb 28 06:30:39 PM PST 24
Peak memory 205980 kb
Host smart-06db272c-4aac-4366-b27c-d9fb83b76342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362493163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3362493163
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.834850638
Short name T754
Test name
Test status
Simulation time 166341243 ps
CPU time 4.36 seconds
Started Feb 28 06:30:43 PM PST 24
Finished Feb 28 06:30:48 PM PST 24
Peak memory 206656 kb
Host smart-b74c4205-c5fe-48ae-a7dc-50239b229db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834850638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.834850638
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1190367083
Short name T14
Test name
Test status
Simulation time 4456416496 ps
CPU time 14.42 seconds
Started Feb 28 06:30:48 PM PST 24
Finished Feb 28 06:31:02 PM PST 24
Peak memory 210828 kb
Host smart-85d0cc73-f14d-454d-90d1-2dda1a8a8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190367083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1190367083
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1563566468
Short name T440
Test name
Test status
Simulation time 161321805 ps
CPU time 0.93 seconds
Started Feb 28 06:32:32 PM PST 24
Finished Feb 28 06:32:33 PM PST 24
Peak memory 205284 kb
Host smart-8d309e56-543a-44a0-b851-18972a149f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563566468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1563566468
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.217886415
Short name T270
Test name
Test status
Simulation time 62939442 ps
CPU time 4.6 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 214672 kb
Host smart-d9cf7c28-8e3e-4896-8085-d84b06ce7dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217886415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.217886415
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2903199266
Short name T871
Test name
Test status
Simulation time 816523837 ps
CPU time 19.84 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:47 PM PST 24
Peak memory 214036 kb
Host smart-ad84aa7f-59e0-4ea0-9027-97c650348665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903199266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2903199266
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1968974856
Short name T670
Test name
Test status
Simulation time 65190088 ps
CPU time 2.36 seconds
Started Feb 28 06:32:26 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 207472 kb
Host smart-8780307c-5aaa-4c10-865a-740b36c8c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968974856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1968974856
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1791802288
Short name T342
Test name
Test status
Simulation time 568988138 ps
CPU time 5.49 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:33 PM PST 24
Peak memory 219812 kb
Host smart-d20a116c-6a7c-4a60-919d-4d23ac4c7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791802288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1791802288
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.900180269
Short name T707
Test name
Test status
Simulation time 1124167545 ps
CPU time 7.51 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:35 PM PST 24
Peak memory 219492 kb
Host smart-fdc83bce-3185-4342-80a4-41ccf22c765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900180269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.900180269
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1575290214
Short name T567
Test name
Test status
Simulation time 1781302638 ps
CPU time 47.09 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:33:14 PM PST 24
Peak memory 213740 kb
Host smart-469ed400-60d3-435b-8e46-9e585c176bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575290214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1575290214
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3217901284
Short name T293
Test name
Test status
Simulation time 292305389 ps
CPU time 3.71 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 207712 kb
Host smart-846720c7-0aa5-4a21-b8a2-43983548f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217901284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3217901284
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2901772520
Short name T458
Test name
Test status
Simulation time 695828349 ps
CPU time 8 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 207144 kb
Host smart-eaeb4530-7d28-4998-b58e-c57277a9560b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901772520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2901772520
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.865935197
Short name T450
Test name
Test status
Simulation time 361490786 ps
CPU time 2.86 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 206060 kb
Host smart-1be17f31-dc16-4f5a-8ab2-b4f401577518
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865935197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.865935197
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1726636227
Short name T877
Test name
Test status
Simulation time 122751895 ps
CPU time 2.48 seconds
Started Feb 28 06:32:25 PM PST 24
Finished Feb 28 06:32:27 PM PST 24
Peak memory 205984 kb
Host smart-0defc437-c258-41cc-a66a-e920e3e562ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726636227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1726636227
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3698912946
Short name T747
Test name
Test status
Simulation time 342808053 ps
CPU time 3.61 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:30 PM PST 24
Peak memory 208748 kb
Host smart-be2a7ce5-649c-4d3f-af3e-713aadb85d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698912946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3698912946
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2916782799
Short name T898
Test name
Test status
Simulation time 700085111 ps
CPU time 7.83 seconds
Started Feb 28 06:32:23 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 207504 kb
Host smart-ab074488-59d8-4ee1-8685-4617c734a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916782799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2916782799
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2528739649
Short name T367
Test name
Test status
Simulation time 3462801505 ps
CPU time 50.09 seconds
Started Feb 28 06:32:34 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 215700 kb
Host smart-6cbadc92-57b7-4c4b-ab06-8fdd697c3e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528739649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2528739649
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.251945757
Short name T370
Test name
Test status
Simulation time 39638313 ps
CPU time 2.29 seconds
Started Feb 28 06:32:27 PM PST 24
Finished Feb 28 06:32:29 PM PST 24
Peak memory 206016 kb
Host smart-174544a5-934e-4258-8464-6ea068db753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251945757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.251945757
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2430763279
Short name T172
Test name
Test status
Simulation time 26281867 ps
CPU time 1.76 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:30 PM PST 24
Peak memory 208944 kb
Host smart-6c1bc054-e8da-4062-aa3c-b6c7741fa97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430763279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2430763279
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3845468793
Short name T442
Test name
Test status
Simulation time 43395652 ps
CPU time 0.88 seconds
Started Feb 28 06:32:31 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 205284 kb
Host smart-a43c08d3-b652-48d1-a4f9-fe0263920d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845468793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3845468793
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2985655649
Short name T309
Test name
Test status
Simulation time 363795046 ps
CPU time 3.03 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:32 PM PST 24
Peak memory 214464 kb
Host smart-c3f08763-e784-4481-b04a-959c8740c9dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985655649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2985655649
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.920078107
Short name T32
Test name
Test status
Simulation time 758588576 ps
CPU time 5.95 seconds
Started Feb 28 06:32:31 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 214056 kb
Host smart-e529365c-2310-477b-bf08-ff8737bc7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920078107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.920078107
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.784510531
Short name T589
Test name
Test status
Simulation time 13835059 ps
CPU time 1.23 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:31 PM PST 24
Peak memory 206208 kb
Host smart-67d440c0-d3fa-4668-a0e5-c183963b99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784510531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.784510531
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3712314200
Short name T61
Test name
Test status
Simulation time 480515996 ps
CPU time 5.28 seconds
Started Feb 28 06:32:35 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 213596 kb
Host smart-3d9fa1f7-ad8d-4ebc-9f7e-2887c6cb30f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712314200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3712314200
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.3956165013
Short name T382
Test name
Test status
Simulation time 17558926477 ps
CPU time 66.05 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:33:35 PM PST 24
Peak memory 217548 kb
Host smart-a5345ebc-c0dd-495e-9c83-b79a3c036f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956165013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3956165013
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3755259962
Short name T725
Test name
Test status
Simulation time 237534742 ps
CPU time 5.69 seconds
Started Feb 28 06:32:35 PM PST 24
Finished Feb 28 06:32:41 PM PST 24
Peak memory 207252 kb
Host smart-e1dab019-0fb1-4e79-abb4-d790b10e6746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755259962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3755259962
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.135427006
Short name T774
Test name
Test status
Simulation time 906775307 ps
CPU time 10.77 seconds
Started Feb 28 06:32:34 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 208080 kb
Host smart-bd8464a0-1a05-4d13-a8c0-7c3cd65ea302
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135427006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.135427006
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1151507386
Short name T873
Test name
Test status
Simulation time 573339248 ps
CPU time 3.69 seconds
Started Feb 28 06:32:31 PM PST 24
Finished Feb 28 06:32:35 PM PST 24
Peak memory 207980 kb
Host smart-fecb34ce-992f-47b5-9fa7-f6e4c33aa1f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151507386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1151507386
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1550398394
Short name T118
Test name
Test status
Simulation time 54366213 ps
CPU time 2.58 seconds
Started Feb 28 06:32:30 PM PST 24
Finished Feb 28 06:32:33 PM PST 24
Peak memory 205944 kb
Host smart-adc29c2e-c32c-4418-8600-27f0f79f0ff3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550398394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1550398394
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1482200238
Short name T674
Test name
Test status
Simulation time 94132356 ps
CPU time 3.24 seconds
Started Feb 28 06:32:29 PM PST 24
Finished Feb 28 06:32:33 PM PST 24
Peak memory 208252 kb
Host smart-63909612-4f8a-4a4c-808f-b9923f4a0684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482200238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1482200238
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.664661454
Short name T484
Test name
Test status
Simulation time 245948217 ps
CPU time 3.24 seconds
Started Feb 28 06:32:32 PM PST 24
Finished Feb 28 06:32:35 PM PST 24
Peak memory 205924 kb
Host smart-0895665f-e65a-4ff6-8665-e85885b109ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664661454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.664661454
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2802378308
Short name T294
Test name
Test status
Simulation time 1003321059 ps
CPU time 23.64 seconds
Started Feb 28 06:32:28 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 219108 kb
Host smart-6d6a8526-2194-4063-b336-707949ea1299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802378308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2802378308
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3320414837
Short name T649
Test name
Test status
Simulation time 511325806 ps
CPU time 8.27 seconds
Started Feb 28 06:32:31 PM PST 24
Finished Feb 28 06:32:39 PM PST 24
Peak memory 213668 kb
Host smart-b8054041-af75-4760-90c6-38b320730c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320414837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3320414837
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1257109459
Short name T456
Test name
Test status
Simulation time 16516058 ps
CPU time 0.77 seconds
Started Feb 28 06:32:38 PM PST 24
Finished Feb 28 06:32:39 PM PST 24
Peak memory 205224 kb
Host smart-9c81bccb-96bf-466d-bf8e-1fb5cc10747e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257109459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1257109459
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.612871417
Short name T29
Test name
Test status
Simulation time 73672349 ps
CPU time 2.45 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:39 PM PST 24
Peak memory 208736 kb
Host smart-04855e24-b315-474f-881c-4ec67a63eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612871417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.612871417
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.107467898
Short name T888
Test name
Test status
Simulation time 280224609 ps
CPU time 4.3 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 217516 kb
Host smart-aaded5ef-f18e-40b2-8add-0efea0af320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107467898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.107467898
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3845412603
Short name T100
Test name
Test status
Simulation time 57371046 ps
CPU time 3.66 seconds
Started Feb 28 06:32:33 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 208200 kb
Host smart-c045720f-cf91-4532-9995-c01eeb1e32f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845412603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3845412603
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2973778310
Short name T336
Test name
Test status
Simulation time 700607314 ps
CPU time 11.69 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:48 PM PST 24
Peak memory 221820 kb
Host smart-82947571-ef42-4067-9617-a0c823ccd332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973778310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2973778310
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2172715782
Short name T478
Test name
Test status
Simulation time 443643440 ps
CPU time 5.46 seconds
Started Feb 28 06:32:34 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 209152 kb
Host smart-c9dd3f46-e657-4dae-8976-44227be568bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172715782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2172715782
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.354177293
Short name T600
Test name
Test status
Simulation time 169777975 ps
CPU time 5.19 seconds
Started Feb 28 06:32:35 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 208992 kb
Host smart-39ee774b-6022-4b09-a343-bfed575300ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354177293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.354177293
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.560227760
Short name T259
Test name
Test status
Simulation time 1830205530 ps
CPU time 4.2 seconds
Started Feb 28 06:32:33 PM PST 24
Finished Feb 28 06:32:37 PM PST 24
Peak memory 205980 kb
Host smart-2b8e061d-52f6-4de6-93b3-634571d00bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560227760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.560227760
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3869092125
Short name T795
Test name
Test status
Simulation time 1260832448 ps
CPU time 7.52 seconds
Started Feb 28 06:32:37 PM PST 24
Finished Feb 28 06:32:44 PM PST 24
Peak memory 207920 kb
Host smart-6eed10cc-c456-48ed-b269-0c0b348cdf10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869092125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3869092125
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2599057770
Short name T476
Test name
Test status
Simulation time 308059372 ps
CPU time 6.58 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:43 PM PST 24
Peak memory 207148 kb
Host smart-80c5eeb0-73f2-4ee5-aedd-6aafcf3defca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599057770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2599057770
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1788935581
Short name T272
Test name
Test status
Simulation time 421890929 ps
CPU time 12.26 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:48 PM PST 24
Peak memory 207768 kb
Host smart-d6dba8b2-0059-4bd1-8f81-ade78af55bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788935581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1788935581
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2816921453
Short name T588
Test name
Test status
Simulation time 1494440155 ps
CPU time 27.67 seconds
Started Feb 28 06:32:40 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 213608 kb
Host smart-00a03a3e-62aa-4926-8326-ed68f98da6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816921453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2816921453
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3103768342
Short name T635
Test name
Test status
Simulation time 1389335774 ps
CPU time 16.64 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:53 PM PST 24
Peak memory 207116 kb
Host smart-a38c6ab0-5897-41d3-a1fd-2f06f0b067cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103768342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3103768342
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.385595875
Short name T319
Test name
Test status
Simulation time 2240504139 ps
CPU time 41.9 seconds
Started Feb 28 06:32:37 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 215968 kb
Host smart-9e442ba0-98a3-4dda-9499-039cc665690c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385595875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.385595875
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3489107663
Short name T223
Test name
Test status
Simulation time 6906355079 ps
CPU time 34.03 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:33:10 PM PST 24
Peak memory 208364 kb
Host smart-39afac09-0296-47b3-9b95-7ef5dc8b94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489107663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3489107663
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2246799556
Short name T856
Test name
Test status
Simulation time 119283705 ps
CPU time 2.69 seconds
Started Feb 28 06:32:40 PM PST 24
Finished Feb 28 06:32:43 PM PST 24
Peak memory 209480 kb
Host smart-f4224956-06b9-40df-9601-3557f470b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246799556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2246799556
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.563390652
Short name T107
Test name
Test status
Simulation time 11240308 ps
CPU time 0.75 seconds
Started Feb 28 06:32:39 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 205336 kb
Host smart-011c6e3d-012a-49f7-9ff7-c6121def5eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563390652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.563390652
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1722727580
Short name T428
Test name
Test status
Simulation time 43618351 ps
CPU time 3.39 seconds
Started Feb 28 06:32:42 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 213648 kb
Host smart-c653fa70-4bed-4a91-963f-73d812847abe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722727580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1722727580
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.821415449
Short name T324
Test name
Test status
Simulation time 170473795 ps
CPU time 2.95 seconds
Started Feb 28 06:32:38 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 209368 kb
Host smart-bdd0e6f2-6084-4a62-9b26-ad980706efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821415449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.821415449
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3851525360
Short name T228
Test name
Test status
Simulation time 135484562 ps
CPU time 3.82 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:48 PM PST 24
Peak memory 209596 kb
Host smart-fa941436-0550-4088-96ad-da3c3eae154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851525360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3851525360
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3128089450
Short name T698
Test name
Test status
Simulation time 55294762 ps
CPU time 2.18 seconds
Started Feb 28 06:32:38 PM PST 24
Finished Feb 28 06:32:41 PM PST 24
Peak memory 218716 kb
Host smart-ab4a3c3d-9e63-4b8d-8807-a5d7e5cf6b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128089450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3128089450
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2376318134
Short name T847
Test name
Test status
Simulation time 668671763 ps
CPU time 6.72 seconds
Started Feb 28 06:32:38 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 207544 kb
Host smart-3b14be75-4c23-4330-b5bf-97ee0cd4867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376318134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2376318134
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2529162613
Short name T659
Test name
Test status
Simulation time 39248633 ps
CPU time 1.82 seconds
Started Feb 28 06:32:36 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 206648 kb
Host smart-9664fa81-fa14-4fe9-8283-3acc3ccaf64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529162613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2529162613
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2639463336
Short name T115
Test name
Test status
Simulation time 112672504 ps
CPU time 4.35 seconds
Started Feb 28 06:32:37 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 206020 kb
Host smart-7f2bcf86-4f81-4f1f-bc38-9e1af21273a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639463336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2639463336
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3079975840
Short name T553
Test name
Test status
Simulation time 583617677 ps
CPU time 9.89 seconds
Started Feb 28 06:32:35 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 207260 kb
Host smart-0bb09abf-cf11-41fa-9ae6-a77f0f221a72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079975840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3079975840
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1842618369
Short name T681
Test name
Test status
Simulation time 61652596 ps
CPU time 3.12 seconds
Started Feb 28 06:32:35 PM PST 24
Finished Feb 28 06:32:38 PM PST 24
Peak memory 207968 kb
Host smart-4185d5b5-3b00-4fe2-aa7e-5964f7150b61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842618369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1842618369
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.428643300
Short name T583
Test name
Test status
Simulation time 157020521 ps
CPU time 2.46 seconds
Started Feb 28 06:32:40 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 214908 kb
Host smart-10cb7ece-3c59-449d-8f2b-c1fc3c2834fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428643300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.428643300
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1269503039
Short name T513
Test name
Test status
Simulation time 154584290 ps
CPU time 2.93 seconds
Started Feb 28 06:32:37 PM PST 24
Finished Feb 28 06:32:40 PM PST 24
Peak memory 205988 kb
Host smart-ebdd449b-3b56-4ff2-ab92-d275256ac644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269503039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1269503039
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2001035708
Short name T810
Test name
Test status
Simulation time 653766617 ps
CPU time 6.73 seconds
Started Feb 28 06:32:40 PM PST 24
Finished Feb 28 06:32:47 PM PST 24
Peak memory 207032 kb
Host smart-9c6661b7-c7cf-46bc-978c-d6b390806214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001035708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2001035708
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2687998966
Short name T556
Test name
Test status
Simulation time 133678730 ps
CPU time 2.95 seconds
Started Feb 28 06:32:39 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 208980 kb
Host smart-dcba87d8-1c0d-4eb1-8e9c-b45ef37437e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687998966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2687998966
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2682728239
Short name T802
Test name
Test status
Simulation time 34845428 ps
CPU time 0.84 seconds
Started Feb 28 06:32:41 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 205336 kb
Host smart-948775ae-415c-47b5-9250-0b4ecbe67273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682728239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2682728239
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1506290798
Short name T417
Test name
Test status
Simulation time 56077728 ps
CPU time 3.75 seconds
Started Feb 28 06:32:41 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 213616 kb
Host smart-65cae990-d344-4d94-9b0f-4359ee1dc9ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506290798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1506290798
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2220104926
Short name T616
Test name
Test status
Simulation time 772592201 ps
CPU time 5.22 seconds
Started Feb 28 06:32:43 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 208736 kb
Host smart-6f9f260d-2e30-46cb-a2d2-b4f695d06717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220104926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2220104926
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3915471990
Short name T850
Test name
Test status
Simulation time 137923584 ps
CPU time 3.42 seconds
Started Feb 28 06:32:41 PM PST 24
Finished Feb 28 06:32:45 PM PST 24
Peak memory 217804 kb
Host smart-38be5418-8597-490c-b437-697175190838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915471990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3915471990
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.858006350
Short name T723
Test name
Test status
Simulation time 215812716 ps
CPU time 5.09 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 220024 kb
Host smart-35ee45f3-f700-42a7-bf90-1fe867fb4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858006350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.858006350
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4054888138
Short name T828
Test name
Test status
Simulation time 167741926 ps
CPU time 4.35 seconds
Started Feb 28 06:32:42 PM PST 24
Finished Feb 28 06:32:47 PM PST 24
Peak memory 209928 kb
Host smart-9a22fb9d-c671-44e1-89c9-b20b86a042f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054888138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4054888138
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.302087592
Short name T249
Test name
Test status
Simulation time 44579610 ps
CPU time 2.82 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 209004 kb
Host smart-fcc9d82b-fff3-483b-8cd1-cc929c93cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302087592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.302087592
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4208898078
Short name T702
Test name
Test status
Simulation time 288457055 ps
CPU time 5.92 seconds
Started Feb 28 06:32:41 PM PST 24
Finished Feb 28 06:32:47 PM PST 24
Peak memory 207356 kb
Host smart-200c5899-7200-4271-91db-582b709b690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208898078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4208898078
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3844111071
Short name T708
Test name
Test status
Simulation time 77808392 ps
CPU time 1.98 seconds
Started Feb 28 06:32:39 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 206036 kb
Host smart-c8a16387-b8c6-4998-99ee-b1d2a5918f99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844111071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3844111071
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1736684855
Short name T606
Test name
Test status
Simulation time 68131574 ps
CPU time 3.33 seconds
Started Feb 28 06:32:38 PM PST 24
Finished Feb 28 06:32:42 PM PST 24
Peak memory 207832 kb
Host smart-931215a0-de55-4217-b95c-a033f8f1bc81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736684855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1736684855
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1874447289
Short name T716
Test name
Test status
Simulation time 2440196248 ps
CPU time 27.85 seconds
Started Feb 28 06:32:43 PM PST 24
Finished Feb 28 06:33:10 PM PST 24
Peak memory 207956 kb
Host smart-5c4fb00a-037b-4134-846c-98b8e7f88c1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874447289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1874447289
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3716877737
Short name T323
Test name
Test status
Simulation time 364930664 ps
CPU time 4.28 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 217484 kb
Host smart-7488a723-1738-4cf2-8606-33ca887af314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716877737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3716877737
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1021849184
Short name T640
Test name
Test status
Simulation time 200330761 ps
CPU time 5.52 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 207424 kb
Host smart-900c7a53-7ff6-4c08-9a1c-5fd30d2582df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021849184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1021849184
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1746974280
Short name T210
Test name
Test status
Simulation time 6910999198 ps
CPU time 71.18 seconds
Started Feb 28 06:32:43 PM PST 24
Finished Feb 28 06:33:54 PM PST 24
Peak memory 221988 kb
Host smart-ea2bd6c4-a26f-4975-9740-27428814673a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746974280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1746974280
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2738855313
Short name T135
Test name
Test status
Simulation time 545659260 ps
CPU time 7.4 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 218912 kb
Host smart-db0395ec-5f78-43be-870b-2d92d284a74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738855313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2738855313
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.383601403
Short name T401
Test name
Test status
Simulation time 87474025 ps
CPU time 4.51 seconds
Started Feb 28 06:32:45 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 217476 kb
Host smart-1d5f5881-4396-4232-ac50-f077943bfb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383601403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.383601403
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4102492362
Short name T712
Test name
Test status
Simulation time 114830414 ps
CPU time 2.02 seconds
Started Feb 28 06:32:42 PM PST 24
Finished Feb 28 06:32:44 PM PST 24
Peak memory 209240 kb
Host smart-b895fcae-35c9-4acd-823b-bf8b8cd34a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102492362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4102492362
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.443593887
Short name T535
Test name
Test status
Simulation time 57776479 ps
CPU time 0.89 seconds
Started Feb 28 06:32:50 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 205344 kb
Host smart-0330cd48-7eda-4649-9957-e80f51cfa3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443593887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.443593887
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1203346772
Short name T400
Test name
Test status
Simulation time 43133930 ps
CPU time 3.51 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:33:00 PM PST 24
Peak memory 213716 kb
Host smart-6fa7d379-77ce-4c18-bdc5-e826dbff4618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203346772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1203346772
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3571973275
Short name T816
Test name
Test status
Simulation time 145211891 ps
CPU time 2.33 seconds
Started Feb 28 06:32:50 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 206448 kb
Host smart-b7938fd5-f95e-4ede-8717-bedc0bd5ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571973275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3571973275
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2979060006
Short name T860
Test name
Test status
Simulation time 664880704 ps
CPU time 3.26 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 208252 kb
Host smart-a0e89a50-eb9e-4899-93dc-f9591bd61c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979060006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2979060006
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2197536086
Short name T499
Test name
Test status
Simulation time 308087715 ps
CPU time 3.2 seconds
Started Feb 28 06:32:45 PM PST 24
Finished Feb 28 06:32:48 PM PST 24
Peak memory 218792 kb
Host smart-700f8844-57dc-45a6-af5c-7448806021ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197536086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2197536086
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4232351753
Short name T298
Test name
Test status
Simulation time 249683678 ps
CPU time 5.33 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 208348 kb
Host smart-7e5cef12-7605-4ecd-bf1d-a7f26073538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232351753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4232351753
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2204671373
Short name T542
Test name
Test status
Simulation time 220175796 ps
CPU time 6.5 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 206868 kb
Host smart-1a185771-0c8d-4ddf-acae-a21f9514cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204671373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2204671373
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4260412531
Short name T494
Test name
Test status
Simulation time 638286365 ps
CPU time 8.11 seconds
Started Feb 28 06:32:45 PM PST 24
Finished Feb 28 06:32:53 PM PST 24
Peak memory 207184 kb
Host smart-99493140-861a-4a4f-ba78-e30ff36a125c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260412531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4260412531
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2193031257
Short name T632
Test name
Test status
Simulation time 31200210 ps
CPU time 2.17 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:46 PM PST 24
Peak memory 205976 kb
Host smart-c5994a06-bc66-4b0d-820d-c6280daa3fb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193031257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2193031257
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.754929027
Short name T117
Test name
Test status
Simulation time 207149051 ps
CPU time 6.4 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:32:55 PM PST 24
Peak memory 207596 kb
Host smart-9e206634-d04b-46da-a76e-831b827ebf8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754929027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.754929027
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3363748301
Short name T812
Test name
Test status
Simulation time 65068336 ps
CPU time 2.48 seconds
Started Feb 28 06:32:50 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 215048 kb
Host smart-56b6f975-34a1-47cc-8b23-44cd0cfcdfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363748301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3363748301
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2766607042
Short name T727
Test name
Test status
Simulation time 298592337 ps
CPU time 6.1 seconds
Started Feb 28 06:32:42 PM PST 24
Finished Feb 28 06:32:48 PM PST 24
Peak memory 206012 kb
Host smart-877ec432-d552-478e-ae95-d92b3c3e0320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766607042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2766607042
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2868590522
Short name T344
Test name
Test status
Simulation time 9003514867 ps
CPU time 68.79 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:33:58 PM PST 24
Peak memory 214360 kb
Host smart-0f90c634-008b-4eae-8bcb-015d79a120a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868590522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2868590522
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4242581554
Short name T565
Test name
Test status
Simulation time 628747890 ps
CPU time 3.18 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 208224 kb
Host smart-a5c69cb7-292a-4699-9506-57df53e4c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242581554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4242581554
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3813964707
Short name T68
Test name
Test status
Simulation time 235039581 ps
CPU time 5.3 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 209652 kb
Host smart-abe93dcf-c668-409a-b59b-b9bb7a27a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813964707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3813964707
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3226106254
Short name T853
Test name
Test status
Simulation time 211114031 ps
CPU time 0.77 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:32:56 PM PST 24
Peak memory 205208 kb
Host smart-49cfd2aa-8d9a-4979-93f3-1a7775e55ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226106254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3226106254
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2561564950
Short name T422
Test name
Test status
Simulation time 697327339 ps
CPU time 3.83 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 213528 kb
Host smart-8ccde051-92ec-4163-82d7-4bf17ded87bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561564950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2561564950
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.657576816
Short name T9
Test name
Test status
Simulation time 75161974 ps
CPU time 3.42 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 217136 kb
Host smart-8d5ed3f7-c482-4d61-a66c-0257695abcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657576816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.657576816
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2494095800
Short name T404
Test name
Test status
Simulation time 2263732868 ps
CPU time 43.74 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:33:31 PM PST 24
Peak memory 209092 kb
Host smart-b0a5c4e6-a931-4f21-97b9-8de9ddcb0227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494095800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2494095800
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1286852606
Short name T387
Test name
Test status
Simulation time 4094751766 ps
CPU time 32.17 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:31 PM PST 24
Peak memory 210832 kb
Host smart-912e7a4e-5a74-4fff-994c-4ff190f6decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286852606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1286852606
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4007774948
Short name T885
Test name
Test status
Simulation time 267288767 ps
CPU time 2.47 seconds
Started Feb 28 06:32:51 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 213648 kb
Host smart-42bffbf7-0b1f-4ca1-a93f-8c35208771cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007774948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4007774948
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3165337170
Short name T773
Test name
Test status
Simulation time 782349455 ps
CPU time 20.75 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:33:09 PM PST 24
Peak memory 208256 kb
Host smart-b91973ca-5104-4658-889e-a1b852e7ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165337170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3165337170
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.627919711
Short name T207
Test name
Test status
Simulation time 88238192 ps
CPU time 1.87 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 206020 kb
Host smart-a6e9e8f9-c4bf-4339-809d-597a39273344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627919711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.627919711
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.445577399
Short name T573
Test name
Test status
Simulation time 7680639334 ps
CPU time 58.38 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:33:45 PM PST 24
Peak memory 207632 kb
Host smart-ea0bd83b-3fa9-49ab-9872-e3f48f7c80f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445577399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.445577399
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1476344787
Short name T86
Test name
Test status
Simulation time 209766212 ps
CPU time 5.94 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 207156 kb
Host smart-0b814ea9-c79e-478b-852d-ed0265e28d8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476344787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1476344787
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1985896125
Short name T838
Test name
Test status
Simulation time 168143574 ps
CPU time 5.19 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 206196 kb
Host smart-ab233ab9-b48a-47fe-b77b-69cfbedde0bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985896125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1985896125
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2026715073
Short name T558
Test name
Test status
Simulation time 56722494 ps
CPU time 2.1 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 208940 kb
Host smart-d3f504b2-937a-4b4d-b09a-97bedbe0d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026715073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2026715073
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2509973661
Short name T436
Test name
Test status
Simulation time 602140233 ps
CPU time 4.58 seconds
Started Feb 28 06:32:46 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 206156 kb
Host smart-71d4572c-43cf-4d8e-afc7-f9dc4541a993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509973661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2509973661
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4171713246
Short name T735
Test name
Test status
Simulation time 546646966 ps
CPU time 19.88 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 215104 kb
Host smart-0f40e264-b4b4-4644-a008-60ad2f06fba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171713246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4171713246
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3721119975
Short name T889
Test name
Test status
Simulation time 161813318 ps
CPU time 6.82 seconds
Started Feb 28 06:32:44 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 208876 kb
Host smart-31a25869-8413-4fa5-883a-70d3bade88e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721119975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3721119975
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3732028521
Short name T209
Test name
Test status
Simulation time 62860908 ps
CPU time 2.63 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 209036 kb
Host smart-dbac78a4-23f8-4494-acb5-3422f0e3ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732028521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3732028521
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3147954288
Short name T731
Test name
Test status
Simulation time 48896339 ps
CPU time 0.83 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 205336 kb
Host smart-98d69ad9-78e7-4354-9ae7-3cc05a259f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147954288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3147954288
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.621741998
Short name T420
Test name
Test status
Simulation time 424342275 ps
CPU time 4.21 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 213684 kb
Host smart-9c59b77c-126f-4506-9b3a-ba26aaa7847d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621741998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.621741998
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3503900396
Short name T884
Test name
Test status
Simulation time 159527321 ps
CPU time 6.39 seconds
Started Feb 28 06:32:51 PM PST 24
Finished Feb 28 06:32:58 PM PST 24
Peak memory 207780 kb
Host smart-50295383-24c5-4344-bc94-ba733283a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503900396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3503900396
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3609073686
Short name T368
Test name
Test status
Simulation time 482411787 ps
CPU time 5.84 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 209212 kb
Host smart-3ce604c6-4f5a-4d0b-b0fa-d330720cb5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609073686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3609073686
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.848411988
Short name T162
Test name
Test status
Simulation time 42080386 ps
CPU time 2.49 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:49 PM PST 24
Peak memory 219556 kb
Host smart-d6209c0a-71af-416f-b7b3-5d0dbbc47954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848411988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.848411988
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1900280009
Short name T652
Test name
Test status
Simulation time 1409056049 ps
CPU time 11.76 seconds
Started Feb 28 06:32:50 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 207012 kb
Host smart-97fed919-ee55-4405-9347-300c055e9814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900280009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1900280009
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4177133876
Short name T809
Test name
Test status
Simulation time 182363284 ps
CPU time 3.18 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 206564 kb
Host smart-c54993ce-cdea-4320-87b6-96f0ef38be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177133876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4177133876
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1916493544
Short name T770
Test name
Test status
Simulation time 135401586 ps
CPU time 2.29 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 206056 kb
Host smart-a3ed1d3b-ab17-467b-9019-4026d2d42def
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916493544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1916493544
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.99468687
Short name T353
Test name
Test status
Simulation time 74370125 ps
CPU time 3.32 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:32:53 PM PST 24
Peak memory 207116 kb
Host smart-7fd9011e-797d-4936-a2d5-78cb039305e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99468687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.99468687
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1241039239
Short name T15
Test name
Test status
Simulation time 424807604 ps
CPU time 9.12 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:32:59 PM PST 24
Peak memory 205996 kb
Host smart-e6723aa5-826c-46dc-bee8-711370a2655f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241039239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1241039239
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3790124972
Short name T715
Test name
Test status
Simulation time 93012308 ps
CPU time 2.91 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:50 PM PST 24
Peak memory 208412 kb
Host smart-1653f607-a514-4b8d-bbde-feb2aae34bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790124972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3790124972
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3968154585
Short name T537
Test name
Test status
Simulation time 311779112 ps
CPU time 3.33 seconds
Started Feb 28 06:32:48 PM PST 24
Finished Feb 28 06:32:52 PM PST 24
Peak memory 207508 kb
Host smart-b143e6d0-fd4d-4d58-9da4-b8d88010b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968154585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3968154585
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.601874778
Short name T215
Test name
Test status
Simulation time 330906660 ps
CPU time 11.76 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 208580 kb
Host smart-8efa71ae-51b4-4124-a1cd-160699067424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601874778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.601874778
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1818971901
Short name T580
Test name
Test status
Simulation time 765842753 ps
CPU time 4.13 seconds
Started Feb 28 06:32:47 PM PST 24
Finished Feb 28 06:32:51 PM PST 24
Peak memory 209988 kb
Host smart-4ad916b5-19b1-4775-9c0c-8e59f86e1f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818971901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1818971901
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3641553719
Short name T16
Test name
Test status
Simulation time 58482961 ps
CPU time 0.82 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 205316 kb
Host smart-b0996134-5a64-4a6d-8cd0-b8ede6a0ae70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641553719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3641553719
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3518106632
Short name T846
Test name
Test status
Simulation time 6232162274 ps
CPU time 39.04 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:33:38 PM PST 24
Peak memory 207924 kb
Host smart-069c6c4c-f220-427e-bb25-995f6e0b67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518106632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3518106632
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.442348708
Short name T290
Test name
Test status
Simulation time 76074762 ps
CPU time 3.71 seconds
Started Feb 28 06:32:51 PM PST 24
Finished Feb 28 06:32:55 PM PST 24
Peak memory 221808 kb
Host smart-a25d4835-1fef-4be1-8379-14a0fe46d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442348708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.442348708
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2036023570
Short name T376
Test name
Test status
Simulation time 509480132 ps
CPU time 5.28 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:58 PM PST 24
Peak memory 211224 kb
Host smart-ce49ca85-c30f-460f-92ab-dc13ab516df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036023570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2036023570
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.881345088
Short name T894
Test name
Test status
Simulation time 84120663 ps
CPU time 3.06 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 219620 kb
Host smart-82b082a9-bf6e-4bd5-a141-491fce2f198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881345088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.881345088
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1684145360
Short name T138
Test name
Test status
Simulation time 158576183 ps
CPU time 7 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:33:00 PM PST 24
Peak memory 209188 kb
Host smart-edf2e909-4bbc-4f50-a9c3-bba53d0d9fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684145360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1684145360
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2637311019
Short name T373
Test name
Test status
Simulation time 569331210 ps
CPU time 17.42 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:33:12 PM PST 24
Peak memory 207676 kb
Host smart-148418cf-ebad-4ae9-adcf-5796251f938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637311019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2637311019
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2340927604
Short name T642
Test name
Test status
Simulation time 292509074 ps
CPU time 6.88 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:33:00 PM PST 24
Peak memory 206608 kb
Host smart-67804dc7-5a52-4373-af60-53e613e0ce6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340927604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2340927604
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1984934583
Short name T849
Test name
Test status
Simulation time 1667466225 ps
CPU time 11.09 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:33:00 PM PST 24
Peak memory 206884 kb
Host smart-11d317dc-dcac-4324-a69d-293fb8c540df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984934583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1984934583
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1590582018
Short name T497
Test name
Test status
Simulation time 355819945 ps
CPU time 3.66 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:32:56 PM PST 24
Peak memory 205884 kb
Host smart-5c79728e-8eab-449c-a4b6-274d84c2b53c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590582018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1590582018
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3726307032
Short name T384
Test name
Test status
Simulation time 410643229 ps
CPU time 2.61 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:32:55 PM PST 24
Peak memory 209356 kb
Host smart-fbc834fc-5f77-429f-888f-a2528dc7cde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726307032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3726307032
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2763568632
Short name T518
Test name
Test status
Simulation time 1494749242 ps
CPU time 4.94 seconds
Started Feb 28 06:32:49 PM PST 24
Finished Feb 28 06:32:55 PM PST 24
Peak memory 207616 kb
Host smart-87682bdb-1c26-40b3-b001-678d4d4f4a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763568632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2763568632
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1837800520
Short name T146
Test name
Test status
Simulation time 998949235 ps
CPU time 19.68 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:33:14 PM PST 24
Peak memory 222056 kb
Host smart-a64d93b8-e63c-4051-8711-aa1b1cb8e15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837800520 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1837800520
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1852108206
Short name T826
Test name
Test status
Simulation time 96895314 ps
CPU time 4.61 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 213600 kb
Host smart-9a323350-776c-4254-95dd-5ff6b594d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852108206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1852108206
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2369794582
Short name T686
Test name
Test status
Simulation time 254159733 ps
CPU time 2.46 seconds
Started Feb 28 06:32:51 PM PST 24
Finished Feb 28 06:32:54 PM PST 24
Peak memory 209392 kb
Host smart-c6258e40-3a06-40f3-b6d8-29a2fbd7fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369794582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2369794582
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3120885094
Short name T792
Test name
Test status
Simulation time 66877353 ps
CPU time 0.8 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:32:58 PM PST 24
Peak memory 205264 kb
Host smart-6ab38f09-91db-4cb1-863d-f8d0c3d53e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120885094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3120885094
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2338797767
Short name T413
Test name
Test status
Simulation time 484379349 ps
CPU time 7.45 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 214684 kb
Host smart-6780ce40-f337-4ed9-8e2f-4922dee50c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338797767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2338797767
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1970692063
Short name T34
Test name
Test status
Simulation time 395331980 ps
CPU time 6.99 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 208676 kb
Host smart-395721af-84bf-4185-8fdf-3e89c433939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970692063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1970692063
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.744942851
Short name T77
Test name
Test status
Simulation time 1434837843 ps
CPU time 6.18 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:32:59 PM PST 24
Peak memory 209096 kb
Host smart-aa119ddd-ffa7-4d7a-9411-83b223437bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744942851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.744942851
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2808885802
Short name T95
Test name
Test status
Simulation time 466632499 ps
CPU time 5.52 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:06 PM PST 24
Peak memory 208892 kb
Host smart-27025a45-a2c4-406e-a8ab-7641bfd90916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808885802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2808885802
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3626992015
Short name T645
Test name
Test status
Simulation time 203548222 ps
CPU time 3.01 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 206780 kb
Host smart-d29be4e8-7dfd-45cd-a8db-99cee41f810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626992015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3626992015
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1726378617
Short name T813
Test name
Test status
Simulation time 292795994 ps
CPU time 5.98 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:59 PM PST 24
Peak memory 206672 kb
Host smart-6a817e59-09ef-4aac-a08a-cc528fddda37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726378617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1726378617
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4158322232
Short name T615
Test name
Test status
Simulation time 279490201 ps
CPU time 2.96 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:32:59 PM PST 24
Peak memory 205788 kb
Host smart-c3297e73-d8e7-4a68-b775-286825e2ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158322232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4158322232
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.875563749
Short name T576
Test name
Test status
Simulation time 57259223 ps
CPU time 2.91 seconds
Started Feb 28 06:32:52 PM PST 24
Finished Feb 28 06:32:56 PM PST 24
Peak memory 207008 kb
Host smart-f8903f53-ff75-4f22-bbbf-6d24a7547878
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875563749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.875563749
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.4258584265
Short name T340
Test name
Test status
Simulation time 307598115 ps
CPU time 11.54 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:11 PM PST 24
Peak memory 207808 kb
Host smart-5b73a460-941d-417c-a4be-99643567d4c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258584265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.4258584265
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.338332132
Short name T231
Test name
Test status
Simulation time 194450465 ps
CPU time 2.92 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 205856 kb
Host smart-66fb0073-f8bb-45aa-8f2a-c653e1a9f969
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338332132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.338332132
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.957872964
Short name T785
Test name
Test status
Simulation time 248230682 ps
CPU time 3.26 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 217604 kb
Host smart-e46191dc-85f5-46bb-b1ac-20e7b9e95fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957872964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.957872964
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3687128923
Short name T449
Test name
Test status
Simulation time 148238658 ps
CPU time 3.53 seconds
Started Feb 28 06:32:50 PM PST 24
Finished Feb 28 06:32:55 PM PST 24
Peak memory 207392 kb
Host smart-befafacb-285b-49da-8e11-fe3744da8726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687128923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3687128923
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2631028603
Short name T352
Test name
Test status
Simulation time 704894752 ps
CPU time 27.02 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 215876 kb
Host smart-621651c3-8c4d-444a-ac66-e95ea43ccb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631028603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2631028603
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2078024569
Short name T673
Test name
Test status
Simulation time 196025381 ps
CPU time 5.27 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 207756 kb
Host smart-e20fb3f0-57b9-40db-bac7-ba2d558f0cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078024569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2078024569
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2469435499
Short name T815
Test name
Test status
Simulation time 2584720621 ps
CPU time 13.96 seconds
Started Feb 28 06:32:55 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 210344 kb
Host smart-3e0bf8dc-d022-4d5a-8917-b75da403e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469435499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2469435499
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2267334659
Short name T759
Test name
Test status
Simulation time 12113312 ps
CPU time 0.8 seconds
Started Feb 28 06:30:54 PM PST 24
Finished Feb 28 06:30:55 PM PST 24
Peak memory 205428 kb
Host smart-d2aa0fca-ca1a-4118-a131-73c2d0f784e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267334659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2267334659
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1164904016
Short name T369
Test name
Test status
Simulation time 288963425 ps
CPU time 4.09 seconds
Started Feb 28 06:30:49 PM PST 24
Finished Feb 28 06:30:53 PM PST 24
Peak memory 214792 kb
Host smart-222f8d1c-72f1-4dac-a8d4-acdc72ae06b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164904016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1164904016
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2046159858
Short name T8
Test name
Test status
Simulation time 122759516 ps
CPU time 2.75 seconds
Started Feb 28 06:30:50 PM PST 24
Finished Feb 28 06:30:53 PM PST 24
Peak memory 209368 kb
Host smart-01d96256-64f6-498b-aeed-264b266e4486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046159858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2046159858
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2616833372
Short name T768
Test name
Test status
Simulation time 2139893779 ps
CPU time 8.36 seconds
Started Feb 28 06:30:50 PM PST 24
Finished Feb 28 06:30:58 PM PST 24
Peak memory 217704 kb
Host smart-cd4156ee-8420-4555-b3e3-d87e2f6dc6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616833372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2616833372
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3642616714
Short name T574
Test name
Test status
Simulation time 163414106 ps
CPU time 5.67 seconds
Started Feb 28 06:30:54 PM PST 24
Finished Feb 28 06:31:00 PM PST 24
Peak memory 213660 kb
Host smart-2bdae678-6f3c-4d00-a87c-81afa6ba2644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642616714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3642616714
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1754028799
Short name T286
Test name
Test status
Simulation time 612816921 ps
CPU time 8.85 seconds
Started Feb 28 06:30:52 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 209712 kb
Host smart-2ecbc8e5-4089-4dcf-a991-45601bce980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754028799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1754028799
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.2721426457
Short name T520
Test name
Test status
Simulation time 148806264 ps
CPU time 4.1 seconds
Started Feb 28 06:30:49 PM PST 24
Finished Feb 28 06:30:53 PM PST 24
Peak memory 206032 kb
Host smart-2b608fd5-4dfd-492b-aa0a-0f275decfbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721426457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2721426457
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3899476901
Short name T113
Test name
Test status
Simulation time 313205143 ps
CPU time 10.59 seconds
Started Feb 28 06:30:52 PM PST 24
Finished Feb 28 06:31:03 PM PST 24
Peak memory 230648 kb
Host smart-de0ad645-3fdf-43e2-a873-54ad724e3f5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899476901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3899476901
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4283751068
Short name T752
Test name
Test status
Simulation time 72290399 ps
CPU time 2.61 seconds
Started Feb 28 06:30:47 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 207932 kb
Host smart-5b4d0ee8-f23c-4d48-ab79-ec30b767018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283751068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4283751068
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2712177687
Short name T843
Test name
Test status
Simulation time 401571108 ps
CPU time 3.12 seconds
Started Feb 28 06:30:48 PM PST 24
Finished Feb 28 06:30:51 PM PST 24
Peak memory 208020 kb
Host smart-678628c6-d498-40d1-a505-3250319e87a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712177687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2712177687
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2748002055
Short name T486
Test name
Test status
Simulation time 67058243 ps
CPU time 2.22 seconds
Started Feb 28 06:30:48 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 208048 kb
Host smart-f1a63a40-2188-46a5-9556-28c0e367e4cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748002055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2748002055
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1732593405
Short name T648
Test name
Test status
Simulation time 66254449 ps
CPU time 3.48 seconds
Started Feb 28 06:30:46 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 207712 kb
Host smart-d7fff075-70c4-450f-8368-bc1f2cc8e843
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732593405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1732593405
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.8250406
Short name T317
Test name
Test status
Simulation time 161184115 ps
CPU time 3.16 seconds
Started Feb 28 06:30:54 PM PST 24
Finished Feb 28 06:30:57 PM PST 24
Peak memory 209196 kb
Host smart-4f5990a5-96c8-4438-8436-3922083c9da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8250406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.8250406
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1218110620
Short name T492
Test name
Test status
Simulation time 81989493 ps
CPU time 3.62 seconds
Started Feb 28 06:30:46 PM PST 24
Finished Feb 28 06:30:50 PM PST 24
Peak memory 207588 kb
Host smart-f7572c1f-7423-474b-a6f9-a36349c163b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218110620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1218110620
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3909423007
Short name T133
Test name
Test status
Simulation time 1097893455 ps
CPU time 34.88 seconds
Started Feb 28 06:30:55 PM PST 24
Finished Feb 28 06:31:30 PM PST 24
Peak memory 221932 kb
Host smart-5aee673e-c7cd-44d7-b275-daeb0a065235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909423007 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3909423007
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3921271807
Short name T886
Test name
Test status
Simulation time 1193711404 ps
CPU time 10.02 seconds
Started Feb 28 06:30:50 PM PST 24
Finished Feb 28 06:31:00 PM PST 24
Peak memory 207984 kb
Host smart-c26b0ef9-3075-401e-8ba9-db4eebfa95d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921271807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3921271807
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2122804988
Short name T669
Test name
Test status
Simulation time 62634094 ps
CPU time 3.24 seconds
Started Feb 28 06:30:53 PM PST 24
Finished Feb 28 06:30:57 PM PST 24
Peak memory 209304 kb
Host smart-24c18ca4-fc74-49a4-82fd-2d3c5a6adf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122804988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2122804988
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3635972933
Short name T475
Test name
Test status
Simulation time 42563581 ps
CPU time 0.72 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:00 PM PST 24
Peak memory 205296 kb
Host smart-f8868e57-fd3e-4ac2-8639-690101d9c28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635972933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3635972933
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1084811364
Short name T713
Test name
Test status
Simulation time 49647657 ps
CPU time 2.16 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 209012 kb
Host smart-e4487e2b-5867-4bbf-92ce-c6f93285440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084811364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1084811364
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.770005234
Short name T305
Test name
Test status
Simulation time 83700694 ps
CPU time 2.12 seconds
Started Feb 28 06:32:58 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 207708 kb
Host smart-89b2505d-b59f-4c8c-8fb8-0d1e4ea89113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770005234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.770005234
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_random.2585061673
Short name T630
Test name
Test status
Simulation time 180709009 ps
CPU time 3.48 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:32:58 PM PST 24
Peak memory 207936 kb
Host smart-c72ac2af-834f-403b-be8a-6fc55de22a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585061673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2585061673
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3383681476
Short name T308
Test name
Test status
Simulation time 74138619 ps
CPU time 3.51 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:58 PM PST 24
Peak memory 207820 kb
Host smart-b7f2d95a-2e21-4baf-a06a-024777a22c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383681476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3383681476
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1117346939
Short name T744
Test name
Test status
Simulation time 116112010 ps
CPU time 2.86 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 206940 kb
Host smart-84ddffa7-c8da-4e79-be9c-b7bea02de11b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117346939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1117346939
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.569827863
Short name T864
Test name
Test status
Simulation time 120080211 ps
CPU time 4.47 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:59 PM PST 24
Peak memory 207260 kb
Host smart-9978d54e-d1c3-4deb-9616-8342685f9b46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569827863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.569827863
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3227549828
Short name T3
Test name
Test status
Simulation time 146632848 ps
CPU time 2.46 seconds
Started Feb 28 06:32:53 PM PST 24
Finished Feb 28 06:32:57 PM PST 24
Peak memory 206000 kb
Host smart-b9bb0be2-a7f2-4969-8b2e-145c46145b99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227549828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3227549828
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1224867651
Short name T562
Test name
Test status
Simulation time 402965862 ps
CPU time 3.3 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 208136 kb
Host smart-8d4d45b3-43ef-406e-9653-c034f49a3224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224867651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1224867651
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.262343991
Short name T599
Test name
Test status
Simulation time 43281238 ps
CPU time 2.19 seconds
Started Feb 28 06:32:54 PM PST 24
Finished Feb 28 06:32:57 PM PST 24
Peak memory 206028 kb
Host smart-0a32a0fa-2191-4a9e-9826-8dbf62ba916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262343991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.262343991
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1366772592
Short name T78
Test name
Test status
Simulation time 1268660750 ps
CPU time 47.24 seconds
Started Feb 28 06:32:56 PM PST 24
Finished Feb 28 06:33:46 PM PST 24
Peak memory 214980 kb
Host smart-81e71643-ea1f-404a-af8a-714cd28dbab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366772592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1366772592
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2130701011
Short name T803
Test name
Test status
Simulation time 484953917 ps
CPU time 7.47 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 206640 kb
Host smart-cc87b3e0-d7a2-4bd1-bf57-c8de757263e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130701011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2130701011
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.250387803
Short name T145
Test name
Test status
Simulation time 100085162 ps
CPU time 2.54 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 208960 kb
Host smart-80792c25-8bbf-443d-9f1a-e5e5b3b07b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250387803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.250387803
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2392203086
Short name T677
Test name
Test status
Simulation time 13713873 ps
CPU time 0.98 seconds
Started Feb 28 06:33:01 PM PST 24
Finished Feb 28 06:33:02 PM PST 24
Peak memory 205548 kb
Host smart-0cd3a25f-affe-4afb-87da-2d9af02e83f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392203086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2392203086
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2800507686
Short name T277
Test name
Test status
Simulation time 154229369 ps
CPU time 3.01 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 214500 kb
Host smart-84aa3b13-bbd9-4630-bb4d-a316ccd65a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800507686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2800507686
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1659622094
Short name T41
Test name
Test status
Simulation time 216716852 ps
CPU time 7.44 seconds
Started Feb 28 06:33:02 PM PST 24
Finished Feb 28 06:33:09 PM PST 24
Peak memory 207868 kb
Host smart-a18901c5-0512-4afa-972f-032652bf7fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659622094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1659622094
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2334379094
Short name T591
Test name
Test status
Simulation time 42462578 ps
CPU time 2.52 seconds
Started Feb 28 06:33:03 PM PST 24
Finished Feb 28 06:33:05 PM PST 24
Peak memory 207328 kb
Host smart-e7bb0c07-ccbb-4bb6-a058-25efc73eec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334379094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2334379094
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1636962066
Short name T25
Test name
Test status
Simulation time 39245346 ps
CPU time 3.32 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 207524 kb
Host smart-849ac2ab-b8e8-46f5-abef-e2bb6d14afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636962066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1636962066
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4246720417
Short name T264
Test name
Test status
Simulation time 333041444 ps
CPU time 5.92 seconds
Started Feb 28 06:33:02 PM PST 24
Finished Feb 28 06:33:09 PM PST 24
Peak memory 213556 kb
Host smart-345d6454-b444-4fd9-a0dc-53b788b24335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246720417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4246720417
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.780547416
Short name T781
Test name
Test status
Simulation time 660043755 ps
CPU time 3.09 seconds
Started Feb 28 06:33:02 PM PST 24
Finished Feb 28 06:33:05 PM PST 24
Peak memory 208960 kb
Host smart-926946d0-48a8-46a5-b039-07d1791a4c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780547416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.780547416
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2641548563
Short name T371
Test name
Test status
Simulation time 68267946 ps
CPU time 3.55 seconds
Started Feb 28 06:33:03 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 213756 kb
Host smart-c4f667c0-7d52-46f2-abb9-86f9f669d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641548563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2641548563
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.825366934
Short name T130
Test name
Test status
Simulation time 980827862 ps
CPU time 23.52 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:23 PM PST 24
Peak memory 207712 kb
Host smart-62b58058-864a-40f4-b8d7-be78512ecafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825366934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.825366934
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.236855866
Short name T407
Test name
Test status
Simulation time 653065739 ps
CPU time 5.06 seconds
Started Feb 28 06:32:58 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 205804 kb
Host smart-e15ab4fb-bcea-4b27-984c-98a0e86980a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236855866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.236855866
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.170736753
Short name T766
Test name
Test status
Simulation time 241418358 ps
CPU time 2.43 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:01 PM PST 24
Peak memory 206456 kb
Host smart-2d9e0948-a506-4faa-950a-a64a266ff205
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170736753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.170736753
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2721307863
Short name T737
Test name
Test status
Simulation time 162653723 ps
CPU time 3.49 seconds
Started Feb 28 06:33:01 PM PST 24
Finished Feb 28 06:33:05 PM PST 24
Peak memory 207744 kb
Host smart-80d148be-fcf3-4320-80ec-01e4d57b5df1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721307863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2721307863
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2557113962
Short name T230
Test name
Test status
Simulation time 97169411 ps
CPU time 2.86 seconds
Started Feb 28 06:33:02 PM PST 24
Finished Feb 28 06:33:05 PM PST 24
Peak memory 213608 kb
Host smart-f77563b0-567f-472b-a625-2726c88bcef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557113962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2557113962
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2464025182
Short name T842
Test name
Test status
Simulation time 4912953164 ps
CPU time 48.24 seconds
Started Feb 28 06:32:57 PM PST 24
Finished Feb 28 06:33:47 PM PST 24
Peak memory 207328 kb
Host smart-10080a7b-656d-4ad7-807b-afa14c92c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464025182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2464025182
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.953040774
Short name T845
Test name
Test status
Simulation time 223891759 ps
CPU time 5.01 seconds
Started Feb 28 06:33:03 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 207860 kb
Host smart-9b1e6c71-f2de-413e-97d6-dd9039b56a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953040774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.953040774
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.798652957
Short name T451
Test name
Test status
Simulation time 22700616 ps
CPU time 1.01 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 205468 kb
Host smart-00e23365-9acb-4738-b4d7-f460260a0b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798652957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.798652957
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.105465484
Short name T427
Test name
Test status
Simulation time 72041853 ps
CPU time 2.96 seconds
Started Feb 28 06:33:05 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 213760 kb
Host smart-22d1fe63-5a26-437f-8486-4ea85e6ac65b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105465484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.105465484
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1681160881
Short name T742
Test name
Test status
Simulation time 503374095 ps
CPU time 2.83 seconds
Started Feb 28 06:33:05 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 216212 kb
Host smart-e419effd-a978-436e-ad1c-a4065daac5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681160881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1681160881
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2263610849
Short name T717
Test name
Test status
Simulation time 455694179 ps
CPU time 2.66 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 217796 kb
Host smart-fe0d532f-cf21-4f3b-938f-a1059db7f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263610849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2263610849
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.742038720
Short name T605
Test name
Test status
Simulation time 418754688 ps
CPU time 4.21 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:33:11 PM PST 24
Peak memory 208432 kb
Host smart-58f26af2-8ecb-4589-bbd0-33298daa30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742038720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.742038720
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3218907359
Short name T375
Test name
Test status
Simulation time 2118789676 ps
CPU time 75.24 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:34:22 PM PST 24
Peak memory 226112 kb
Host smart-2ccf15f0-8004-4219-999f-51686b3cadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218907359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3218907359
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.954384280
Short name T238
Test name
Test status
Simulation time 209583384 ps
CPU time 2.91 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 218908 kb
Host smart-2ebf2eb4-88bd-49cd-b15c-d889cc46f098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954384280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.954384280
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2490555621
Short name T500
Test name
Test status
Simulation time 199173933 ps
CPU time 4.32 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 207364 kb
Host smart-647a181e-bc74-4f78-9479-e868bb5d86e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490555621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2490555621
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3756991288
Short name T719
Test name
Test status
Simulation time 492430824 ps
CPU time 2.82 seconds
Started Feb 28 06:33:01 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 205368 kb
Host smart-c968852f-bf39-4439-b62a-21dd211c9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756991288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3756991288
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1200627134
Short name T869
Test name
Test status
Simulation time 2993200806 ps
CPU time 14.79 seconds
Started Feb 28 06:33:01 PM PST 24
Finished Feb 28 06:33:16 PM PST 24
Peak memory 207932 kb
Host smart-0b0d04a5-7674-4e08-99d3-96d2cde6de1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200627134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1200627134
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1564438852
Short name T510
Test name
Test status
Simulation time 215460665 ps
CPU time 3.6 seconds
Started Feb 28 06:32:59 PM PST 24
Finished Feb 28 06:33:03 PM PST 24
Peak memory 207764 kb
Host smart-c4327dbb-2ddd-4c91-b448-db3f0ba38721
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564438852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1564438852
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2027103797
Short name T839
Test name
Test status
Simulation time 163299432 ps
CPU time 4.86 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:05 PM PST 24
Peak memory 206036 kb
Host smart-a69243f4-0274-4b39-b2e4-edc8279aa0b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027103797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2027103797
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.205131217
Short name T769
Test name
Test status
Simulation time 296798635 ps
CPU time 10.91 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 217736 kb
Host smart-1c5adbd3-fc8d-4cd8-80eb-ea2f4132c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205131217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.205131217
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2681777662
Short name T570
Test name
Test status
Simulation time 98978299 ps
CPU time 3 seconds
Started Feb 28 06:33:00 PM PST 24
Finished Feb 28 06:33:04 PM PST 24
Peak memory 205928 kb
Host smart-55e78954-976f-4ec8-95cd-4dcc490da2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681777662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2681777662
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4117457576
Short name T876
Test name
Test status
Simulation time 22646048548 ps
CPU time 170.2 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:35:55 PM PST 24
Peak memory 218612 kb
Host smart-a30c8bf2-e478-4b62-a368-b4b95bd6b112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117457576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4117457576
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4288312622
Short name T50
Test name
Test status
Simulation time 186021647 ps
CPU time 11.43 seconds
Started Feb 28 06:33:08 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 221596 kb
Host smart-45fa209d-8efe-49ee-bed0-b266fa7791b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288312622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4288312622
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1000021019
Short name T331
Test name
Test status
Simulation time 246360854 ps
CPU time 7.68 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:16 PM PST 24
Peak memory 208436 kb
Host smart-cd700530-1bfe-4fc3-9625-e3c2300b5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000021019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1000021019
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2017719478
Short name T62
Test name
Test status
Simulation time 143905065 ps
CPU time 2.99 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:07 PM PST 24
Peak memory 209328 kb
Host smart-b556f0e6-ea6b-47f0-b390-c30117b9bee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017719478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2017719478
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4034270358
Short name T438
Test name
Test status
Simulation time 10216485 ps
CPU time 0.86 seconds
Started Feb 28 06:33:10 PM PST 24
Finished Feb 28 06:33:11 PM PST 24
Peak memory 205264 kb
Host smart-6cdbcf0c-5c6f-4616-8db9-df65ff9e5478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034270358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4034270358
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3762224063
Short name T421
Test name
Test status
Simulation time 185946911 ps
CPU time 9.95 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:33:16 PM PST 24
Peak memory 213848 kb
Host smart-db2a4b81-a38d-4bd7-81a1-a796bdcb868a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762224063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3762224063
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1598541138
Short name T777
Test name
Test status
Simulation time 139282068 ps
CPU time 3.98 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 214088 kb
Host smart-fdd7a205-efed-462d-b189-b41a5de32cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598541138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1598541138
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.578949727
Short name T74
Test name
Test status
Simulation time 1005774390 ps
CPU time 3.08 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:12 PM PST 24
Peak memory 213648 kb
Host smart-dcb9d1d8-53a3-41a6-af46-ead5645064b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578949727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.578949727
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2267170698
Short name T101
Test name
Test status
Simulation time 140914336 ps
CPU time 6.01 seconds
Started Feb 28 06:33:03 PM PST 24
Finished Feb 28 06:33:09 PM PST 24
Peak memory 220108 kb
Host smart-2af974e6-8149-43a8-8a8f-76cfa976284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267170698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2267170698
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3586899729
Short name T318
Test name
Test status
Simulation time 626859592 ps
CPU time 6.33 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 221844 kb
Host smart-cd579bc8-a3e7-410f-b701-355ee4520b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586899729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3586899729
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3462076874
Short name T252
Test name
Test status
Simulation time 904997126 ps
CPU time 4.12 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:09 PM PST 24
Peak memory 209280 kb
Host smart-c91a6f9f-7df1-4de7-b641-f170eaa63393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462076874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3462076874
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4265367017
Short name T84
Test name
Test status
Simulation time 416645713 ps
CPU time 10.28 seconds
Started Feb 28 06:33:05 PM PST 24
Finished Feb 28 06:33:16 PM PST 24
Peak memory 213596 kb
Host smart-d0a05dc7-7ee0-49e7-a71d-11f2c42fc961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265367017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4265367017
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.160107262
Short name T893
Test name
Test status
Simulation time 75451308 ps
CPU time 1.75 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:06 PM PST 24
Peak memory 205500 kb
Host smart-2d860b8c-1ebd-42a9-a410-b9e85e6fd565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160107262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.160107262
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.444615768
Short name T557
Test name
Test status
Simulation time 353951134 ps
CPU time 4.57 seconds
Started Feb 28 06:33:05 PM PST 24
Finished Feb 28 06:33:10 PM PST 24
Peak memory 206008 kb
Host smart-a8cb17a4-0e4a-4c54-98ea-205c6d780c86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444615768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.444615768
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4078620396
Short name T825
Test name
Test status
Simulation time 346522367 ps
CPU time 5.56 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:10 PM PST 24
Peak memory 205812 kb
Host smart-8eff95e0-ab86-4b66-b97d-3b83c29ba1a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078620396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4078620396
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3064556837
Short name T346
Test name
Test status
Simulation time 1714152120 ps
CPU time 59.73 seconds
Started Feb 28 06:33:06 PM PST 24
Finished Feb 28 06:34:06 PM PST 24
Peak memory 208064 kb
Host smart-e8f57501-9a73-44c5-90d3-dac6080a4a17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064556837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3064556837
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1250425554
Short name T643
Test name
Test status
Simulation time 112723059 ps
CPU time 2.67 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:11 PM PST 24
Peak memory 208904 kb
Host smart-bc94ad41-3211-416c-ac07-1fed31bd49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250425554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1250425554
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1650434513
Short name T114
Test name
Test status
Simulation time 1252632831 ps
CPU time 20.9 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 207068 kb
Host smart-b5b13d89-d548-4ced-a6a5-0f0dc1c80548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650434513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1650434513
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2086560882
Short name T814
Test name
Test status
Simulation time 168868548 ps
CPU time 4.32 seconds
Started Feb 28 06:33:04 PM PST 24
Finished Feb 28 06:33:08 PM PST 24
Peak memory 208688 kb
Host smart-81611b57-1002-40dd-955e-aac6ac3910b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086560882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2086560882
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.951339920
Short name T397
Test name
Test status
Simulation time 204512895 ps
CPU time 1.65 seconds
Started Feb 28 06:33:08 PM PST 24
Finished Feb 28 06:33:10 PM PST 24
Peak memory 208964 kb
Host smart-d7a16c9f-f577-48ca-9b14-99252faa8013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951339920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.951339920
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4072424508
Short name T464
Test name
Test status
Simulation time 28626106 ps
CPU time 0.82 seconds
Started Feb 28 06:33:13 PM PST 24
Finished Feb 28 06:33:15 PM PST 24
Peak memory 205324 kb
Host smart-4ca8aca9-a011-4ef0-93a6-e5746f265b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072424508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4072424508
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1469427168
Short name T327
Test name
Test status
Simulation time 115081263 ps
CPU time 6.39 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:15 PM PST 24
Peak memory 214776 kb
Host smart-b65de729-c135-4db0-80a0-a475ae6f7e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469427168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1469427168
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3892010237
Short name T246
Test name
Test status
Simulation time 260748996 ps
CPU time 10.63 seconds
Started Feb 28 06:33:11 PM PST 24
Finished Feb 28 06:33:22 PM PST 24
Peak memory 208284 kb
Host smart-85fc6353-1590-4fe8-b685-f42e11105732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892010237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3892010237
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1609244321
Short name T617
Test name
Test status
Simulation time 64232851 ps
CPU time 1.45 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:17 PM PST 24
Peak memory 208208 kb
Host smart-aa6d0e48-0c8f-48f5-b5a3-200798e435b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609244321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1609244321
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.641654027
Short name T806
Test name
Test status
Simulation time 77904687 ps
CPU time 3.21 seconds
Started Feb 28 06:33:10 PM PST 24
Finished Feb 28 06:33:14 PM PST 24
Peak memory 215500 kb
Host smart-42863e6e-e7cc-4e37-8df3-16e7e18c7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641654027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.641654027
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1719489636
Short name T266
Test name
Test status
Simulation time 67864650 ps
CPU time 3.03 seconds
Started Feb 28 06:33:09 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 208476 kb
Host smart-8d863d96-03b8-4577-bde0-38e860db3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719489636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1719489636
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3164392303
Short name T45
Test name
Test status
Simulation time 169334387 ps
CPU time 3.07 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 208344 kb
Host smart-957c8411-7c67-4658-96ae-0450f89feffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164392303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3164392303
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1400220960
Short name T226
Test name
Test status
Simulation time 458834429 ps
CPU time 4.04 seconds
Started Feb 28 06:33:08 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 207192 kb
Host smart-3c6fcb11-25aa-4db1-b902-b6105105fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400220960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1400220960
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1690217160
Short name T782
Test name
Test status
Simulation time 7222802226 ps
CPU time 47.42 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:56 PM PST 24
Peak memory 207232 kb
Host smart-638759f4-69d4-4447-9ddb-7d627d4847cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690217160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1690217160
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2628645711
Short name T607
Test name
Test status
Simulation time 332008526 ps
CPU time 4.6 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:13 PM PST 24
Peak memory 206928 kb
Host smart-77749278-098b-49da-aa6c-04c3b19f859e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628645711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2628645711
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1810042985
Short name T724
Test name
Test status
Simulation time 1515864100 ps
CPU time 50.17 seconds
Started Feb 28 06:33:10 PM PST 24
Finished Feb 28 06:34:01 PM PST 24
Peak memory 208020 kb
Host smart-ce60ecaf-005a-4733-87de-a12b642150a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810042985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1810042985
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2456746965
Short name T689
Test name
Test status
Simulation time 143592597 ps
CPU time 5.27 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:14 PM PST 24
Peak memory 207812 kb
Host smart-8738534f-49cd-4f60-9442-d79c9c45885a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456746965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2456746965
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.862327639
Short name T625
Test name
Test status
Simulation time 2241470673 ps
CPU time 10.18 seconds
Started Feb 28 06:33:09 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 207956 kb
Host smart-f4f495c6-53cf-4a9e-820f-4f21fe90bcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862327639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.862327639
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3327454354
Short name T811
Test name
Test status
Simulation time 50855783 ps
CPU time 2.57 seconds
Started Feb 28 06:33:07 PM PST 24
Finished Feb 28 06:33:11 PM PST 24
Peak memory 207564 kb
Host smart-8702abde-16f9-43d6-9863-594f0714cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327454354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3327454354
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.618407091
Short name T762
Test name
Test status
Simulation time 2687001581 ps
CPU time 17.82 seconds
Started Feb 28 06:33:12 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 215576 kb
Host smart-34fa437b-2e73-4fa0-8a97-dcc64242f141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618407091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.618407091
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3003863342
Short name T349
Test name
Test status
Simulation time 135681140 ps
CPU time 3.96 seconds
Started Feb 28 06:33:12 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 208876 kb
Host smart-a085dcf9-d611-441e-870b-4b46f79d4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003863342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3003863342
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1446422304
Short name T718
Test name
Test status
Simulation time 403985943 ps
CPU time 2.48 seconds
Started Feb 28 06:33:13 PM PST 24
Finished Feb 28 06:33:17 PM PST 24
Peak memory 209220 kb
Host smart-145e5346-7cc4-4088-961b-96e80253a858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446422304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1446422304
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.603200102
Short name T477
Test name
Test status
Simulation time 46648587 ps
CPU time 0.82 seconds
Started Feb 28 06:33:12 PM PST 24
Finished Feb 28 06:33:15 PM PST 24
Peak memory 205212 kb
Host smart-102ec094-caec-44a2-a587-91085f2aacb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603200102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.603200102
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3758124783
Short name T362
Test name
Test status
Simulation time 493944225 ps
CPU time 6.92 seconds
Started Feb 28 06:33:12 PM PST 24
Finished Feb 28 06:33:21 PM PST 24
Peak memory 221880 kb
Host smart-62ea7c8b-0d01-405e-bb81-5890e912ea42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758124783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3758124783
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.149048998
Short name T683
Test name
Test status
Simulation time 158684036 ps
CPU time 3.19 seconds
Started Feb 28 06:33:16 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 209620 kb
Host smart-5daed573-79b0-4cb4-aa56-87143e427d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149048998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.149048998
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3454674658
Short name T426
Test name
Test status
Simulation time 194437690 ps
CPU time 2.01 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:17 PM PST 24
Peak memory 213720 kb
Host smart-1c21910a-7aa5-4c26-937e-67f117c84e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454674658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3454674658
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2826276989
Short name T800
Test name
Test status
Simulation time 4283880741 ps
CPU time 37.16 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:53 PM PST 24
Peak memory 213744 kb
Host smart-6a5c1293-8b46-4cd7-873d-7d00e9f45493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826276989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2826276989
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1422558701
Short name T304
Test name
Test status
Simulation time 1302977911 ps
CPU time 9.62 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 210520 kb
Host smart-4498faaa-2206-4d6d-afd2-ff1c001c78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422558701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1422558701
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3758836123
Short name T798
Test name
Test status
Simulation time 515217241 ps
CPU time 4.1 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 219500 kb
Host smart-10c3f574-952b-42ad-bcf2-b9e986599210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758836123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3758836123
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.179200232
Short name T832
Test name
Test status
Simulation time 440451396 ps
CPU time 12.39 seconds
Started Feb 28 06:33:11 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 208452 kb
Host smart-7ce2daf2-f061-4e29-8cdf-d4e4b312f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179200232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.179200232
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1916851903
Short name T389
Test name
Test status
Simulation time 757515265 ps
CPU time 5.87 seconds
Started Feb 28 06:33:11 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 207868 kb
Host smart-0d764919-6c58-4316-b932-b95ac2922251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916851903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1916851903
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1900641431
Short name T334
Test name
Test status
Simulation time 23606793 ps
CPU time 1.85 seconds
Started Feb 28 06:33:12 PM PST 24
Finished Feb 28 06:33:16 PM PST 24
Peak memory 206008 kb
Host smart-f347601c-c42a-4a1e-9100-c1f780d938ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900641431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1900641431
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1582992511
Short name T571
Test name
Test status
Simulation time 1081746331 ps
CPU time 28.9 seconds
Started Feb 28 06:33:09 PM PST 24
Finished Feb 28 06:33:39 PM PST 24
Peak memory 208076 kb
Host smart-057b0b4b-4386-444b-be5d-5df9f8bd3cb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582992511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1582992511
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1280074891
Short name T691
Test name
Test status
Simulation time 406701315 ps
CPU time 3.06 seconds
Started Feb 28 06:33:11 PM PST 24
Finished Feb 28 06:33:15 PM PST 24
Peak memory 207992 kb
Host smart-b3f3a50f-4ecf-410c-9f40-3536944594ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280074891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1280074891
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1373363293
Short name T472
Test name
Test status
Simulation time 192700803 ps
CPU time 2.71 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 208944 kb
Host smart-3790821f-1630-4226-bb9e-871311256a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373363293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1373363293
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1079110103
Short name T216
Test name
Test status
Simulation time 112380171 ps
CPU time 2.41 seconds
Started Feb 28 06:33:09 PM PST 24
Finished Feb 28 06:33:12 PM PST 24
Peak memory 205940 kb
Host smart-5ab35acb-b8cf-447b-b90a-7cb95126a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079110103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1079110103
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2696573535
Short name T43
Test name
Test status
Simulation time 782813598 ps
CPU time 21.63 seconds
Started Feb 28 06:33:16 PM PST 24
Finished Feb 28 06:33:39 PM PST 24
Peak memory 213708 kb
Host smart-afcc43ee-c9f5-4c82-b7eb-de5f924bb75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696573535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2696573535
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1818113214
Short name T355
Test name
Test status
Simulation time 39095302424 ps
CPU time 78.56 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:34:35 PM PST 24
Peak memory 221872 kb
Host smart-bbf102c9-e2e8-4ea2-9141-a77dceccd5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818113214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1818113214
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1981664965
Short name T67
Test name
Test status
Simulation time 64474706 ps
CPU time 3.05 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:17 PM PST 24
Peak memory 209268 kb
Host smart-61be063f-0ccc-4203-bcb1-2510b226217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981664965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1981664965
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2617472171
Short name T212
Test name
Test status
Simulation time 23167051 ps
CPU time 1.13 seconds
Started Feb 28 06:33:16 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 205568 kb
Host smart-c6f7ab93-0448-4084-bfdf-14a2c45f95d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617472171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2617472171
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2652095409
Short name T835
Test name
Test status
Simulation time 66623133 ps
CPU time 3.03 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 220768 kb
Host smart-90f02709-ac66-4991-9fc8-0cdca6da6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652095409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2652095409
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1689841686
Short name T206
Test name
Test status
Simulation time 46459385 ps
CPU time 1.89 seconds
Started Feb 28 06:33:18 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 205976 kb
Host smart-1591c735-be34-4063-ba53-1586c3da0835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689841686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1689841686
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3636626429
Short name T679
Test name
Test status
Simulation time 606193926 ps
CPU time 7.69 seconds
Started Feb 28 06:33:17 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 213744 kb
Host smart-a92f964f-7f48-4d6e-b284-f98455090d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636626429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3636626429
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.46828484
Short name T388
Test name
Test status
Simulation time 491749321 ps
CPU time 16.97 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:38 PM PST 24
Peak memory 213596 kb
Host smart-2ad46af6-4776-4322-99f8-4dbd5eaae2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46828484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.46828484
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2846272875
Short name T52
Test name
Test status
Simulation time 67213554 ps
CPU time 3.49 seconds
Started Feb 28 06:33:15 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 221828 kb
Host smart-65d92885-14c2-4201-86b3-a80bf587f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846272875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2846272875
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4176587348
Short name T300
Test name
Test status
Simulation time 97069455 ps
CPU time 4.74 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 207832 kb
Host smart-7e906024-55a3-41c0-99af-1eeff3d73e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176587348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4176587348
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2065860262
Short name T620
Test name
Test status
Simulation time 4038900296 ps
CPU time 42.88 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:57 PM PST 24
Peak memory 207680 kb
Host smart-e8849f6f-8a6f-47c6-8d30-d243ce949b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065860262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2065860262
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1751204684
Short name T527
Test name
Test status
Simulation time 199551500 ps
CPU time 3.39 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:18 PM PST 24
Peak memory 206168 kb
Host smart-e060c92b-03b3-4a29-8a98-bf60d845deb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751204684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1751204684
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.796705917
Short name T463
Test name
Test status
Simulation time 171870000 ps
CPU time 6.47 seconds
Started Feb 28 06:33:18 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 207564 kb
Host smart-d9a45476-f980-4cf1-b73c-666a8f46090b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796705917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.796705917
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2322576387
Short name T529
Test name
Test status
Simulation time 1573572102 ps
CPU time 7.89 seconds
Started Feb 28 06:33:13 PM PST 24
Finished Feb 28 06:33:22 PM PST 24
Peak memory 207728 kb
Host smart-4107d764-68b9-4d7a-800f-e127191e9d89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322576387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2322576387
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2364306713
Short name T229
Test name
Test status
Simulation time 1385903580 ps
CPU time 19.97 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:41 PM PST 24
Peak memory 207504 kb
Host smart-9c246a1d-1133-49a4-a5b4-31836918f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364306713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2364306713
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2200016041
Short name T841
Test name
Test status
Simulation time 327392323 ps
CPU time 4.73 seconds
Started Feb 28 06:33:14 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 205920 kb
Host smart-baaa4f22-6db6-4c4e-84c0-f4864422650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200016041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2200016041
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2704442284
Short name T80
Test name
Test status
Simulation time 20393041572 ps
CPU time 55.3 seconds
Started Feb 28 06:33:18 PM PST 24
Finished Feb 28 06:34:13 PM PST 24
Peak memory 222024 kb
Host smart-4f5c9169-b886-4294-aa04-c2fbea43dd1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704442284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2704442284
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3122402015
Short name T865
Test name
Test status
Simulation time 1064960393 ps
CPU time 34.56 seconds
Started Feb 28 06:33:13 PM PST 24
Finished Feb 28 06:33:49 PM PST 24
Peak memory 207944 kb
Host smart-d2e31202-9428-44da-aac9-4c456fe7942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122402015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3122402015
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1023940409
Short name T720
Test name
Test status
Simulation time 33796678 ps
CPU time 2.13 seconds
Started Feb 28 06:33:17 PM PST 24
Finished Feb 28 06:33:19 PM PST 24
Peak memory 209136 kb
Host smart-82425c49-6826-4342-9b7a-857cccedbfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023940409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1023940409
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1664485959
Short name T490
Test name
Test status
Simulation time 66774162 ps
CPU time 0.87 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:22 PM PST 24
Peak memory 205332 kb
Host smart-8dd00615-a63d-41eb-b75b-3ea43129632f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664485959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1664485959
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2932522739
Short name T30
Test name
Test status
Simulation time 833126763 ps
CPU time 5.45 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:27 PM PST 24
Peak memory 214008 kb
Host smart-f39ff026-8273-49da-b1c1-72ec664c9497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932522739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2932522739
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3594165584
Short name T262
Test name
Test status
Simulation time 53827652 ps
CPU time 1.51 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 207148 kb
Host smart-5c0b409e-1b4f-4d3b-939c-5fd636b2f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594165584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3594165584
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.521595315
Short name T380
Test name
Test status
Simulation time 139119725 ps
CPU time 3.94 seconds
Started Feb 28 06:33:24 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 207544 kb
Host smart-60256a21-0078-4c30-a0d4-bb4a8a7dea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521595315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.521595315
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1789789132
Short name T339
Test name
Test status
Simulation time 288171342 ps
CPU time 9.35 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 213628 kb
Host smart-d6d98501-ac43-4653-aa23-d143ffb6735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789789132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1789789132
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3397745503
Short name T44
Test name
Test status
Simulation time 144647424 ps
CPU time 5 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 221836 kb
Host smart-9ee49038-eac4-4740-b73b-f7939dca0f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397745503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3397745503
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2409901787
Short name T90
Test name
Test status
Simulation time 291792073 ps
CPU time 8.92 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 207804 kb
Host smart-920c2fea-51f7-4ba9-bced-8c6eb15d0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409901787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2409901787
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1644096683
Short name T313
Test name
Test status
Simulation time 655746694 ps
CPU time 9.43 seconds
Started Feb 28 06:33:19 PM PST 24
Finished Feb 28 06:33:31 PM PST 24
Peak memory 208068 kb
Host smart-947e95ec-6cb7-44d0-bb82-06ce2c2e8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644096683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1644096683
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2895530498
Short name T276
Test name
Test status
Simulation time 563991406 ps
CPU time 2.71 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 205892 kb
Host smart-f5fae1a7-016d-4f53-9865-fc2b50f36b09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895530498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2895530498
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2194993128
Short name T784
Test name
Test status
Simulation time 153892980 ps
CPU time 3.61 seconds
Started Feb 28 06:33:17 PM PST 24
Finished Feb 28 06:33:21 PM PST 24
Peak memory 205940 kb
Host smart-ce837f9f-925a-41e3-b9c7-fed952cf6047
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194993128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2194993128
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1609705055
Short name T685
Test name
Test status
Simulation time 58680639 ps
CPU time 3.37 seconds
Started Feb 28 06:33:18 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 207956 kb
Host smart-adfd8c0a-e53f-40a6-a786-93ee40f87c0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609705055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1609705055
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2797298027
Short name T447
Test name
Test status
Simulation time 58849004 ps
CPU time 2.92 seconds
Started Feb 28 06:33:19 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 217572 kb
Host smart-9834e7f5-55bd-4145-8c59-c2c6f629b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797298027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2797298027
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2416079336
Short name T435
Test name
Test status
Simulation time 63131930 ps
CPU time 3.26 seconds
Started Feb 28 06:33:17 PM PST 24
Finished Feb 28 06:33:20 PM PST 24
Peak memory 207424 kb
Host smart-7dd29cf1-dc1d-4df8-aa88-22d53ddd6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416079336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2416079336
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.432244047
Short name T675
Test name
Test status
Simulation time 179473248 ps
CPU time 2.62 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 206096 kb
Host smart-62af7fad-6bf7-4bf3-b117-c27848891c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432244047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.432244047
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2487129152
Short name T466
Test name
Test status
Simulation time 413279429 ps
CPU time 7.37 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 206284 kb
Host smart-cb2a5a2d-8d83-4068-9362-eb72b826004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487129152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2487129152
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2007929669
Short name T690
Test name
Test status
Simulation time 289908470 ps
CPU time 3.8 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:28 PM PST 24
Peak memory 209208 kb
Host smart-d7181899-7eda-4f33-b10e-058657ae7f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007929669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2007929669
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.639176346
Short name T514
Test name
Test status
Simulation time 28724598 ps
CPU time 0.78 seconds
Started Feb 28 06:33:30 PM PST 24
Finished Feb 28 06:33:31 PM PST 24
Peak memory 205324 kb
Host smart-eaa9c370-ce90-41fc-842e-832e669ebcd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639176346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.639176346
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3570955419
Short name T753
Test name
Test status
Simulation time 106227450 ps
CPU time 2.25 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 214284 kb
Host smart-f5148c3f-4685-47ff-ace6-f2f4d064d543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570955419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3570955419
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3838713263
Short name T851
Test name
Test status
Simulation time 575916815 ps
CPU time 4.77 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 208464 kb
Host smart-d32fa7b0-64c6-4ac8-83e2-ff360a34bbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838713263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3838713263
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2348081947
Short name T566
Test name
Test status
Simulation time 90749742 ps
CPU time 4.29 seconds
Started Feb 28 06:33:24 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 213660 kb
Host smart-e77be1b5-4831-46bc-b475-deb4e0a238a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348081947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2348081947
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3867380420
Short name T315
Test name
Test status
Simulation time 1710893865 ps
CPU time 53.08 seconds
Started Feb 28 06:33:24 PM PST 24
Finished Feb 28 06:34:18 PM PST 24
Peak memory 224380 kb
Host smart-02e5cde7-1e5d-4a82-9caf-8ddf374d0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867380420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3867380420
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1630396613
Short name T7
Test name
Test status
Simulation time 3049748560 ps
CPU time 76.84 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:34:39 PM PST 24
Peak memory 213680 kb
Host smart-136c1a7f-73e9-4f91-a743-87dbfd217376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630396613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1630396613
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3485470506
Short name T218
Test name
Test status
Simulation time 135271821 ps
CPU time 6.2 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:28 PM PST 24
Peak memory 208852 kb
Host smart-1f6eaa96-8444-4c46-bafd-0259a2961045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485470506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3485470506
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3300354883
Short name T730
Test name
Test status
Simulation time 117288853 ps
CPU time 4.83 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:27 PM PST 24
Peak memory 207668 kb
Host smart-1313e0ab-9ec2-4443-804b-53ef41fc5932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300354883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3300354883
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1101153096
Short name T641
Test name
Test status
Simulation time 194588307 ps
CPU time 2.78 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:24 PM PST 24
Peak memory 206012 kb
Host smart-89f6aa48-74ba-4410-acf3-a4e06d5b6185
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101153096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1101153096
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3031124485
Short name T619
Test name
Test status
Simulation time 781429339 ps
CPU time 4.56 seconds
Started Feb 28 06:33:21 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 206004 kb
Host smart-38de66ce-e264-4298-bc42-67a58ab2132e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031124485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3031124485
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2845606396
Short name T540
Test name
Test status
Simulation time 842109773 ps
CPU time 7.53 seconds
Started Feb 28 06:33:20 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 207748 kb
Host smart-646382c3-3c2b-419d-a0bc-df9878d413cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845606396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2845606396
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1543827377
Short name T287
Test name
Test status
Simulation time 50342649 ps
CPU time 1.87 seconds
Started Feb 28 06:33:30 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 209016 kb
Host smart-671c1703-0971-4940-8381-2b1b28daf692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543827377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1543827377
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3095417572
Short name T225
Test name
Test status
Simulation time 483352153 ps
CPU time 15.34 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:40 PM PST 24
Peak memory 207852 kb
Host smart-3293943a-26f2-4a87-8276-b33a7ac62f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095417572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3095417572
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1009639100
Short name T268
Test name
Test status
Simulation time 81455051 ps
CPU time 4.47 seconds
Started Feb 28 06:33:31 PM PST 24
Finished Feb 28 06:33:36 PM PST 24
Peak memory 206476 kb
Host smart-ced72c1f-2527-47fd-8ae8-d3aa567591e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009639100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1009639100
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3459008233
Short name T627
Test name
Test status
Simulation time 906059931 ps
CPU time 20.74 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:44 PM PST 24
Peak memory 221896 kb
Host smart-a8966161-c7fc-47fa-a92b-77d98099655e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459008233 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3459008233
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1946972947
Short name T280
Test name
Test status
Simulation time 369835991 ps
CPU time 5.67 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:28 PM PST 24
Peak memory 207472 kb
Host smart-53fe9e47-3844-4f80-b768-6e1f2013c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946972947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1946972947
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2614544188
Short name T188
Test name
Test status
Simulation time 74627291 ps
CPU time 2.06 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:27 PM PST 24
Peak memory 209008 kb
Host smart-36939050-9f47-4816-a206-6d4024d47c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614544188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2614544188
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2279575417
Short name T868
Test name
Test status
Simulation time 52876849 ps
CPU time 0.9 seconds
Started Feb 28 06:33:31 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 205260 kb
Host smart-9217b3a0-396e-4124-bb6e-0a52bbfa5a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279575417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2279575417
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.39688337
Short name T72
Test name
Test status
Simulation time 63793230 ps
CPU time 2.86 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 217780 kb
Host smart-9cbebecb-f1ac-4072-9439-b277d6b9e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39688337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.39688337
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3225827518
Short name T867
Test name
Test status
Simulation time 781904740 ps
CPU time 16.33 seconds
Started Feb 28 06:33:31 PM PST 24
Finished Feb 28 06:33:48 PM PST 24
Peak memory 208812 kb
Host smart-fa7c416b-1463-4289-b3f4-93d575186748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225827518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3225827518
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3170172144
Short name T93
Test name
Test status
Simulation time 200983078 ps
CPU time 3.34 seconds
Started Feb 28 06:33:24 PM PST 24
Finished Feb 28 06:33:28 PM PST 24
Peak memory 213680 kb
Host smart-03fe7519-0c99-4b1f-acf5-c49f24463969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170172144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3170172144
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1596315900
Short name T237
Test name
Test status
Simulation time 964896098 ps
CPU time 4.65 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:26 PM PST 24
Peak memory 209348 kb
Host smart-cb80a5c0-925c-4ef3-9712-67c019e77541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596315900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1596315900
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.580039021
Short name T783
Test name
Test status
Simulation time 209885135 ps
CPU time 6.25 seconds
Started Feb 28 06:33:24 PM PST 24
Finished Feb 28 06:33:31 PM PST 24
Peak memory 208584 kb
Host smart-9a7e6cef-b020-4e9c-9854-a803313e9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580039021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.580039021
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3659164862
Short name T434
Test name
Test status
Simulation time 280144943 ps
CPU time 7.13 seconds
Started Feb 28 06:33:25 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 207612 kb
Host smart-6d6a8ed1-8c00-45b0-8bf4-df5f611e760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659164862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3659164862
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.491667690
Short name T468
Test name
Test status
Simulation time 136164239 ps
CPU time 5.1 seconds
Started Feb 28 06:33:23 PM PST 24
Finished Feb 28 06:33:28 PM PST 24
Peak memory 207520 kb
Host smart-b9c23679-8790-43ca-bee0-effe659ebef9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491667690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.491667690
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2201722934
Short name T748
Test name
Test status
Simulation time 827261523 ps
CPU time 4.49 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:27 PM PST 24
Peak memory 208244 kb
Host smart-3d865ffb-75b3-4c78-965e-ec89dfa010b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201722934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2201722934
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3744808063
Short name T448
Test name
Test status
Simulation time 529542908 ps
CPU time 6.16 seconds
Started Feb 28 06:33:30 PM PST 24
Finished Feb 28 06:33:36 PM PST 24
Peak memory 207128 kb
Host smart-36a8edfb-e714-4784-abbf-595e95a3f785
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744808063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3744808063
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4101497467
Short name T601
Test name
Test status
Simulation time 304722654 ps
CPU time 2.41 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:25 PM PST 24
Peak memory 207604 kb
Host smart-28f8ca59-a2fd-4dd1-9b22-2b64b0390159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101497467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4101497467
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.115765529
Short name T824
Test name
Test status
Simulation time 1462797269 ps
CPU time 13.39 seconds
Started Feb 28 06:33:26 PM PST 24
Finished Feb 28 06:33:39 PM PST 24
Peak memory 207436 kb
Host smart-152de910-da16-46db-96b8-a20e820a9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115765529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.115765529
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2661976120
Short name T63
Test name
Test status
Simulation time 280256825 ps
CPU time 12.25 seconds
Started Feb 28 06:33:27 PM PST 24
Finished Feb 28 06:33:40 PM PST 24
Peak memory 214240 kb
Host smart-32473355-ad39-4115-818c-bb2c15e43b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661976120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2661976120
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3979952453
Short name T671
Test name
Test status
Simulation time 218297009 ps
CPU time 6.62 seconds
Started Feb 28 06:33:22 PM PST 24
Finished Feb 28 06:33:29 PM PST 24
Peak memory 208184 kb
Host smart-a6456d2a-19d7-44f4-b572-aad6fcfb4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979952453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3979952453
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2661033993
Short name T394
Test name
Test status
Simulation time 81394841 ps
CPU time 2.15 seconds
Started Feb 28 06:33:30 PM PST 24
Finished Feb 28 06:33:32 PM PST 24
Peak memory 208844 kb
Host smart-c6775f78-de44-4631-a23d-9e1f9b9e5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661033993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2661033993
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3377924321
Short name T485
Test name
Test status
Simulation time 16431785 ps
CPU time 0.7 seconds
Started Feb 28 06:31:14 PM PST 24
Finished Feb 28 06:31:15 PM PST 24
Peak memory 205208 kb
Host smart-7ae2ded4-e6dc-42f8-8f6d-3e6300012b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377924321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3377924321
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.568939814
Short name T429
Test name
Test status
Simulation time 42520933 ps
CPU time 3.17 seconds
Started Feb 28 06:30:56 PM PST 24
Finished Feb 28 06:30:59 PM PST 24
Peak memory 213660 kb
Host smart-aa184cab-c5d5-4c9f-bc89-df30a3ffd10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568939814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.568939814
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1310383151
Short name T892
Test name
Test status
Simulation time 76442077 ps
CPU time 3.62 seconds
Started Feb 28 06:30:55 PM PST 24
Finished Feb 28 06:30:59 PM PST 24
Peak memory 217676 kb
Host smart-59bf7d65-4ff3-48c7-a564-3fb41a318e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310383151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1310383151
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2222946434
Short name T656
Test name
Test status
Simulation time 306193631 ps
CPU time 4.05 seconds
Started Feb 28 06:31:01 PM PST 24
Finished Feb 28 06:31:05 PM PST 24
Peak memory 208908 kb
Host smart-15894904-82f1-4113-9143-8e3c2470607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222946434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2222946434
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.553052909
Short name T208
Test name
Test status
Simulation time 64220157 ps
CPU time 3.27 seconds
Started Feb 28 06:31:04 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 210548 kb
Host smart-fda23cc0-6fe8-405c-b2f2-137b60c857c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553052909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.553052909
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3490606054
Short name T882
Test name
Test status
Simulation time 65188896 ps
CPU time 3.16 seconds
Started Feb 28 06:30:59 PM PST 24
Finished Feb 28 06:31:02 PM PST 24
Peak memory 209096 kb
Host smart-2b9e487a-4484-498f-86dd-f0cbb40140ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490606054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3490606054
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1689454504
Short name T372
Test name
Test status
Simulation time 57521696 ps
CPU time 3.55 seconds
Started Feb 28 06:30:59 PM PST 24
Finished Feb 28 06:31:03 PM PST 24
Peak memory 207296 kb
Host smart-375a4d83-490f-430a-8e8a-8ae71d01a13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689454504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1689454504
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3648711156
Short name T474
Test name
Test status
Simulation time 337435385 ps
CPU time 3.86 seconds
Started Feb 28 06:30:57 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 207120 kb
Host smart-6718a595-b5dd-4ad4-9db8-3387e73d85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648711156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3648711156
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1801983189
Short name T281
Test name
Test status
Simulation time 226783303 ps
CPU time 7.03 seconds
Started Feb 28 06:30:56 PM PST 24
Finished Feb 28 06:31:03 PM PST 24
Peak memory 207256 kb
Host smart-a8ca4290-77d7-4a8b-a0de-334ea75e7ee6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801983189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1801983189
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2572666691
Short name T852
Test name
Test status
Simulation time 20531873 ps
CPU time 1.84 seconds
Started Feb 28 06:30:52 PM PST 24
Finished Feb 28 06:30:54 PM PST 24
Peak memory 206020 kb
Host smart-0f1e68c3-bc6e-45c9-b9e3-b3e3b51ddf18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572666691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2572666691
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3707619727
Short name T728
Test name
Test status
Simulation time 2395042572 ps
CPU time 25.18 seconds
Started Feb 28 06:30:56 PM PST 24
Finished Feb 28 06:31:21 PM PST 24
Peak memory 207476 kb
Host smart-5b063e2c-5bfb-43eb-bbfb-3399777abaa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707619727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3707619727
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.985740376
Short name T515
Test name
Test status
Simulation time 104425124 ps
CPU time 1.82 seconds
Started Feb 28 06:30:59 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 209116 kb
Host smart-09b56223-e564-4c07-9f07-b8d81bff9516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985740376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.985740376
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3978188997
Short name T406
Test name
Test status
Simulation time 1138691471 ps
CPU time 33.69 seconds
Started Feb 28 06:30:54 PM PST 24
Finished Feb 28 06:31:28 PM PST 24
Peak memory 207916 kb
Host smart-fb2d0b9f-26c7-4dc1-be62-df2a02d17125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978188997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3978188997
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2807910306
Short name T687
Test name
Test status
Simulation time 1453349464 ps
CPU time 39.13 seconds
Started Feb 28 06:30:58 PM PST 24
Finished Feb 28 06:31:37 PM PST 24
Peak memory 214552 kb
Host smart-1b92537e-d34b-494b-a676-6084800acd23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807910306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2807910306
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.400498067
Short name T536
Test name
Test status
Simulation time 128244745 ps
CPU time 4.42 seconds
Started Feb 28 06:30:55 PM PST 24
Finished Feb 28 06:30:59 PM PST 24
Peak memory 206024 kb
Host smart-56d704c3-8038-4a72-8982-8352fe94e52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400498067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.400498067
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4180423301
Short name T611
Test name
Test status
Simulation time 126477444 ps
CPU time 1.92 seconds
Started Feb 28 06:30:59 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 209000 kb
Host smart-4a7f664a-a55a-426a-b377-e5c97c168db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180423301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4180423301
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3528568050
Short name T471
Test name
Test status
Simulation time 62296341 ps
CPU time 0.99 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:04 PM PST 24
Peak memory 205476 kb
Host smart-ff40753c-cef9-4757-9545-95b725ea0c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528568050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3528568050
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1123991169
Short name T289
Test name
Test status
Simulation time 243422666 ps
CPU time 4.68 seconds
Started Feb 28 06:31:04 PM PST 24
Finished Feb 28 06:31:09 PM PST 24
Peak memory 214624 kb
Host smart-73b51361-34fd-4514-a80e-416252497882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123991169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1123991169
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2930925339
Short name T35
Test name
Test status
Simulation time 50548383 ps
CPU time 1.83 seconds
Started Feb 28 06:31:04 PM PST 24
Finished Feb 28 06:31:06 PM PST 24
Peak memory 207660 kb
Host smart-202ae8c4-3498-463b-b3b0-684df1f9ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930925339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2930925339
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4175051644
Short name T764
Test name
Test status
Simulation time 242122051 ps
CPU time 3.17 seconds
Started Feb 28 06:31:01 PM PST 24
Finished Feb 28 06:31:04 PM PST 24
Peak memory 209456 kb
Host smart-cbd72a6a-96b6-41e2-98aa-e57065903860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175051644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4175051644
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3555379855
Short name T341
Test name
Test status
Simulation time 114780053 ps
CPU time 4.56 seconds
Started Feb 28 06:31:05 PM PST 24
Finished Feb 28 06:31:09 PM PST 24
Peak memory 213600 kb
Host smart-7d8a3ccc-d352-4a17-86a7-19c59b6b61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555379855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3555379855
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2053684973
Short name T539
Test name
Test status
Simulation time 130579580 ps
CPU time 3.51 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:06 PM PST 24
Peak memory 219560 kb
Host smart-81e76043-09be-4390-885f-93663e3ecf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053684973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2053684973
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.912703261
Short name T141
Test name
Test status
Simulation time 228413826 ps
CPU time 6.81 seconds
Started Feb 28 06:31:04 PM PST 24
Finished Feb 28 06:31:11 PM PST 24
Peak memory 213604 kb
Host smart-b69e59be-733a-4277-8768-36df538a054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912703261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.912703261
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1500974878
Short name T668
Test name
Test status
Simulation time 183731977 ps
CPU time 4.32 seconds
Started Feb 28 06:31:00 PM PST 24
Finished Feb 28 06:31:04 PM PST 24
Peak memory 205860 kb
Host smart-de3818a6-31be-4f40-b262-44b1614e74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500974878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1500974878
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2298747016
Short name T577
Test name
Test status
Simulation time 197718211 ps
CPU time 2.84 seconds
Started Feb 28 06:30:58 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 206056 kb
Host smart-0cf975b1-5cf7-44eb-837c-f12ade631ba8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298747016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2298747016
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4277289784
Short name T760
Test name
Test status
Simulation time 112795821 ps
CPU time 2.81 seconds
Started Feb 28 06:31:04 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 208104 kb
Host smart-ec98d420-d865-4ca3-9e9c-350e78d23b51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277289784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4277289784
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2655263032
Short name T89
Test name
Test status
Simulation time 121331556 ps
CPU time 2.46 seconds
Started Feb 28 06:30:59 PM PST 24
Finished Feb 28 06:31:01 PM PST 24
Peak memory 205984 kb
Host smart-1e8110ed-f1be-4567-abf4-910909e0b7e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655263032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2655263032
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4288470616
Short name T131
Test name
Test status
Simulation time 76504678 ps
CPU time 3.12 seconds
Started Feb 28 06:31:01 PM PST 24
Finished Feb 28 06:31:04 PM PST 24
Peak memory 209112 kb
Host smart-81bb9ae3-8402-47cb-8f96-617c66323225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288470616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4288470616
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3431590566
Short name T495
Test name
Test status
Simulation time 254789507 ps
CPU time 3.3 seconds
Started Feb 28 06:31:00 PM PST 24
Finished Feb 28 06:31:03 PM PST 24
Peak memory 207768 kb
Host smart-6bae7c29-689c-4f88-a545-d13d3d4d41b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431590566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3431590566
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.366516892
Short name T586
Test name
Test status
Simulation time 484130077 ps
CPU time 5.95 seconds
Started Feb 28 06:31:02 PM PST 24
Finished Feb 28 06:31:08 PM PST 24
Peak memory 209500 kb
Host smart-1a857c65-19bd-4ec6-b908-cd15b119f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366516892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.366516892
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1802308456
Short name T189
Test name
Test status
Simulation time 782909530 ps
CPU time 3.91 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 210088 kb
Host smart-d6118d37-99dc-41b5-b89e-fb940485001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802308456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1802308456
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2126113553
Short name T703
Test name
Test status
Simulation time 36717221 ps
CPU time 0.92 seconds
Started Feb 28 06:31:07 PM PST 24
Finished Feb 28 06:31:08 PM PST 24
Peak memory 205340 kb
Host smart-3c208e93-e347-425e-aa32-c7c9a1d1beba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126113553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2126113553
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2076877837
Short name T354
Test name
Test status
Simulation time 513710811 ps
CPU time 2.43 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:08 PM PST 24
Peak memory 213632 kb
Host smart-e5cf9aac-36bd-4001-82e6-efa1b4778178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076877837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2076877837
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4126068128
Short name T805
Test name
Test status
Simulation time 1370449437 ps
CPU time 5.64 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:12 PM PST 24
Peak memory 209008 kb
Host smart-0c88bc2a-7c07-4246-9eb3-ad977a05c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126068128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4126068128
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1015307530
Short name T46
Test name
Test status
Simulation time 296684126 ps
CPU time 2.8 seconds
Started Feb 28 06:31:08 PM PST 24
Finished Feb 28 06:31:11 PM PST 24
Peak memory 208504 kb
Host smart-5163a53f-05c1-4cc5-909e-b86839d970f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015307530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1015307530
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4168218740
Short name T560
Test name
Test status
Simulation time 2012877885 ps
CPU time 26.4 seconds
Started Feb 28 06:31:07 PM PST 24
Finished Feb 28 06:31:33 PM PST 24
Peak memory 218852 kb
Host smart-42df65c8-6509-4058-9b81-b64994c98529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168218740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4168218740
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1834739539
Short name T883
Test name
Test status
Simulation time 519864291 ps
CPU time 3.88 seconds
Started Feb 28 06:31:07 PM PST 24
Finished Feb 28 06:31:11 PM PST 24
Peak memory 214904 kb
Host smart-217fa470-c650-45aa-8e8f-e59ba821c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834739539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1834739539
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2152666447
Short name T269
Test name
Test status
Simulation time 301220385 ps
CPU time 7.85 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:11 PM PST 24
Peak memory 217588 kb
Host smart-8d394d4d-fbac-48c1-992e-8191095918d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152666447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2152666447
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2114053997
Short name T410
Test name
Test status
Simulation time 877284301 ps
CPU time 27.29 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:33 PM PST 24
Peak memory 207980 kb
Host smart-f5f3c659-b1f8-4e7b-b600-de334d5dfd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114053997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2114053997
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.222922206
Short name T412
Test name
Test status
Simulation time 24563707 ps
CPU time 1.97 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:05 PM PST 24
Peak memory 207736 kb
Host smart-e14341a1-5368-45bb-be09-d5dd592f50a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222922206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.222922206
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2028770350
Short name T904
Test name
Test status
Simulation time 638537283 ps
CPU time 4.59 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:10 PM PST 24
Peak memory 206020 kb
Host smart-bcf44f1d-7dc1-420b-8fd5-55198480e493
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028770350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2028770350
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1239605789
Short name T295
Test name
Test status
Simulation time 828877723 ps
CPU time 5.95 seconds
Started Feb 28 06:31:01 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 207908 kb
Host smart-89d9bbf5-c970-4a9b-bfeb-af6683325f89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239605789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1239605789
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2708955131
Short name T425
Test name
Test status
Simulation time 172962797 ps
CPU time 2.35 seconds
Started Feb 28 06:31:06 PM PST 24
Finished Feb 28 06:31:08 PM PST 24
Peak memory 213648 kb
Host smart-150a81a0-53c5-46c1-a1d4-5a3a2fa37126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708955131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2708955131
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1334521372
Short name T688
Test name
Test status
Simulation time 386318040 ps
CPU time 4.57 seconds
Started Feb 28 06:31:03 PM PST 24
Finished Feb 28 06:31:08 PM PST 24
Peak memory 207444 kb
Host smart-f72583ea-50b0-430b-8a53-f1076ccf2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334521372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1334521372
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1833991376
Short name T258
Test name
Test status
Simulation time 226354775 ps
CPU time 6.91 seconds
Started Feb 28 06:31:05 PM PST 24
Finished Feb 28 06:31:12 PM PST 24
Peak memory 214108 kb
Host smart-2d85e4ea-858c-4b07-8dfb-1e63ea574597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833991376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1833991376
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1817998548
Short name T480
Test name
Test status
Simulation time 686495547 ps
CPU time 8.32 seconds
Started Feb 28 06:31:08 PM PST 24
Finished Feb 28 06:31:16 PM PST 24
Peak memory 207292 kb
Host smart-69495af1-845e-4ebf-9177-5f9da873c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817998548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1817998548
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1921378772
Short name T525
Test name
Test status
Simulation time 117926911 ps
CPU time 2.08 seconds
Started Feb 28 06:31:05 PM PST 24
Finished Feb 28 06:31:07 PM PST 24
Peak memory 208836 kb
Host smart-3775d3f2-3956-4d63-8254-4142c2cf6a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921378772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1921378772
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4170082753
Short name T796
Test name
Test status
Simulation time 37154315 ps
CPU time 0.71 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:14 PM PST 24
Peak memory 205364 kb
Host smart-05cb26fd-4e41-4b4d-81bf-697519422ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170082753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4170082753
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2298906721
Short name T431
Test name
Test status
Simulation time 345749664 ps
CPU time 4.63 seconds
Started Feb 28 06:31:11 PM PST 24
Finished Feb 28 06:31:15 PM PST 24
Peak memory 213576 kb
Host smart-1d7ce972-4073-4f3d-b52e-3f3f2378630e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298906721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2298906721
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.962812632
Short name T71
Test name
Test status
Simulation time 195198477 ps
CPU time 3.92 seconds
Started Feb 28 06:31:11 PM PST 24
Finished Feb 28 06:31:15 PM PST 24
Peak memory 215376 kb
Host smart-66a66b7c-daf1-4ae2-bf4e-fce274ae933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962812632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.962812632
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3983128405
Short name T794
Test name
Test status
Simulation time 1683260251 ps
CPU time 30.03 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:40 PM PST 24
Peak memory 213648 kb
Host smart-76a29ada-0894-4af2-a2bc-81601a624f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983128405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3983128405
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4140334304
Short name T98
Test name
Test status
Simulation time 181231685 ps
CPU time 3.11 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:13 PM PST 24
Peak memory 208308 kb
Host smart-fe439e81-d6ec-4ada-a761-4c50e36058e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140334304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4140334304
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.399052225
Short name T108
Test name
Test status
Simulation time 1759730634 ps
CPU time 33.77 seconds
Started Feb 28 06:31:11 PM PST 24
Finished Feb 28 06:31:45 PM PST 24
Peak memory 213588 kb
Host smart-b503585b-2f7b-4167-9dce-96625276c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399052225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.399052225
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4287988596
Short name T621
Test name
Test status
Simulation time 147905023 ps
CPU time 6.28 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:17 PM PST 24
Peak memory 219460 kb
Host smart-b3ecd70f-ffc7-490a-aa3b-e8b1a6216f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287988596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4287988596
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2925551745
Short name T647
Test name
Test status
Simulation time 215970602 ps
CPU time 5.93 seconds
Started Feb 28 06:31:12 PM PST 24
Finished Feb 28 06:31:18 PM PST 24
Peak memory 208104 kb
Host smart-4e0cf60e-14c3-4a4f-bb74-130da8cc930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925551745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2925551745
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1244877669
Short name T348
Test name
Test status
Simulation time 320896466 ps
CPU time 4.14 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:17 PM PST 24
Peak memory 207672 kb
Host smart-69b8f31c-92d7-4584-9c0c-9f9713daa014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244877669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1244877669
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3348220815
Short name T385
Test name
Test status
Simulation time 64230774 ps
CPU time 2.62 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:13 PM PST 24
Peak memory 207732 kb
Host smart-b791d48f-4b93-4a7b-9555-3d5125d8ae3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348220815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3348220815
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2733155462
Short name T618
Test name
Test status
Simulation time 205161932 ps
CPU time 5.04 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:15 PM PST 24
Peak memory 207768 kb
Host smart-5898f3dd-1d14-4850-bedf-80456d3dd02e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733155462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2733155462
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3871911772
Short name T356
Test name
Test status
Simulation time 61424961 ps
CPU time 2.38 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:12 PM PST 24
Peak memory 205916 kb
Host smart-e110edd4-041c-46e1-8f84-97116ad9be7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871911772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3871911772
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1128279700
Short name T793
Test name
Test status
Simulation time 74486882 ps
CPU time 3.24 seconds
Started Feb 28 06:31:09 PM PST 24
Finished Feb 28 06:31:13 PM PST 24
Peak memory 213516 kb
Host smart-5fffed4d-dd38-4dc8-a644-994956d70a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128279700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1128279700
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2995260647
Short name T896
Test name
Test status
Simulation time 5911297204 ps
CPU time 21.86 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:32 PM PST 24
Peak memory 207640 kb
Host smart-660c7ffa-fda2-4125-ba8c-e1ffefa4749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995260647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2995260647
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.540026373
Short name T374
Test name
Test status
Simulation time 471256447 ps
CPU time 12.98 seconds
Started Feb 28 06:31:10 PM PST 24
Finished Feb 28 06:31:23 PM PST 24
Peak memory 221708 kb
Host smart-e4eb1810-e92f-4203-a90f-fe9cc22bcd98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540026373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.540026373
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1048191387
Short name T48
Test name
Test status
Simulation time 4706530430 ps
CPU time 11.94 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:26 PM PST 24
Peak memory 222116 kb
Host smart-3a7111d3-3765-4899-bbdc-da61dd488eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048191387 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1048191387
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1755923545
Short name T582
Test name
Test status
Simulation time 146659531 ps
CPU time 2.7 seconds
Started Feb 28 06:31:09 PM PST 24
Finished Feb 28 06:31:12 PM PST 24
Peak memory 217508 kb
Host smart-015e1b52-72f1-4381-883b-3f39a7b497ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755923545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1755923545
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2700786742
Short name T584
Test name
Test status
Simulation time 81516433 ps
CPU time 2.19 seconds
Started Feb 28 06:31:09 PM PST 24
Finished Feb 28 06:31:11 PM PST 24
Peak memory 209060 kb
Host smart-0d16d792-135a-42ea-9e3d-5127d4f82a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700786742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2700786742
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3277360534
Short name T736
Test name
Test status
Simulation time 17228962 ps
CPU time 0.73 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:31:16 PM PST 24
Peak memory 205384 kb
Host smart-b7c3de6c-d3c5-47d3-8733-09c350fd9d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277360534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3277360534
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3291894281
Short name T432
Test name
Test status
Simulation time 196769817 ps
CPU time 4.69 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:31:20 PM PST 24
Peak memory 213696 kb
Host smart-ea5d898e-92ce-4aff-9f00-c6a726b6d631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291894281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3291894281
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.821165432
Short name T55
Test name
Test status
Simulation time 78361907 ps
CPU time 2.22 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:31:17 PM PST 24
Peak memory 208252 kb
Host smart-362691d2-c07b-47ee-a8ea-6308ea8a985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821165432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.821165432
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.166686091
Short name T750
Test name
Test status
Simulation time 9359227602 ps
CPU time 48.97 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:32:08 PM PST 24
Peak memory 213704 kb
Host smart-e15765e3-a5f7-4c03-8f64-9891349df065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166686091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.166686091
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2663508988
Short name T283
Test name
Test status
Simulation time 16328773400 ps
CPU time 76.14 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:32:36 PM PST 24
Peak memory 238140 kb
Host smart-0930ce12-d6f1-474c-9b7c-b460234ff251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663508988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2663508988
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3690712073
Short name T245
Test name
Test status
Simulation time 456771602 ps
CPU time 4.17 seconds
Started Feb 28 06:31:14 PM PST 24
Finished Feb 28 06:31:18 PM PST 24
Peak memory 213640 kb
Host smart-8a22a644-bac7-4de2-8843-54d72647e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690712073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3690712073
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1391987753
Short name T297
Test name
Test status
Simulation time 180100893 ps
CPU time 6.59 seconds
Started Feb 28 06:31:12 PM PST 24
Finished Feb 28 06:31:19 PM PST 24
Peak memory 213660 kb
Host smart-9cd990e0-386b-4b34-ba4e-e4fd1ba9e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391987753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1391987753
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4270743887
Short name T663
Test name
Test status
Simulation time 220680180 ps
CPU time 6.16 seconds
Started Feb 28 06:31:14 PM PST 24
Finished Feb 28 06:31:20 PM PST 24
Peak memory 207536 kb
Host smart-787e712b-7d05-4b9d-b82d-17af3bbc6a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270743887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4270743887
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3246572182
Short name T467
Test name
Test status
Simulation time 688722019 ps
CPU time 20.68 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:33 PM PST 24
Peak memory 207120 kb
Host smart-3e8851db-229b-4493-87e6-e64ab9f8f952
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246572182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3246572182
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.972562959
Short name T638
Test name
Test status
Simulation time 963794916 ps
CPU time 9.52 seconds
Started Feb 28 06:31:11 PM PST 24
Finished Feb 28 06:31:21 PM PST 24
Peak memory 207748 kb
Host smart-d4b527dc-ad9d-4fbf-8674-4daabd0f6a13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972562959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.972562959
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2369539983
Short name T654
Test name
Test status
Simulation time 784953103 ps
CPU time 5.34 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:19 PM PST 24
Peak memory 207756 kb
Host smart-352c4348-772f-476f-817f-aa3ea4a85e60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369539983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2369539983
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2796691235
Short name T895
Test name
Test status
Simulation time 294731406 ps
CPU time 2.2 seconds
Started Feb 28 06:31:19 PM PST 24
Finished Feb 28 06:31:22 PM PST 24
Peak memory 208052 kb
Host smart-ffac2255-0f23-4ec6-87b3-d031071f4cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796691235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2796691235
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3914342920
Short name T479
Test name
Test status
Simulation time 368555230 ps
CPU time 12.7 seconds
Started Feb 28 06:31:13 PM PST 24
Finished Feb 28 06:31:26 PM PST 24
Peak memory 207140 kb
Host smart-44d1ed7f-e979-4fd8-8b9e-fd01d7597608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914342920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3914342920
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.621929904
Short name T242
Test name
Test status
Simulation time 8317723812 ps
CPU time 62.25 seconds
Started Feb 28 06:31:15 PM PST 24
Finished Feb 28 06:32:17 PM PST 24
Peak memory 216596 kb
Host smart-d7d89c82-faec-4af1-adc3-6a5fa6385d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621929904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.621929904
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.103399573
Short name T827
Test name
Test status
Simulation time 736297659 ps
CPU time 11.41 seconds
Started Feb 28 06:31:16 PM PST 24
Finished Feb 28 06:31:28 PM PST 24
Peak memory 219604 kb
Host smart-f405cc41-70d9-42ea-a3f5-755ade422893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103399573 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.103399573
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2017237684
Short name T383
Test name
Test status
Simulation time 332627678 ps
CPU time 4.43 seconds
Started Feb 28 06:31:14 PM PST 24
Finished Feb 28 06:31:19 PM PST 24
Peak memory 207892 kb
Host smart-1d623c25-78d1-421a-a609-6fdf51d4ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017237684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2017237684
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2239696762
Short name T393
Test name
Test status
Simulation time 1049549669 ps
CPU time 3.48 seconds
Started Feb 28 06:31:16 PM PST 24
Finished Feb 28 06:31:20 PM PST 24
Peak memory 209180 kb
Host smart-7aeac7fc-a27b-45bd-84a0-3e8d6d55930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239696762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2239696762
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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