Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T28	1		T44	1		T45	2
auto[OpGenId]	11	1			T8	1		T68	1		T242	1
auto[OpGenSwOut]	10	1			T39	1		T243	1		T244	1
auto[OpGenHwOut]	18	1			T12	1		T7	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1742	1			T15	1		T6	180		T44	1
auto[StInit]	85	1			T28	1		T37	1		T44	1
auto[StCreatorRootKey]	60	1			T15	2		T45	2		T20	1
auto[StOwnerIntKey]	35	1			T5	1		T59	1		T60	1
auto[StOwnerKey]	42	1			T38	1		T45	2		T65	1
auto[StDisabled]	464	1			T15	2		T44	3		T71	1
auto[StInvalid]	44	1			T24	1		T41	1		T77	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3455

1

T1

1

T2

1

T3

1

auto[1]

89

1

T28

1

T44

1

T45

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1736	1			T15	1		T6	180		T44	1
auto[StReset]	auto[1]	6	1			T49	1		T36	1		T50	1
auto[StInit]	auto[0]	46	1			T37	1		T52	1		T30	1
auto[StInit]	auto[1]	39	1			T28	1		T44	1		T143	1
auto[StCreatorRootKey]	auto[0]	43	1			T15	2		T45	1		T20	1
auto[StCreatorRootKey]	auto[1]	17	1			T45	1		T55	1		T242	1
auto[StOwnerIntKey]	auto[0]	26	1			T5	1		T59	1		T60	1
auto[StOwnerIntKey]	auto[1]	9	1			T121	1		T245	1		T246	1
auto[StOwnerKey]	auto[0]	34	1			T38	1		T45	2		T65	1
auto[StOwnerKey]	auto[1]	8	1			T7	1		T68	1		T69	1
auto[StDisabled]	auto[0]	454	1			T15	2		T44	3		T71	1
auto[StDisabled]	auto[1]	10	1			T45	1		T12	1		T8	1
auto[StInvalid]	auto[0]	44	1			T24	1		T41	1		T77	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T49	1		T36	1		T50	1
auto[StInit]	auto[OpAdvance]	20	1			T28	1		T44	1		T143	1
auto[StInit]	auto[OpGenId]	7	1			T247	1		T248	1		T79	2
auto[StInit]	auto[OpGenSwOut]	5	1			T39	1		T243	1		T244	1
auto[StInit]	auto[OpGenHwOut]	7	1			T8	1		T68	1		T249	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T45	1		T55	1		T35	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T242	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T250	1		T251	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T252	1		T253	1		T254	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T245	1		T255	1		T256	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T51	1		T257	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T121	1		T246	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	4	1			T69	1		T258	1		T259	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T68	1		T260	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T7	1		T261	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T45	1		T262	1		T263	1
auto[StDisabled]	auto[OpGenId]	1	1			T8	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T79	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T12	1		T245	1		T251	1