Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4763

1

T1

2

T2

11

T4

3

auto[1]

542

1

T1

6

T16

1

T19

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4763

1

T1

2

T2

11

T4

3

auto[1]

542

1

T1

6

T16

1

T19

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4671

1

T1

8

T2

5

T4

3

auto[1]

634

1

T2

6

T16

1

T43

6

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4671

1

T1

8

T2

5

T4

3

auto[1]

634

1

T2

6

T16

1

T43

6

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	447	1			T4	1		T15	1		T42	3
auto[OpGenId]	1125	1			T4	1		T15	3		T42	4
auto[OpGenSwOut]	1070	1			T15	2		T16	1		T42	6
auto[OpGenHwOut]	2587	1			T1	8		T2	11		T4	1
auto[OpDisable]	76	1			T12	2		T57	1		T73	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	447	1			T4	1		T15	1		T42	3
auto[OpGenId]	1125	1			T4	1		T15	3		T42	4
auto[OpGenSwOut]	1070	1			T15	2		T16	1		T42	6
auto[OpGenHwOut]	2587	1			T1	8		T2	11		T4	1
auto[OpDisable]	76	1			T12	2		T57	1		T73	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T1

8

T2

11

T4

3

auto[1]

573

1

T17

3

T18

3

T42

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4732

1

T1

8

T2

11

T4

3

auto[1]

573

1

T17

3

T18

3

T42

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5014

1

T1

8

T2

11

T4

3

auto[1]

291

1

T42

16

T141

6

T142

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1832	1			T1	3		T2	3		T4	2
auto[1]	712	1			T2	3		T15	1		T17	2
auto[2]	685	1			T1	3		T2	1		T15	2
auto[3]	672	1			T1	1		T2	2		T16	2
auto[4]	360	1			T15	1		T18	1		T19	1
auto[5]	348	1			T2	1		T4	1		T15	1
auto[6]	367	1			T1	1		T17	3		T139	2
auto[7]	329	1			T2	1		T18	1		T140	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1404	1			T1	1		T2	2		T4	1
clear_one[1]	712	1			T2	3		T15	1		T17	2
clear_one[2]	685	1			T1	3		T2	1		T15	2
clear_one[3]	672	1			T1	1		T2	2		T16	2
clear_none	1832	1			T1	3		T2	3		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	947	1			T2	3		T4	2		T15	2
auto[StInit]	788	1			T1	1		T2	1		T15	2
auto[StCreatorRootKey]	556	1			T1	1		T2	1		T4	1
auto[StOwnerIntKey]	520	1			T1	1		T2	1		T15	1
auto[StOwnerKey]	497	1			T1	1		T2	1		T15	1
auto[StDisabled]	1839	1			T1	4		T2	4		T15	2
auto[StInvalid]	158	1			T24	2		T41	3		T77	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	947	1			T2	3		T4	2		T15	2
auto[StInit]	788	1			T1	1		T2	1		T15	2
auto[StCreatorRootKey]	556	1			T1	1		T2	1		T4	1
auto[StOwnerIntKey]	520	1			T1	1		T2	1		T15	1
auto[StOwnerKey]	497	1			T1	1		T2	1		T15	1
auto[StDisabled]	1839	1			T1	4		T2	4		T15	2
auto[StInvalid]	158	1			T24	2		T41	3		T77	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T264	1		T265	1		T266	1
auto[0]	auto[StReset]	auto[OpGenId]	163	1			T15	1		T140	1		T29	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	137	1			T41	1		T53	1		T223	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	249	1			T2	1		T4	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	55	1			T53	1		T45	1		T86	1
auto[0]	auto[StInit]	auto[OpGenId]	123	1			T42	1		T44	1		T26	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	88	1			T26	2		T12	2		T7	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	194	1			T1	1		T15	1		T17	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T4	1		T267	1		T268	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	50	1			T29	1		T93	1		T227	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	48	1			T57	1		T220	1		T8	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	72	1			T2	1		T19	1		T42	3
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T269	1		T270	1		T271	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T42	2		T38	1		T272	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T107	1		T223	1		T71	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T230	1		T238	1		T83	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	17	1			T273	1		T274	1		T275	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	25	1			T15	1		T142	1		T212	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T124	1		T119	1		T245	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	60	1			T1	1		T2	1		T43	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	32	1			T42	2		T272	1		T124	1
auto[0]	auto[StDisabled]	auto[OpGenId]	56	1			T226	2		T55	1		T124	3
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T42	2		T229	1		T45	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T1	1		T18	1		T19	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T74	1		T64	1		T70	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	5	1			T276	1		T277	1		T278	1
auto[0]	auto[StInvalid]	auto[OpGenId]	12	1			T77	1		T235	1		T94	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T24	1		T276	1		T279	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T77	1		T53	1		T101	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T53	1		T101	1		T280	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T223	1		T39	1		T8	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	37	1			T281	1		T46	1		T83	1
auto[1]	auto[StInit]	auto[OpAdvance]	9	1			T90	1		T89	1		T282	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T262	1		T283	1		T284	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	21	1			T25	1		T233	1		T55	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T210	1		T285	1		T286	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T287	1		T288	1		T289	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T55	1		T201	1		T8	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T7	1		T55	1		T68	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T139	1		T290	1		T87	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T291	1		T256	1		T292	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T64	1		T8	1		T293	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T29	1		T56	1		T294	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T2	1		T17	1		T234	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T55	1		T92	1		T295	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T42	1		T296	1		T297	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T64	1		T62	2		T298	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T17	1		T109	1		T238	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T86	1		T204	2		T128	1
auto[1]	auto[StDisabled]	auto[OpGenId]	57	1			T142	2		T12	1		T87	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T15	1		T12	1		T123	3
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T2	2		T18	2		T19	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T12	2		T73	1		T55	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T102	1		T103	1		T283	2
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T94	1		T299	1		T300	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T225	1		T301	1		T302	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T53	1		T103	1		T303	1
auto[2]	auto[StReset]	auto[OpGenId]	8	1			T304	2		T305	1		T306	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T236	1		T7	1		T307	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T2	1		T16	1		T109	1
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T27	1		T124	2		T308	1
auto[2]	auto[StInit]	auto[OpGenId]	20	1			T25	1		T223	1		T8	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T12	1		T207	1		T90	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	35	1			T232	1		T45	1		T240	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T309	1		T310	2		T311	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T56	1		T242	1		T312	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T108	1		T230	1		T124	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T237	1		T22	1		T313	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T15	1		T272	1		T314	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T108	1		T204	1		T315	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T55	1		T309	1		T316	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T109	1		T232	1		T290	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T142	1		T12	1		T317	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	9	1			T272	1		T318	1		T242	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T45	1		T12	1		T211	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T240	1		T87	1		T88	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	22	1			T42	1		T55	1		T319	1
auto[2]	auto[StDisabled]	auto[OpGenId]	49	1			T31	1		T86	1		T212	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T15	1		T42	4		T45	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T1	3		T17	1		T43	1
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T57	1		T320	1		T321	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T300	1		T322	1		T305	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T41	1		T91	1		T323	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T324	2		T183	1		T279	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T235	1		T94	1		T325	2
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T41	1		T26	1		T12	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T21	1		T201	1		T124	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	41	1			T2	1		T109	1		T53	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T141	2		T326	2		T276	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T8	2		T327	1		T328	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	7	1			T329	1		T328	1		T82	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	27	1			T237	1		T86	1		T330	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T296	1		T81	1		T331	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T85	1		T40	1		T120	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T332	1		T333	1		T334	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	48	1			T1	1		T43	1		T239	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T335	1		T253	1		T336	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T211	1		T63	1		T247	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T16	1		T12	2		T125	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T43	1		T239	1		T141	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T118	1		T128	3		T337	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T141	1		T12	1		T55	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T141	1		T242	1		T338	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T281	1		T290	1		T241	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T226	1		T216	1		T8	1
auto[3]	auto[StDisabled]	auto[OpGenId]	58	1			T29	1		T12	1		T216	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T223	1		T12	1		T85	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T2	1		T16	1		T19	2
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T58	1		T55	1		T245	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	2	1			T299	1		T339	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T24	1		T53	2		T91	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T183	1		-	-		-	-
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T41	1		T91	1		T299	1
auto[4]	auto[StReset]	auto[OpGenId]	13	1			T26	1		T8	1		T68	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T71	1		T318	1		T197	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T109	1		T281	1		T234	1
auto[4]	auto[StInit]	auto[OpAdvance]	9	1			T27	2		T22	1		T56	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T15	1		T210	1		T63	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T226	1		T120	1		T63	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T143	1		T327	1		T340	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T256	1		T335	1		T341	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T272	2		T8	1		T245	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T342	1		T78	1		T343	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T232	1		T215	1		T280	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T121	1		T344	2		T288	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T140	1		T236	1		T8	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T118	1		T345	1		T346	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T281	1		T347	1		T55	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T348	1		T349	1		T259	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T350	1		T345	1		T351	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T352	1		T353	1		T186	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T19	1		T45	1		T234	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T354	1		T128	2		T345	1
auto[4]	auto[StDisabled]	auto[OpGenId]	22	1			T55	1		T8	1		T62	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T122	1		T222	1		T7	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T18	1		T141	2		T238	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T120	1		T355	1		T356	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T283	1		T299	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T225	1		T357	1		T358	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T300	1		T276	1		T277	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T233	1		T278	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	15	1			T4	1		T223	2		T320	2
auto[5]	auto[StReset]	auto[OpGenSwOut]	17	1			T12	2		T64	1		T245	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T15	1		T281	1		T237	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T326	1		T359	1		T360	1
auto[5]	auto[StInit]	auto[OpGenId]	9	1			T361	1		T326	1		T56	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	10	1			T90	1		T201	1		T329	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	7	1			T2	1		T362	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T207	1		T363	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T45	1		T8	1		T297	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T129	1		T262	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T17	1		T18	1		T281	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T72	1		T260	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T364	1		T365	1		T366	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T58	1		T367	1		T368	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T18	1		T19	1		T369	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T12	1		T370	1		T371	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T307	1		T119	1		T372	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T140	1		T373	1		T364	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T29	1		T232	1		T236	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T86	2		T207	1		T351	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T7	1		T272	1		T70	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T7	1		T318	1		T269	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T42	3		T232	1		T238	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T79	1		T81	1		T304	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T197	1		T374	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T41	1		T102	1		T375	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T53	1		T323	1		T300	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T283	1		T278	1		T325	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T245	1		T49	1		T352	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T40	1		T56	1		T320	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T83	1		T202	1		T307	1
auto[6]	auto[StInit]	auto[OpAdvance]	8	1			T216	1		T22	1		T89	1
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T64	1		T56	1		T196	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T359	1		T376	1		T304	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T281	1		T377	1		T217	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T216	2		T378	2		T379	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T12	1		T56	1		T63	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T12	1		T81	1		T380	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T234	1		T381	1		T217	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T378	1		T372	1		T382	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T312	1		T383	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T93	1		T31	1		T12	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T1	1		T139	1		T240	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T40	1		T378	1		T253	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T319	1		T245	1		T384	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T256	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T12	1		T285	1		T385	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	24	1			T229	1		T272	1		T118	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T12	1		T84	1		T122	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T12	1		T272	1		T118	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T17	3		T139	1		T239	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T293	1		T335	1		T306	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T303	1		T386	1		T374	1
auto[6]	auto[StInvalid]	auto[OpGenId]	2	1			T276	1		T387	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T323	1		T302	1		T386	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T94	1		T388	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T141	1		T45	1		T7	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T236	1		T255	1		T79	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T377	1		T21	1		T285	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T12	1		T96	1		T389	1
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T140	1		T25	1		T282	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T22	1		T363	1		T382	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	19	1			T109	1		T234	1		T390	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T128	1		T191	1		T265	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T391	1		T82	1		T392	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T47	1		T242	1		T393	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T88	1		T394	1		T8	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T128	1		T79	1		T395	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T396	1		T397	1		T398	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T63	1		T191	1		T82	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T215	1		T399	1		T400	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T229	1		T201	1		T63	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T8	1		T372	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T8	2		T248	1		T401	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T18	1		T45	1		T202	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T207	1		T216	1		T68	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T12	1		T211	1		T296	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T223	1		T58	1		T55	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T2	1		T239	1		T281	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T56	1		T304	1		T402	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T279	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T77	1		T339	1		T388	2
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T101	1		T235	1		T299	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T103	1		T386	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1404

1

T1

1

T2

2

T4

1

clear_one[1]

auto[0]

auto[0]

auto[0]

376

1

T15

1

T19

1

T29

2

clear_one[1]

auto[0]

auto[0]

auto[1]

128

1

T17

2

T18

2

T42

1

clear_one[1]

auto[0]

auto[1]

auto[0]

138

1

T2

3

T232

1

T290

1

clear_one[1]

auto[0]

auto[1]

auto[1]

70

1

T85

4

T87

1

T55

3

clear_one[2]

auto[0]

auto[0]

auto[0]

401

1

T2

1

T15

2

T16

1

clear_one[2]

auto[0]

auto[0]

auto[1]

145

1

T17

1

T139

1

T93

1

clear_one[2]

auto[1]

auto[0]

auto[0]

116

1

T1

3

T42

1

T109

1

clear_one[2]

auto[1]

auto[0]

auto[1]

23

1

T142

2

T58

1

T55

1

clear_one[3]

auto[0]

auto[0]

auto[0]

374

1

T2

1

T16

1

T139

1

clear_one[3]

auto[0]

auto[1]

auto[0]

123

1

T2

1

T43

5

T239

2

clear_one[3]

auto[1]

auto[0]

auto[0]

119

1

T1

1

T19

2

T109

2

clear_one[3]

auto[1]

auto[1]

auto[0]

56

1

T16

1

T226

1

T141

3

clear_none

auto[0]

auto[0]

auto[0]

1305

1

T1

1

T2

1

T4

2

clear_none

auto[0]

auto[0]

auto[1]

116

1

T18

1

T139

1

T281

2

clear_none

auto[0]

auto[1]

auto[0]

148

1

T2

2

T43

1

T93

1

clear_none

auto[0]

auto[1]

auto[1]

35

1

T229

1

T142

1

T8

1

clear_none

auto[1]

auto[0]

auto[0]

127

1

T1

2

T19

2

T44

1

clear_none

auto[1]

auto[0]

auto[1]

37

1

T42

2

T38

1

T230

1

clear_none

auto[1]

auto[1]

auto[0]

45

1

T226

2

T71

1

T70

1

clear_none

auto[1]

auto[1]

auto[1]

19

1

T68

1

T403

1

T267

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1318	1			T1	1		T2	2		T4	1
clear_all	auto[1]	86	1			T42	2		T141	1		T86	1
clear_one[1]	auto[0]	660	1			T2	3		T15	1		T17	2
clear_one[1]	auto[1]	52	1			T142	1		T85	3		T86	1
clear_one[2]	auto[0]	644	1			T1	3		T2	1		T15	2
clear_one[2]	auto[1]	41	1			T42	5		T142	2		T272	2
clear_one[3]	auto[0]	641	1			T1	1		T2	2		T16	2
clear_one[3]	auto[1]	31	1			T141	5		T85	4		T216	3
clear_none	auto[0]	1751	1			T1	3		T2	3		T4	2
clear_none	auto[1]	81	1			T42	9		T85	2		T86	1