Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11881

1

T1

5

T2

11

T3

17

auto[Attestation]

8544

1

T1

3

T2

5

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3083	1			T4	5		T5	1		T15	6
auto[Aes]	3641	1			T1	8		T3	3		T4	3
auto[Kmac]	3615	1			T2	16		T3	1		T5	1
auto[Otbn]	3634	1			T3	4		T4	2		T15	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8102	1			T1	8		T2	8		T3	8
auto[OpGenId]	6452	1			T3	13		T4	5		T5	4
auto[OpGenSwOut]	6362	1			T3	8		T4	2		T5	3
auto[OpGenHwOut]	7611	1			T1	8		T2	16		T4	8
auto[OpDisable]	152	1			T47	1		T48	1		T12	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10741

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

17938

1

T1

8

T2

16

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6373	1			T1	1		T2	9		T3	14
auto[StInit]	4797	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3186	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2896	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2464	1			T1	2		T2	2		T3	2
auto[StDisabled]	8015	1			T1	7		T2	7		T3	7
auto[StInvalid]	948	1			T24	28		T41	23		T77	31

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	294	1			T4	1		T108	1		T30	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	162	1			T4	1		T5	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T15	1		T107	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T38	1		T29	1		T107	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	40	1			T86	1		T55	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	225	1			T15	1		T42	3		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T24	1		T77	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	337	1			T3	2		T16	3		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	133	1			T38	1		T25	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	98	1			T15	1		T108	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T42	1		T141	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T106	1		T141	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	211	1			T42	1		T223	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T41	1		T77	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	331	1			T3	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	136	1			T25	1		T44	2		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T107	1		T93	2		T45	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T16	1		T29	1		T12	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	71	1			T45	2		T224	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	230	1			T42	1		T29	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	24	1			T77	1		T53	1		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	285	1			T3	1		T16	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	136	1			T25	1		T108	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T106	1		T47	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T29	1		T44	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	59	1			T3	1		T93	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	227	1			T3	1		T42	2		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	35	1			T77	1		T101	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	87	1			T15	1		T45	6		T12	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	135	1			T26	2		T226	1		T71	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	99	1			T15	1		T107	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T16	1		T59	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T226	1		T45	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T15	1		T108	1		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T24	2		T77	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T15	1		T45	3		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T16	1		T37	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T15	1		T227	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T3	1		T5	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T228	1		T58	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	196	1			T15	1		T44	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T24	1		T41	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	82	1			T41	1		T45	3		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T25	2		T227	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T15	1		T224	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T5	1		T44	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T16	1		T140	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	204	1			T15	1		T229	1		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	24	1			T24	3		T41	1		T101	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	88	1			T41	1		T45	3		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T15	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T15	2		T230	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T108	1		T141	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	60	1			T140	1		T93	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	226	1			T3	1		T44	1		T93	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T24	1		T41	2		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	270	1			T4	3		T28	2		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	133	1			T42	2		T24	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T12	1		T66	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T71	1		T59	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T44	1		T93	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	218	1			T93	1		T226	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T41	1		T77	3		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	460	1			T16	1		T29	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	169	1			T1	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T1	1		T4	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T38	1		T109	1		T230	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T1	1		T19	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	270	1			T1	2		T16	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	39	1			T24	1		T41	2		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	408	1			T2	8		T16	3		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	144	1			T25	2		T93	1		T30	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T43	1		T108	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	112	1			T230	1		T141	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T140	1		T232	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	280	1			T2	3		T43	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T53	1		T233	3		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	459	1			T28	1		T29	1		T108	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	154	1			T15	1		T16	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T17	1		T234	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T17	1		T18	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T38	1		T139	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	256	1			T17	2		T18	3		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T41	2		T101	1		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T41	1		T45	2		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	120	1			T15	1		T26	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T47	2		T45	1		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T141	1		T45	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T45	1		T31	1		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	194	1			T29	1		T93	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T24	1		T41	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T15	2		T45	3		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	139	1			T229	1		T45	1		T237	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T4	1		T42	1		T227	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T1	1		T19	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T107	1		T109	1		T238	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	318	1			T1	2		T16	2		T19	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	22	1			T24	3		T77	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T45	1		T12	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	167	1			T2	1		T15	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T2	1		T239	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	110	1			T2	1		T43	1		T239	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	103	1			T2	1		T43	1		T140	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	300	1			T2	1		T16	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	19	1			T24	2		T41	2		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T15	1		T41	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	184	1			T16	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T4	2		T18	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T42	1		T240	1		T241	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T17	1		T18	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T16	1		T17	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	32	1			T77	1		T53	2		T225	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	185	1			T15	1		T38	1		T107	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	729	1			T4	2		T5	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	222	1			T15	1		T42	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	733	1			T3	2		T16	3		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	203	1			T16	1		T107	1		T93	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	738	1			T3	1		T28	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	201	1			T3	1		T29	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	704	1			T3	2		T16	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T15	1		T107	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	488	1			T15	2		T16	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	197	1			T3	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	448	1			T15	2		T16	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	188	1			T5	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	446	1			T15	1		T24	3		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	192	1			T15	2		T140	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	482	1			T3	1		T15	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	176	1			T44	1		T93	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	670	1			T4	3		T28	2		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	259	1			T1	2		T4	2		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	954	1			T1	3		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	290	1			T43	1		T140	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	877	1			T2	11		T16	3		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	301	1			T17	2		T18	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	909	1			T15	1		T16	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	202	1			T47	2		T141	1		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	427	1			T15	1		T24	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	284	1			T1	1		T4	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	544	1			T1	2		T15	2		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	314	1			T2	3		T43	2		T140	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	559	1			T2	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T4	2		T17	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	573	1			T15	1		T16	2		T17	3