Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3003

1

T4

4

T15

10

T16

7

auto[1]

294

1

T42

13

T141

10

T142

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T93	1		T230	1		T26	1
auto[134217728:268435455]	106	1			T15	1		T42	1		T108	1
auto[268435456:402653183]	94	1			T15	1		T71	1		T236	1
auto[402653184:536870911]	88	1			T16	1		T44	1		T93	1
auto[536870912:671088639]	112	1			T42	2		T38	1		T29	1
auto[671088640:805306367]	111	1			T28	1		T38	1		T29	1
auto[805306368:939524095]	118	1			T42	2		T25	1		T108	1
auto[939524096:1073741823]	88	1			T42	1		T101	1		T141	1
auto[1073741824:1207959551]	88	1			T42	3		T93	1		T30	1
auto[1207959552:1342177279]	82	1			T24	1		T12	1		T86	1
auto[1342177280:1476395007]	102	1			T42	2		T53	2		T141	2
auto[1476395008:1610612735]	107	1			T15	1		T29	1		T107	1
auto[1610612736:1744830463]	117	1			T16	1		T42	1		T230	1
auto[1744830464:1879048191]	112	1			T100	1		T57	1		T86	2
auto[1879048192:2013265919]	123	1			T16	1		T42	1		T29	1
auto[2013265920:2147483647]	101	1			T4	1		T24	1		T107	1
auto[2147483648:2281701375]	102	1			T15	1		T41	1		T25	1
auto[2281701376:2415919103]	105	1			T4	1		T15	1		T42	1
auto[2415919104:2550136831]	110	1			T28	1		T77	1		T108	1
auto[2550136832:2684354559]	102	1			T4	1		T16	1		T38	1
auto[2684354560:2818572287]	108	1			T16	1		T28	1		T140	1
auto[2818572288:2952790015]	116	1			T15	1		T42	1		T29	1
auto[2952790016:3087007743]	105	1			T15	1		T28	1		T44	1
auto[3087007744:3221225471]	110	1			T16	2		T41	2		T93	1
auto[3221225472:3355443199]	93	1			T25	1		T141	1		T45	1
auto[3355443200:3489660927]	107	1			T15	1		T29	1		T141	1
auto[3489660928:3623878655]	91	1			T4	1		T42	2		T24	1
auto[3623878656:3758096383]	102	1			T141	1		T85	2		T86	1
auto[3758096384:3892314111]	98	1			T46	1		T142	2		T85	1
auto[3892314112:4026531839]	107	1			T15	2		T29	1		T142	2
auto[4026531840:4160749567]	85	1			T42	1		T226	1		T141	1
auto[4160749568:4294967295]	100	1			T24	1		T107	1		T77	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T93	1		T230	1		T26	1
auto[0:134217727]	auto[1]	11	1			T122	1		T216	1		T128	1
auto[134217728:268435455]	auto[0]	98	1			T15	1		T108	1		T53	1
auto[134217728:268435455]	auto[1]	8	1			T42	1		T141	1		T265	1
auto[268435456:402653183]	auto[0]	83	1			T15	1		T71	1		T236	1
auto[268435456:402653183]	auto[1]	11	1			T123	1		T124	1		T128	1
auto[402653184:536870911]	auto[0]	79	1			T16	1		T44	1		T93	1
auto[402653184:536870911]	auto[1]	9	1			T141	1		T85	1		T123	2
auto[536870912:671088639]	auto[0]	108	1			T42	2		T38	1		T29	1
auto[536870912:671088639]	auto[1]	4	1			T142	1		T216	1		T345	1
auto[671088640:805306367]	auto[0]	101	1			T28	1		T38	1		T29	1
auto[671088640:805306367]	auto[1]	10	1			T216	1		T378	2		T264	1
auto[805306368:939524095]	auto[0]	104	1			T25	1		T108	1		T141	1
auto[805306368:939524095]	auto[1]	14	1			T42	2		T123	2		T309	1
auto[939524096:1073741823]	auto[0]	76	1			T42	1		T101	1		T100	1
auto[939524096:1073741823]	auto[1]	12	1			T141	1		T123	1		T439	1
auto[1073741824:1207959551]	auto[0]	82	1			T93	1		T30	1		T101	2
auto[1073741824:1207959551]	auto[1]	6	1			T42	3		T292	1		T395	1
auto[1207959552:1342177279]	auto[0]	77	1			T24	1		T12	1		T86	1
auto[1207959552:1342177279]	auto[1]	5	1			T275	1		T442	1		T331	1
auto[1342177280:1476395007]	auto[0]	94	1			T42	1		T53	2		T141	1
auto[1342177280:1476395007]	auto[1]	8	1			T42	1		T141	1		T142	1
auto[1476395008:1610612735]	auto[0]	97	1			T15	1		T29	1		T107	1
auto[1476395008:1610612735]	auto[1]	10	1			T272	1		T123	1		T270	1
auto[1610612736:1744830463]	auto[0]	105	1			T16	1		T230	1		T53	1
auto[1610612736:1744830463]	auto[1]	12	1			T42	1		T141	1		T272	1
auto[1744830464:1879048191]	auto[0]	104	1			T100	1		T57	1		T86	1
auto[1744830464:1879048191]	auto[1]	8	1			T86	1		T439	1		T292	1
auto[1879048192:2013265919]	auto[0]	111	1			T16	1		T29	1		T44	1
auto[1879048192:2013265919]	auto[1]	12	1			T42	1		T86	1		T309	1
auto[2013265920:2147483647]	auto[0]	95	1			T4	1		T24	1		T107	1
auto[2013265920:2147483647]	auto[1]	6	1			T85	1		T351	1		T275	2
auto[2147483648:2281701375]	auto[0]	94	1			T15	1		T41	1		T25	1
auto[2147483648:2281701375]	auto[1]	8	1			T142	1		T124	1		T345	1
auto[2281701376:2415919103]	auto[0]	94	1			T4	1		T15	1		T38	1
auto[2281701376:2415919103]	auto[1]	11	1			T42	1		T272	1		T123	1
auto[2415919104:2550136831]	auto[0]	92	1			T28	1		T77	1		T108	1
auto[2415919104:2550136831]	auto[1]	18	1			T142	1		T85	1		T272	1
auto[2550136832:2684354559]	auto[0]	93	1			T4	1		T16	1		T38	1
auto[2550136832:2684354559]	auto[1]	9	1			T216	2		T123	1		T270	1
auto[2684354560:2818572287]	auto[0]	101	1			T16	1		T28	1		T140	1
auto[2684354560:2818572287]	auto[1]	7	1			T86	1		T216	2		T265	1
auto[2818572288:2952790015]	auto[0]	107	1			T15	1		T29	1		T41	1
auto[2818572288:2952790015]	auto[1]	9	1			T42	1		T265	1		T292	1
auto[2952790016:3087007743]	auto[0]	98	1			T15	1		T28	1		T44	1
auto[2952790016:3087007743]	auto[1]	7	1			T351	1		T310	2		T336	1
auto[3087007744:3221225471]	auto[0]	96	1			T16	2		T41	2		T93	1
auto[3087007744:3221225471]	auto[1]	14	1			T272	1		T123	1		T128	1
auto[3221225472:3355443199]	auto[0]	84	1			T25	1		T45	1		T85	1
auto[3221225472:3355443199]	auto[1]	9	1			T141	1		T86	1		T216	1
auto[3355443200:3489660927]	auto[0]	97	1			T15	1		T29	1		T12	1
auto[3355443200:3489660927]	auto[1]	10	1			T141	1		T275	1		T411	1
auto[3489660928:3623878655]	auto[0]	83	1			T4	1		T24	1		T101	1
auto[3489660928:3623878655]	auto[1]	8	1			T42	2		T141	1		T265	1
auto[3623878656:3758096383]	auto[0]	91	1			T361	1		T58	1		T434	1
auto[3623878656:3758096383]	auto[1]	11	1			T141	1		T85	2		T86	1
auto[3758096384:3892314111]	auto[0]	88	1			T46	1		T85	1		T207	1
auto[3758096384:3892314111]	auto[1]	10	1			T142	2		T123	1		T124	1
auto[3892314112:4026531839]	auto[0]	101	1			T15	2		T29	1		T142	2
auto[3892314112:4026531839]	auto[1]	6	1			T128	1		T351	1		T439	1
auto[4026531840:4160749567]	auto[0]	81	1			T42	1		T226	1		T12	3
auto[4026531840:4160749567]	auto[1]	4	1			T141	1		T142	1		T128	1
auto[4160749568:4294967295]	auto[0]	93	1			T24	1		T107	1		T77	1
auto[4160749568:4294967295]	auto[1]	7	1			T272	1		T129	1		T439	1